Trevor Woerner | 513f640 | 2020-05-06 08:02:41 -0400 | [diff] [blame] | 1 | if ARCH_TEGRA |
Masahiro Yamada | 73a5b1a | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 2 | |
Simon Glass | 035939e | 2021-07-10 21:14:30 -0600 | [diff] [blame] | 3 | config SPL_GPIO |
Simon Glass | 0bdfc3e | 2016-09-12 23:18:39 -0600 | [diff] [blame] | 4 | default y |
| 5 | |
Simon Glass | f2a8946 | 2016-09-12 23:18:41 -0600 | [diff] [blame] | 6 | config SPL_LIBCOMMON_SUPPORT |
| 7 | default y |
| 8 | |
Simon Glass | b16c92c | 2016-09-12 23:18:43 -0600 | [diff] [blame] | 9 | config SPL_LIBGENERIC_SUPPORT |
| 10 | default y |
| 11 | |
Simon Glass | f4d6039 | 2021-08-08 12:20:12 -0600 | [diff] [blame] | 12 | config SPL_SERIAL |
Simon Glass | e076d6f | 2016-09-12 23:18:56 -0600 | [diff] [blame] | 13 | default y |
| 14 | |
Thierry Reding | 45ad0b0 | 2019-04-15 11:32:18 +0200 | [diff] [blame] | 15 | config TEGRA_CLKRST |
| 16 | bool |
| 17 | |
Thierry Reding | c3598a4 | 2019-04-15 11:32:19 +0200 | [diff] [blame] | 18 | config TEGRA_GP_PADCTRL |
| 19 | bool |
| 20 | |
Stephen Warren | adf3abd | 2016-07-18 12:17:11 -0600 | [diff] [blame] | 21 | config TEGRA_IVC |
| 22 | bool "Tegra IVC protocol" |
| 23 | help |
| 24 | IVC (Inter-VM Communication) protocol is a Tegra-specific IPC |
| 25 | (Inter Processor Communication) framework. Within the context of |
| 26 | U-Boot, it is typically used for communication between the main CPU |
| 27 | and various auxiliary processors. |
| 28 | |
Thierry Reding | 17987bb | 2019-04-15 11:32:20 +0200 | [diff] [blame] | 29 | config TEGRA_MC |
| 30 | bool |
| 31 | |
Thierry Reding | 7c0b150 | 2019-04-15 11:32:21 +0200 | [diff] [blame] | 32 | config TEGRA_PINCTRL |
| 33 | bool |
| 34 | |
Thierry Reding | 8ffbcfc | 2019-04-15 11:32:22 +0200 | [diff] [blame] | 35 | config TEGRA_PMC |
| 36 | bool |
| 37 | |
Thierry Reding | ce7eb16 | 2019-04-15 11:32:25 +0200 | [diff] [blame] | 38 | config TEGRA_PMC_SECURE |
| 39 | bool |
| 40 | depends on TEGRA_PMC |
| 41 | |
Stephen Warren | 8c29e65 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 42 | config TEGRA_COMMON |
| 43 | bool "Tegra common options" |
Michal Simek | 84f3dec | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 44 | select BOARD_EARLY_INIT_F |
Stephen Warren | 905752c | 2016-09-13 10:46:00 -0600 | [diff] [blame] | 45 | select CLK |
Tom Warren | 7b5002e | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 46 | select DM |
Simon Glass | a403c9f | 2015-11-29 13:18:01 -0700 | [diff] [blame] | 47 | select DM_ETH |
Tom Warren | 7b5002e | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 48 | select DM_GPIO |
Stephen Warren | 8c29e65 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 49 | select DM_I2C |
Simon Glass | 01e9940 | 2015-10-18 21:17:16 -0600 | [diff] [blame] | 50 | select DM_KEYBOARD |
Tom Warren | a66f772 | 2016-09-13 10:45:48 -0600 | [diff] [blame] | 51 | select DM_MMC |
Simon Glass | d8af3c9 | 2016-01-30 16:38:01 -0700 | [diff] [blame] | 52 | select DM_PWM |
Stephen Warren | 905752c | 2016-09-13 10:46:00 -0600 | [diff] [blame] | 53 | select DM_RESET |
Stephen Warren | 8c29e65 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 54 | select DM_SERIAL |
| 55 | select DM_SPI |
| 56 | select DM_SPI_FLASH |
Stephen Warren | 905752c | 2016-09-13 10:46:00 -0600 | [diff] [blame] | 57 | select MISC |
Stephen Warren | 8c29e65 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 58 | select OF_CONTROL |
Michal Simek | 84f3dec | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 59 | select SPI |
Michal Simek | 2e7c819 | 2018-07-23 15:55:14 +0200 | [diff] [blame] | 60 | imply CMD_DM |
Daniel Thompson | a9e2c67 | 2017-05-19 17:26:58 +0100 | [diff] [blame] | 61 | imply CRC32_VERIFY |
Stephen Warren | 8c29e65 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 62 | |
Stephen Warren | 905752c | 2016-09-13 10:46:00 -0600 | [diff] [blame] | 63 | config TEGRA_NO_BPMP |
| 64 | bool "Tegra common options for SoCs without BPMP" |
| 65 | select TEGRA_CAR |
| 66 | select TEGRA_CAR_CLOCK |
| 67 | select TEGRA_CAR_RESET |
| 68 | |
Stephen Warren | 8c29e65 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 69 | config TEGRA_ARMV7_COMMON |
| 70 | bool "Tegra 32-bit common options" |
Simon Glass | a0c3276 | 2020-07-19 13:56:00 -0600 | [diff] [blame] | 71 | select BINMAN |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 72 | select CPU_V7A |
Stephen Warren | 8c29e65 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 73 | select SPL |
Ley Foon Tan | 48fcc4a | 2017-05-03 17:13:32 +0800 | [diff] [blame] | 74 | select SPL_BOARD_INIT if SPL |
Tom Rini | e1e8544 | 2021-08-27 21:18:30 -0400 | [diff] [blame] | 75 | select SPL_SKIP_LOWLEVEL_INIT_ONLY if SPL |
Stephen Warren | 8c29e65 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 76 | select SUPPORT_SPL |
Thierry Reding | 45ad0b0 | 2019-04-15 11:32:18 +0200 | [diff] [blame] | 77 | select TEGRA_CLKRST |
Stephen Warren | 8c29e65 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 78 | select TEGRA_COMMON |
Stephen Warren | af974be | 2016-05-12 12:07:41 -0600 | [diff] [blame] | 79 | select TEGRA_GPIO |
Thierry Reding | c3598a4 | 2019-04-15 11:32:19 +0200 | [diff] [blame] | 80 | select TEGRA_GP_PADCTRL |
Thierry Reding | 17987bb | 2019-04-15 11:32:20 +0200 | [diff] [blame] | 81 | select TEGRA_MC |
Stephen Warren | 905752c | 2016-09-13 10:46:00 -0600 | [diff] [blame] | 82 | select TEGRA_NO_BPMP |
Thierry Reding | 7c0b150 | 2019-04-15 11:32:21 +0200 | [diff] [blame] | 83 | select TEGRA_PINCTRL |
Thierry Reding | 8ffbcfc | 2019-04-15 11:32:22 +0200 | [diff] [blame] | 84 | select TEGRA_PMC |
Stephen Warren | 8c29e65 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 85 | |
| 86 | config TEGRA_ARMV8_COMMON |
| 87 | bool "Tegra 64-bit common options" |
| 88 | select ARM64 |
Masahiro Yamada | bf4645c | 2019-06-26 13:51:46 +0900 | [diff] [blame] | 89 | select INIT_SP_RELATIVE |
Stephen Warren | eab3605 | 2018-01-03 14:31:52 -0700 | [diff] [blame] | 90 | select LINUX_KERNEL_IMAGE_HEADER |
Thierry Reding | 29ce1d0 | 2019-04-15 11:32:32 +0200 | [diff] [blame] | 91 | select POSITION_INDEPENDENT |
Stephen Warren | 8c29e65 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 92 | select TEGRA_COMMON |
Tom Warren | 7b5002e | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 93 | |
Stephen Warren | eab3605 | 2018-01-03 14:31:52 -0700 | [diff] [blame] | 94 | if TEGRA_ARMV8_COMMON |
| 95 | config LNX_KRNL_IMG_TEXT_OFFSET_BASE |
| 96 | default 0x80000000 |
| 97 | endif |
| 98 | |
Masahiro Yamada | 73a5b1a | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 99 | choice |
| 100 | prompt "Tegra SoC select" |
Joe Hershberger | f069960 | 2015-05-12 14:46:23 -0500 | [diff] [blame] | 101 | optional |
Masahiro Yamada | 73a5b1a | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 102 | |
| 103 | config TEGRA20 |
| 104 | bool "Tegra20 family" |
Tom Rini | bacb52c | 2017-03-07 07:13:42 -0500 | [diff] [blame] | 105 | select ARM_ERRATA_716044 |
| 106 | select ARM_ERRATA_742230 |
| 107 | select ARM_ERRATA_751472 |
Tom Warren | 7b5002e | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 108 | select TEGRA_ARMV7_COMMON |
Masahiro Yamada | 73a5b1a | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 109 | |
| 110 | config TEGRA30 |
| 111 | bool "Tegra30 family" |
Tom Rini | bacb52c | 2017-03-07 07:13:42 -0500 | [diff] [blame] | 112 | select ARM_ERRATA_743622 |
| 113 | select ARM_ERRATA_751472 |
Tom Warren | 7b5002e | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 114 | select TEGRA_ARMV7_COMMON |
Masahiro Yamada | 73a5b1a | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 115 | |
| 116 | config TEGRA114 |
| 117 | bool "Tegra114 family" |
Tom Warren | 7b5002e | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 118 | select TEGRA_ARMV7_COMMON |
Masahiro Yamada | 73a5b1a | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 119 | |
| 120 | config TEGRA124 |
| 121 | bool "Tegra124 family" |
Tom Warren | 7b5002e | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 122 | select TEGRA_ARMV7_COMMON |
Simon Glass | 0662cf2 | 2017-07-25 08:29:58 -0600 | [diff] [blame] | 123 | imply REGMAP |
| 124 | imply SYSCON |
Masahiro Yamada | 73a5b1a | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 125 | |
Tom Warren | ab0cc6b | 2015-03-04 16:36:00 -0700 | [diff] [blame] | 126 | config TEGRA210 |
| 127 | bool "Tegra210 family" |
Tom Rini | 249f11f | 2021-08-19 14:19:39 -0400 | [diff] [blame] | 128 | select GICV2 |
Stephen Warren | 8c29e65 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 129 | select TEGRA_ARMV8_COMMON |
Thierry Reding | 45ad0b0 | 2019-04-15 11:32:18 +0200 | [diff] [blame] | 130 | select TEGRA_CLKRST |
Michal Simek | 84f3dec | 2018-07-23 15:55:13 +0200 | [diff] [blame] | 131 | select TEGRA_GPIO |
Thierry Reding | c3598a4 | 2019-04-15 11:32:19 +0200 | [diff] [blame] | 132 | select TEGRA_GP_PADCTRL |
Thierry Reding | 17987bb | 2019-04-15 11:32:20 +0200 | [diff] [blame] | 133 | select TEGRA_MC |
Stephen Warren | 905752c | 2016-09-13 10:46:00 -0600 | [diff] [blame] | 134 | select TEGRA_NO_BPMP |
Thierry Reding | 7c0b150 | 2019-04-15 11:32:21 +0200 | [diff] [blame] | 135 | select TEGRA_PINCTRL |
Thierry Reding | 8ffbcfc | 2019-04-15 11:32:22 +0200 | [diff] [blame] | 136 | select TEGRA_PMC |
Thierry Reding | ce7eb16 | 2019-04-15 11:32:25 +0200 | [diff] [blame] | 137 | select TEGRA_PMC_SECURE |
Tom Warren | ab0cc6b | 2015-03-04 16:36:00 -0700 | [diff] [blame] | 138 | |
Stephen Warren | 03667eb | 2016-05-12 13:32:55 -0600 | [diff] [blame] | 139 | config TEGRA186 |
| 140 | bool "Tegra186 family" |
Stephen Warren | e0e2b26 | 2016-06-17 09:43:57 -0600 | [diff] [blame] | 141 | select DM_MAILBOX |
Tom Rini | 249f11f | 2021-08-19 14:19:39 -0400 | [diff] [blame] | 142 | select GICV2 |
Stephen Warren | a214892 | 2016-08-08 09:41:34 -0600 | [diff] [blame] | 143 | select TEGRA186_BPMP |
Stephen Warren | e8e3f20 | 2016-08-08 11:28:24 -0600 | [diff] [blame] | 144 | select TEGRA186_CLOCK |
Stephen Warren | 03667eb | 2016-05-12 13:32:55 -0600 | [diff] [blame] | 145 | select TEGRA186_GPIO |
Stephen Warren | fccc9c5 | 2016-08-08 11:28:25 -0600 | [diff] [blame] | 146 | select TEGRA186_RESET |
Stephen Warren | 03667eb | 2016-05-12 13:32:55 -0600 | [diff] [blame] | 147 | select TEGRA_ARMV8_COMMON |
Stephen Warren | e0e2b26 | 2016-06-17 09:43:57 -0600 | [diff] [blame] | 148 | select TEGRA_HSP |
Stephen Warren | adf3abd | 2016-07-18 12:17:11 -0600 | [diff] [blame] | 149 | select TEGRA_IVC |
Stephen Warren | 03667eb | 2016-05-12 13:32:55 -0600 | [diff] [blame] | 150 | |
Masahiro Yamada | 73a5b1a | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 151 | endchoice |
| 152 | |
Stephen Warren | 5a44ab4 | 2016-01-26 10:59:42 -0700 | [diff] [blame] | 153 | config TEGRA_DISCONNECT_UDC_ON_BOOT |
| 154 | bool "Disconnect USB device mode controller on boot" |
Thierry Reding | 4e9260c | 2019-04-15 11:32:26 +0200 | [diff] [blame] | 155 | depends on CI_UDC |
Stephen Warren | 5a44ab4 | 2016-01-26 10:59:42 -0700 | [diff] [blame] | 156 | default y |
| 157 | help |
| 158 | When loading U-Boot into RAM over USB protocols using tools such as |
| 159 | tegrarcm or L4T's exec-uboot.sh/tegraflash.py, Tegra's USB device |
| 160 | mode controller is initialized and enumerated by the host PC running |
| 161 | the tool. Unfortunately, these tools do not shut down the USB |
| 162 | controller before executing the downloaded code, and so the host PC |
| 163 | does not "de-enumerate" the USB device. This option shuts down the |
| 164 | USB controller when U-Boot boots to avoid leaving a stale USB device |
| 165 | present. |
| 166 | |
Simon Glass | 838723b | 2015-02-11 16:32:59 -0700 | [diff] [blame] | 167 | config SYS_MALLOC_F_LEN |
| 168 | default 0x1800 |
| 169 | |
Masahiro Yamada | ed1632a | 2015-02-20 17:04:04 +0900 | [diff] [blame] | 170 | source "arch/arm/mach-tegra/tegra20/Kconfig" |
| 171 | source "arch/arm/mach-tegra/tegra30/Kconfig" |
| 172 | source "arch/arm/mach-tegra/tegra114/Kconfig" |
| 173 | source "arch/arm/mach-tegra/tegra124/Kconfig" |
Tom Warren | ab0cc6b | 2015-03-04 16:36:00 -0700 | [diff] [blame] | 174 | source "arch/arm/mach-tegra/tegra210/Kconfig" |
Stephen Warren | 03667eb | 2016-05-12 13:32:55 -0600 | [diff] [blame] | 175 | source "arch/arm/mach-tegra/tegra186/Kconfig" |
Masahiro Yamada | 73a5b1a | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 176 | |
Simon Glass | bd74b03 | 2017-05-17 03:25:11 -0600 | [diff] [blame] | 177 | config CMD_ENTERRCM |
| 178 | bool "Enable 'enterrcm' command" |
| 179 | default y |
| 180 | help |
| 181 | Tegra's boot ROM supports a mode whereby code may be downloaded and |
| 182 | flash-programmed over a USB connection. On dev boards, this is |
| 183 | typically entered by holding down a "force recovery" button and |
| 184 | resetting the CPU. However, not all boards have such a button (one |
| 185 | example is the Compulab Trimslice), so a method to enter RCM from |
| 186 | software is useful. |
| 187 | |
| 188 | Even on boards other than Trimslice, controlling this over a UART |
| 189 | may be useful, e.g. to allow simple remote control without the need |
| 190 | for mechanical button actuators, or hooking up relays/... to the |
| 191 | button. |
| 192 | |
Masahiro Yamada | 73a5b1a | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 193 | endif |