blob: faa73559fd426dc7868b44573f019dd6123454a0 [file] [log] [blame]
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +09001if TEGRA
2
Simon Glass0bdfc3e2016-09-12 23:18:39 -06003config SPL_GPIO_SUPPORT
4 default y
5
Simon Glassf2a89462016-09-12 23:18:41 -06006config SPL_LIBCOMMON_SUPPORT
7 default y
8
Simon Glassb16c92c2016-09-12 23:18:43 -06009config SPL_LIBGENERIC_SUPPORT
10 default y
11
Simon Glasse076d6f2016-09-12 23:18:56 -060012config SPL_SERIAL_SUPPORT
13 default y
14
Thierry Reding45ad0b02019-04-15 11:32:18 +020015config TEGRA_CLKRST
16 bool
17
Thierry Redingc3598a42019-04-15 11:32:19 +020018config TEGRA_GP_PADCTRL
19 bool
20
Stephen Warrenadf3abd2016-07-18 12:17:11 -060021config TEGRA_IVC
22 bool "Tegra IVC protocol"
23 help
24 IVC (Inter-VM Communication) protocol is a Tegra-specific IPC
25 (Inter Processor Communication) framework. Within the context of
26 U-Boot, it is typically used for communication between the main CPU
27 and various auxiliary processors.
28
Thierry Reding17987bb2019-04-15 11:32:20 +020029config TEGRA_MC
30 bool
31
Thierry Reding7c0b1502019-04-15 11:32:21 +020032config TEGRA_PINCTRL
33 bool
34
Thierry Reding8ffbcfc2019-04-15 11:32:22 +020035config TEGRA_PMC
36 bool
37
Thierry Redingce7eb162019-04-15 11:32:25 +020038config TEGRA_PMC_SECURE
39 bool
40 depends on TEGRA_PMC
41
Stephen Warren8c29e652015-11-23 10:32:01 -070042config TEGRA_COMMON
43 bool "Tegra common options"
Michal Simek84f3dec2018-07-23 15:55:13 +020044 select BINMAN
45 select BOARD_EARLY_INIT_F
Stephen Warren905752c2016-09-13 10:46:00 -060046 select CLK
Tom Warren7b5002e2015-07-17 08:12:51 -070047 select DM
Simon Glassa403c9f2015-11-29 13:18:01 -070048 select DM_ETH
Tom Warren7b5002e2015-07-17 08:12:51 -070049 select DM_GPIO
Stephen Warren8c29e652015-11-23 10:32:01 -070050 select DM_I2C
Simon Glass01e99402015-10-18 21:17:16 -060051 select DM_KEYBOARD
Tom Warrena66f7722016-09-13 10:45:48 -060052 select DM_MMC
Simon Glassd8af3c92016-01-30 16:38:01 -070053 select DM_PWM
Stephen Warren905752c2016-09-13 10:46:00 -060054 select DM_RESET
Stephen Warren8c29e652015-11-23 10:32:01 -070055 select DM_SERIAL
56 select DM_SPI
57 select DM_SPI_FLASH
Stephen Warren905752c2016-09-13 10:46:00 -060058 select MISC
Stephen Warren8c29e652015-11-23 10:32:01 -070059 select OF_CONTROL
Michal Simek84f3dec2018-07-23 15:55:13 +020060 select SPI
Simon Glassfe4ee972016-02-16 18:09:19 -070061 select VIDCONSOLE_AS_LCD if DM_VIDEO
Michal Simek2e7c8192018-07-23 15:55:14 +020062 imply CMD_DM
Daniel Thompsona9e2c672017-05-19 17:26:58 +010063 imply CRC32_VERIFY
Stephen Warren8c29e652015-11-23 10:32:01 -070064
Stephen Warren905752c2016-09-13 10:46:00 -060065config TEGRA_NO_BPMP
66 bool "Tegra common options for SoCs without BPMP"
67 select TEGRA_CAR
68 select TEGRA_CAR_CLOCK
69 select TEGRA_CAR_RESET
70
Stephen Warren8c29e652015-11-23 10:32:01 -070071config TEGRA_ARMV7_COMMON
72 bool "Tegra 32-bit common options"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053073 select CPU_V7A
Stephen Warren8c29e652015-11-23 10:32:01 -070074 select SPL
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080075 select SPL_BOARD_INIT if SPL
Stephen Warren8c29e652015-11-23 10:32:01 -070076 select SUPPORT_SPL
Thierry Reding45ad0b02019-04-15 11:32:18 +020077 select TEGRA_CLKRST
Stephen Warren8c29e652015-11-23 10:32:01 -070078 select TEGRA_COMMON
Stephen Warrenaf974be2016-05-12 12:07:41 -060079 select TEGRA_GPIO
Thierry Redingc3598a42019-04-15 11:32:19 +020080 select TEGRA_GP_PADCTRL
Thierry Reding17987bb2019-04-15 11:32:20 +020081 select TEGRA_MC
Stephen Warren905752c2016-09-13 10:46:00 -060082 select TEGRA_NO_BPMP
Thierry Reding7c0b1502019-04-15 11:32:21 +020083 select TEGRA_PINCTRL
Thierry Reding8ffbcfc2019-04-15 11:32:22 +020084 select TEGRA_PMC
Stephen Warren8c29e652015-11-23 10:32:01 -070085
86config TEGRA_ARMV8_COMMON
87 bool "Tegra 64-bit common options"
88 select ARM64
Stephen Warreneab36052018-01-03 14:31:52 -070089 select LINUX_KERNEL_IMAGE_HEADER
Stephen Warren8c29e652015-11-23 10:32:01 -070090 select TEGRA_COMMON
Tom Warren7b5002e2015-07-17 08:12:51 -070091
Stephen Warreneab36052018-01-03 14:31:52 -070092if TEGRA_ARMV8_COMMON
93config LNX_KRNL_IMG_TEXT_OFFSET_BASE
94 default 0x80000000
95endif
96
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +090097choice
98 prompt "Tegra SoC select"
Joe Hershbergerf0699602015-05-12 14:46:23 -050099 optional
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900100
101config TEGRA20
102 bool "Tegra20 family"
Tom Rinibacb52c2017-03-07 07:13:42 -0500103 select ARM_ERRATA_716044
104 select ARM_ERRATA_742230
105 select ARM_ERRATA_751472
Tom Warren7b5002e2015-07-17 08:12:51 -0700106 select TEGRA_ARMV7_COMMON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900107
108config TEGRA30
109 bool "Tegra30 family"
Tom Rinibacb52c2017-03-07 07:13:42 -0500110 select ARM_ERRATA_743622
111 select ARM_ERRATA_751472
Tom Warren7b5002e2015-07-17 08:12:51 -0700112 select TEGRA_ARMV7_COMMON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900113
114config TEGRA114
115 bool "Tegra114 family"
Tom Warren7b5002e2015-07-17 08:12:51 -0700116 select TEGRA_ARMV7_COMMON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900117
118config TEGRA124
119 bool "Tegra124 family"
Tom Warren7b5002e2015-07-17 08:12:51 -0700120 select TEGRA_ARMV7_COMMON
Simon Glass0662cf22017-07-25 08:29:58 -0600121 imply REGMAP
122 imply SYSCON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900123
Tom Warrenab0cc6b2015-03-04 16:36:00 -0700124config TEGRA210
125 bool "Tegra210 family"
Stephen Warren8c29e652015-11-23 10:32:01 -0700126 select TEGRA_ARMV8_COMMON
Thierry Reding45ad0b02019-04-15 11:32:18 +0200127 select TEGRA_CLKRST
Michal Simek84f3dec2018-07-23 15:55:13 +0200128 select TEGRA_GPIO
Thierry Redingc3598a42019-04-15 11:32:19 +0200129 select TEGRA_GP_PADCTRL
Thierry Reding17987bb2019-04-15 11:32:20 +0200130 select TEGRA_MC
Stephen Warren905752c2016-09-13 10:46:00 -0600131 select TEGRA_NO_BPMP
Thierry Reding7c0b1502019-04-15 11:32:21 +0200132 select TEGRA_PINCTRL
Thierry Reding8ffbcfc2019-04-15 11:32:22 +0200133 select TEGRA_PMC
Thierry Redingce7eb162019-04-15 11:32:25 +0200134 select TEGRA_PMC_SECURE
Tom Warrenab0cc6b2015-03-04 16:36:00 -0700135
Stephen Warren03667eb2016-05-12 13:32:55 -0600136config TEGRA186
137 bool "Tegra186 family"
Stephen Warrene0e2b262016-06-17 09:43:57 -0600138 select DM_MAILBOX
Stephen Warrena2148922016-08-08 09:41:34 -0600139 select TEGRA186_BPMP
Stephen Warrene8e3f202016-08-08 11:28:24 -0600140 select TEGRA186_CLOCK
Stephen Warren03667eb2016-05-12 13:32:55 -0600141 select TEGRA186_GPIO
Stephen Warrenfccc9c52016-08-08 11:28:25 -0600142 select TEGRA186_RESET
Stephen Warren03667eb2016-05-12 13:32:55 -0600143 select TEGRA_ARMV8_COMMON
Stephen Warrene0e2b262016-06-17 09:43:57 -0600144 select TEGRA_HSP
Stephen Warrenadf3abd2016-07-18 12:17:11 -0600145 select TEGRA_IVC
Stephen Warren03667eb2016-05-12 13:32:55 -0600146
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900147endchoice
148
Stephen Warren5a44ab42016-01-26 10:59:42 -0700149config TEGRA_DISCONNECT_UDC_ON_BOOT
150 bool "Disconnect USB device mode controller on boot"
Thierry Reding4e9260c2019-04-15 11:32:26 +0200151 depends on CI_UDC
Stephen Warren5a44ab42016-01-26 10:59:42 -0700152 default y
153 help
154 When loading U-Boot into RAM over USB protocols using tools such as
155 tegrarcm or L4T's exec-uboot.sh/tegraflash.py, Tegra's USB device
156 mode controller is initialized and enumerated by the host PC running
157 the tool. Unfortunately, these tools do not shut down the USB
158 controller before executing the downloaded code, and so the host PC
159 does not "de-enumerate" the USB device. This option shuts down the
160 USB controller when U-Boot boots to avoid leaving a stale USB device
161 present.
162
Simon Glass838723b2015-02-11 16:32:59 -0700163config SYS_MALLOC_F_LEN
164 default 0x1800
165
Masahiro Yamadaed1632a2015-02-20 17:04:04 +0900166source "arch/arm/mach-tegra/tegra20/Kconfig"
167source "arch/arm/mach-tegra/tegra30/Kconfig"
168source "arch/arm/mach-tegra/tegra114/Kconfig"
169source "arch/arm/mach-tegra/tegra124/Kconfig"
Tom Warrenab0cc6b2015-03-04 16:36:00 -0700170source "arch/arm/mach-tegra/tegra210/Kconfig"
Stephen Warren03667eb2016-05-12 13:32:55 -0600171source "arch/arm/mach-tegra/tegra186/Kconfig"
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900172
Simon Glassbd74b032017-05-17 03:25:11 -0600173config CMD_ENTERRCM
174 bool "Enable 'enterrcm' command"
175 default y
176 help
177 Tegra's boot ROM supports a mode whereby code may be downloaded and
178 flash-programmed over a USB connection. On dev boards, this is
179 typically entered by holding down a "force recovery" button and
180 resetting the CPU. However, not all boards have such a button (one
181 example is the Compulab Trimslice), so a method to enter RCM from
182 software is useful.
183
184 Even on boards other than Trimslice, controlling this over a UART
185 may be useful, e.g. to allow simple remote control without the need
186 for mechanical button actuators, or hooking up relays/... to the
187 button.
188
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900189endif