blob: 265051b18aaff5c8f167db44c9a5f52254610429 [file] [log] [blame]
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +09001if TEGRA
2
Simon Glass0bdfc3e2016-09-12 23:18:39 -06003config SPL_GPIO_SUPPORT
4 default y
5
Simon Glassf2a89462016-09-12 23:18:41 -06006config SPL_LIBCOMMON_SUPPORT
7 default y
8
Simon Glassb16c92c2016-09-12 23:18:43 -06009config SPL_LIBGENERIC_SUPPORT
10 default y
11
Simon Glasse076d6f2016-09-12 23:18:56 -060012config SPL_SERIAL_SUPPORT
13 default y
14
Thierry Reding45ad0b02019-04-15 11:32:18 +020015config TEGRA_CLKRST
16 bool
17
Thierry Redingc3598a42019-04-15 11:32:19 +020018config TEGRA_GP_PADCTRL
19 bool
20
Stephen Warrenadf3abd2016-07-18 12:17:11 -060021config TEGRA_IVC
22 bool "Tegra IVC protocol"
23 help
24 IVC (Inter-VM Communication) protocol is a Tegra-specific IPC
25 (Inter Processor Communication) framework. Within the context of
26 U-Boot, it is typically used for communication between the main CPU
27 and various auxiliary processors.
28
Stephen Warren8c29e652015-11-23 10:32:01 -070029config TEGRA_COMMON
30 bool "Tegra common options"
Michal Simek84f3dec2018-07-23 15:55:13 +020031 select BINMAN
32 select BOARD_EARLY_INIT_F
Stephen Warren905752c2016-09-13 10:46:00 -060033 select CLK
Tom Warren7b5002e2015-07-17 08:12:51 -070034 select DM
Simon Glassa403c9f2015-11-29 13:18:01 -070035 select DM_ETH
Tom Warren7b5002e2015-07-17 08:12:51 -070036 select DM_GPIO
Stephen Warren8c29e652015-11-23 10:32:01 -070037 select DM_I2C
Simon Glass01e99402015-10-18 21:17:16 -060038 select DM_KEYBOARD
Tom Warrena66f7722016-09-13 10:45:48 -060039 select DM_MMC
Simon Glassd8af3c92016-01-30 16:38:01 -070040 select DM_PWM
Stephen Warren905752c2016-09-13 10:46:00 -060041 select DM_RESET
Stephen Warren8c29e652015-11-23 10:32:01 -070042 select DM_SERIAL
43 select DM_SPI
44 select DM_SPI_FLASH
Stephen Warren905752c2016-09-13 10:46:00 -060045 select MISC
Stephen Warren8c29e652015-11-23 10:32:01 -070046 select OF_CONTROL
Michal Simek84f3dec2018-07-23 15:55:13 +020047 select SPI
Simon Glassfe4ee972016-02-16 18:09:19 -070048 select VIDCONSOLE_AS_LCD if DM_VIDEO
Michal Simek2e7c8192018-07-23 15:55:14 +020049 imply CMD_DM
Daniel Thompsona9e2c672017-05-19 17:26:58 +010050 imply CRC32_VERIFY
Stephen Warren8c29e652015-11-23 10:32:01 -070051
Stephen Warren905752c2016-09-13 10:46:00 -060052config TEGRA_NO_BPMP
53 bool "Tegra common options for SoCs without BPMP"
54 select TEGRA_CAR
55 select TEGRA_CAR_CLOCK
56 select TEGRA_CAR_RESET
57
Stephen Warren8c29e652015-11-23 10:32:01 -070058config TEGRA_ARMV7_COMMON
59 bool "Tegra 32-bit common options"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053060 select CPU_V7A
Stephen Warren8c29e652015-11-23 10:32:01 -070061 select SPL
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080062 select SPL_BOARD_INIT if SPL
Stephen Warren8c29e652015-11-23 10:32:01 -070063 select SUPPORT_SPL
Thierry Reding45ad0b02019-04-15 11:32:18 +020064 select TEGRA_CLKRST
Stephen Warren8c29e652015-11-23 10:32:01 -070065 select TEGRA_COMMON
Stephen Warrenaf974be2016-05-12 12:07:41 -060066 select TEGRA_GPIO
Thierry Redingc3598a42019-04-15 11:32:19 +020067 select TEGRA_GP_PADCTRL
Stephen Warren905752c2016-09-13 10:46:00 -060068 select TEGRA_NO_BPMP
Stephen Warren8c29e652015-11-23 10:32:01 -070069
70config TEGRA_ARMV8_COMMON
71 bool "Tegra 64-bit common options"
72 select ARM64
Stephen Warreneab36052018-01-03 14:31:52 -070073 select LINUX_KERNEL_IMAGE_HEADER
Stephen Warren8c29e652015-11-23 10:32:01 -070074 select TEGRA_COMMON
Tom Warren7b5002e2015-07-17 08:12:51 -070075
Stephen Warreneab36052018-01-03 14:31:52 -070076if TEGRA_ARMV8_COMMON
77config LNX_KRNL_IMG_TEXT_OFFSET_BASE
78 default 0x80000000
79endif
80
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +090081choice
82 prompt "Tegra SoC select"
Joe Hershbergerf0699602015-05-12 14:46:23 -050083 optional
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +090084
85config TEGRA20
86 bool "Tegra20 family"
Tom Rinibacb52c2017-03-07 07:13:42 -050087 select ARM_ERRATA_716044
88 select ARM_ERRATA_742230
89 select ARM_ERRATA_751472
Tom Warren7b5002e2015-07-17 08:12:51 -070090 select TEGRA_ARMV7_COMMON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +090091
92config TEGRA30
93 bool "Tegra30 family"
Tom Rinibacb52c2017-03-07 07:13:42 -050094 select ARM_ERRATA_743622
95 select ARM_ERRATA_751472
Tom Warren7b5002e2015-07-17 08:12:51 -070096 select TEGRA_ARMV7_COMMON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +090097
98config TEGRA114
99 bool "Tegra114 family"
Tom Warren7b5002e2015-07-17 08:12:51 -0700100 select TEGRA_ARMV7_COMMON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900101
102config TEGRA124
103 bool "Tegra124 family"
Tom Warren7b5002e2015-07-17 08:12:51 -0700104 select TEGRA_ARMV7_COMMON
Simon Glass0662cf22017-07-25 08:29:58 -0600105 imply REGMAP
106 imply SYSCON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900107
Tom Warrenab0cc6b2015-03-04 16:36:00 -0700108config TEGRA210
109 bool "Tegra210 family"
Stephen Warren8c29e652015-11-23 10:32:01 -0700110 select TEGRA_ARMV8_COMMON
Thierry Reding45ad0b02019-04-15 11:32:18 +0200111 select TEGRA_CLKRST
Michal Simek84f3dec2018-07-23 15:55:13 +0200112 select TEGRA_GPIO
Thierry Redingc3598a42019-04-15 11:32:19 +0200113 select TEGRA_GP_PADCTRL
Stephen Warren905752c2016-09-13 10:46:00 -0600114 select TEGRA_NO_BPMP
Tom Warrenab0cc6b2015-03-04 16:36:00 -0700115
Stephen Warren03667eb2016-05-12 13:32:55 -0600116config TEGRA186
117 bool "Tegra186 family"
Stephen Warrene0e2b262016-06-17 09:43:57 -0600118 select DM_MAILBOX
Stephen Warrena2148922016-08-08 09:41:34 -0600119 select TEGRA186_BPMP
Stephen Warrene8e3f202016-08-08 11:28:24 -0600120 select TEGRA186_CLOCK
Stephen Warren03667eb2016-05-12 13:32:55 -0600121 select TEGRA186_GPIO
Stephen Warrenfccc9c52016-08-08 11:28:25 -0600122 select TEGRA186_RESET
Stephen Warren03667eb2016-05-12 13:32:55 -0600123 select TEGRA_ARMV8_COMMON
Stephen Warrene0e2b262016-06-17 09:43:57 -0600124 select TEGRA_HSP
Stephen Warrenadf3abd2016-07-18 12:17:11 -0600125 select TEGRA_IVC
Stephen Warren03667eb2016-05-12 13:32:55 -0600126
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900127endchoice
128
Stephen Warren5a44ab42016-01-26 10:59:42 -0700129config TEGRA_DISCONNECT_UDC_ON_BOOT
130 bool "Disconnect USB device mode controller on boot"
131 default y
132 help
133 When loading U-Boot into RAM over USB protocols using tools such as
134 tegrarcm or L4T's exec-uboot.sh/tegraflash.py, Tegra's USB device
135 mode controller is initialized and enumerated by the host PC running
136 the tool. Unfortunately, these tools do not shut down the USB
137 controller before executing the downloaded code, and so the host PC
138 does not "de-enumerate" the USB device. This option shuts down the
139 USB controller when U-Boot boots to avoid leaving a stale USB device
140 present.
141
Simon Glass838723b2015-02-11 16:32:59 -0700142config SYS_MALLOC_F_LEN
143 default 0x1800
144
Masahiro Yamadaed1632a2015-02-20 17:04:04 +0900145source "arch/arm/mach-tegra/tegra20/Kconfig"
146source "arch/arm/mach-tegra/tegra30/Kconfig"
147source "arch/arm/mach-tegra/tegra114/Kconfig"
148source "arch/arm/mach-tegra/tegra124/Kconfig"
Tom Warrenab0cc6b2015-03-04 16:36:00 -0700149source "arch/arm/mach-tegra/tegra210/Kconfig"
Stephen Warren03667eb2016-05-12 13:32:55 -0600150source "arch/arm/mach-tegra/tegra186/Kconfig"
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900151
Simon Glassbd74b032017-05-17 03:25:11 -0600152config CMD_ENTERRCM
153 bool "Enable 'enterrcm' command"
154 default y
155 help
156 Tegra's boot ROM supports a mode whereby code may be downloaded and
157 flash-programmed over a USB connection. On dev boards, this is
158 typically entered by holding down a "force recovery" button and
159 resetting the CPU. However, not all boards have such a button (one
160 example is the Compulab Trimslice), so a method to enter RCM from
161 software is useful.
162
163 Even on boards other than Trimslice, controlling this over a UART
164 may be useful, e.g. to allow simple remote control without the need
165 for mechanical button actuators, or hooking up relays/... to the
166 button.
167
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900168endif