Blame - arch/arm/mach-tegra/Kconfig - filogic/uboot

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Masahiro Yamada	73a5b1a	2014-08-31 07:10:56 +0900	[diff] [blame]	1	if TEGRA
				2
Simon Glass	0bdfc3e	2016-09-12 23:18:39 -0600	[diff] [blame]	3	config SPL_GPIO_SUPPORT
				4	default y
				5
Simon Glass	f2a8946	2016-09-12 23:18:41 -0600	[diff] [blame]	6	config SPL_LIBCOMMON_SUPPORT
				7	default y
				8
Simon Glass	b16c92c	2016-09-12 23:18:43 -0600	[diff] [blame]	9	config SPL_LIBGENERIC_SUPPORT
				10	default y
				11
Simon Glass	e076d6f	2016-09-12 23:18:56 -0600	[diff] [blame]	12	config SPL_SERIAL_SUPPORT
				13	default y
				14
Stephen Warren	adf3abd	2016-07-18 12:17:11 -0600	[diff] [blame]	15	config TEGRA_IVC
				16	bool "Tegra IVC protocol"
				17	help
				18	IVC (Inter-VM Communication) protocol is a Tegra-specific IPC
				19	(Inter Processor Communication) framework. Within the context of
				20	U-Boot, it is typically used for communication between the main CPU
				21	and various auxiliary processors.
				22
Stephen Warren	8c29e65	2015-11-23 10:32:01 -0700	[diff] [blame]	23	config TEGRA_COMMON
				24	bool "Tegra common options"
Stephen Warren	905752c	2016-09-13 10:46:00 -0600	[diff] [blame]	25	select CLK
Tom Warren	7b5002e	2015-07-17 08:12:51 -0700	[diff] [blame]	26	select DM
Simon Glass	a403c9f	2015-11-29 13:18:01 -0700	[diff] [blame]	27	select DM_ETH
Tom Warren	7b5002e	2015-07-17 08:12:51 -0700	[diff] [blame]	28	select DM_GPIO
Stephen Warren	8c29e65	2015-11-23 10:32:01 -0700	[diff] [blame]	29	select DM_I2C
Simon Glass	01e9940	2015-10-18 21:17:16 -0600	[diff] [blame]	30	select DM_KEYBOARD
Tom Warren	a66f772	2016-09-13 10:45:48 -0600	[diff] [blame]	31	select DM_MMC
Simon Glass	d8af3c9	2016-01-30 16:38:01 -0700	[diff] [blame]	32	select DM_PWM
Stephen Warren	905752c	2016-09-13 10:46:00 -0600	[diff] [blame]	33	select DM_RESET
Stephen Warren	8c29e65	2015-11-23 10:32:01 -0700	[diff] [blame]	34	select DM_SERIAL
				35	select DM_SPI
				36	select DM_SPI_FLASH
Stephen Warren	905752c	2016-09-13 10:46:00 -0600	[diff] [blame]	37	select MISC
Stephen Warren	8c29e65	2015-11-23 10:32:01 -0700	[diff] [blame]	38	select OF_CONTROL
Simon Glass	fe4ee97	2016-02-16 18:09:19 -0700	[diff] [blame]	39	select VIDCONSOLE_AS_LCD if DM_VIDEO
Simon Glass	7a99a87	2017-01-23 13:31:20 -0700	[diff] [blame]	40	select BOARD_EARLY_INIT_F
Stephen Warren	8c29e65	2015-11-23 10:32:01 -0700	[diff] [blame]	41
Stephen Warren	905752c	2016-09-13 10:46:00 -0600	[diff] [blame]	42	config TEGRA_NO_BPMP
				43	bool "Tegra common options for SoCs without BPMP"
				44	select TEGRA_CAR
				45	select TEGRA_CAR_CLOCK
				46	select TEGRA_CAR_RESET
				47
Stephen Warren	8c29e65	2015-11-23 10:32:01 -0700	[diff] [blame]	48	config TEGRA_ARMV7_COMMON
				49	bool "Tegra 32-bit common options"
				50	select CPU_V7
				51	select SPL
				52	select SUPPORT_SPL
				53	select TEGRA_COMMON
Stephen Warren	af974be	2016-05-12 12:07:41 -0600	[diff] [blame]	54	select TEGRA_GPIO
Stephen Warren	905752c	2016-09-13 10:46:00 -0600	[diff] [blame]	55	select TEGRA_NO_BPMP
Stephen Warren	8c29e65	2015-11-23 10:32:01 -0700	[diff] [blame]	56
				57	config TEGRA_ARMV8_COMMON
				58	bool "Tegra 64-bit common options"
				59	select ARM64
				60	select TEGRA_COMMON
Tom Warren	7b5002e	2015-07-17 08:12:51 -0700	[diff] [blame]	61
Masahiro Yamada	73a5b1a	2014-08-31 07:10:56 +0900	[diff] [blame]	62	choice
				63	prompt "Tegra SoC select"
Joe Hershberger	f069960	2015-05-12 14:46:23 -0500	[diff] [blame]	64	optional
Masahiro Yamada	73a5b1a	2014-08-31 07:10:56 +0900	[diff] [blame]	65
				66	config TEGRA20
				67	bool "Tegra20 family"
Tom Rini	bacb52c	2017-03-07 07:13:42 -0500	[diff] [blame^]	68	select ARM_ERRATA_716044
				69	select ARM_ERRATA_742230
				70	select ARM_ERRATA_751472
Tom Warren	7b5002e	2015-07-17 08:12:51 -0700	[diff] [blame]	71	select TEGRA_ARMV7_COMMON
Masahiro Yamada	73a5b1a	2014-08-31 07:10:56 +0900	[diff] [blame]	72
				73	config TEGRA30
				74	bool "Tegra30 family"
Tom Rini	bacb52c	2017-03-07 07:13:42 -0500	[diff] [blame^]	75	select ARM_ERRATA_743622
				76	select ARM_ERRATA_751472
Tom Warren	7b5002e	2015-07-17 08:12:51 -0700	[diff] [blame]	77	select TEGRA_ARMV7_COMMON
Masahiro Yamada	73a5b1a	2014-08-31 07:10:56 +0900	[diff] [blame]	78
				79	config TEGRA114
				80	bool "Tegra114 family"
Tom Warren	7b5002e	2015-07-17 08:12:51 -0700	[diff] [blame]	81	select TEGRA_ARMV7_COMMON
Masahiro Yamada	73a5b1a	2014-08-31 07:10:56 +0900	[diff] [blame]	82
				83	config TEGRA124
				84	bool "Tegra124 family"
Tom Warren	7b5002e	2015-07-17 08:12:51 -0700	[diff] [blame]	85	select TEGRA_ARMV7_COMMON
Masahiro Yamada	73a5b1a	2014-08-31 07:10:56 +0900	[diff] [blame]	86
Tom Warren	ab0cc6b	2015-03-04 16:36:00 -0700	[diff] [blame]	87	config TEGRA210
				88	bool "Tegra210 family"
Stephen Warren	af974be	2016-05-12 12:07:41 -0600	[diff] [blame]	89	select TEGRA_GPIO
Stephen Warren	8c29e65	2015-11-23 10:32:01 -0700	[diff] [blame]	90	select TEGRA_ARMV8_COMMON
Stephen Warren	905752c	2016-09-13 10:46:00 -0600	[diff] [blame]	91	select TEGRA_NO_BPMP
Tom Warren	ab0cc6b	2015-03-04 16:36:00 -0700	[diff] [blame]	92
Stephen Warren	03667eb	2016-05-12 13:32:55 -0600	[diff] [blame]	93	config TEGRA186
				94	bool "Tegra186 family"
Stephen Warren	e0e2b26	2016-06-17 09:43:57 -0600	[diff] [blame]	95	select DM_MAILBOX
Stephen Warren	a214892	2016-08-08 09:41:34 -0600	[diff] [blame]	96	select TEGRA186_BPMP
Stephen Warren	e8e3f20	2016-08-08 11:28:24 -0600	[diff] [blame]	97	select TEGRA186_CLOCK
Stephen Warren	03667eb	2016-05-12 13:32:55 -0600	[diff] [blame]	98	select TEGRA186_GPIO
Stephen Warren	fccc9c5	2016-08-08 11:28:25 -0600	[diff] [blame]	99	select TEGRA186_RESET
Stephen Warren	03667eb	2016-05-12 13:32:55 -0600	[diff] [blame]	100	select TEGRA_ARMV8_COMMON
Stephen Warren	e0e2b26	2016-06-17 09:43:57 -0600	[diff] [blame]	101	select TEGRA_HSP
Stephen Warren	adf3abd	2016-07-18 12:17:11 -0600	[diff] [blame]	102	select TEGRA_IVC
Stephen Warren	03667eb	2016-05-12 13:32:55 -0600	[diff] [blame]	103
Masahiro Yamada	73a5b1a	2014-08-31 07:10:56 +0900	[diff] [blame]	104	endchoice
				105
Stephen Warren	5a44ab4	2016-01-26 10:59:42 -0700	[diff] [blame]	106	config TEGRA_DISCONNECT_UDC_ON_BOOT
				107	bool "Disconnect USB device mode controller on boot"
				108	default y
				109	help
				110	When loading U-Boot into RAM over USB protocols using tools such as
				111	tegrarcm or L4T's exec-uboot.sh/tegraflash.py, Tegra's USB device
				112	mode controller is initialized and enumerated by the host PC running
				113	the tool. Unfortunately, these tools do not shut down the USB
				114	controller before executing the downloaded code, and so the host PC
				115	does not "de-enumerate" the USB device. This option shuts down the
				116	USB controller when U-Boot boots to avoid leaving a stale USB device
				117	present.
				118
Simon Glass	838723b	2015-02-11 16:32:59 -0700	[diff] [blame]	119	config SYS_MALLOC_F_LEN
				120	default 0x1800
				121
Masahiro Yamada	ed1632a	2015-02-20 17:04:04 +0900	[diff] [blame]	122	source "arch/arm/mach-tegra/tegra20/Kconfig"
				123	source "arch/arm/mach-tegra/tegra30/Kconfig"
				124	source "arch/arm/mach-tegra/tegra114/Kconfig"
				125	source "arch/arm/mach-tegra/tegra124/Kconfig"
Tom Warren	ab0cc6b	2015-03-04 16:36:00 -0700	[diff] [blame]	126	source "arch/arm/mach-tegra/tegra210/Kconfig"
Stephen Warren	03667eb	2016-05-12 13:32:55 -0600	[diff] [blame]	127	source "arch/arm/mach-tegra/tegra186/Kconfig"
Masahiro Yamada	73a5b1a	2014-08-31 07:10:56 +0900	[diff] [blame]	128
				129	endif