Masahiro Yamada | 73a5b1a | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 1 | if TEGRA |
| 2 | |
Stephen Warren | adf3abd | 2016-07-18 12:17:11 -0600 | [diff] [blame^] | 3 | config TEGRA_IVC |
| 4 | bool "Tegra IVC protocol" |
| 5 | help |
| 6 | IVC (Inter-VM Communication) protocol is a Tegra-specific IPC |
| 7 | (Inter Processor Communication) framework. Within the context of |
| 8 | U-Boot, it is typically used for communication between the main CPU |
| 9 | and various auxiliary processors. |
| 10 | |
Stephen Warren | 8c29e65 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 11 | config TEGRA_COMMON |
| 12 | bool "Tegra common options" |
Tom Warren | 7b5002e | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 13 | select DM |
Simon Glass | a403c9f | 2015-11-29 13:18:01 -0700 | [diff] [blame] | 14 | select DM_ETH |
Tom Warren | 7b5002e | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 15 | select DM_GPIO |
Stephen Warren | 8c29e65 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 16 | select DM_I2C |
Simon Glass | 01e9940 | 2015-10-18 21:17:16 -0600 | [diff] [blame] | 17 | select DM_KEYBOARD |
Simon Glass | 46fcfc1 | 2015-11-19 20:27:02 -0700 | [diff] [blame] | 18 | select DM_PCI |
Simon Glass | eca7b0d | 2015-11-26 19:51:30 -0700 | [diff] [blame] | 19 | select DM_PCI_COMPAT |
Simon Glass | d8af3c9 | 2016-01-30 16:38:01 -0700 | [diff] [blame] | 20 | select DM_PWM |
Stephen Warren | 8c29e65 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 21 | select DM_SERIAL |
| 22 | select DM_SPI |
| 23 | select DM_SPI_FLASH |
| 24 | select OF_CONTROL |
Simon Glass | fe4ee97 | 2016-02-16 18:09:19 -0700 | [diff] [blame] | 25 | select VIDCONSOLE_AS_LCD if DM_VIDEO |
Stephen Warren | 8c29e65 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 26 | |
| 27 | config TEGRA_ARMV7_COMMON |
| 28 | bool "Tegra 32-bit common options" |
| 29 | select CPU_V7 |
| 30 | select SPL |
| 31 | select SUPPORT_SPL |
| 32 | select TEGRA_COMMON |
Stephen Warren | af974be | 2016-05-12 12:07:41 -0600 | [diff] [blame] | 33 | select TEGRA_GPIO |
Stephen Warren | 8c29e65 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 34 | |
| 35 | config TEGRA_ARMV8_COMMON |
| 36 | bool "Tegra 64-bit common options" |
| 37 | select ARM64 |
| 38 | select TEGRA_COMMON |
Tom Warren | 7b5002e | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 39 | |
Masahiro Yamada | 73a5b1a | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 40 | choice |
| 41 | prompt "Tegra SoC select" |
Joe Hershberger | f069960 | 2015-05-12 14:46:23 -0500 | [diff] [blame] | 42 | optional |
Masahiro Yamada | 73a5b1a | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 43 | |
| 44 | config TEGRA20 |
| 45 | bool "Tegra20 family" |
Tom Warren | 7b5002e | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 46 | select TEGRA_ARMV7_COMMON |
Masahiro Yamada | 73a5b1a | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 47 | |
| 48 | config TEGRA30 |
| 49 | bool "Tegra30 family" |
Tom Warren | 7b5002e | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 50 | select TEGRA_ARMV7_COMMON |
Masahiro Yamada | 73a5b1a | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 51 | |
| 52 | config TEGRA114 |
| 53 | bool "Tegra114 family" |
Tom Warren | 7b5002e | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 54 | select TEGRA_ARMV7_COMMON |
Masahiro Yamada | 73a5b1a | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 55 | |
| 56 | config TEGRA124 |
| 57 | bool "Tegra124 family" |
Tom Warren | 7b5002e | 2015-07-17 08:12:51 -0700 | [diff] [blame] | 58 | select TEGRA_ARMV7_COMMON |
Masahiro Yamada | 73a5b1a | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 59 | |
Tom Warren | ab0cc6b | 2015-03-04 16:36:00 -0700 | [diff] [blame] | 60 | config TEGRA210 |
| 61 | bool "Tegra210 family" |
Stephen Warren | af974be | 2016-05-12 12:07:41 -0600 | [diff] [blame] | 62 | select TEGRA_GPIO |
Stephen Warren | 8c29e65 | 2015-11-23 10:32:01 -0700 | [diff] [blame] | 63 | select TEGRA_ARMV8_COMMON |
Tom Warren | ab0cc6b | 2015-03-04 16:36:00 -0700 | [diff] [blame] | 64 | |
Stephen Warren | 03667eb | 2016-05-12 13:32:55 -0600 | [diff] [blame] | 65 | config TEGRA186 |
| 66 | bool "Tegra186 family" |
Stephen Warren | e0e2b26 | 2016-06-17 09:43:57 -0600 | [diff] [blame] | 67 | select DM_MAILBOX |
Stephen Warren | 03667eb | 2016-05-12 13:32:55 -0600 | [diff] [blame] | 68 | select TEGRA186_GPIO |
| 69 | select TEGRA_ARMV8_COMMON |
Stephen Warren | e0e2b26 | 2016-06-17 09:43:57 -0600 | [diff] [blame] | 70 | select TEGRA_HSP |
Stephen Warren | adf3abd | 2016-07-18 12:17:11 -0600 | [diff] [blame^] | 71 | select TEGRA_IVC |
Stephen Warren | 03667eb | 2016-05-12 13:32:55 -0600 | [diff] [blame] | 72 | |
Masahiro Yamada | 73a5b1a | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 73 | endchoice |
| 74 | |
Stephen Warren | 5a44ab4 | 2016-01-26 10:59:42 -0700 | [diff] [blame] | 75 | config TEGRA_DISCONNECT_UDC_ON_BOOT |
| 76 | bool "Disconnect USB device mode controller on boot" |
| 77 | default y |
| 78 | help |
| 79 | When loading U-Boot into RAM over USB protocols using tools such as |
| 80 | tegrarcm or L4T's exec-uboot.sh/tegraflash.py, Tegra's USB device |
| 81 | mode controller is initialized and enumerated by the host PC running |
| 82 | the tool. Unfortunately, these tools do not shut down the USB |
| 83 | controller before executing the downloaded code, and so the host PC |
| 84 | does not "de-enumerate" the USB device. This option shuts down the |
| 85 | USB controller when U-Boot boots to avoid leaving a stale USB device |
| 86 | present. |
| 87 | |
Simon Glass | 838723b | 2015-02-11 16:32:59 -0700 | [diff] [blame] | 88 | config SYS_MALLOC_F_LEN |
| 89 | default 0x1800 |
| 90 | |
Masahiro Yamada | ed1632a | 2015-02-20 17:04:04 +0900 | [diff] [blame] | 91 | source "arch/arm/mach-tegra/tegra20/Kconfig" |
| 92 | source "arch/arm/mach-tegra/tegra30/Kconfig" |
| 93 | source "arch/arm/mach-tegra/tegra114/Kconfig" |
| 94 | source "arch/arm/mach-tegra/tegra124/Kconfig" |
Tom Warren | ab0cc6b | 2015-03-04 16:36:00 -0700 | [diff] [blame] | 95 | source "arch/arm/mach-tegra/tegra210/Kconfig" |
Stephen Warren | 03667eb | 2016-05-12 13:32:55 -0600 | [diff] [blame] | 96 | source "arch/arm/mach-tegra/tegra186/Kconfig" |
Masahiro Yamada | 73a5b1a | 2014-08-31 07:10:56 +0900 | [diff] [blame] | 97 | |
| 98 | endif |