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Masahiro Yamada73a5b1a2014-08-31 07:10:56 +09001if TEGRA
2
Simon Glass0bdfc3e2016-09-12 23:18:39 -06003config SPL_GPIO_SUPPORT
4 default y
5
Simon Glassf2a89462016-09-12 23:18:41 -06006config SPL_LIBCOMMON_SUPPORT
7 default y
8
Simon Glassb16c92c2016-09-12 23:18:43 -06009config SPL_LIBGENERIC_SUPPORT
10 default y
11
Simon Glasse076d6f2016-09-12 23:18:56 -060012config SPL_SERIAL_SUPPORT
13 default y
14
Thierry Reding45ad0b02019-04-15 11:32:18 +020015config TEGRA_CLKRST
16 bool
17
Thierry Redingc3598a42019-04-15 11:32:19 +020018config TEGRA_GP_PADCTRL
19 bool
20
Stephen Warrenadf3abd2016-07-18 12:17:11 -060021config TEGRA_IVC
22 bool "Tegra IVC protocol"
23 help
24 IVC (Inter-VM Communication) protocol is a Tegra-specific IPC
25 (Inter Processor Communication) framework. Within the context of
26 U-Boot, it is typically used for communication between the main CPU
27 and various auxiliary processors.
28
Thierry Reding17987bb2019-04-15 11:32:20 +020029config TEGRA_MC
30 bool
31
Stephen Warren8c29e652015-11-23 10:32:01 -070032config TEGRA_COMMON
33 bool "Tegra common options"
Michal Simek84f3dec2018-07-23 15:55:13 +020034 select BINMAN
35 select BOARD_EARLY_INIT_F
Stephen Warren905752c2016-09-13 10:46:00 -060036 select CLK
Tom Warren7b5002e2015-07-17 08:12:51 -070037 select DM
Simon Glassa403c9f2015-11-29 13:18:01 -070038 select DM_ETH
Tom Warren7b5002e2015-07-17 08:12:51 -070039 select DM_GPIO
Stephen Warren8c29e652015-11-23 10:32:01 -070040 select DM_I2C
Simon Glass01e99402015-10-18 21:17:16 -060041 select DM_KEYBOARD
Tom Warrena66f7722016-09-13 10:45:48 -060042 select DM_MMC
Simon Glassd8af3c92016-01-30 16:38:01 -070043 select DM_PWM
Stephen Warren905752c2016-09-13 10:46:00 -060044 select DM_RESET
Stephen Warren8c29e652015-11-23 10:32:01 -070045 select DM_SERIAL
46 select DM_SPI
47 select DM_SPI_FLASH
Stephen Warren905752c2016-09-13 10:46:00 -060048 select MISC
Stephen Warren8c29e652015-11-23 10:32:01 -070049 select OF_CONTROL
Michal Simek84f3dec2018-07-23 15:55:13 +020050 select SPI
Simon Glassfe4ee972016-02-16 18:09:19 -070051 select VIDCONSOLE_AS_LCD if DM_VIDEO
Michal Simek2e7c8192018-07-23 15:55:14 +020052 imply CMD_DM
Daniel Thompsona9e2c672017-05-19 17:26:58 +010053 imply CRC32_VERIFY
Stephen Warren8c29e652015-11-23 10:32:01 -070054
Stephen Warren905752c2016-09-13 10:46:00 -060055config TEGRA_NO_BPMP
56 bool "Tegra common options for SoCs without BPMP"
57 select TEGRA_CAR
58 select TEGRA_CAR_CLOCK
59 select TEGRA_CAR_RESET
60
Stephen Warren8c29e652015-11-23 10:32:01 -070061config TEGRA_ARMV7_COMMON
62 bool "Tegra 32-bit common options"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053063 select CPU_V7A
Stephen Warren8c29e652015-11-23 10:32:01 -070064 select SPL
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080065 select SPL_BOARD_INIT if SPL
Stephen Warren8c29e652015-11-23 10:32:01 -070066 select SUPPORT_SPL
Thierry Reding45ad0b02019-04-15 11:32:18 +020067 select TEGRA_CLKRST
Stephen Warren8c29e652015-11-23 10:32:01 -070068 select TEGRA_COMMON
Stephen Warrenaf974be2016-05-12 12:07:41 -060069 select TEGRA_GPIO
Thierry Redingc3598a42019-04-15 11:32:19 +020070 select TEGRA_GP_PADCTRL
Thierry Reding17987bb2019-04-15 11:32:20 +020071 select TEGRA_MC
Stephen Warren905752c2016-09-13 10:46:00 -060072 select TEGRA_NO_BPMP
Stephen Warren8c29e652015-11-23 10:32:01 -070073
74config TEGRA_ARMV8_COMMON
75 bool "Tegra 64-bit common options"
76 select ARM64
Stephen Warreneab36052018-01-03 14:31:52 -070077 select LINUX_KERNEL_IMAGE_HEADER
Stephen Warren8c29e652015-11-23 10:32:01 -070078 select TEGRA_COMMON
Tom Warren7b5002e2015-07-17 08:12:51 -070079
Stephen Warreneab36052018-01-03 14:31:52 -070080if TEGRA_ARMV8_COMMON
81config LNX_KRNL_IMG_TEXT_OFFSET_BASE
82 default 0x80000000
83endif
84
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +090085choice
86 prompt "Tegra SoC select"
Joe Hershbergerf0699602015-05-12 14:46:23 -050087 optional
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +090088
89config TEGRA20
90 bool "Tegra20 family"
Tom Rinibacb52c2017-03-07 07:13:42 -050091 select ARM_ERRATA_716044
92 select ARM_ERRATA_742230
93 select ARM_ERRATA_751472
Tom Warren7b5002e2015-07-17 08:12:51 -070094 select TEGRA_ARMV7_COMMON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +090095
96config TEGRA30
97 bool "Tegra30 family"
Tom Rinibacb52c2017-03-07 07:13:42 -050098 select ARM_ERRATA_743622
99 select ARM_ERRATA_751472
Tom Warren7b5002e2015-07-17 08:12:51 -0700100 select TEGRA_ARMV7_COMMON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900101
102config TEGRA114
103 bool "Tegra114 family"
Tom Warren7b5002e2015-07-17 08:12:51 -0700104 select TEGRA_ARMV7_COMMON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900105
106config TEGRA124
107 bool "Tegra124 family"
Tom Warren7b5002e2015-07-17 08:12:51 -0700108 select TEGRA_ARMV7_COMMON
Simon Glass0662cf22017-07-25 08:29:58 -0600109 imply REGMAP
110 imply SYSCON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900111
Tom Warrenab0cc6b2015-03-04 16:36:00 -0700112config TEGRA210
113 bool "Tegra210 family"
Stephen Warren8c29e652015-11-23 10:32:01 -0700114 select TEGRA_ARMV8_COMMON
Thierry Reding45ad0b02019-04-15 11:32:18 +0200115 select TEGRA_CLKRST
Michal Simek84f3dec2018-07-23 15:55:13 +0200116 select TEGRA_GPIO
Thierry Redingc3598a42019-04-15 11:32:19 +0200117 select TEGRA_GP_PADCTRL
Thierry Reding17987bb2019-04-15 11:32:20 +0200118 select TEGRA_MC
Stephen Warren905752c2016-09-13 10:46:00 -0600119 select TEGRA_NO_BPMP
Tom Warrenab0cc6b2015-03-04 16:36:00 -0700120
Stephen Warren03667eb2016-05-12 13:32:55 -0600121config TEGRA186
122 bool "Tegra186 family"
Stephen Warrene0e2b262016-06-17 09:43:57 -0600123 select DM_MAILBOX
Stephen Warrena2148922016-08-08 09:41:34 -0600124 select TEGRA186_BPMP
Stephen Warrene8e3f202016-08-08 11:28:24 -0600125 select TEGRA186_CLOCK
Stephen Warren03667eb2016-05-12 13:32:55 -0600126 select TEGRA186_GPIO
Stephen Warrenfccc9c52016-08-08 11:28:25 -0600127 select TEGRA186_RESET
Stephen Warren03667eb2016-05-12 13:32:55 -0600128 select TEGRA_ARMV8_COMMON
Stephen Warrene0e2b262016-06-17 09:43:57 -0600129 select TEGRA_HSP
Stephen Warrenadf3abd2016-07-18 12:17:11 -0600130 select TEGRA_IVC
Stephen Warren03667eb2016-05-12 13:32:55 -0600131
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900132endchoice
133
Stephen Warren5a44ab42016-01-26 10:59:42 -0700134config TEGRA_DISCONNECT_UDC_ON_BOOT
135 bool "Disconnect USB device mode controller on boot"
136 default y
137 help
138 When loading U-Boot into RAM over USB protocols using tools such as
139 tegrarcm or L4T's exec-uboot.sh/tegraflash.py, Tegra's USB device
140 mode controller is initialized and enumerated by the host PC running
141 the tool. Unfortunately, these tools do not shut down the USB
142 controller before executing the downloaded code, and so the host PC
143 does not "de-enumerate" the USB device. This option shuts down the
144 USB controller when U-Boot boots to avoid leaving a stale USB device
145 present.
146
Simon Glass838723b2015-02-11 16:32:59 -0700147config SYS_MALLOC_F_LEN
148 default 0x1800
149
Masahiro Yamadaed1632a2015-02-20 17:04:04 +0900150source "arch/arm/mach-tegra/tegra20/Kconfig"
151source "arch/arm/mach-tegra/tegra30/Kconfig"
152source "arch/arm/mach-tegra/tegra114/Kconfig"
153source "arch/arm/mach-tegra/tegra124/Kconfig"
Tom Warrenab0cc6b2015-03-04 16:36:00 -0700154source "arch/arm/mach-tegra/tegra210/Kconfig"
Stephen Warren03667eb2016-05-12 13:32:55 -0600155source "arch/arm/mach-tegra/tegra186/Kconfig"
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900156
Simon Glassbd74b032017-05-17 03:25:11 -0600157config CMD_ENTERRCM
158 bool "Enable 'enterrcm' command"
159 default y
160 help
161 Tegra's boot ROM supports a mode whereby code may be downloaded and
162 flash-programmed over a USB connection. On dev boards, this is
163 typically entered by holding down a "force recovery" button and
164 resetting the CPU. However, not all boards have such a button (one
165 example is the Compulab Trimslice), so a method to enter RCM from
166 software is useful.
167
168 Even on boards other than Trimslice, controlling this over a UART
169 may be useful, e.g. to allow simple remote control without the need
170 for mechanical button actuators, or hooking up relays/... to the
171 button.
172
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900173endif