blob: 478c7a9e388a26397935eb0181ea1e66ec57090a [file] [log] [blame]
Trevor Woerner513f6402020-05-06 08:02:41 -04001if ARCH_TEGRA
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +09002
Simon Glass035939e2021-07-10 21:14:30 -06003config SPL_GPIO
Simon Glass0bdfc3e2016-09-12 23:18:39 -06004 default y
5
Simon Glassf2a89462016-09-12 23:18:41 -06006config SPL_LIBCOMMON_SUPPORT
7 default y
8
Simon Glassb16c92c2016-09-12 23:18:43 -06009config SPL_LIBGENERIC_SUPPORT
10 default y
11
Simon Glasse076d6f2016-09-12 23:18:56 -060012config SPL_SERIAL_SUPPORT
13 default y
14
Thierry Reding45ad0b02019-04-15 11:32:18 +020015config TEGRA_CLKRST
16 bool
17
Thierry Redingc3598a42019-04-15 11:32:19 +020018config TEGRA_GP_PADCTRL
19 bool
20
Stephen Warrenadf3abd2016-07-18 12:17:11 -060021config TEGRA_IVC
22 bool "Tegra IVC protocol"
23 help
24 IVC (Inter-VM Communication) protocol is a Tegra-specific IPC
25 (Inter Processor Communication) framework. Within the context of
26 U-Boot, it is typically used for communication between the main CPU
27 and various auxiliary processors.
28
Thierry Reding17987bb2019-04-15 11:32:20 +020029config TEGRA_MC
30 bool
31
Thierry Reding7c0b1502019-04-15 11:32:21 +020032config TEGRA_PINCTRL
33 bool
34
Thierry Reding8ffbcfc2019-04-15 11:32:22 +020035config TEGRA_PMC
36 bool
37
Thierry Redingce7eb162019-04-15 11:32:25 +020038config TEGRA_PMC_SECURE
39 bool
40 depends on TEGRA_PMC
41
Stephen Warren8c29e652015-11-23 10:32:01 -070042config TEGRA_COMMON
43 bool "Tegra common options"
Michal Simek84f3dec2018-07-23 15:55:13 +020044 select BOARD_EARLY_INIT_F
Stephen Warren905752c2016-09-13 10:46:00 -060045 select CLK
Tom Warren7b5002e2015-07-17 08:12:51 -070046 select DM
Simon Glassa403c9f2015-11-29 13:18:01 -070047 select DM_ETH
Tom Warren7b5002e2015-07-17 08:12:51 -070048 select DM_GPIO
Stephen Warren8c29e652015-11-23 10:32:01 -070049 select DM_I2C
Simon Glass01e99402015-10-18 21:17:16 -060050 select DM_KEYBOARD
Tom Warrena66f7722016-09-13 10:45:48 -060051 select DM_MMC
Simon Glassd8af3c92016-01-30 16:38:01 -070052 select DM_PWM
Stephen Warren905752c2016-09-13 10:46:00 -060053 select DM_RESET
Stephen Warren8c29e652015-11-23 10:32:01 -070054 select DM_SERIAL
55 select DM_SPI
56 select DM_SPI_FLASH
Stephen Warren905752c2016-09-13 10:46:00 -060057 select MISC
Stephen Warren8c29e652015-11-23 10:32:01 -070058 select OF_CONTROL
Michal Simek84f3dec2018-07-23 15:55:13 +020059 select SPI
Michal Simek2e7c8192018-07-23 15:55:14 +020060 imply CMD_DM
Daniel Thompsona9e2c672017-05-19 17:26:58 +010061 imply CRC32_VERIFY
Stephen Warren8c29e652015-11-23 10:32:01 -070062
Stephen Warren905752c2016-09-13 10:46:00 -060063config TEGRA_NO_BPMP
64 bool "Tegra common options for SoCs without BPMP"
65 select TEGRA_CAR
66 select TEGRA_CAR_CLOCK
67 select TEGRA_CAR_RESET
68
Stephen Warren8c29e652015-11-23 10:32:01 -070069config TEGRA_ARMV7_COMMON
70 bool "Tegra 32-bit common options"
Simon Glassa0c32762020-07-19 13:56:00 -060071 select BINMAN
Lokesh Vutla81b1a672018-04-26 18:21:26 +053072 select CPU_V7A
Stephen Warren8c29e652015-11-23 10:32:01 -070073 select SPL
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080074 select SPL_BOARD_INIT if SPL
Stephen Warren8c29e652015-11-23 10:32:01 -070075 select SUPPORT_SPL
Thierry Reding45ad0b02019-04-15 11:32:18 +020076 select TEGRA_CLKRST
Stephen Warren8c29e652015-11-23 10:32:01 -070077 select TEGRA_COMMON
Stephen Warrenaf974be2016-05-12 12:07:41 -060078 select TEGRA_GPIO
Thierry Redingc3598a42019-04-15 11:32:19 +020079 select TEGRA_GP_PADCTRL
Thierry Reding17987bb2019-04-15 11:32:20 +020080 select TEGRA_MC
Stephen Warren905752c2016-09-13 10:46:00 -060081 select TEGRA_NO_BPMP
Thierry Reding7c0b1502019-04-15 11:32:21 +020082 select TEGRA_PINCTRL
Thierry Reding8ffbcfc2019-04-15 11:32:22 +020083 select TEGRA_PMC
Stephen Warren8c29e652015-11-23 10:32:01 -070084
85config TEGRA_ARMV8_COMMON
86 bool "Tegra 64-bit common options"
87 select ARM64
Masahiro Yamadabf4645c2019-06-26 13:51:46 +090088 select INIT_SP_RELATIVE
Stephen Warreneab36052018-01-03 14:31:52 -070089 select LINUX_KERNEL_IMAGE_HEADER
Thierry Reding29ce1d02019-04-15 11:32:32 +020090 select POSITION_INDEPENDENT
Stephen Warren8c29e652015-11-23 10:32:01 -070091 select TEGRA_COMMON
Tom Warren7b5002e2015-07-17 08:12:51 -070092
Stephen Warreneab36052018-01-03 14:31:52 -070093if TEGRA_ARMV8_COMMON
94config LNX_KRNL_IMG_TEXT_OFFSET_BASE
95 default 0x80000000
96endif
97
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +090098choice
99 prompt "Tegra SoC select"
Joe Hershbergerf0699602015-05-12 14:46:23 -0500100 optional
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900101
102config TEGRA20
103 bool "Tegra20 family"
Tom Rinibacb52c2017-03-07 07:13:42 -0500104 select ARM_ERRATA_716044
105 select ARM_ERRATA_742230
106 select ARM_ERRATA_751472
Tom Warren7b5002e2015-07-17 08:12:51 -0700107 select TEGRA_ARMV7_COMMON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900108
109config TEGRA30
110 bool "Tegra30 family"
Tom Rinibacb52c2017-03-07 07:13:42 -0500111 select ARM_ERRATA_743622
112 select ARM_ERRATA_751472
Tom Warren7b5002e2015-07-17 08:12:51 -0700113 select TEGRA_ARMV7_COMMON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900114
115config TEGRA114
116 bool "Tegra114 family"
Tom Warren7b5002e2015-07-17 08:12:51 -0700117 select TEGRA_ARMV7_COMMON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900118
119config TEGRA124
120 bool "Tegra124 family"
Tom Warren7b5002e2015-07-17 08:12:51 -0700121 select TEGRA_ARMV7_COMMON
Simon Glass0662cf22017-07-25 08:29:58 -0600122 imply REGMAP
123 imply SYSCON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900124
Tom Warrenab0cc6b2015-03-04 16:36:00 -0700125config TEGRA210
126 bool "Tegra210 family"
Stephen Warren8c29e652015-11-23 10:32:01 -0700127 select TEGRA_ARMV8_COMMON
Thierry Reding45ad0b02019-04-15 11:32:18 +0200128 select TEGRA_CLKRST
Michal Simek84f3dec2018-07-23 15:55:13 +0200129 select TEGRA_GPIO
Thierry Redingc3598a42019-04-15 11:32:19 +0200130 select TEGRA_GP_PADCTRL
Thierry Reding17987bb2019-04-15 11:32:20 +0200131 select TEGRA_MC
Stephen Warren905752c2016-09-13 10:46:00 -0600132 select TEGRA_NO_BPMP
Thierry Reding7c0b1502019-04-15 11:32:21 +0200133 select TEGRA_PINCTRL
Thierry Reding8ffbcfc2019-04-15 11:32:22 +0200134 select TEGRA_PMC
Thierry Redingce7eb162019-04-15 11:32:25 +0200135 select TEGRA_PMC_SECURE
Tom Warrenab0cc6b2015-03-04 16:36:00 -0700136
Stephen Warren03667eb2016-05-12 13:32:55 -0600137config TEGRA186
138 bool "Tegra186 family"
Stephen Warrene0e2b262016-06-17 09:43:57 -0600139 select DM_MAILBOX
Stephen Warrena2148922016-08-08 09:41:34 -0600140 select TEGRA186_BPMP
Stephen Warrene8e3f202016-08-08 11:28:24 -0600141 select TEGRA186_CLOCK
Stephen Warren03667eb2016-05-12 13:32:55 -0600142 select TEGRA186_GPIO
Stephen Warrenfccc9c52016-08-08 11:28:25 -0600143 select TEGRA186_RESET
Stephen Warren03667eb2016-05-12 13:32:55 -0600144 select TEGRA_ARMV8_COMMON
Stephen Warrene0e2b262016-06-17 09:43:57 -0600145 select TEGRA_HSP
Stephen Warrenadf3abd2016-07-18 12:17:11 -0600146 select TEGRA_IVC
Stephen Warren03667eb2016-05-12 13:32:55 -0600147
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900148endchoice
149
Stephen Warren5a44ab42016-01-26 10:59:42 -0700150config TEGRA_DISCONNECT_UDC_ON_BOOT
151 bool "Disconnect USB device mode controller on boot"
Thierry Reding4e9260c2019-04-15 11:32:26 +0200152 depends on CI_UDC
Stephen Warren5a44ab42016-01-26 10:59:42 -0700153 default y
154 help
155 When loading U-Boot into RAM over USB protocols using tools such as
156 tegrarcm or L4T's exec-uboot.sh/tegraflash.py, Tegra's USB device
157 mode controller is initialized and enumerated by the host PC running
158 the tool. Unfortunately, these tools do not shut down the USB
159 controller before executing the downloaded code, and so the host PC
160 does not "de-enumerate" the USB device. This option shuts down the
161 USB controller when U-Boot boots to avoid leaving a stale USB device
162 present.
163
Simon Glass838723b2015-02-11 16:32:59 -0700164config SYS_MALLOC_F_LEN
165 default 0x1800
166
Masahiro Yamadaed1632a2015-02-20 17:04:04 +0900167source "arch/arm/mach-tegra/tegra20/Kconfig"
168source "arch/arm/mach-tegra/tegra30/Kconfig"
169source "arch/arm/mach-tegra/tegra114/Kconfig"
170source "arch/arm/mach-tegra/tegra124/Kconfig"
Tom Warrenab0cc6b2015-03-04 16:36:00 -0700171source "arch/arm/mach-tegra/tegra210/Kconfig"
Stephen Warren03667eb2016-05-12 13:32:55 -0600172source "arch/arm/mach-tegra/tegra186/Kconfig"
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900173
Simon Glassbd74b032017-05-17 03:25:11 -0600174config CMD_ENTERRCM
175 bool "Enable 'enterrcm' command"
176 default y
177 help
178 Tegra's boot ROM supports a mode whereby code may be downloaded and
179 flash-programmed over a USB connection. On dev boards, this is
180 typically entered by holding down a "force recovery" button and
181 resetting the CPU. However, not all boards have such a button (one
182 example is the Compulab Trimslice), so a method to enter RCM from
183 software is useful.
184
185 Even on boards other than Trimslice, controlling this over a UART
186 may be useful, e.g. to allow simple remote control without the need
187 for mechanical button actuators, or hooking up relays/... to the
188 button.
189
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900190endif