blob: 7026c73bc69810135e9796f0c57b2e9e7a17059a [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Eddie James1a55a7a2023-10-24 10:43:51 -050012#include <config.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010013#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010015#include <dt-bindings/input/input.h>
Heiko Schocher350d2522025-01-28 14:52:46 +010016#include <dt-bindings/leds/common.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040017#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053018#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010019
Simon Glassb2c1cac2014-02-26 15:59:21 -070020/ {
21 model = "sandbox";
22 compatible = "sandbox";
23 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060024 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070025
Simon Glassfef72b72014-07-23 06:55:03 -060026 aliases {
27 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010028 ethernet0 = "/eth@10002000";
29 ethernet2 = &swp_0;
30 ethernet3 = &eth_3;
31 ethernet4 = &dsa_eth0;
32 ethernet5 = &eth_5;
Sean Anderson67d93a42022-05-05 13:11:30 -040033 ethernet6 = "/eth@10004000";
34 ethernet7 = &swp_1;
35 ethernet8 = &phy_eth0;
Simon Glass5620cf82018-10-01 12:22:40 -060036 gpio1 = &gpio_a;
37 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010038 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070039 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060040 mmc0 = "/mmc0";
41 mmc1 = "/mmc1";
Simon Glassf1eba352022-10-20 18:23:20 -060042 mmc2 = "/mmc2";
43 mmc3 = "/mmc3";
Simon Glassfff928c2023-08-24 13:55:41 -060044 mmc4 = "/mmc4";
45 mmc5 = "/mmc5";
Alexander Gendin038cb022023-10-09 01:24:36 +000046 mmc6 = "/mmc6";
Mattijs Korpershoekd77f8152024-07-10 10:40:06 +020047 mmc7 = "/mmc7";
Guillaume La Roque368ad9e2024-11-26 09:06:13 +010048 mmc8 = "/mmc8";
Bin Meng408e5902018-08-03 01:14:41 -070049 pci0 = &pci0;
50 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070051 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020052 remoteproc0 = &rproc_1;
53 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060054 rtc0 = &rtc_0;
55 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060056 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020057 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070058 testbus3 = "/some-bus";
59 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070060 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070061 testfdt3 = "/b-test";
62 testfdt5 = "/some-bus/c-test@5";
63 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070064 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020065 fdt-dummy0 = "/translation-test@8000/dev@0,0";
66 fdt-dummy1 = "/translation-test@8000/dev@1,100";
67 fdt-dummy2 = "/translation-test@8000/dev@2,200";
68 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060069 usb0 = &usb_0;
70 usb1 = &usb_1;
71 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020072 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020073 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060074 };
75
Eddie James1a55a7a2023-10-24 10:43:51 -050076 reserved-memory {
77 #address-cells = <1>;
78 #size-cells = <1>;
79 ranges;
80
81 event_log: tcg_event_log {
82 no-map;
Sughosh Ganu3f768682024-08-26 17:29:32 +053083 reg = <(CFG_SYS_SDRAM_BASE + 0x100000) 0x2000>;
Eddie James1a55a7a2023-10-24 10:43:51 -050084 };
85 };
86
Simon Glass5e135d32022-10-20 18:23:15 -060087 binman: binman {
Philippe Reynes462d1632022-03-28 22:56:53 +020088 };
89
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020090 config {
Simon Glass0034d962021-08-07 07:24:01 -060091 testing-bool;
92 testing-int = <123>;
93 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020094 environment {
95 from_fdt = "yes";
96 fdt_env_path = "";
97 };
98 };
99
Michal Simek43c42bd2023-08-31 08:59:05 +0200100 options {
101 u-boot {
102 compatible = "u-boot,config";
103 bootscr-ram-offset = /bits/ 64 <0x12345678>;
Michal Simek6a7c1ce2023-08-31 09:04:27 +0200104 bootscr-flash-offset = /bits/ 64 <0>;
105 bootscr-flash-size = /bits/ 64 <0x2000>;
Christian Marangifd53ad42024-11-10 12:50:27 +0100106 boot-led = <&sandbox_led_green>;
107 activity-led = <&sandbox_led_red>;
Christian Marangicdc38152024-10-01 14:24:44 +0200108 testing-bool;
109 testing-int = <123>;
110 testing-str = "testing";
Christian Marangi81ce47e2024-11-10 12:50:25 +0100111 testing-phandle = <&phandle_node_1>;
Michal Simek43c42bd2023-08-31 08:59:05 +0200112 };
113 };
114
Simon Glassb255efc2022-04-24 23:31:24 -0600115 bootstd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700116 bootph-verify;
Simon Glassb255efc2022-04-24 23:31:24 -0600117 compatible = "u-boot,boot-std";
118
119 filename-prefixes = "/", "/boot/";
120 bootdev-order = "mmc2", "mmc1";
121
Simon Glassb71d7f72023-05-10 16:34:46 -0600122 extlinux {
123 compatible = "u-boot,extlinux";
Simon Glassb255efc2022-04-24 23:31:24 -0600124 };
125
126 efi {
127 compatible = "u-boot,distro-efi";
128 };
Simon Glassa9289612022-10-20 18:23:14 -0600129
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600130 theme {
131 font-size = <30>;
Simon Glass86f1ac52023-06-01 10:23:00 -0600132 menu-inset = <3>;
133 menuitem-gap-y = <1>;
Simon Glass65d3cc42025-04-02 06:29:34 +1300134 white-on-black;
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600135 };
136
Simon Glass82adc292023-08-14 16:40:30 -0600137 cedit-theme {
138 font-size = <30>;
139 menu-inset = <3>;
140 menuitem-gap-y = <1>;
141 };
142
Simon Glassf1eba352022-10-20 18:23:20 -0600143 /*
144 * This is used for the VBE OS-request tests. A FAT filesystem
145 * created in a partition with the VBE information appearing
Michal Simek33224372023-09-07 14:55:48 +0200146 * before the partition starts
Simon Glassf1eba352022-10-20 18:23:20 -0600147 */
Simon Glassa9289612022-10-20 18:23:14 -0600148 firmware0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700149 bootph-verify;
Simon Glassa9289612022-10-20 18:23:14 -0600150 compatible = "fwupd,vbe-simple";
151 storage = "mmc1";
152 skip-offset = <0x200>;
153 area-start = <0x400>;
154 area-size = <0x1000>;
155 state-offset = <0x400>;
156 state-size = <0x40>;
157 version-offset = <0x800>;
158 version-size = <0x100>;
159 };
Simon Glassf1eba352022-10-20 18:23:20 -0600160
161 /*
162 * This is used for the VBE VPL tests. The MMC device holds the
163 * binman image.bin file. The test progresses through each phase
164 * of U-Boot, loading each in turn from MMC.
165 *
166 * Note that the test enables this node (and mmc3) before
167 * running U-Boot
168 */
169 firmware1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700170 bootph-verify;
Simon Glassf1eba352022-10-20 18:23:20 -0600171 status = "disabled";
172 compatible = "fwupd,vbe-simple";
173 storage = "mmc3";
Simon Glass9bb73e32023-04-02 14:01:24 +1200174 skip-offset = <0x800000>;
Simon Glassf1eba352022-10-20 18:23:20 -0600175 area-start = <0>;
176 area-size = <0xe00000>;
177 state-offset = <0xdffc00>;
178 state-size = <0x40>;
179 version-offset = <0xdffe00>;
180 version-size = <0x100>;
181 };
Simon Glassb255efc2022-04-24 23:31:24 -0600182 };
183
Simon Glass61300722023-06-01 10:23:01 -0600184 cedit: cedit {
185 };
186
Andrew Scull451b8b12022-05-30 10:00:12 +0000187 fuzzing-engine {
188 compatible = "sandbox,fuzzing-engine";
189 };
190
Nandor Han6521e5d2021-06-10 16:56:44 +0300191 reboot-mode0 {
192 compatible = "reboot-mode-gpio";
193 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
194 u-boot,env-variable = "bootstatus";
195 mode-test = <0x01>;
196 mode-download = <0x03>;
197 };
198
Nandor Han7e4067a2021-06-10 16:56:45 +0300199 reboot_mode1: reboot-mode@14 {
200 compatible = "reboot-mode-rtc";
201 rtc = <&rtc_0>;
202 reg = <0x30 4>;
203 u-boot,env-variable = "bootstatus";
204 big-endian;
205 mode-test = <0x21969147>;
206 mode-download = <0x51939147>;
207 };
208
Simon Glassed96cde2018-12-10 10:37:33 -0700209 audio: audio-codec {
210 compatible = "sandbox,audio-codec";
211 #sound-dai-cells = <1>;
212 };
213
Philippe Reynes1ee26482020-07-24 18:19:51 +0200214 buttons {
215 compatible = "gpio-keys";
216
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200217 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200218 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200219 label = "button1";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300220 linux,code = <BTN_1>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200221 };
222
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200223 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200224 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200225 label = "button2";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300226 linux,code = <BTN_2>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200227 };
228 };
229
Marek Szyprowskiad398592021-02-18 11:33:18 +0100230 buttons2 {
231 compatible = "adc-keys";
232 io-channels = <&adc 3>;
233 keyup-threshold-microvolt = <3000000>;
234
235 button-up {
236 label = "button3";
237 linux,code = <KEY_F3>;
238 press-threshold-microvolt = <1500000>;
239 };
240
241 button-down {
242 label = "button4";
243 linux,code = <KEY_F4>;
244 press-threshold-microvolt = <1000000>;
245 };
246
247 button-enter {
248 label = "button5";
249 linux,code = <KEY_F5>;
250 press-threshold-microvolt = <500000>;
251 };
252 };
253
Simon Glassc953aaf2018-12-10 10:37:34 -0700254 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600255 reg = <0 0>;
256 compatible = "google,cros-ec-sandbox";
257
258 /*
259 * This describes the flash memory within the EC. Note
260 * that the STM32L flash erases to 0, not 0xff.
261 */
262 flash {
263 image-pos = <0x08000000>;
264 size = <0x20000>;
265 erase-value = <0>;
266
267 /* Information for sandbox */
268 ro {
269 image-pos = <0>;
270 size = <0xf000>;
271 };
272 wp-ro {
273 image-pos = <0xf000>;
274 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700275 used = <0x884>;
276 compress = "lz4";
277 uncomp-size = <0xcf8>;
278 hash {
279 algo = "sha256";
280 value = [00 01 02 03 04 05 06 07
281 08 09 0a 0b 0c 0d 0e 0f
282 10 11 12 13 14 15 16 17
283 18 19 1a 1b 1c 1d 1e 1f];
284 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600285 };
286 rw {
287 image-pos = <0x10000>;
288 size = <0x10000>;
289 };
290 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300291
292 cros_ec_pwm: cros-ec-pwm {
293 compatible = "google,cros-ec-pwm";
294 #pwm-cells = <1>;
295 };
296
Simon Glass699c9ca2018-10-01 12:22:08 -0600297 };
298
Yannick Fertré9712c822019-10-07 15:29:05 +0200299 dsi_host: dsi_host {
300 compatible = "sandbox,dsi-host";
301 };
302
Christian Marangia1a1e0e2024-11-10 12:50:23 +0100303 phandle_node_1: phandle-node-1 {
304 };
305
306 phandle_node_2: phandle-node-2 {
307 };
308
Simon Glassb2c1cac2014-02-26 15:59:21 -0700309 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600310 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700311 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600312 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700313 ping-add = <0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700314 bootph-all;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100315 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
316 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700317 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100318 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
319 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
320 <&gpio_b 7 GPIO_IN 3 2 1>,
321 <&gpio_b 8 GPIO_OUT 3 2 1>,
322 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100323 test3-gpios =
324 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
325 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
326 <&gpio_c 2 GPIO_OUT>,
327 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
328 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200329 <&gpio_c 5 GPIO_IN>,
330 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
331 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530332 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
333 test5-gpios = <&gpio_a 19>;
334
Simon Glass73025392021-10-23 17:26:04 -0600335 bool-value;
Stefan Herbrechtsmeier1b090e62022-06-14 15:21:30 +0200336 int8-value = /bits/ 8 <0x12>;
337 int16-value = /bits/ 16 <0x1234>;
Simon Glass6df01f92018-12-10 10:37:37 -0700338 int-value = <1234>;
339 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200340 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200341 int-array = <5678 9123 4567>;
Michal Simek08a194e2023-08-25 11:37:46 +0200342 int64-array = /bits/ 64 <0x1111222233334444 0x4444333322221111>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600343 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700344 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600345 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200346 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Christian Marangia1a1e0e2024-11-10 12:50:23 +0100347 phandle-nodes = <&phandle_node_1>, <&phandle_node_2>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530348
349 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
350 <&muxcontroller0 2>, <&muxcontroller0 3>,
351 <&muxcontroller1>;
352 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
353 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100354 display-timings {
355 timing0: 240x320 {
356 clock-frequency = <6500000>;
357 hactive = <240>;
358 vactive = <320>;
359 hfront-porch = <6>;
360 hback-porch = <7>;
361 hsync-len = <1>;
362 vback-porch = <5>;
363 vfront-porch = <8>;
364 vsync-len = <2>;
365 hsync-active = <1>;
366 vsync-active = <0>;
367 de-active = <1>;
368 pixelclk-active = <1>;
369 interlaced;
370 doublescan;
371 doubleclk;
372 };
373 timing1: 480x800 {
374 clock-frequency = <9000000>;
375 hactive = <480>;
376 vactive = <800>;
377 hfront-porch = <10>;
378 hback-porch = <59>;
379 hsync-len = <12>;
380 vback-porch = <15>;
381 vfront-porch = <17>;
382 vsync-len = <16>;
383 hsync-active = <0>;
384 vsync-active = <1>;
385 de-active = <0>;
386 pixelclk-active = <0>;
387 };
388 timing2: 800x480 {
389 clock-frequency = <33500000>;
390 hactive = <800>;
391 vactive = <480>;
392 hback-porch = <89>;
393 hfront-porch = <164>;
394 vback-porch = <23>;
395 vfront-porch = <10>;
396 hsync-len = <11>;
397 vsync-len = <13>;
398 };
399 };
Raphael Gallais-Poua853b922023-05-11 16:36:52 +0200400 panel-timing {
Nikhil M Jainbb9d1312023-01-31 15:35:15 +0530401 clock-frequency = <6500000>;
402 hactive = <240>;
403 vactive = <320>;
404 hfront-porch = <6>;
405 hback-porch = <7>;
406 hsync-len = <1>;
407 vback-porch = <5>;
408 vfront-porch = <8>;
409 vsync-len = <2>;
410 hsync-active = <1>;
411 vsync-active = <0>;
412 de-active = <1>;
413 pixelclk-active = <1>;
414 interlaced;
415 doublescan;
416 doubleclk;
417 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700418 };
419
420 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600421 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700422 compatible = "not,compatible";
423 };
424
425 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600426 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700427 };
428
Simon Glass5620cf82018-10-01 12:22:40 -0600429 backlight: backlight {
430 compatible = "pwm-backlight";
431 enable-gpios = <&gpio_a 1>;
432 power-supply = <&ldo_1>;
433 pwms = <&pwm 0 1000>;
434 default-brightness-level = <5>;
435 brightness-levels = <0 16 32 64 128 170 202 234 255>;
436 };
437
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200438 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200439 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200440 bind-test-child1 {
441 compatible = "sandbox,phy";
442 #phy-cells = <1>;
443 };
444
445 bind-test-child2 {
446 compatible = "simple-bus";
447 };
448 };
449
Simon Glassb2c1cac2014-02-26 15:59:21 -0700450 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600451 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700452 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600453 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700454 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530455
456 mux-controls = <&muxcontroller0 0>;
457 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700458 };
459
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200460 phy_provider0: gen_phy@0 {
461 compatible = "sandbox,phy";
462 #phy-cells = <1>;
463 };
464
465 phy_provider1: gen_phy@1 {
466 compatible = "sandbox,phy";
467 #phy-cells = <0>;
468 broken;
469 };
470
developer71092972020-05-02 11:35:12 +0200471 phy_provider2: gen_phy@2 {
472 compatible = "sandbox,phy";
473 #phy-cells = <0>;
474 };
475
Jonas Karlman9f89e682023-08-31 22:16:35 +0000476 phy_provider3: gen_phy@3 {
477 compatible = "sandbox,phy";
478 #phy-cells = <2>;
479 };
480
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200481 gen_phy_user: gen_phy_user {
482 compatible = "simple-bus";
483 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
484 phy-names = "phy1", "phy2", "phy3";
485 };
486
developer71092972020-05-02 11:35:12 +0200487 gen_phy_user1: gen_phy_user1 {
488 compatible = "simple-bus";
489 phys = <&phy_provider0 0>, <&phy_provider2>;
490 phy-names = "phy1", "phy2";
491 };
492
Jonas Karlman9f89e682023-08-31 22:16:35 +0000493 gen_phy_user2: gen_phy_user2 {
494 compatible = "simple-bus";
495 phys = <&phy_provider3 0 0>;
496 phy-names = "phy1";
497 };
498
Simon Glassb2c1cac2014-02-26 15:59:21 -0700499 some-bus {
500 #address-cells = <1>;
501 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600502 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600503 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600504 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700505 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600506 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700507 compatible = "denx,u-boot-fdt-test";
508 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600509 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700510 ping-add = <5>;
511 };
Simon Glass40717422014-07-23 06:55:18 -0600512 c-test@0 {
513 compatible = "denx,u-boot-fdt-test";
514 reg = <0>;
515 ping-expect = <6>;
516 ping-add = <6>;
517 };
518 c-test@1 {
519 compatible = "denx,u-boot-fdt-test";
520 reg = <1>;
521 ping-expect = <7>;
522 ping-add = <7>;
523 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700524 };
525
526 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600527 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600528 ping-expect = <6>;
529 ping-add = <6>;
530 compatible = "google,another-fdt-test";
531 };
532
533 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600534 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600535 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700536 ping-add = <6>;
537 compatible = "google,another-fdt-test";
538 };
539
Simon Glass0ccb0972015-01-25 08:27:05 -0700540 f-test {
Patrick Rudolph0fe88cc2024-10-23 15:20:05 +0200541 #interrupt-cells = <2>;
542 interrupt-parent = <&irq>;
543 interrupts = <4 0>;
Simon Glass0ccb0972015-01-25 08:27:05 -0700544 compatible = "denx,u-boot-fdt-test";
545 };
546
547 g-test {
548 compatible = "denx,u-boot-fdt-test";
549 };
550
Bin Mengd9d24782018-10-10 22:07:01 -0700551 h-test {
552 compatible = "denx,u-boot-fdt-test1";
553 };
554
developercf8bc132020-05-02 11:35:10 +0200555 i-test {
556 compatible = "mediatek,u-boot-fdt-test";
557 #address-cells = <1>;
558 #size-cells = <0>;
559
560 subnode@0 {
561 reg = <0>;
562 };
563
564 subnode@1 {
565 reg = <1>;
566 };
567
568 subnode@2 {
569 reg = <2>;
570 };
571 };
572
Simon Glass204675c2019-12-29 21:19:25 -0700573 devres-test {
574 compatible = "denx,u-boot-devres-test";
575 };
576
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530577 another-test {
578 reg = <0 2>;
579 compatible = "denx,u-boot-fdt-test";
580 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
581 test5-gpios = <&gpio_a 19>;
582 };
583
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100584 mmio-bus@0 {
585 #address-cells = <1>;
586 #size-cells = <1>;
587 compatible = "denx,u-boot-test-bus";
588 dma-ranges = <0x10000000 0x00000000 0x00040000>;
589
590 subnode@0 {
591 compatible = "denx,u-boot-fdt-test";
592 };
593 };
594
595 mmio-bus@1 {
596 #address-cells = <1>;
597 #size-cells = <1>;
598 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100599
600 subnode@0 {
601 compatible = "denx,u-boot-fdt-test";
602 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100603 };
604
Simon Glass3c601b12020-07-07 13:12:06 -0600605 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600606 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600607 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600608 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600609 child {
610 compatible = "denx,u-boot-acpi-test";
611 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600612 };
613
Simon Glass3c601b12020-07-07 13:12:06 -0600614 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600615 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600616 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600617 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600618 };
619
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200620 clocks {
621 clk_fixed: clk-fixed {
622 compatible = "fixed-clock";
623 #clock-cells = <0>;
624 clock-frequency = <1234>;
625 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000626
627 clk_fixed_factor: clk-fixed-factor {
628 compatible = "fixed-factor-clock";
629 #clock-cells = <0>;
630 clock-div = <3>;
631 clock-mult = <2>;
632 clocks = <&clk_fixed>;
633 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200634
635 osc {
636 compatible = "fixed-clock";
637 #clock-cells = <0>;
638 clock-frequency = <20000000>;
639 };
Stephen Warrena9622432016-06-17 09:44:00 -0600640 };
641
642 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600643 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600644 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200645 assigned-clocks = <&clk_sandbox 3>;
646 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600647 };
648
649 clk-test {
650 compatible = "sandbox,clk-test";
651 clocks = <&clk_fixed>,
652 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200653 <&clk_sandbox 0>,
Yang Xiwene89289c2023-12-16 02:28:52 +0800654 <&ccf 11>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200655 <&clk_sandbox 3>,
656 <&clk_sandbox 2>;
Yang Xiwene89289c2023-12-16 02:28:52 +0800657 clock-names = "fixed", "i2c", "spi", "i2c_root", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600658 };
659
Ashok Reddy Soma8f03cef2023-08-30 10:31:42 +0200660 clk-test2 {
661 compatible = "sandbox,clk-test";
662 assigned-clock-rates = <321>;
663 };
664
665 clk-test3 {
666 compatible = "sandbox,clk-test";
667 assigned-clocks = <&clk_sandbox 1>;
668 };
669
670 clk-test4 {
671 compatible = "sandbox,clk-test";
672 assigned-clock-rates = <654>, <321>;
673 assigned-clocks = <&clk_sandbox 1>;
674 };
675
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200676 ccf: clk-ccf {
677 compatible = "sandbox,clk-ccf";
Yang Xiwene89289c2023-12-16 02:28:52 +0800678 #clock-cells = <1>;
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200679 };
680
Simon Glass507ab962021-12-04 08:56:31 -0700681 efi-media {
682 compatible = "sandbox,efi-media";
683 };
684
Simon Glass5b968632015-05-22 15:42:15 -0600685 eth@10002000 {
686 compatible = "sandbox,eth";
687 reg = <0x10002000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600688 };
689
690 eth_5: eth@10003000 {
691 compatible = "sandbox,eth";
692 reg = <0x10003000 0x1000>;
Sean Anderson13652b82022-05-05 13:11:44 -0400693 nvmem-cells = <&eth5_addr>;
694 nvmem-cell-names = "mac-address";
Simon Glass5b968632015-05-22 15:42:15 -0600695 };
696
Bin Meng04a11cb2015-08-27 22:25:53 -0700697 eth_3: sbe5 {
698 compatible = "sandbox,eth";
699 reg = <0x10005000 0x1000>;
Sean Andersone2dc0e62022-05-05 13:11:42 -0400700 nvmem-cells = <&eth3_addr>;
701 nvmem-cell-names = "mac-address";
Bin Meng04a11cb2015-08-27 22:25:53 -0700702 };
703
Simon Glass5b968632015-05-22 15:42:15 -0600704 eth@10004000 {
705 compatible = "sandbox,eth";
706 reg = <0x10004000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600707 };
708
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200709 phy_eth0: phy-test-eth {
710 compatible = "sandbox,eth";
711 reg = <0x10007000 0x1000>;
Sean Anderson24b1b8d2022-05-05 13:11:35 -0400712 mac-address = [ 02 00 11 22 33 49 ];
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200713 phy-handle = <&ethphy1>;
Marek Behúnbc194772022-04-07 00:33:01 +0200714 phy-mode = "2500base-x";
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200715 };
716
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800717 dsa_eth0: dsa-test-eth {
718 compatible = "sandbox,eth";
719 reg = <0x10006000 0x1000>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400720 nvmem-cells = <&eth4_addr>;
721 nvmem-cell-names = "mac-address";
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800722 };
723
724 dsa-test {
725 compatible = "sandbox,dsa";
726
727 ports {
728 #address-cells = <1>;
729 #size-cells = <0>;
730 swp_0: port@0 {
731 reg = <0>;
732 label = "lan0";
733 phy-mode = "rgmii-rxid";
734
735 fixed-link {
736 speed = <100>;
737 full-duplex;
738 };
739 };
740
741 swp_1: port@1 {
742 reg = <1>;
743 label = "lan1";
744 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800745 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800746 };
747
748 port@2 {
749 reg = <2>;
750 ethernet = <&dsa_eth0>;
751
752 fixed-link {
753 speed = <1000>;
754 full-duplex;
755 };
756 };
757 };
758 };
759
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700760 firmware {
761 sandbox_firmware: sandbox-firmware {
762 compatible = "sandbox,firmware";
763 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200764
Etienne Carriere09665cb2022-02-21 09:22:39 +0100765 scmi {
Etienne Carriere02fd1262020-09-09 18:44:00 +0200766 compatible = "sandbox,scmi-agent";
767 #address-cells = <1>;
768 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200769
AKASHI Takahiro535a7bd2023-10-16 14:39:45 +0900770 pwrdom_scmi: protocol@11 {
771 reg = <0x11>;
772 #power-domain-cells = <1>;
773 };
774
Etienne Carriere09665cb2022-02-21 09:22:39 +0100775 clk_scmi: protocol@14 {
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200776 reg = <0x14>;
777 #clock-cells = <1>;
AKASHI Takahirocc4ecda2023-10-11 19:06:59 +0900778 linaro,sandbox-channel-id = <0x14>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200779 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200780
Etienne Carriere09665cb2022-02-21 09:22:39 +0100781 reset_scmi: protocol@16 {
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200782 reg = <0x16>;
783 #reset-cells = <1>;
784 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100785
786 protocol@17 {
787 reg = <0x17>;
788
789 regulators {
790 #address-cells = <1>;
791 #size-cells = <0>;
792
Etienne Carriere09665cb2022-02-21 09:22:39 +0100793 regul0_scmi: reg@0 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100794 reg = <0>;
795 regulator-name = "sandbox-voltd0";
796 regulator-min-microvolt = <1100000>;
797 regulator-max-microvolt = <3300000>;
798 };
Etienne Carriere09665cb2022-02-21 09:22:39 +0100799 regul1_scmi: reg@1 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100800 reg = <0x1>;
801 regulator-name = "sandbox-voltd1";
802 regulator-min-microvolt = <1800000>;
803 };
804 };
805 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200806 };
Alexey Romanov9dc617d2023-09-21 11:13:36 +0300807
808 sm: secure-monitor {
809 compatible = "sandbox,sm";
810 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700811 };
812
Alexander Dahl6ac319d2022-09-30 14:04:30 +0200813 fpga {
814 compatible = "sandbox,fpga";
815 };
816
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100817 pinctrl-gpio {
818 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700819
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100820 gpio_a: base-gpios {
821 compatible = "sandbox,gpio";
822 gpio-controller;
823 #gpio-cells = <1>;
824 gpio-bank-name = "a";
Heiko Schocher350d2522025-01-28 14:52:46 +0100825 sandbox,gpio-count = <25>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200826 hog_input_active_low {
827 gpio-hog;
828 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200829 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200830 };
831 hog_input_active_high {
832 gpio-hog;
833 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200834 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200835 };
836 hog_output_low {
837 gpio-hog;
838 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200839 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200840 };
841 hog_output_high {
842 gpio-hog;
843 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200844 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200845 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100846 };
847
848 gpio_b: extra-gpios {
849 compatible = "sandbox,gpio";
850 gpio-controller;
851 #gpio-cells = <5>;
852 gpio-bank-name = "b";
853 sandbox,gpio-count = <10>;
854 };
Simon Glass25348a42014-10-13 23:42:11 -0600855
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100856 gpio_c: pinmux-gpios {
857 compatible = "sandbox,gpio";
858 gpio-controller;
859 #gpio-cells = <2>;
860 gpio-bank-name = "c";
861 sandbox,gpio-count = <10>;
862 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100863 };
864
Simon Glass7df766e2014-12-10 08:55:55 -0700865 i2c@0 {
866 #address-cells = <1>;
867 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600868 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700869 compatible = "sandbox,i2c";
870 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200871 pinctrl-names = "default";
872 pinctrl-0 = <&pinmux_i2c0_pins>;
873
Simon Glass7df766e2014-12-10 08:55:55 -0700874 eeprom@2c {
Sean Andersone2dc0e62022-05-05 13:11:42 -0400875 #address-cells = <1>;
876 #size-cells = <1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700877 reg = <0x2c>;
878 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700879 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200880 partitions {
881 compatible = "fixed-partitions";
882 #address-cells = <1>;
883 #size-cells = <1>;
884 bootcount_i2c: bootcount@10 {
885 reg = <10 2>;
886 };
887 };
Sean Andersone2dc0e62022-05-05 13:11:42 -0400888
889 eth3_addr: mac-address@24 {
890 reg = <24 6>;
891 };
Simon Glass7df766e2014-12-10 08:55:55 -0700892 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200893
Simon Glass336b2952015-05-22 15:42:17 -0600894 rtc_0: rtc@43 {
Sean Anderson5768e8b2022-05-05 13:11:43 -0400895 #address-cells = <1>;
896 #size-cells = <1>;
Simon Glass336b2952015-05-22 15:42:17 -0600897 reg = <0x43>;
898 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700899 sandbox,emul = <&emul0>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400900
901 eth4_addr: mac-address@40 {
902 reg = <0x40 6>;
903 };
Simon Glass336b2952015-05-22 15:42:17 -0600904 };
905
906 rtc_1: rtc@61 {
907 reg = <0x61>;
908 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700909 sandbox,emul = <&emul1>;
910 };
911
912 i2c_emul: emul {
913 reg = <0xff>;
914 compatible = "sandbox,i2c-emul-parent";
915 emul_eeprom: emul-eeprom {
916 compatible = "sandbox,i2c-eeprom";
917 sandbox,filename = "i2c.bin";
918 sandbox,size = <256>;
919 };
920 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700921 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700922 };
923 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700924 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600925 };
926 };
927
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200928 sandbox_pmic: sandbox_pmic {
929 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700930 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200931 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200932
933 mc34708: pmic@41 {
934 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700935 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200936 };
Simon Glass7df766e2014-12-10 08:55:55 -0700937 };
938
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100939 bootcount@0 {
940 compatible = "u-boot,bootcount-rtc";
941 rtc = <&rtc_1>;
942 offset = <0x13>;
943 };
944
Michal Simek4f18f922020-05-28 11:48:55 +0200945 bootcount {
946 compatible = "u-boot,bootcount-i2c-eeprom";
947 i2c-eeprom = <&bootcount_i2c>;
948 };
949
Nandor Han88895812021-06-10 15:40:38 +0300950 bootcount_4@0 {
951 compatible = "u-boot,bootcount-syscon";
952 syscon = <&syscon0>;
953 reg = <0x0 0x04>, <0x0 0x04>;
954 reg-names = "syscon_reg", "offset";
955 };
956
957 bootcount_2@0 {
958 compatible = "u-boot,bootcount-syscon";
959 syscon = <&syscon0>;
960 reg = <0x0 0x04>, <0x0 0x02> ;
961 reg-names = "syscon_reg", "offset";
962 };
963
Marek Szyprowskiad398592021-02-18 11:33:18 +0100964 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100965 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100966 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100967 vdd-supply = <&buck2>;
968 vss-microvolts = <0>;
969 };
970
Mark Kettenis67748ee2021-10-23 16:58:02 +0200971 iommu: iommu@0 {
972 compatible = "sandbox,iommu";
973 #iommu-cells = <0>;
974 };
975
Simon Glass515dcff2020-02-06 09:55:00 -0700976 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700977 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700978 interrupt-controller;
979 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700980 };
981
Simon Glass90b6fef2016-01-18 19:52:26 -0700982 lcd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700983 bootph-all;
Simon Glass90b6fef2016-01-18 19:52:26 -0700984 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200985 pinctrl-names = "default";
986 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700987 xres = <1366>;
988 yres = <768>;
989 };
990
Simon Glassd783eb32015-07-06 12:54:34 -0600991 leds {
992 compatible = "gpio-leds";
993
Christian Marangifd53ad42024-11-10 12:50:27 +0100994 sandbox_led_red: iracibble {
Simon Glassd783eb32015-07-06 12:54:34 -0600995 gpios = <&gpio_a 1 0>;
996 label = "sandbox:red";
997 };
998
Christian Marangifd53ad42024-11-10 12:50:27 +0100999 sandbox_led_green: martinet {
Simon Glassd783eb32015-07-06 12:54:34 -06001000 gpios = <&gpio_a 2 0>;
1001 label = "sandbox:green";
1002 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +02001003
1004 default_on {
1005 gpios = <&gpio_a 5 0>;
1006 label = "sandbox:default_on";
1007 default-state = "on";
1008 };
1009
1010 default_off {
1011 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -04001012 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +02001013 default-state = "off";
1014 };
Heiko Schocher350d2522025-01-28 14:52:46 +01001015
1016 led-20 {
1017 gpios = <&gpio_a 20 0>;
1018 /* label intentionally omitted */
1019 function = LED_FUNCTION_STATUS;
1020 color = <LED_COLOR_ID_RED>;
1021 function-enumerator = <20>;
1022 };
1023
1024 led-21 {
1025 gpios = <&gpio_a 21 0>;
1026 /* label intentionally omitted */
1027 function = LED_FUNCTION_STATUS;
1028 color = <LED_COLOR_ID_GREEN>;
1029 };
1030
1031 led-22 {
1032 gpios = <&gpio_a 22 0>;
1033 /* label intentionally omitted */
1034 function = LED_FUNCTION_STATUS;
1035 };
1036
1037 led-23 {
1038 gpios = <&gpio_a 23 0>;
1039 /* label intentionally omitted */
1040 color = <LED_COLOR_ID_GREEN>;
1041 };
1042
1043 led-24 {
1044 gpios = <&gpio_a 24 0>;
1045 label = "sandbox:function";
1046 function = LED_FUNCTION_STATUS;
1047 color = <LED_COLOR_ID_GREEN>;
1048 };
Simon Glassd783eb32015-07-06 12:54:34 -06001049 };
1050
Svyatoslav Ryhel1d91d5d2025-02-16 19:09:31 +02001051 lvds-encoder {
1052 compatible = "lvds-encoder";
1053
1054 ports {
1055 #address-cells = <1>;
1056 #size-cells = <0>;
1057
1058 port@0 {
1059 reg = <0>;
1060
1061 bridge_input: endpoint {
1062 /* link to output */
1063 };
1064 };
1065
1066 port@1 {
1067 reg = <1>;
1068
1069 bridge_output: endpoint {
1070 remote-endpoint = <&panel_input>;
1071 };
1072 };
1073 };
1074 };
1075
Paul Doelle709f0372022-07-04 09:00:25 +00001076 wdt-gpio-toggle {
Simon Glasse0f8cd22023-08-10 09:53:13 -06001077 gpios = <&gpio_a 8 0>;
Rasmus Villemoes2b673872021-08-19 11:57:05 +02001078 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001079 hw_margin_ms = <100>;
Paul Doelle709f0372022-07-04 09:00:25 +00001080 hw_algo = "toggle";
1081 always-running;
1082 };
1083
1084 wdt-gpio-level {
1085 gpios = <&gpio_a 7 0>;
1086 compatible = "linux,wdt-gpio";
1087 hw_margin_ms = <100>;
1088 hw_algo = "level";
Rasmus Villemoes2b673872021-08-19 11:57:05 +02001089 always-running;
1090 };
1091
Stephen Warren62f2c902016-05-16 17:41:37 -06001092 mbox: mbox {
1093 compatible = "sandbox,mbox";
1094 #mbox-cells = <1>;
1095 };
1096
1097 mbox-test {
1098 compatible = "sandbox,mbox-test";
1099 mboxes = <&mbox 100>, <&mbox 1>;
1100 mbox-names = "other", "test";
1101 };
1102
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001103 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001104 #address-cells = <1>;
1105 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -04001106 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001107 cpu1: cpu@1 {
1108 device_type = "cpu";
1109 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -04001110 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001111 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001112 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001113 };
Mario Sixdea5df72018-08-06 10:23:44 +02001114
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001115 cpu2: cpu@2 {
1116 device_type = "cpu";
1117 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001118 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001119 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001120 };
Mario Sixdea5df72018-08-06 10:23:44 +02001121
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001122 cpu3: cpu@3 {
1123 device_type = "cpu";
1124 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001125 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001126 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001127 };
Mario Sixdea5df72018-08-06 10:23:44 +02001128 };
1129
Dave Gerlach75dbdfc2020-07-15 23:39:58 -05001130 chipid: chipid {
1131 compatible = "sandbox,soc";
1132 };
1133
Simon Glassc953aaf2018-12-10 10:37:34 -07001134 i2s: i2s {
1135 compatible = "sandbox,i2s";
1136 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -07001137 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -07001138 };
1139
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +02001140 nop-test_0 {
1141 compatible = "sandbox,nop_sandbox1";
1142 nop-test_1 {
1143 compatible = "sandbox,nop_sandbox2";
1144 bind = "True";
1145 };
1146 nop-test_2 {
1147 compatible = "sandbox,nop_sandbox2";
1148 bind = "False";
1149 };
1150 };
1151
Roger Quadrosb0679a72022-10-20 16:30:46 +03001152 memory-controller {
1153 compatible = "sandbox,memory";
1154 };
1155
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001156 misc-test {
Sean Anderson13652b82022-05-05 13:11:44 -04001157 #address-cells = <1>;
1158 #size-cells = <1>;
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001159 compatible = "sandbox,misc_sandbox";
Sean Anderson13652b82022-05-05 13:11:44 -04001160
1161 eth5_addr: mac-address@10 {
1162 reg = <0x10 6>;
1163 };
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001164 };
1165
Simon Glasse4fef742017-04-23 20:02:07 -06001166 mmc2 {
1167 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -06001168 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -06001169 };
1170
Simon Glassb255efc2022-04-24 23:31:24 -06001171 /* This is used for the bootdev tests */
Simon Glasse4fef742017-04-23 20:02:07 -06001172 mmc1 {
1173 compatible = "sandbox,mmc";
Simon Glassb255efc2022-04-24 23:31:24 -06001174 filename = "mmc1.img";
Simon Glasse4fef742017-04-23 20:02:07 -06001175 };
1176
Simon Glassb255efc2022-04-24 23:31:24 -06001177 /* This is used for the fastboot tests */
Sughosh Ganu77079e72022-10-21 18:16:05 +05301178 mmc0: mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -06001179 compatible = "sandbox,mmc";
1180 };
1181
Simon Glassf1eba352022-10-20 18:23:20 -06001182 /* This is used for VBE VPL tests */
1183 mmc3 {
1184 status = "disabled";
1185 compatible = "sandbox,mmc";
1186 filename = "image.bin";
1187 non-removable;
1188 };
1189
Simon Glassd2bc33ed2023-01-06 08:52:41 -06001190 /* This is used for bootstd bootmenu tests */
1191 mmc4 {
1192 status = "disabled";
1193 compatible = "sandbox,mmc";
1194 filename = "mmc4.img";
1195 };
1196
Simon Glassfff928c2023-08-24 13:55:41 -06001197 /* This is used for ChromiumOS tests */
1198 mmc5 {
1199 status = "disabled";
1200 compatible = "sandbox,mmc";
1201 filename = "mmc5.img";
1202 };
1203
Alexander Gendin038cb022023-10-09 01:24:36 +00001204 /* This is used for mbr tests */
1205 mmc6 {
1206 status = "disabled";
1207 compatible = "sandbox,mmc";
1208 filename = "mmc6.img";
1209 };
1210
Guillaume La Roque368ad9e2024-11-26 09:06:13 +01001211 /* This is used for Android boot image v4 tests */
Mattijs Korpershoekd77f8152024-07-10 10:40:06 +02001212 mmc7 {
1213 status = "disabled";
1214 compatible = "sandbox,mmc";
1215 filename = "mmc7.img";
1216 };
1217
Guillaume La Roque368ad9e2024-11-26 09:06:13 +01001218 /* This is used for Android boot image v2 tests. */
1219 mmc8 {
1220 status = "disabled";
1221 compatible = "sandbox,mmc";
1222 filename = "mmc8.img";
1223 };
1224
Simon Glass53a68b32019-02-16 20:24:50 -07001225 pch {
1226 compatible = "sandbox,pch";
1227 };
1228
Tom Rini4a3ca482020-02-11 12:41:23 -05001229 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -07001230 compatible = "sandbox,pci";
1231 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001232 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001233 #address-cells = <3>;
1234 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -06001235 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -07001236 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Mark Kettenis5dfd4ec2023-01-21 20:27:57 +01001237 iommu-map = <0x0010 &iommu 0 1>;
1238 iommu-map-mask = <0xfffffff8>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001239 pci@0,0 {
1240 compatible = "pci-generic";
1241 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001242 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001243 };
Alex Margineanf1274432019-06-07 11:24:24 +03001244 pci@1,0 {
1245 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001246 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
Simon Glass4289c262023-09-26 08:14:58 -06001247 reg = <0x02000814 0 0 0x80 0
1248 0x01000810 0 0 0xc0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001249 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +03001250 };
Simon Glass937bb472019-12-06 21:41:57 -07001251 p2sb-pci@2,0 {
1252 compatible = "sandbox,p2sb";
1253 reg = <0x02001010 0 0 0 0>;
1254 sandbox,emul = <&p2sb_emul>;
1255
1256 adder {
1257 intel,p2sb-port-id = <3>;
1258 compatible = "sandbox,adder";
1259 };
1260 };
Simon Glass8c501022019-12-06 21:41:54 -07001261 pci@1e,0 {
1262 compatible = "sandbox,pmc";
1263 reg = <0xf000 0 0 0 0>;
1264 sandbox,emul = <&pmc_emul1e>;
1265 acpi-base = <0x400>;
1266 gpe0-dwx-mask = <0xf>;
1267 gpe0-dwx-shift-base = <4>;
1268 gpe0-dw = <6 7 9>;
1269 gpe0-sts = <0x20>;
1270 gpe0-en = <0x30>;
1271 };
Simon Glass3a6eae62015-03-05 12:25:34 -07001272 pci@1f,0 {
1273 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001274 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
Simon Glass4289c262023-09-26 08:14:58 -06001275 reg = <0x0100f810 0 0 0x100 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001276 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001277 };
1278 };
1279
Simon Glassb98ba4c2019-09-25 08:56:10 -06001280 pci-emul0 {
1281 compatible = "sandbox,pci-emul-parent";
1282 swap_case_emul0_0: emul0@0,0 {
1283 compatible = "sandbox,swap-case";
1284 };
1285 swap_case_emul0_1: emul0@1,0 {
1286 compatible = "sandbox,swap-case";
1287 use-ea;
1288 };
1289 swap_case_emul0_1f: emul0@1f,0 {
1290 compatible = "sandbox,swap-case";
1291 };
Simon Glass937bb472019-12-06 21:41:57 -07001292 p2sb_emul: emul@2,0 {
1293 compatible = "sandbox,p2sb-emul";
1294 };
Simon Glass8c501022019-12-06 21:41:54 -07001295 pmc_emul1e: emul@1e,0 {
1296 compatible = "sandbox,pmc-emul";
1297 };
Simon Glassb98ba4c2019-09-25 08:56:10 -06001298 };
1299
Tom Rini4a3ca482020-02-11 12:41:23 -05001300 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -07001301 compatible = "sandbox,pci";
1302 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001303 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -07001304 #address-cells = <3>;
1305 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001306 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scullc7456a42022-04-21 16:11:09 +00001307 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001308 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -07001309 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +02001310 0x0c 0x00 0x1234 0x5678
1311 0x10 0x00 0x1234 0x5678>;
1312 pci@10,0 {
1313 reg = <0x8000 0 0 0 0>;
1314 };
Bin Meng408e5902018-08-03 01:14:41 -07001315 };
1316
Tom Rini4a3ca482020-02-11 12:41:23 -05001317 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -07001318 compatible = "sandbox,pci";
1319 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001320 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -07001321 #address-cells = <3>;
1322 #size-cells = <2>;
1323 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1324 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1325 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1326 pci@1f,0 {
1327 compatible = "pci-generic";
1328 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001329 sandbox,emul = <&swap_case_emul2_1f>;
1330 };
1331 };
1332
1333 pci-emul2 {
1334 compatible = "sandbox,pci-emul-parent";
1335 swap_case_emul2_1f: emul2@1f,0 {
1336 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001337 };
1338 };
1339
Ramon Friedc64f19b2019-04-27 11:15:23 +03001340 pci_ep: pci_ep {
1341 compatible = "sandbox,pci_ep";
1342 };
1343
Simon Glass9c433fe2017-04-23 20:10:44 -06001344 probing {
1345 compatible = "simple-bus";
1346 test1 {
1347 compatible = "denx,u-boot-probe-test";
1348 };
1349
1350 test2 {
1351 compatible = "denx,u-boot-probe-test";
1352 };
1353
1354 test3 {
1355 compatible = "denx,u-boot-probe-test";
1356 };
1357
1358 test4 {
1359 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001360 first-syscon = <&syscon0>;
1361 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001362 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001363 };
1364 };
1365
Stephen Warren92c67fa2016-07-13 13:45:31 -06001366 pwrdom: power-domain {
1367 compatible = "sandbox,power-domain";
1368 #power-domain-cells = <1>;
1369 };
1370
1371 power-domain-test {
1372 compatible = "sandbox,power-domain-test";
1373 power-domains = <&pwrdom 2>;
1374 };
1375
Simon Glass5620cf82018-10-01 12:22:40 -06001376 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001377 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001378 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001379 pinctrl-names = "default";
1380 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001381 };
1382
1383 pwm2 {
1384 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001385 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001386 };
1387
Simon Glass3d355e62015-07-06 12:54:31 -06001388 ram {
1389 compatible = "sandbox,ram";
1390 };
1391
Simon Glassd860f222015-07-06 12:54:29 -06001392 reset@0 {
1393 compatible = "sandbox,warm-reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001394 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001395 };
1396
1397 reset@1 {
1398 compatible = "sandbox,reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001399 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001400 };
1401
Stephen Warren6488e642016-06-17 09:43:59 -06001402 resetc: reset-ctl {
1403 compatible = "sandbox,reset-ctl";
1404 #reset-cells = <1>;
1405 };
1406
1407 reset-ctl-test {
1408 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001409 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1410 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001411 };
1412
Sughosh Ganu23e37512019-12-28 23:58:31 +05301413 rng {
1414 compatible = "sandbox,sandbox-rng";
1415 };
1416
Nishanth Menonedf85812015-09-17 15:42:41 -05001417 rproc_1: rproc@1 {
1418 compatible = "sandbox,test-processor";
1419 remoteproc-name = "remoteproc-test-dev1";
1420 };
1421
1422 rproc_2: rproc@2 {
1423 compatible = "sandbox,test-processor";
1424 internal-memory-mapped;
1425 remoteproc-name = "remoteproc-test-dev2";
1426 };
1427
Simon Glass5620cf82018-10-01 12:22:40 -06001428 panel {
1429 compatible = "simple-panel";
1430 backlight = <&backlight 0 100>;
Svyatoslav Ryhel1d91d5d2025-02-16 19:09:31 +02001431
1432 display-timings {
1433 timing@0 {
1434 /* 1280x800@60Hz */
1435 clock-frequency = <68000000>;
1436 hactive = <1280>;
1437 hfront-porch = <48>;
1438 hback-porch = <18>;
1439 hsync-len = <30>;
1440 vactive = <800>;
1441 vfront-porch = <3>;
1442 vback-porch = <12>;
1443 vsync-len = <5>;
1444 };
1445 };
1446
1447 port {
1448 panel_input: endpoint {
1449 remote-endpoint = <&bridge_output>;
1450 };
1451 };
Simon Glass5620cf82018-10-01 12:22:40 -06001452 };
1453
Simon Glass509f32e2022-09-21 16:21:47 +02001454 scsi {
1455 compatible = "sandbox,scsi";
1456 sandbox,filepath = "scsi.img";
1457 };
1458
Ramon Fried26ed32e2018-07-02 02:57:59 +03001459 smem@0 {
1460 compatible = "sandbox,smem";
1461 };
1462
Simon Glass76072ac2018-12-10 10:37:36 -07001463 sound {
1464 compatible = "sandbox,sound";
1465 cpu {
1466 sound-dai = <&i2s 0>;
1467 };
1468
1469 codec {
1470 sound-dai = <&audio 0>;
1471 };
1472 };
1473
Simon Glass25348a42014-10-13 23:42:11 -06001474 spi@0 {
1475 #address-cells = <1>;
1476 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001477 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001478 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001479 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001480 pinctrl-names = "default";
1481 pinctrl-0 = <&pinmux_spi0_pins>;
1482
Simon Glass25348a42014-10-13 23:42:11 -06001483 spi.bin@0 {
1484 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001485 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001486 spi-max-frequency = <40000000>;
1487 sandbox,filename = "spi.bin";
1488 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001489 spi.bin@1 {
1490 reg = <1>;
1491 compatible = "spansion,m25p16", "jedec,spi-nor";
1492 spi-max-frequency = <50000000>;
1493 sandbox,filename = "spi.bin";
1494 spi-cpol;
1495 spi-cpha;
1496 };
Simon Glass25348a42014-10-13 23:42:11 -06001497 };
1498
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001499 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001500 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001501 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001502 };
1503
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001504 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001505 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001506 reg = <0x20 5
1507 0x28 6
1508 0x30 7
1509 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001510 };
1511
Patrick Delaunayee010432019-03-07 09:57:13 +01001512 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001513 compatible = "simple-mfd", "syscon";
1514 reg = <0x40 5
1515 0x48 6
1516 0x50 7
1517 0x58 8>;
1518 };
1519
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301520 syscon3: syscon@3 {
1521 compatible = "simple-mfd", "syscon";
1522 reg = <0x000100 0x10>;
1523
1524 muxcontroller0: a-mux-controller {
1525 compatible = "mmio-mux";
1526 #mux-control-cells = <1>;
1527
1528 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1529 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1530 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1531 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1532 u-boot,mux-autoprobe;
1533 };
1534 };
1535
1536 muxcontroller1: emul-mux-controller {
1537 compatible = "mux-emul";
1538 #mux-control-cells = <0>;
1539 u-boot,mux-autoprobe;
1540 idle-state = <0xabcd>;
1541 };
1542
Simon Glass791a17f2020-12-16 21:20:27 -07001543 testfdtm0 {
1544 compatible = "denx,u-boot-fdtm-test";
1545 };
1546
1547 testfdtm1: testfdtm1 {
1548 compatible = "denx,u-boot-fdtm-test";
1549 };
1550
1551 testfdtm2 {
1552 compatible = "denx,u-boot-fdtm-test";
1553 };
1554
Sean Anderson79d3bba2020-09-28 10:52:23 -04001555 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001556 compatible = "sandbox,timer";
1557 clock-frequency = <1000000>;
1558 };
1559
Sean Anderson79d3bba2020-09-28 10:52:23 -04001560 timer@1 {
1561 compatible = "sandbox,timer";
1562 sandbox,timebase-frequency-fallback;
1563 };
1564
Miquel Raynal80938c12018-05-15 11:57:27 +02001565 tpm2 {
1566 compatible = "sandbox,tpm2";
Eddie James1a55a7a2023-10-24 10:43:51 -05001567 memory-region = <&event_log>;
Miquel Raynal80938c12018-05-15 11:57:27 +02001568 };
1569
Simon Glasseef107e2023-02-21 06:24:51 -07001570 tpm {
1571 compatible = "google,sandbox-tpm";
1572 };
1573
Simon Glass5b968632015-05-22 15:42:15 -06001574 uart0: serial {
1575 compatible = "sandbox,serial";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001576 bootph-all;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001577 pinctrl-names = "default";
1578 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001579 };
1580
Simon Glass31680482015-03-25 12:23:05 -06001581 usb_0: usb@0 {
1582 compatible = "sandbox,usb";
1583 status = "disabled";
1584 hub {
1585 compatible = "sandbox,usb-hub";
1586 #address-cells = <1>;
1587 #size-cells = <0>;
1588 flash-stick {
1589 reg = <0>;
1590 compatible = "sandbox,usb-flash";
1591 };
1592 };
1593 };
1594
1595 usb_1: usb@1 {
1596 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001597 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001598 hub {
1599 compatible = "usb-hub";
1600 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001601 #address-cells = <1>;
1602 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001603 hub-emul {
1604 compatible = "sandbox,usb-hub";
1605 #address-cells = <1>;
1606 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001607 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001608 reg = <0>;
1609 compatible = "sandbox,usb-flash";
1610 sandbox,filepath = "testflash.bin";
1611 };
1612
Simon Glass4700fe52015-11-08 23:48:01 -07001613 flash-stick@1 {
1614 reg = <1>;
1615 compatible = "sandbox,usb-flash";
Simon Glass64c63252024-11-07 14:31:49 -07001616 sandbox,filepath = "flash1.img";
Simon Glass4700fe52015-11-08 23:48:01 -07001617 };
1618
1619 flash-stick@2 {
1620 reg = <2>;
1621 compatible = "sandbox,usb-flash";
1622 sandbox,filepath = "testflash2.bin";
1623 };
1624
Simon Glassc0ccc722015-11-08 23:48:08 -07001625 keyb@3 {
1626 reg = <3>;
1627 compatible = "sandbox,usb-keyb";
1628 };
1629
Simon Glass31680482015-03-25 12:23:05 -06001630 };
Michael Walle7c961322020-06-02 01:47:07 +02001631
1632 usbstor@1 {
1633 reg = <1>;
1634 };
1635 usbstor@3 {
1636 reg = <3>;
1637 };
Simon Glass31680482015-03-25 12:23:05 -06001638 };
1639 };
1640
1641 usb_2: usb@2 {
1642 compatible = "sandbox,usb";
1643 status = "disabled";
1644 };
1645
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001646 spmi: spmi@0 {
1647 compatible = "sandbox,spmi";
1648 #address-cells = <0x1>;
1649 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001650 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001651 pm8916@0 {
1652 compatible = "qcom,spmi-pmic";
1653 reg = <0x0 0x1>;
1654 #address-cells = <0x1>;
1655 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001656 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001657
1658 spmi_gpios: gpios@c000 {
1659 compatible = "qcom,pm8916-gpio";
1660 reg = <0xc000 0x400>;
Caleb Connolly1edc45f2024-01-08 15:30:51 +00001661 gpio-ranges = <&spmi_gpios 0 0 4>;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001662 gpio-controller;
1663 gpio-count = <4>;
1664 #gpio-cells = <2>;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001665 };
1666 };
1667 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001668
1669 wdt0: wdt@0 {
1670 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001671 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001672 };
Rob Clarka471b672018-01-10 11:33:30 +01001673
Mario Six95922152018-08-09 14:51:19 +02001674 axi: axi@0 {
1675 compatible = "sandbox,axi";
1676 #address-cells = <0x1>;
1677 #size-cells = <0x1>;
1678 store@0 {
1679 compatible = "sandbox,sandbox_store";
1680 reg = <0x0 0x400>;
1681 };
1682 };
1683
Rob Clarka471b672018-01-10 11:33:30 +01001684 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001685 #address-cells = <1>;
1686 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001687 setting = "sunrise ohoka";
1688 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001689 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001690 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Algapally Santosh Sagardf178992023-09-21 16:50:43 +05301691 stdout-path = "serial0:115200n8";
Rob Clarka471b672018-01-10 11:33:30 +01001692 chosen-test {
1693 compatible = "denx,u-boot-fdt-test";
1694 reg = <9 1>;
1695 };
1696 };
Mario Six35616ef2018-03-12 14:53:33 +01001697
1698 translation-test@8000 {
1699 compatible = "simple-bus";
1700 reg = <0x8000 0x4000>;
1701
1702 #address-cells = <0x2>;
1703 #size-cells = <0x1>;
1704
1705 ranges = <0 0x0 0x8000 0x1000
1706 1 0x100 0x9000 0x1000
1707 2 0x200 0xA000 0x1000
1708 3 0x300 0xB000 0x1000
1709 >;
1710
Fabien Dessenne22236e02019-05-31 15:11:30 +02001711 dma-ranges = <0 0x000 0x10000000 0x1000
1712 1 0x100 0x20000000 0x1000
1713 >;
1714
Mario Six35616ef2018-03-12 14:53:33 +01001715 dev@0,0 {
1716 compatible = "denx,u-boot-fdt-dummy";
1717 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +01001718 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001719 };
1720
1721 dev@1,100 {
1722 compatible = "denx,u-boot-fdt-dummy";
1723 reg = <1 0x100 0x1000>;
1724
1725 };
1726
1727 dev@2,200 {
1728 compatible = "denx,u-boot-fdt-dummy";
1729 reg = <2 0x200 0x1000>;
1730 };
1731
1732
1733 noxlatebus@3,300 {
1734 compatible = "simple-bus";
1735 reg = <3 0x300 0x1000>;
1736
1737 #address-cells = <0x1>;
1738 #size-cells = <0x0>;
1739
1740 dev@42 {
1741 compatible = "denx,u-boot-fdt-dummy";
1742 reg = <0x42>;
1743 };
1744 };
1745 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001746
Dzmitry Sankouski54f4c832023-01-22 18:21:23 +03001747 ofnode-foreach {
1748 compatible = "foreach";
1749
1750 first {
1751 prop1 = <1>;
1752 prop2 = <2>;
1753 };
1754
1755 second {
1756 prop1 = <1>;
1757 prop2 = <2>;
1758 };
1759 };
1760
Mario Six02ad6fb2018-09-27 09:19:31 +02001761 osd {
1762 compatible = "sandbox,sandbox_osd";
1763 };
Tom Rinib93eea72018-09-30 18:16:51 -04001764
Jens Wiklander86afaa62018-09-25 16:40:16 +02001765 sandbox_tee {
1766 compatible = "sandbox,tee";
1767 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001768
1769 sandbox_virtio1 {
1770 compatible = "sandbox,virtio1";
Simon Glass8de5a542023-01-17 10:47:51 -07001771 virtio-type = <4>; /* rng */
Bin Meng1bb290d2018-10-15 02:21:26 -07001772 };
1773
1774 sandbox_virtio2 {
1775 compatible = "sandbox,virtio2";
1776 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001777
Simon Glass8de5a542023-01-17 10:47:51 -07001778 sandbox-virtio-blk {
1779 compatible = "sandbox,virtio1";
1780 virtio-type = <2>; /* block */
1781 };
1782
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001783 sandbox_scmi {
1784 compatible = "sandbox,scmi-devices";
AKASHI Takahiro535a7bd2023-10-16 14:39:45 +09001785 power-domains = <&pwrdom_scmi 2>;
Etienne Carrierebf1f1322022-02-21 09:22:41 +01001786 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere09665cb2022-02-21 09:22:39 +01001787 resets = <&reset_scmi 3>;
1788 regul0-supply = <&regul0_scmi>;
1789 regul1-supply = <&regul1_scmi>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001790 };
1791
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001792 pinctrl {
1793 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001794
Sean Anderson3438e3b2020-09-14 11:01:57 -04001795 pinctrl-names = "default", "alternate";
1796 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1797 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001798
Sean Anderson3438e3b2020-09-14 11:01:57 -04001799 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001800 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001801 pins = "P5";
1802 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001803 bias-pull-up;
1804 input-disable;
1805 };
1806 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001807 pins = "P6";
1808 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001809 output-high;
1810 drive-open-drain;
1811 };
1812 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001813 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001814 bias-pull-down;
1815 input-enable;
1816 };
1817 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001818 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001819 bias-disable;
1820 };
1821 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001822
1823 pinctrl_i2c: i2c {
1824 groups {
1825 groups = "I2C_UART";
1826 function = "I2C";
1827 };
1828
1829 pins {
1830 pins = "P0", "P1";
1831 drive-open-drain;
1832 };
1833 };
1834
1835 pinctrl_i2s: i2s {
1836 groups = "SPI_I2S";
1837 function = "I2S";
1838 };
1839
1840 pinctrl_spi: spi {
1841 groups = "SPI_I2S";
1842 function = "SPI";
1843
1844 cs {
1845 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1846 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1847 };
1848 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001849 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001850
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001851 pinctrl-single-no-width {
1852 compatible = "pinctrl-single";
1853 reg = <0x0000 0x238>;
1854 #pinctrl-cells = <1>;
1855 pinctrl-single,function-mask = <0x7f>;
1856 };
1857
1858 pinctrl-single-pins {
1859 compatible = "pinctrl-single";
1860 reg = <0x0000 0x238>;
1861 #pinctrl-cells = <1>;
1862 pinctrl-single,register-width = <32>;
1863 pinctrl-single,function-mask = <0x7f>;
1864
1865 pinmux_pwm_pins: pinmux_pwm_pins {
1866 pinctrl-single,pins = < 0x48 0x06 >;
1867 };
1868
1869 pinmux_spi0_pins: pinmux_spi0_pins {
1870 pinctrl-single,pins = <
1871 0x190 0x0c
1872 0x194 0x0c
1873 0x198 0x23
1874 0x19c 0x0c
1875 >;
1876 };
1877
1878 pinmux_uart0_pins: pinmux_uart0_pins {
1879 pinctrl-single,pins = <
1880 0x70 0x30
1881 0x74 0x00
1882 >;
1883 };
1884 };
1885
1886 pinctrl-single-bits {
1887 compatible = "pinctrl-single";
1888 reg = <0x0000 0x50>;
1889 #pinctrl-cells = <2>;
1890 pinctrl-single,bit-per-mux;
1891 pinctrl-single,register-width = <32>;
1892 pinctrl-single,function-mask = <0xf>;
1893
1894 pinmux_i2c0_pins: pinmux_i2c0_pins {
1895 pinctrl-single,bits = <
1896 0x10 0x00002200 0x0000ff00
1897 >;
1898 };
1899
1900 pinmux_lcd_pins: pinmux_lcd_pins {
1901 pinctrl-single,bits = <
1902 0x40 0x22222200 0xffffff00
1903 0x44 0x22222222 0xffffffff
1904 0x48 0x00000022 0x000000ff
1905 0x48 0x02000000 0x0f000000
1906 0x4c 0x02000022 0x0f0000ff
1907 >;
1908 };
1909 };
1910
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001911 hwspinlock@0 {
1912 compatible = "sandbox,hwspinlock";
1913 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001914
1915 dma: dma {
1916 compatible = "sandbox,dma";
1917 #dma-cells = <1>;
1918
1919 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1920 dma-names = "m2m", "tx0", "rx0";
1921 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001922
Alex Marginean0649be52019-07-12 10:13:53 +03001923 /*
1924 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1925 * end of the test. If parent mdio is removed first, clean-up of the
1926 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1927 * active at the end of the test. That it turn doesn't allow the mdio
1928 * class to be destroyed, triggering an error.
1929 */
1930 mdio-mux-test {
1931 compatible = "sandbox,mdio-mux";
1932 #address-cells = <1>;
1933 #size-cells = <0>;
1934 mdio-parent-bus = <&mdio>;
1935
1936 mdio-ch-test@0 {
1937 reg = <0>;
1938 };
1939 mdio-ch-test@1 {
1940 reg = <1>;
1941 };
1942 };
1943
1944 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001945 compatible = "sandbox,mdio";
Marek Behúnf4f1ddc2022-04-07 00:32:57 +02001946 #address-cells = <1>;
1947 #size-cells = <0>;
1948
1949 ethphy1: ethernet-phy@1 {
1950 reg = <1>;
1951 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001952 };
Sean Andersonb7860542020-06-24 06:41:12 -04001953
1954 pm-bus-test {
1955 compatible = "simple-pm-bus";
1956 clocks = <&clk_sandbox 4>;
1957 power-domains = <&pwrdom 1>;
1958 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001959
1960 resetc2: syscon-reset {
1961 compatible = "syscon-reset";
1962 #reset-cells = <1>;
1963 regmap = <&syscon0>;
1964 offset = <1>;
1965 mask = <0x27FFFFFF>;
1966 assert-high = <0>;
1967 };
1968
1969 syscon-reset-test {
1970 compatible = "sandbox,misc_sandbox";
1971 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1972 reset-names = "valid", "no_mask", "out_of_range";
1973 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301974
Simon Glass458b66a2020-11-05 06:32:05 -07001975 sysinfo {
1976 compatible = "sandbox,sysinfo-sandbox";
1977 };
1978
Sean Anderson1c830672021-04-20 10:50:58 -04001979 sysinfo-gpio {
1980 compatible = "gpio-sysinfo";
1981 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1982 revisions = <19>, <5>;
1983 names = "rev_a", "foo";
1984 };
1985
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301986 some_regmapped-bus {
1987 #address-cells = <0x1>;
1988 #size-cells = <0x1>;
1989
1990 ranges = <0x0 0x0 0x10>;
1991 compatible = "simple-bus";
1992
1993 regmap-test_0 {
1994 reg = <0 0x10>;
1995 compatible = "sandbox,regmap_test";
1996 };
1997 };
Robert Marko9cf87122022-09-06 13:30:35 +02001998
1999 thermal {
2000 compatible = "sandbox,thermal";
2001 };
Sughosh Ganu77079e72022-10-21 18:16:05 +05302002
2003 fwu-mdata {
2004 compatible = "u-boot,fwu-mdata-gpt";
2005 fwu-mdata-store = <&mmc0>;
2006 };
Abdellatif El Khlifi6b005872023-04-17 10:11:55 +01002007
2008 nvmxip-qspi1@08000000 {
2009 compatible = "nvmxip,qspi";
2010 reg = <0x08000000 0x00200000>;
2011 lba_shift = <9>;
2012 lba = <4096>;
2013 };
2014
2015 nvmxip-qspi2@08200000 {
2016 compatible = "nvmxip,qspi";
2017 reg = <0x08200000 0x00100000>;
2018 lba_shift = <9>;
2019 lba = <2048>;
2020 };
Svyatoslav Ryhel669f5c82023-04-25 10:57:21 +03002021
2022 extcon {
2023 compatible = "sandbox,extcon";
2024 };
Abdellatif El Khlifi4970d5b2023-08-04 14:33:41 +01002025
2026 arm-ffa-emul {
2027 compatible = "sandbox,arm-ffa-emul";
2028
2029 sandbox-arm-ffa {
2030 compatible = "sandbox,arm-ffa";
2031 };
2032 };
Sean Anderson326422b2023-11-04 16:37:52 -04002033
2034 nand-controller {
2035 #address-cells = <1>;
2036 #size-cells = <0>;
2037 compatible = "sandbox,nand";
2038
2039 nand@0 {
2040 reg = <0>;
2041 nand-ecc-mode = "soft";
2042 sandbox,id = [00 e3];
2043 sandbox,erasesize = <(8 * 1024)>;
2044 sandbox,oobsize = <16>;
2045 sandbox,pagesize = <512>;
2046 sandbox,pages = <0x2000>;
2047 sandbox,err-count = <1>;
2048 sandbox,err-step-size = <512>;
2049 };
2050
2051 /* MT29F64G08AKABA */
2052 nand@1 {
2053 reg = <1>;
2054 nand-ecc-mode = "soft_bch";
2055 sandbox,id = [2C 48 00 26 89 00 00 00];
2056 sandbox,onfi = [
2057 4f 4e 46 49 0e 00 5a 00
2058 ff 01 00 00 00 00 03 00
2059 00 00 00 00 00 00 00 00
2060 00 00 00 00 00 00 00 00
2061 4d 49 43 52 4f 4e 20 20
2062 20 20 20 20 4d 54 32 39
2063 46 36 34 47 30 38 41 4b
2064 41 42 41 43 35 20 20 20
2065 2c 00 00 00 00 00 00 00
2066 00 00 00 00 00 00 00 00
2067 00 10 00 00 e0 00 00 02
2068 00 00 1c 00 80 00 00 00
2069 00 10 00 00 02 23 01 50
2070 00 01 05 01 00 00 04 00
2071 04 01 1e 00 00 00 00 00
2072 00 00 00 00 00 00 00 00
2073 0e 1f 00 1f 00 f4 01 ac
2074 0d 19 00 c8 00 00 00 00
2075 00 00 00 00 00 00 0a 07
2076 19 00 00 00 00 00 00 00
2077 00 00 00 00 01 00 01 00
2078 00 00 04 10 01 81 04 02
2079 02 01 1e 90 00 00 00 00
2080 00 00 00 00 00 00 00 00
2081 00 00 00 00 00 00 00 00
2082 00 00 00 00 00 00 00 00
2083 00 00 00 00 00 00 00 00
2084 00 00 00 00 00 00 00 00
2085 00 00 00 00 00 00 00 00
2086 00 00 00 00 00 00 00 00
2087 00 00 00 00 00 00 00 00
2088 00 00 00 00 00 03 20 7d
2089 ];
2090 sandbox,erasesize = <(512 * 1024)>;
2091 sandbox,oobsize = <224>;
2092 sandbox,pagesize = <4096>;
2093 sandbox,pages = <0x200000>;
2094 sandbox,err-count = <3>;
2095 sandbox,err-step-size = <512>;
2096 };
2097 };
Svyatoslav Ryhel1f5298f2025-02-16 13:14:40 +02002098
2099 graph1 {
2100 ports {
2101 #address-cells = <1>;
2102 #size-cells = <0>;
2103
2104 port@0 {
2105 #address-cells = <1>;
2106 #size-cells = <0>;
2107
2108 reg = <0>;
2109
2110 endpoint@0 {
2111 reg = <0>;
2112 };
2113
2114 endpoint@1 {
2115 reg = <1>;
2116 };
2117 };
2118
2119 port@1 {
2120 reg = <1>;
2121
2122 endpoint {
2123 test-property-0;
2124 };
2125 };
2126
2127 port@2 {
2128 #address-cells = <1>;
2129 #size-cells = <0>;
2130
2131 reg = <2>;
2132
2133 graph2_link: endpoint@0 {
2134 reg = <0>;
2135 test-property-1;
2136 remote-endpoint = <&graph1_link>;
2137 };
2138
2139 endpoint@1 {
2140 reg = <1>;
2141 };
2142 };
2143 };
2144 };
2145
2146 graph2 {
2147 port {
2148 graph1_link: endpoint {
2149 remote-endpoint = <&graph2_link>;
2150 };
2151 };
2152 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07002153};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02002154
2155#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01002156#include "cros-ec-keyboard.dtsi"
Simon Glass5e135d32022-10-20 18:23:15 -06002157
2158#ifdef CONFIG_SANDBOX_VPL
2159#include "sandbox_vpl.dtsi"
2160#endif
Simon Glass61300722023-06-01 10:23:01 -06002161
Sughosh Ganu05137922024-03-27 16:19:00 +05302162#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
2163#include "sandbox_capsule.dtsi"
2164#endif
2165
Simon Glass61300722023-06-01 10:23:01 -06002166#include "cedit.dtsi"