blob: 5b54651a1dac0b87cc220f231c3dd99d16b4be6a [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay23aee612020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010017
Simon Glassb2c1cac2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070023
Simon Glassfef72b72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Sean Anderson67d93a42022-05-05 13:11:30 -040031 ethernet6 = "/eth@10004000";
32 ethernet7 = &swp_1;
33 ethernet8 = &phy_eth0;
Simon Glass5620cf82018-10-01 12:22:40 -060034 gpio1 = &gpio_a;
35 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010036 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070037 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060038 mmc0 = "/mmc0";
39 mmc1 = "/mmc1";
Simon Glassf1eba352022-10-20 18:23:20 -060040 mmc2 = "/mmc2";
41 mmc3 = "/mmc3";
Simon Glassfff928c2023-08-24 13:55:41 -060042 mmc4 = "/mmc4";
43 mmc5 = "/mmc5";
Alexander Gendin038cb022023-10-09 01:24:36 +000044 mmc6 = "/mmc6";
Bin Meng408e5902018-08-03 01:14:41 -070045 pci0 = &pci0;
46 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070047 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020048 remoteproc0 = &rproc_1;
49 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060050 rtc0 = &rtc_0;
51 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060052 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020053 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070054 testbus3 = "/some-bus";
55 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070056 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070057 testfdt3 = "/b-test";
58 testfdt5 = "/some-bus/c-test@5";
59 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070060 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020061 fdt-dummy0 = "/translation-test@8000/dev@0,0";
62 fdt-dummy1 = "/translation-test@8000/dev@1,100";
63 fdt-dummy2 = "/translation-test@8000/dev@2,200";
64 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060065 usb0 = &usb_0;
66 usb1 = &usb_1;
67 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020068 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020069 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060070 };
71
Simon Glass5e135d32022-10-20 18:23:15 -060072 binman: binman {
Philippe Reynes462d1632022-03-28 22:56:53 +020073 };
74
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020075 config {
Simon Glass0034d962021-08-07 07:24:01 -060076 testing-bool;
77 testing-int = <123>;
78 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020079 environment {
80 from_fdt = "yes";
81 fdt_env_path = "";
82 };
83 };
84
Michal Simek43c42bd2023-08-31 08:59:05 +020085 options {
86 u-boot {
87 compatible = "u-boot,config";
88 bootscr-ram-offset = /bits/ 64 <0x12345678>;
Michal Simek6a7c1ce2023-08-31 09:04:27 +020089 bootscr-flash-offset = /bits/ 64 <0>;
90 bootscr-flash-size = /bits/ 64 <0x2000>;
Michal Simek43c42bd2023-08-31 08:59:05 +020091 };
92 };
93
Simon Glassb255efc2022-04-24 23:31:24 -060094 bootstd {
Simon Glassd3a98cb2023-02-13 08:56:33 -070095 bootph-verify;
Simon Glassb255efc2022-04-24 23:31:24 -060096 compatible = "u-boot,boot-std";
97
98 filename-prefixes = "/", "/boot/";
99 bootdev-order = "mmc2", "mmc1";
100
Simon Glassb71d7f72023-05-10 16:34:46 -0600101 extlinux {
102 compatible = "u-boot,extlinux";
Simon Glassb255efc2022-04-24 23:31:24 -0600103 };
104
105 efi {
106 compatible = "u-boot,distro-efi";
107 };
Simon Glassa9289612022-10-20 18:23:14 -0600108
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600109 theme {
110 font-size = <30>;
Simon Glass86f1ac52023-06-01 10:23:00 -0600111 menu-inset = <3>;
112 menuitem-gap-y = <1>;
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600113 };
114
Simon Glass82adc292023-08-14 16:40:30 -0600115 cedit-theme {
116 font-size = <30>;
117 menu-inset = <3>;
118 menuitem-gap-y = <1>;
119 };
120
Simon Glassf1eba352022-10-20 18:23:20 -0600121 /*
122 * This is used for the VBE OS-request tests. A FAT filesystem
123 * created in a partition with the VBE information appearing
Michal Simek33224372023-09-07 14:55:48 +0200124 * before the partition starts
Simon Glassf1eba352022-10-20 18:23:20 -0600125 */
Simon Glassa9289612022-10-20 18:23:14 -0600126 firmware0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700127 bootph-verify;
Simon Glassa9289612022-10-20 18:23:14 -0600128 compatible = "fwupd,vbe-simple";
129 storage = "mmc1";
130 skip-offset = <0x200>;
131 area-start = <0x400>;
132 area-size = <0x1000>;
133 state-offset = <0x400>;
134 state-size = <0x40>;
135 version-offset = <0x800>;
136 version-size = <0x100>;
137 };
Simon Glassf1eba352022-10-20 18:23:20 -0600138
139 /*
140 * This is used for the VBE VPL tests. The MMC device holds the
141 * binman image.bin file. The test progresses through each phase
142 * of U-Boot, loading each in turn from MMC.
143 *
144 * Note that the test enables this node (and mmc3) before
145 * running U-Boot
146 */
147 firmware1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700148 bootph-verify;
Simon Glassf1eba352022-10-20 18:23:20 -0600149 status = "disabled";
150 compatible = "fwupd,vbe-simple";
151 storage = "mmc3";
Simon Glass9bb73e32023-04-02 14:01:24 +1200152 skip-offset = <0x800000>;
Simon Glassf1eba352022-10-20 18:23:20 -0600153 area-start = <0>;
154 area-size = <0xe00000>;
155 state-offset = <0xdffc00>;
156 state-size = <0x40>;
157 version-offset = <0xdffe00>;
158 version-size = <0x100>;
159 };
Simon Glassb255efc2022-04-24 23:31:24 -0600160 };
161
Simon Glass61300722023-06-01 10:23:01 -0600162 cedit: cedit {
163 };
164
Andrew Scull451b8b12022-05-30 10:00:12 +0000165 fuzzing-engine {
166 compatible = "sandbox,fuzzing-engine";
167 };
168
Nandor Han6521e5d2021-06-10 16:56:44 +0300169 reboot-mode0 {
170 compatible = "reboot-mode-gpio";
171 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
172 u-boot,env-variable = "bootstatus";
173 mode-test = <0x01>;
174 mode-download = <0x03>;
175 };
176
Nandor Han7e4067a2021-06-10 16:56:45 +0300177 reboot_mode1: reboot-mode@14 {
178 compatible = "reboot-mode-rtc";
179 rtc = <&rtc_0>;
180 reg = <0x30 4>;
181 u-boot,env-variable = "bootstatus";
182 big-endian;
183 mode-test = <0x21969147>;
184 mode-download = <0x51939147>;
185 };
186
Simon Glassed96cde2018-12-10 10:37:33 -0700187 audio: audio-codec {
188 compatible = "sandbox,audio-codec";
189 #sound-dai-cells = <1>;
190 };
191
Philippe Reynes1ee26482020-07-24 18:19:51 +0200192 buttons {
193 compatible = "gpio-keys";
194
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200195 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200196 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200197 label = "button1";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300198 linux,code = <BTN_1>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200199 };
200
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200201 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200202 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200203 label = "button2";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300204 linux,code = <BTN_2>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200205 };
206 };
207
Marek Szyprowskiad398592021-02-18 11:33:18 +0100208 buttons2 {
209 compatible = "adc-keys";
210 io-channels = <&adc 3>;
211 keyup-threshold-microvolt = <3000000>;
212
213 button-up {
214 label = "button3";
215 linux,code = <KEY_F3>;
216 press-threshold-microvolt = <1500000>;
217 };
218
219 button-down {
220 label = "button4";
221 linux,code = <KEY_F4>;
222 press-threshold-microvolt = <1000000>;
223 };
224
225 button-enter {
226 label = "button5";
227 linux,code = <KEY_F5>;
228 press-threshold-microvolt = <500000>;
229 };
230 };
231
Simon Glassc953aaf2018-12-10 10:37:34 -0700232 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600233 reg = <0 0>;
234 compatible = "google,cros-ec-sandbox";
235
236 /*
237 * This describes the flash memory within the EC. Note
238 * that the STM32L flash erases to 0, not 0xff.
239 */
240 flash {
241 image-pos = <0x08000000>;
242 size = <0x20000>;
243 erase-value = <0>;
244
245 /* Information for sandbox */
246 ro {
247 image-pos = <0>;
248 size = <0xf000>;
249 };
250 wp-ro {
251 image-pos = <0xf000>;
252 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700253 used = <0x884>;
254 compress = "lz4";
255 uncomp-size = <0xcf8>;
256 hash {
257 algo = "sha256";
258 value = [00 01 02 03 04 05 06 07
259 08 09 0a 0b 0c 0d 0e 0f
260 10 11 12 13 14 15 16 17
261 18 19 1a 1b 1c 1d 1e 1f];
262 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600263 };
264 rw {
265 image-pos = <0x10000>;
266 size = <0x10000>;
267 };
268 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300269
270 cros_ec_pwm: cros-ec-pwm {
271 compatible = "google,cros-ec-pwm";
272 #pwm-cells = <1>;
273 };
274
Simon Glass699c9ca2018-10-01 12:22:08 -0600275 };
276
Yannick Fertré9712c822019-10-07 15:29:05 +0200277 dsi_host: dsi_host {
278 compatible = "sandbox,dsi-host";
279 };
280
Simon Glassb2c1cac2014-02-26 15:59:21 -0700281 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600282 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700283 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600284 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700285 ping-add = <0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700286 bootph-all;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100287 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
288 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700289 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100290 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
291 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
292 <&gpio_b 7 GPIO_IN 3 2 1>,
293 <&gpio_b 8 GPIO_OUT 3 2 1>,
294 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100295 test3-gpios =
296 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
297 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
298 <&gpio_c 2 GPIO_OUT>,
299 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
300 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200301 <&gpio_c 5 GPIO_IN>,
302 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
303 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530304 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
305 test5-gpios = <&gpio_a 19>;
306
Simon Glass73025392021-10-23 17:26:04 -0600307 bool-value;
Stefan Herbrechtsmeier1b090e62022-06-14 15:21:30 +0200308 int8-value = /bits/ 8 <0x12>;
309 int16-value = /bits/ 16 <0x1234>;
Simon Glass6df01f92018-12-10 10:37:37 -0700310 int-value = <1234>;
311 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200312 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200313 int-array = <5678 9123 4567>;
Michal Simek08a194e2023-08-25 11:37:46 +0200314 int64-array = /bits/ 64 <0x1111222233334444 0x4444333322221111>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600315 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700316 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600317 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200318 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530319
320 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
321 <&muxcontroller0 2>, <&muxcontroller0 3>,
322 <&muxcontroller1>;
323 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
324 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100325 display-timings {
326 timing0: 240x320 {
327 clock-frequency = <6500000>;
328 hactive = <240>;
329 vactive = <320>;
330 hfront-porch = <6>;
331 hback-porch = <7>;
332 hsync-len = <1>;
333 vback-porch = <5>;
334 vfront-porch = <8>;
335 vsync-len = <2>;
336 hsync-active = <1>;
337 vsync-active = <0>;
338 de-active = <1>;
339 pixelclk-active = <1>;
340 interlaced;
341 doublescan;
342 doubleclk;
343 };
344 timing1: 480x800 {
345 clock-frequency = <9000000>;
346 hactive = <480>;
347 vactive = <800>;
348 hfront-porch = <10>;
349 hback-porch = <59>;
350 hsync-len = <12>;
351 vback-porch = <15>;
352 vfront-porch = <17>;
353 vsync-len = <16>;
354 hsync-active = <0>;
355 vsync-active = <1>;
356 de-active = <0>;
357 pixelclk-active = <0>;
358 };
359 timing2: 800x480 {
360 clock-frequency = <33500000>;
361 hactive = <800>;
362 vactive = <480>;
363 hback-porch = <89>;
364 hfront-porch = <164>;
365 vback-porch = <23>;
366 vfront-porch = <10>;
367 hsync-len = <11>;
368 vsync-len = <13>;
369 };
370 };
Raphael Gallais-Poua853b922023-05-11 16:36:52 +0200371 panel-timing {
Nikhil M Jainbb9d1312023-01-31 15:35:15 +0530372 clock-frequency = <6500000>;
373 hactive = <240>;
374 vactive = <320>;
375 hfront-porch = <6>;
376 hback-porch = <7>;
377 hsync-len = <1>;
378 vback-porch = <5>;
379 vfront-porch = <8>;
380 vsync-len = <2>;
381 hsync-active = <1>;
382 vsync-active = <0>;
383 de-active = <1>;
384 pixelclk-active = <1>;
385 interlaced;
386 doublescan;
387 doubleclk;
388 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700389 };
390
391 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600392 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700393 compatible = "not,compatible";
394 };
395
396 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600397 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700398 };
399
Simon Glass5620cf82018-10-01 12:22:40 -0600400 backlight: backlight {
401 compatible = "pwm-backlight";
402 enable-gpios = <&gpio_a 1>;
403 power-supply = <&ldo_1>;
404 pwms = <&pwm 0 1000>;
405 default-brightness-level = <5>;
406 brightness-levels = <0 16 32 64 128 170 202 234 255>;
407 };
408
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200409 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200410 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200411 bind-test-child1 {
412 compatible = "sandbox,phy";
413 #phy-cells = <1>;
414 };
415
416 bind-test-child2 {
417 compatible = "simple-bus";
418 };
419 };
420
Simon Glassb2c1cac2014-02-26 15:59:21 -0700421 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600422 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700423 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600424 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700425 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530426
427 mux-controls = <&muxcontroller0 0>;
428 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700429 };
430
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200431 phy_provider0: gen_phy@0 {
432 compatible = "sandbox,phy";
433 #phy-cells = <1>;
434 };
435
436 phy_provider1: gen_phy@1 {
437 compatible = "sandbox,phy";
438 #phy-cells = <0>;
439 broken;
440 };
441
developer71092972020-05-02 11:35:12 +0200442 phy_provider2: gen_phy@2 {
443 compatible = "sandbox,phy";
444 #phy-cells = <0>;
445 };
446
Jonas Karlman9f89e682023-08-31 22:16:35 +0000447 phy_provider3: gen_phy@3 {
448 compatible = "sandbox,phy";
449 #phy-cells = <2>;
450 };
451
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200452 gen_phy_user: gen_phy_user {
453 compatible = "simple-bus";
454 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
455 phy-names = "phy1", "phy2", "phy3";
456 };
457
developer71092972020-05-02 11:35:12 +0200458 gen_phy_user1: gen_phy_user1 {
459 compatible = "simple-bus";
460 phys = <&phy_provider0 0>, <&phy_provider2>;
461 phy-names = "phy1", "phy2";
462 };
463
Jonas Karlman9f89e682023-08-31 22:16:35 +0000464 gen_phy_user2: gen_phy_user2 {
465 compatible = "simple-bus";
466 phys = <&phy_provider3 0 0>;
467 phy-names = "phy1";
468 };
469
Simon Glassb2c1cac2014-02-26 15:59:21 -0700470 some-bus {
471 #address-cells = <1>;
472 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600473 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600474 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600475 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700476 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600477 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700478 compatible = "denx,u-boot-fdt-test";
479 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600480 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700481 ping-add = <5>;
482 };
Simon Glass40717422014-07-23 06:55:18 -0600483 c-test@0 {
484 compatible = "denx,u-boot-fdt-test";
485 reg = <0>;
486 ping-expect = <6>;
487 ping-add = <6>;
488 };
489 c-test@1 {
490 compatible = "denx,u-boot-fdt-test";
491 reg = <1>;
492 ping-expect = <7>;
493 ping-add = <7>;
494 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700495 };
496
497 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600498 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600499 ping-expect = <6>;
500 ping-add = <6>;
501 compatible = "google,another-fdt-test";
502 };
503
504 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600505 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600506 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700507 ping-add = <6>;
508 compatible = "google,another-fdt-test";
509 };
510
Simon Glass0ccb0972015-01-25 08:27:05 -0700511 f-test {
512 compatible = "denx,u-boot-fdt-test";
513 };
514
515 g-test {
516 compatible = "denx,u-boot-fdt-test";
517 };
518
Bin Mengd9d24782018-10-10 22:07:01 -0700519 h-test {
520 compatible = "denx,u-boot-fdt-test1";
521 };
522
developercf8bc132020-05-02 11:35:10 +0200523 i-test {
524 compatible = "mediatek,u-boot-fdt-test";
525 #address-cells = <1>;
526 #size-cells = <0>;
527
528 subnode@0 {
529 reg = <0>;
530 };
531
532 subnode@1 {
533 reg = <1>;
534 };
535
536 subnode@2 {
537 reg = <2>;
538 };
539 };
540
Simon Glass204675c2019-12-29 21:19:25 -0700541 devres-test {
542 compatible = "denx,u-boot-devres-test";
543 };
544
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530545 another-test {
546 reg = <0 2>;
547 compatible = "denx,u-boot-fdt-test";
548 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
549 test5-gpios = <&gpio_a 19>;
550 };
551
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100552 mmio-bus@0 {
553 #address-cells = <1>;
554 #size-cells = <1>;
555 compatible = "denx,u-boot-test-bus";
556 dma-ranges = <0x10000000 0x00000000 0x00040000>;
557
558 subnode@0 {
559 compatible = "denx,u-boot-fdt-test";
560 };
561 };
562
563 mmio-bus@1 {
564 #address-cells = <1>;
565 #size-cells = <1>;
566 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100567
568 subnode@0 {
569 compatible = "denx,u-boot-fdt-test";
570 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100571 };
572
Simon Glass3c601b12020-07-07 13:12:06 -0600573 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600574 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600575 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600576 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600577 child {
578 compatible = "denx,u-boot-acpi-test";
579 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600580 };
581
Simon Glass3c601b12020-07-07 13:12:06 -0600582 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600583 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600584 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600585 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600586 };
587
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200588 clocks {
589 clk_fixed: clk-fixed {
590 compatible = "fixed-clock";
591 #clock-cells = <0>;
592 clock-frequency = <1234>;
593 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000594
595 clk_fixed_factor: clk-fixed-factor {
596 compatible = "fixed-factor-clock";
597 #clock-cells = <0>;
598 clock-div = <3>;
599 clock-mult = <2>;
600 clocks = <&clk_fixed>;
601 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200602
603 osc {
604 compatible = "fixed-clock";
605 #clock-cells = <0>;
606 clock-frequency = <20000000>;
607 };
Stephen Warrena9622432016-06-17 09:44:00 -0600608 };
609
610 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600611 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600612 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200613 assigned-clocks = <&clk_sandbox 3>;
614 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600615 };
616
617 clk-test {
618 compatible = "sandbox,clk-test";
619 clocks = <&clk_fixed>,
620 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200621 <&clk_sandbox 0>,
622 <&clk_sandbox 3>,
623 <&clk_sandbox 2>;
624 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600625 };
626
Ashok Reddy Soma8f03cef2023-08-30 10:31:42 +0200627 clk-test2 {
628 compatible = "sandbox,clk-test";
629 assigned-clock-rates = <321>;
630 };
631
632 clk-test3 {
633 compatible = "sandbox,clk-test";
634 assigned-clocks = <&clk_sandbox 1>;
635 };
636
637 clk-test4 {
638 compatible = "sandbox,clk-test";
639 assigned-clock-rates = <654>, <321>;
640 assigned-clocks = <&clk_sandbox 1>;
641 };
642
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200643 ccf: clk-ccf {
644 compatible = "sandbox,clk-ccf";
645 };
646
Simon Glass507ab962021-12-04 08:56:31 -0700647 efi-media {
648 compatible = "sandbox,efi-media";
649 };
650
Simon Glass5b968632015-05-22 15:42:15 -0600651 eth@10002000 {
652 compatible = "sandbox,eth";
653 reg = <0x10002000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600654 };
655
656 eth_5: eth@10003000 {
657 compatible = "sandbox,eth";
658 reg = <0x10003000 0x1000>;
Sean Anderson13652b82022-05-05 13:11:44 -0400659 nvmem-cells = <&eth5_addr>;
660 nvmem-cell-names = "mac-address";
Simon Glass5b968632015-05-22 15:42:15 -0600661 };
662
Bin Meng04a11cb2015-08-27 22:25:53 -0700663 eth_3: sbe5 {
664 compatible = "sandbox,eth";
665 reg = <0x10005000 0x1000>;
Sean Andersone2dc0e62022-05-05 13:11:42 -0400666 nvmem-cells = <&eth3_addr>;
667 nvmem-cell-names = "mac-address";
Bin Meng04a11cb2015-08-27 22:25:53 -0700668 };
669
Simon Glass5b968632015-05-22 15:42:15 -0600670 eth@10004000 {
671 compatible = "sandbox,eth";
672 reg = <0x10004000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600673 };
674
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200675 phy_eth0: phy-test-eth {
676 compatible = "sandbox,eth";
677 reg = <0x10007000 0x1000>;
Sean Anderson24b1b8d2022-05-05 13:11:35 -0400678 mac-address = [ 02 00 11 22 33 49 ];
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200679 phy-handle = <&ethphy1>;
Marek BehĂșnbc194772022-04-07 00:33:01 +0200680 phy-mode = "2500base-x";
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200681 };
682
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800683 dsa_eth0: dsa-test-eth {
684 compatible = "sandbox,eth";
685 reg = <0x10006000 0x1000>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400686 nvmem-cells = <&eth4_addr>;
687 nvmem-cell-names = "mac-address";
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800688 };
689
690 dsa-test {
691 compatible = "sandbox,dsa";
692
693 ports {
694 #address-cells = <1>;
695 #size-cells = <0>;
696 swp_0: port@0 {
697 reg = <0>;
698 label = "lan0";
699 phy-mode = "rgmii-rxid";
700
701 fixed-link {
702 speed = <100>;
703 full-duplex;
704 };
705 };
706
707 swp_1: port@1 {
708 reg = <1>;
709 label = "lan1";
710 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800711 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800712 };
713
714 port@2 {
715 reg = <2>;
716 ethernet = <&dsa_eth0>;
717
718 fixed-link {
719 speed = <1000>;
720 full-duplex;
721 };
722 };
723 };
724 };
725
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700726 firmware {
727 sandbox_firmware: sandbox-firmware {
728 compatible = "sandbox,firmware";
729 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200730
Etienne Carriere09665cb2022-02-21 09:22:39 +0100731 scmi {
Etienne Carriere02fd1262020-09-09 18:44:00 +0200732 compatible = "sandbox,scmi-agent";
733 #address-cells = <1>;
734 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200735
AKASHI Takahiro535a7bd2023-10-16 14:39:45 +0900736 pwrdom_scmi: protocol@11 {
737 reg = <0x11>;
738 #power-domain-cells = <1>;
739 };
740
Etienne Carriere09665cb2022-02-21 09:22:39 +0100741 clk_scmi: protocol@14 {
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200742 reg = <0x14>;
743 #clock-cells = <1>;
AKASHI Takahirocc4ecda2023-10-11 19:06:59 +0900744 linaro,sandbox-channel-id = <0x14>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200745 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200746
Etienne Carriere09665cb2022-02-21 09:22:39 +0100747 reset_scmi: protocol@16 {
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200748 reg = <0x16>;
749 #reset-cells = <1>;
750 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100751
752 protocol@17 {
753 reg = <0x17>;
754
755 regulators {
756 #address-cells = <1>;
757 #size-cells = <0>;
758
Etienne Carriere09665cb2022-02-21 09:22:39 +0100759 regul0_scmi: reg@0 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100760 reg = <0>;
761 regulator-name = "sandbox-voltd0";
762 regulator-min-microvolt = <1100000>;
763 regulator-max-microvolt = <3300000>;
764 };
Etienne Carriere09665cb2022-02-21 09:22:39 +0100765 regul1_scmi: reg@1 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100766 reg = <0x1>;
767 regulator-name = "sandbox-voltd1";
768 regulator-min-microvolt = <1800000>;
769 };
770 };
771 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200772 };
Alexey Romanov9dc617d2023-09-21 11:13:36 +0300773
774 sm: secure-monitor {
775 compatible = "sandbox,sm";
776 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700777 };
778
Alexander Dahl6ac319d2022-09-30 14:04:30 +0200779 fpga {
780 compatible = "sandbox,fpga";
781 };
782
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100783 pinctrl-gpio {
784 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700785
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100786 gpio_a: base-gpios {
787 compatible = "sandbox,gpio";
788 gpio-controller;
789 #gpio-cells = <1>;
790 gpio-bank-name = "a";
791 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200792 hog_input_active_low {
793 gpio-hog;
794 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200795 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200796 };
797 hog_input_active_high {
798 gpio-hog;
799 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200800 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200801 };
802 hog_output_low {
803 gpio-hog;
804 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200805 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200806 };
807 hog_output_high {
808 gpio-hog;
809 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200810 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200811 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100812 };
813
814 gpio_b: extra-gpios {
815 compatible = "sandbox,gpio";
816 gpio-controller;
817 #gpio-cells = <5>;
818 gpio-bank-name = "b";
819 sandbox,gpio-count = <10>;
820 };
Simon Glass25348a42014-10-13 23:42:11 -0600821
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100822 gpio_c: pinmux-gpios {
823 compatible = "sandbox,gpio";
824 gpio-controller;
825 #gpio-cells = <2>;
826 gpio-bank-name = "c";
827 sandbox,gpio-count = <10>;
828 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100829 };
830
Simon Glass7df766e2014-12-10 08:55:55 -0700831 i2c@0 {
832 #address-cells = <1>;
833 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600834 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700835 compatible = "sandbox,i2c";
836 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200837 pinctrl-names = "default";
838 pinctrl-0 = <&pinmux_i2c0_pins>;
839
Simon Glass7df766e2014-12-10 08:55:55 -0700840 eeprom@2c {
Sean Andersone2dc0e62022-05-05 13:11:42 -0400841 #address-cells = <1>;
842 #size-cells = <1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700843 reg = <0x2c>;
844 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700845 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200846 partitions {
847 compatible = "fixed-partitions";
848 #address-cells = <1>;
849 #size-cells = <1>;
850 bootcount_i2c: bootcount@10 {
851 reg = <10 2>;
852 };
853 };
Sean Andersone2dc0e62022-05-05 13:11:42 -0400854
855 eth3_addr: mac-address@24 {
856 reg = <24 6>;
857 };
Simon Glass7df766e2014-12-10 08:55:55 -0700858 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200859
Simon Glass336b2952015-05-22 15:42:17 -0600860 rtc_0: rtc@43 {
Sean Anderson5768e8b2022-05-05 13:11:43 -0400861 #address-cells = <1>;
862 #size-cells = <1>;
Simon Glass336b2952015-05-22 15:42:17 -0600863 reg = <0x43>;
864 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700865 sandbox,emul = <&emul0>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400866
867 eth4_addr: mac-address@40 {
868 reg = <0x40 6>;
869 };
Simon Glass336b2952015-05-22 15:42:17 -0600870 };
871
872 rtc_1: rtc@61 {
873 reg = <0x61>;
874 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700875 sandbox,emul = <&emul1>;
876 };
877
878 i2c_emul: emul {
879 reg = <0xff>;
880 compatible = "sandbox,i2c-emul-parent";
881 emul_eeprom: emul-eeprom {
882 compatible = "sandbox,i2c-eeprom";
883 sandbox,filename = "i2c.bin";
884 sandbox,size = <256>;
885 };
886 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700887 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700888 };
889 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700890 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600891 };
892 };
893
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200894 sandbox_pmic: sandbox_pmic {
895 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700896 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200897 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200898
899 mc34708: pmic@41 {
900 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700901 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200902 };
Simon Glass7df766e2014-12-10 08:55:55 -0700903 };
904
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100905 bootcount@0 {
906 compatible = "u-boot,bootcount-rtc";
907 rtc = <&rtc_1>;
908 offset = <0x13>;
909 };
910
Michal Simek4f18f922020-05-28 11:48:55 +0200911 bootcount {
912 compatible = "u-boot,bootcount-i2c-eeprom";
913 i2c-eeprom = <&bootcount_i2c>;
914 };
915
Nandor Han88895812021-06-10 15:40:38 +0300916 bootcount_4@0 {
917 compatible = "u-boot,bootcount-syscon";
918 syscon = <&syscon0>;
919 reg = <0x0 0x04>, <0x0 0x04>;
920 reg-names = "syscon_reg", "offset";
921 };
922
923 bootcount_2@0 {
924 compatible = "u-boot,bootcount-syscon";
925 syscon = <&syscon0>;
926 reg = <0x0 0x04>, <0x0 0x02> ;
927 reg-names = "syscon_reg", "offset";
928 };
929
Marek Szyprowskiad398592021-02-18 11:33:18 +0100930 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100931 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100932 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100933 vdd-supply = <&buck2>;
934 vss-microvolts = <0>;
935 };
936
Mark Kettenis67748ee2021-10-23 16:58:02 +0200937 iommu: iommu@0 {
938 compatible = "sandbox,iommu";
939 #iommu-cells = <0>;
940 };
941
Simon Glass515dcff2020-02-06 09:55:00 -0700942 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700943 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700944 interrupt-controller;
945 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700946 };
947
Simon Glass90b6fef2016-01-18 19:52:26 -0700948 lcd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700949 bootph-all;
Simon Glass90b6fef2016-01-18 19:52:26 -0700950 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200951 pinctrl-names = "default";
952 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700953 xres = <1366>;
954 yres = <768>;
955 };
956
Simon Glassd783eb32015-07-06 12:54:34 -0600957 leds {
958 compatible = "gpio-leds";
959
960 iracibble {
961 gpios = <&gpio_a 1 0>;
962 label = "sandbox:red";
963 };
964
965 martinet {
966 gpios = <&gpio_a 2 0>;
967 label = "sandbox:green";
968 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200969
970 default_on {
971 gpios = <&gpio_a 5 0>;
972 label = "sandbox:default_on";
973 default-state = "on";
974 };
975
976 default_off {
977 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400978 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200979 default-state = "off";
980 };
Simon Glassd783eb32015-07-06 12:54:34 -0600981 };
982
Paul Doelle709f0372022-07-04 09:00:25 +0000983 wdt-gpio-toggle {
Simon Glasse0f8cd22023-08-10 09:53:13 -0600984 gpios = <&gpio_a 8 0>;
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200985 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +0200986 hw_margin_ms = <100>;
Paul Doelle709f0372022-07-04 09:00:25 +0000987 hw_algo = "toggle";
988 always-running;
989 };
990
991 wdt-gpio-level {
992 gpios = <&gpio_a 7 0>;
993 compatible = "linux,wdt-gpio";
994 hw_margin_ms = <100>;
995 hw_algo = "level";
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200996 always-running;
997 };
998
Stephen Warren62f2c902016-05-16 17:41:37 -0600999 mbox: mbox {
1000 compatible = "sandbox,mbox";
1001 #mbox-cells = <1>;
1002 };
1003
1004 mbox-test {
1005 compatible = "sandbox,mbox-test";
1006 mboxes = <&mbox 100>, <&mbox 1>;
1007 mbox-names = "other", "test";
1008 };
1009
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001010 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001011 #address-cells = <1>;
1012 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -04001013 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001014 cpu1: cpu@1 {
1015 device_type = "cpu";
1016 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -04001017 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001018 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001019 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001020 };
Mario Sixdea5df72018-08-06 10:23:44 +02001021
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001022 cpu2: cpu@2 {
1023 device_type = "cpu";
1024 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001025 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001026 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001027 };
Mario Sixdea5df72018-08-06 10:23:44 +02001028
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001029 cpu3: cpu@3 {
1030 device_type = "cpu";
1031 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001032 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001033 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001034 };
Mario Sixdea5df72018-08-06 10:23:44 +02001035 };
1036
Dave Gerlach75dbdfc2020-07-15 23:39:58 -05001037 chipid: chipid {
1038 compatible = "sandbox,soc";
1039 };
1040
Simon Glassc953aaf2018-12-10 10:37:34 -07001041 i2s: i2s {
1042 compatible = "sandbox,i2s";
1043 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -07001044 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -07001045 };
1046
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +02001047 nop-test_0 {
1048 compatible = "sandbox,nop_sandbox1";
1049 nop-test_1 {
1050 compatible = "sandbox,nop_sandbox2";
1051 bind = "True";
1052 };
1053 nop-test_2 {
1054 compatible = "sandbox,nop_sandbox2";
1055 bind = "False";
1056 };
1057 };
1058
Roger Quadrosb0679a72022-10-20 16:30:46 +03001059 memory-controller {
1060 compatible = "sandbox,memory";
1061 };
1062
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001063 misc-test {
Sean Anderson13652b82022-05-05 13:11:44 -04001064 #address-cells = <1>;
1065 #size-cells = <1>;
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001066 compatible = "sandbox,misc_sandbox";
Sean Anderson13652b82022-05-05 13:11:44 -04001067
1068 eth5_addr: mac-address@10 {
1069 reg = <0x10 6>;
1070 };
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001071 };
1072
Simon Glasse4fef742017-04-23 20:02:07 -06001073 mmc2 {
1074 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -06001075 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -06001076 };
1077
Simon Glassb255efc2022-04-24 23:31:24 -06001078 /* This is used for the bootdev tests */
Simon Glasse4fef742017-04-23 20:02:07 -06001079 mmc1 {
1080 compatible = "sandbox,mmc";
Simon Glassb255efc2022-04-24 23:31:24 -06001081 filename = "mmc1.img";
Simon Glasse4fef742017-04-23 20:02:07 -06001082 };
1083
Simon Glassb255efc2022-04-24 23:31:24 -06001084 /* This is used for the fastboot tests */
Sughosh Ganu77079e72022-10-21 18:16:05 +05301085 mmc0: mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -06001086 compatible = "sandbox,mmc";
1087 };
1088
Simon Glassf1eba352022-10-20 18:23:20 -06001089 /* This is used for VBE VPL tests */
1090 mmc3 {
1091 status = "disabled";
1092 compatible = "sandbox,mmc";
1093 filename = "image.bin";
1094 non-removable;
1095 };
1096
Simon Glassd2bc33ed2023-01-06 08:52:41 -06001097 /* This is used for bootstd bootmenu tests */
1098 mmc4 {
1099 status = "disabled";
1100 compatible = "sandbox,mmc";
1101 filename = "mmc4.img";
1102 };
1103
Simon Glassfff928c2023-08-24 13:55:41 -06001104 /* This is used for ChromiumOS tests */
1105 mmc5 {
1106 status = "disabled";
1107 compatible = "sandbox,mmc";
1108 filename = "mmc5.img";
1109 };
1110
Alexander Gendin038cb022023-10-09 01:24:36 +00001111 /* This is used for mbr tests */
1112 mmc6 {
1113 status = "disabled";
1114 compatible = "sandbox,mmc";
1115 filename = "mmc6.img";
1116 };
1117
Simon Glass53a68b32019-02-16 20:24:50 -07001118 pch {
1119 compatible = "sandbox,pch";
1120 };
1121
Tom Rini4a3ca482020-02-11 12:41:23 -05001122 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -07001123 compatible = "sandbox,pci";
1124 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001125 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001126 #address-cells = <3>;
1127 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -06001128 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -07001129 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Mark Kettenis5dfd4ec2023-01-21 20:27:57 +01001130 iommu-map = <0x0010 &iommu 0 1>;
1131 iommu-map-mask = <0xfffffff8>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001132 pci@0,0 {
1133 compatible = "pci-generic";
1134 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001135 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001136 };
Alex Margineanf1274432019-06-07 11:24:24 +03001137 pci@1,0 {
1138 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001139 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
Simon Glass4289c262023-09-26 08:14:58 -06001140 reg = <0x02000814 0 0 0x80 0
1141 0x01000810 0 0 0xc0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001142 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +03001143 };
Simon Glass937bb472019-12-06 21:41:57 -07001144 p2sb-pci@2,0 {
1145 compatible = "sandbox,p2sb";
1146 reg = <0x02001010 0 0 0 0>;
1147 sandbox,emul = <&p2sb_emul>;
1148
1149 adder {
1150 intel,p2sb-port-id = <3>;
1151 compatible = "sandbox,adder";
1152 };
1153 };
Simon Glass8c501022019-12-06 21:41:54 -07001154 pci@1e,0 {
1155 compatible = "sandbox,pmc";
1156 reg = <0xf000 0 0 0 0>;
1157 sandbox,emul = <&pmc_emul1e>;
1158 acpi-base = <0x400>;
1159 gpe0-dwx-mask = <0xf>;
1160 gpe0-dwx-shift-base = <4>;
1161 gpe0-dw = <6 7 9>;
1162 gpe0-sts = <0x20>;
1163 gpe0-en = <0x30>;
1164 };
Simon Glass3a6eae62015-03-05 12:25:34 -07001165 pci@1f,0 {
1166 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001167 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
Simon Glass4289c262023-09-26 08:14:58 -06001168 reg = <0x0100f810 0 0 0x100 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001169 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001170 };
1171 };
1172
Simon Glassb98ba4c2019-09-25 08:56:10 -06001173 pci-emul0 {
1174 compatible = "sandbox,pci-emul-parent";
1175 swap_case_emul0_0: emul0@0,0 {
1176 compatible = "sandbox,swap-case";
1177 };
1178 swap_case_emul0_1: emul0@1,0 {
1179 compatible = "sandbox,swap-case";
1180 use-ea;
1181 };
1182 swap_case_emul0_1f: emul0@1f,0 {
1183 compatible = "sandbox,swap-case";
1184 };
Simon Glass937bb472019-12-06 21:41:57 -07001185 p2sb_emul: emul@2,0 {
1186 compatible = "sandbox,p2sb-emul";
1187 };
Simon Glass8c501022019-12-06 21:41:54 -07001188 pmc_emul1e: emul@1e,0 {
1189 compatible = "sandbox,pmc-emul";
1190 };
Simon Glassb98ba4c2019-09-25 08:56:10 -06001191 };
1192
Tom Rini4a3ca482020-02-11 12:41:23 -05001193 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -07001194 compatible = "sandbox,pci";
1195 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001196 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -07001197 #address-cells = <3>;
1198 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001199 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scullc7456a42022-04-21 16:11:09 +00001200 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001201 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -07001202 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +02001203 0x0c 0x00 0x1234 0x5678
1204 0x10 0x00 0x1234 0x5678>;
1205 pci@10,0 {
1206 reg = <0x8000 0 0 0 0>;
1207 };
Bin Meng408e5902018-08-03 01:14:41 -07001208 };
1209
Tom Rini4a3ca482020-02-11 12:41:23 -05001210 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -07001211 compatible = "sandbox,pci";
1212 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001213 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -07001214 #address-cells = <3>;
1215 #size-cells = <2>;
1216 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1217 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1218 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1219 pci@1f,0 {
1220 compatible = "pci-generic";
1221 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001222 sandbox,emul = <&swap_case_emul2_1f>;
1223 };
1224 };
1225
1226 pci-emul2 {
1227 compatible = "sandbox,pci-emul-parent";
1228 swap_case_emul2_1f: emul2@1f,0 {
1229 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001230 };
1231 };
1232
Ramon Friedc64f19b2019-04-27 11:15:23 +03001233 pci_ep: pci_ep {
1234 compatible = "sandbox,pci_ep";
1235 };
1236
Simon Glass9c433fe2017-04-23 20:10:44 -06001237 probing {
1238 compatible = "simple-bus";
1239 test1 {
1240 compatible = "denx,u-boot-probe-test";
1241 };
1242
1243 test2 {
1244 compatible = "denx,u-boot-probe-test";
1245 };
1246
1247 test3 {
1248 compatible = "denx,u-boot-probe-test";
1249 };
1250
1251 test4 {
1252 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001253 first-syscon = <&syscon0>;
1254 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001255 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001256 };
1257 };
1258
Stephen Warren92c67fa2016-07-13 13:45:31 -06001259 pwrdom: power-domain {
1260 compatible = "sandbox,power-domain";
1261 #power-domain-cells = <1>;
1262 };
1263
1264 power-domain-test {
1265 compatible = "sandbox,power-domain-test";
1266 power-domains = <&pwrdom 2>;
1267 };
1268
Simon Glass5620cf82018-10-01 12:22:40 -06001269 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001270 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001271 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001272 pinctrl-names = "default";
1273 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001274 };
1275
1276 pwm2 {
1277 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001278 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001279 };
1280
Simon Glass3d355e62015-07-06 12:54:31 -06001281 ram {
1282 compatible = "sandbox,ram";
1283 };
1284
Simon Glassd860f222015-07-06 12:54:29 -06001285 reset@0 {
1286 compatible = "sandbox,warm-reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001287 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001288 };
1289
1290 reset@1 {
1291 compatible = "sandbox,reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001292 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001293 };
1294
Stephen Warren6488e642016-06-17 09:43:59 -06001295 resetc: reset-ctl {
1296 compatible = "sandbox,reset-ctl";
1297 #reset-cells = <1>;
1298 };
1299
1300 reset-ctl-test {
1301 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001302 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1303 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001304 };
1305
Sughosh Ganu23e37512019-12-28 23:58:31 +05301306 rng {
1307 compatible = "sandbox,sandbox-rng";
1308 };
1309
Nishanth Menonedf85812015-09-17 15:42:41 -05001310 rproc_1: rproc@1 {
1311 compatible = "sandbox,test-processor";
1312 remoteproc-name = "remoteproc-test-dev1";
1313 };
1314
1315 rproc_2: rproc@2 {
1316 compatible = "sandbox,test-processor";
1317 internal-memory-mapped;
1318 remoteproc-name = "remoteproc-test-dev2";
1319 };
1320
Simon Glass5620cf82018-10-01 12:22:40 -06001321 panel {
1322 compatible = "simple-panel";
1323 backlight = <&backlight 0 100>;
1324 };
1325
Simon Glass509f32e2022-09-21 16:21:47 +02001326 scsi {
1327 compatible = "sandbox,scsi";
1328 sandbox,filepath = "scsi.img";
1329 };
1330
Ramon Fried26ed32e2018-07-02 02:57:59 +03001331 smem@0 {
1332 compatible = "sandbox,smem";
1333 };
1334
Simon Glass76072ac2018-12-10 10:37:36 -07001335 sound {
1336 compatible = "sandbox,sound";
1337 cpu {
1338 sound-dai = <&i2s 0>;
1339 };
1340
1341 codec {
1342 sound-dai = <&audio 0>;
1343 };
1344 };
1345
Simon Glass25348a42014-10-13 23:42:11 -06001346 spi@0 {
1347 #address-cells = <1>;
1348 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001349 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001350 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001351 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001352 pinctrl-names = "default";
1353 pinctrl-0 = <&pinmux_spi0_pins>;
1354
Simon Glass25348a42014-10-13 23:42:11 -06001355 spi.bin@0 {
1356 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001357 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001358 spi-max-frequency = <40000000>;
1359 sandbox,filename = "spi.bin";
1360 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001361 spi.bin@1 {
1362 reg = <1>;
1363 compatible = "spansion,m25p16", "jedec,spi-nor";
1364 spi-max-frequency = <50000000>;
1365 sandbox,filename = "spi.bin";
1366 spi-cpol;
1367 spi-cpha;
1368 };
Simon Glass25348a42014-10-13 23:42:11 -06001369 };
1370
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001371 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001372 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001373 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001374 };
1375
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001376 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001377 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001378 reg = <0x20 5
1379 0x28 6
1380 0x30 7
1381 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001382 };
1383
Patrick Delaunayee010432019-03-07 09:57:13 +01001384 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001385 compatible = "simple-mfd", "syscon";
1386 reg = <0x40 5
1387 0x48 6
1388 0x50 7
1389 0x58 8>;
1390 };
1391
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301392 syscon3: syscon@3 {
1393 compatible = "simple-mfd", "syscon";
1394 reg = <0x000100 0x10>;
1395
1396 muxcontroller0: a-mux-controller {
1397 compatible = "mmio-mux";
1398 #mux-control-cells = <1>;
1399
1400 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1401 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1402 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1403 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1404 u-boot,mux-autoprobe;
1405 };
1406 };
1407
1408 muxcontroller1: emul-mux-controller {
1409 compatible = "mux-emul";
1410 #mux-control-cells = <0>;
1411 u-boot,mux-autoprobe;
1412 idle-state = <0xabcd>;
1413 };
1414
Simon Glass791a17f2020-12-16 21:20:27 -07001415 testfdtm0 {
1416 compatible = "denx,u-boot-fdtm-test";
1417 };
1418
1419 testfdtm1: testfdtm1 {
1420 compatible = "denx,u-boot-fdtm-test";
1421 };
1422
1423 testfdtm2 {
1424 compatible = "denx,u-boot-fdtm-test";
1425 };
1426
Sean Anderson79d3bba2020-09-28 10:52:23 -04001427 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001428 compatible = "sandbox,timer";
1429 clock-frequency = <1000000>;
1430 };
1431
Sean Anderson79d3bba2020-09-28 10:52:23 -04001432 timer@1 {
1433 compatible = "sandbox,timer";
1434 sandbox,timebase-frequency-fallback;
1435 };
1436
Miquel Raynal80938c12018-05-15 11:57:27 +02001437 tpm2 {
1438 compatible = "sandbox,tpm2";
1439 };
1440
Simon Glasseef107e2023-02-21 06:24:51 -07001441 tpm {
1442 compatible = "google,sandbox-tpm";
1443 };
1444
Simon Glass5b968632015-05-22 15:42:15 -06001445 uart0: serial {
1446 compatible = "sandbox,serial";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001447 bootph-all;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001448 pinctrl-names = "default";
1449 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001450 };
1451
Simon Glass31680482015-03-25 12:23:05 -06001452 usb_0: usb@0 {
1453 compatible = "sandbox,usb";
1454 status = "disabled";
1455 hub {
1456 compatible = "sandbox,usb-hub";
1457 #address-cells = <1>;
1458 #size-cells = <0>;
1459 flash-stick {
1460 reg = <0>;
1461 compatible = "sandbox,usb-flash";
1462 };
1463 };
1464 };
1465
1466 usb_1: usb@1 {
1467 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001468 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001469 hub {
1470 compatible = "usb-hub";
1471 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001472 #address-cells = <1>;
1473 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001474 hub-emul {
1475 compatible = "sandbox,usb-hub";
1476 #address-cells = <1>;
1477 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001478 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001479 reg = <0>;
1480 compatible = "sandbox,usb-flash";
1481 sandbox,filepath = "testflash.bin";
1482 };
1483
Simon Glass4700fe52015-11-08 23:48:01 -07001484 flash-stick@1 {
1485 reg = <1>;
1486 compatible = "sandbox,usb-flash";
1487 sandbox,filepath = "testflash1.bin";
1488 };
1489
1490 flash-stick@2 {
1491 reg = <2>;
1492 compatible = "sandbox,usb-flash";
1493 sandbox,filepath = "testflash2.bin";
1494 };
1495
Simon Glassc0ccc722015-11-08 23:48:08 -07001496 keyb@3 {
1497 reg = <3>;
1498 compatible = "sandbox,usb-keyb";
1499 };
1500
Simon Glass31680482015-03-25 12:23:05 -06001501 };
Michael Walle7c961322020-06-02 01:47:07 +02001502
1503 usbstor@1 {
1504 reg = <1>;
1505 };
1506 usbstor@3 {
1507 reg = <3>;
1508 };
Simon Glass31680482015-03-25 12:23:05 -06001509 };
1510 };
1511
1512 usb_2: usb@2 {
1513 compatible = "sandbox,usb";
1514 status = "disabled";
1515 };
1516
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001517 spmi: spmi@0 {
1518 compatible = "sandbox,spmi";
1519 #address-cells = <0x1>;
1520 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001521 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001522 pm8916@0 {
1523 compatible = "qcom,spmi-pmic";
1524 reg = <0x0 0x1>;
1525 #address-cells = <0x1>;
1526 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001527 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001528
1529 spmi_gpios: gpios@c000 {
1530 compatible = "qcom,pm8916-gpio";
1531 reg = <0xc000 0x400>;
1532 gpio-controller;
1533 gpio-count = <4>;
1534 #gpio-cells = <2>;
1535 gpio-bank-name="spmi";
1536 };
1537 };
1538 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001539
1540 wdt0: wdt@0 {
1541 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001542 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001543 };
Rob Clarka471b672018-01-10 11:33:30 +01001544
Mario Six95922152018-08-09 14:51:19 +02001545 axi: axi@0 {
1546 compatible = "sandbox,axi";
1547 #address-cells = <0x1>;
1548 #size-cells = <0x1>;
1549 store@0 {
1550 compatible = "sandbox,sandbox_store";
1551 reg = <0x0 0x400>;
1552 };
1553 };
1554
Rob Clarka471b672018-01-10 11:33:30 +01001555 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001556 #address-cells = <1>;
1557 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001558 setting = "sunrise ohoka";
1559 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001560 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001561 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001562 chosen-test {
1563 compatible = "denx,u-boot-fdt-test";
1564 reg = <9 1>;
1565 };
1566 };
Mario Six35616ef2018-03-12 14:53:33 +01001567
1568 translation-test@8000 {
1569 compatible = "simple-bus";
1570 reg = <0x8000 0x4000>;
1571
1572 #address-cells = <0x2>;
1573 #size-cells = <0x1>;
1574
1575 ranges = <0 0x0 0x8000 0x1000
1576 1 0x100 0x9000 0x1000
1577 2 0x200 0xA000 0x1000
1578 3 0x300 0xB000 0x1000
1579 >;
1580
Fabien Dessenne22236e02019-05-31 15:11:30 +02001581 dma-ranges = <0 0x000 0x10000000 0x1000
1582 1 0x100 0x20000000 0x1000
1583 >;
1584
Mario Six35616ef2018-03-12 14:53:33 +01001585 dev@0,0 {
1586 compatible = "denx,u-boot-fdt-dummy";
1587 reg = <0 0x0 0x1000>;
Álvaro Fernåndez Rojasa3181152018-12-03 19:37:09 +01001588 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001589 };
1590
1591 dev@1,100 {
1592 compatible = "denx,u-boot-fdt-dummy";
1593 reg = <1 0x100 0x1000>;
1594
1595 };
1596
1597 dev@2,200 {
1598 compatible = "denx,u-boot-fdt-dummy";
1599 reg = <2 0x200 0x1000>;
1600 };
1601
1602
1603 noxlatebus@3,300 {
1604 compatible = "simple-bus";
1605 reg = <3 0x300 0x1000>;
1606
1607 #address-cells = <0x1>;
1608 #size-cells = <0x0>;
1609
1610 dev@42 {
1611 compatible = "denx,u-boot-fdt-dummy";
1612 reg = <0x42>;
1613 };
1614 };
1615 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001616
Dzmitry Sankouski54f4c832023-01-22 18:21:23 +03001617 ofnode-foreach {
1618 compatible = "foreach";
1619
1620 first {
1621 prop1 = <1>;
1622 prop2 = <2>;
1623 };
1624
1625 second {
1626 prop1 = <1>;
1627 prop2 = <2>;
1628 };
1629 };
1630
Mario Six02ad6fb2018-09-27 09:19:31 +02001631 osd {
1632 compatible = "sandbox,sandbox_osd";
1633 };
Tom Rinib93eea72018-09-30 18:16:51 -04001634
Jens Wiklander86afaa62018-09-25 16:40:16 +02001635 sandbox_tee {
1636 compatible = "sandbox,tee";
1637 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001638
1639 sandbox_virtio1 {
1640 compatible = "sandbox,virtio1";
Simon Glass8de5a542023-01-17 10:47:51 -07001641 virtio-type = <4>; /* rng */
Bin Meng1bb290d2018-10-15 02:21:26 -07001642 };
1643
1644 sandbox_virtio2 {
1645 compatible = "sandbox,virtio2";
1646 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001647
Simon Glass8de5a542023-01-17 10:47:51 -07001648 sandbox-virtio-blk {
1649 compatible = "sandbox,virtio1";
1650 virtio-type = <2>; /* block */
1651 };
1652
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001653 sandbox_scmi {
1654 compatible = "sandbox,scmi-devices";
AKASHI Takahiro535a7bd2023-10-16 14:39:45 +09001655 power-domains = <&pwrdom_scmi 2>;
Etienne Carrierebf1f1322022-02-21 09:22:41 +01001656 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere09665cb2022-02-21 09:22:39 +01001657 resets = <&reset_scmi 3>;
1658 regul0-supply = <&regul0_scmi>;
1659 regul1-supply = <&regul1_scmi>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001660 };
1661
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001662 pinctrl {
1663 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001664
Sean Anderson3438e3b2020-09-14 11:01:57 -04001665 pinctrl-names = "default", "alternate";
1666 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1667 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001668
Sean Anderson3438e3b2020-09-14 11:01:57 -04001669 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001670 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001671 pins = "P5";
1672 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001673 bias-pull-up;
1674 input-disable;
1675 };
1676 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001677 pins = "P6";
1678 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001679 output-high;
1680 drive-open-drain;
1681 };
1682 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001683 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001684 bias-pull-down;
1685 input-enable;
1686 };
1687 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001688 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001689 bias-disable;
1690 };
1691 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001692
1693 pinctrl_i2c: i2c {
1694 groups {
1695 groups = "I2C_UART";
1696 function = "I2C";
1697 };
1698
1699 pins {
1700 pins = "P0", "P1";
1701 drive-open-drain;
1702 };
1703 };
1704
1705 pinctrl_i2s: i2s {
1706 groups = "SPI_I2S";
1707 function = "I2S";
1708 };
1709
1710 pinctrl_spi: spi {
1711 groups = "SPI_I2S";
1712 function = "SPI";
1713
1714 cs {
1715 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1716 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1717 };
1718 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001719 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001720
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001721 pinctrl-single-no-width {
1722 compatible = "pinctrl-single";
1723 reg = <0x0000 0x238>;
1724 #pinctrl-cells = <1>;
1725 pinctrl-single,function-mask = <0x7f>;
1726 };
1727
1728 pinctrl-single-pins {
1729 compatible = "pinctrl-single";
1730 reg = <0x0000 0x238>;
1731 #pinctrl-cells = <1>;
1732 pinctrl-single,register-width = <32>;
1733 pinctrl-single,function-mask = <0x7f>;
1734
1735 pinmux_pwm_pins: pinmux_pwm_pins {
1736 pinctrl-single,pins = < 0x48 0x06 >;
1737 };
1738
1739 pinmux_spi0_pins: pinmux_spi0_pins {
1740 pinctrl-single,pins = <
1741 0x190 0x0c
1742 0x194 0x0c
1743 0x198 0x23
1744 0x19c 0x0c
1745 >;
1746 };
1747
1748 pinmux_uart0_pins: pinmux_uart0_pins {
1749 pinctrl-single,pins = <
1750 0x70 0x30
1751 0x74 0x00
1752 >;
1753 };
1754 };
1755
1756 pinctrl-single-bits {
1757 compatible = "pinctrl-single";
1758 reg = <0x0000 0x50>;
1759 #pinctrl-cells = <2>;
1760 pinctrl-single,bit-per-mux;
1761 pinctrl-single,register-width = <32>;
1762 pinctrl-single,function-mask = <0xf>;
1763
1764 pinmux_i2c0_pins: pinmux_i2c0_pins {
1765 pinctrl-single,bits = <
1766 0x10 0x00002200 0x0000ff00
1767 >;
1768 };
1769
1770 pinmux_lcd_pins: pinmux_lcd_pins {
1771 pinctrl-single,bits = <
1772 0x40 0x22222200 0xffffff00
1773 0x44 0x22222222 0xffffffff
1774 0x48 0x00000022 0x000000ff
1775 0x48 0x02000000 0x0f000000
1776 0x4c 0x02000022 0x0f0000ff
1777 >;
1778 };
1779 };
1780
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001781 hwspinlock@0 {
1782 compatible = "sandbox,hwspinlock";
1783 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001784
1785 dma: dma {
1786 compatible = "sandbox,dma";
1787 #dma-cells = <1>;
1788
1789 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1790 dma-names = "m2m", "tx0", "rx0";
1791 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001792
Alex Marginean0649be52019-07-12 10:13:53 +03001793 /*
1794 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1795 * end of the test. If parent mdio is removed first, clean-up of the
1796 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1797 * active at the end of the test. That it turn doesn't allow the mdio
1798 * class to be destroyed, triggering an error.
1799 */
1800 mdio-mux-test {
1801 compatible = "sandbox,mdio-mux";
1802 #address-cells = <1>;
1803 #size-cells = <0>;
1804 mdio-parent-bus = <&mdio>;
1805
1806 mdio-ch-test@0 {
1807 reg = <0>;
1808 };
1809 mdio-ch-test@1 {
1810 reg = <1>;
1811 };
1812 };
1813
1814 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001815 compatible = "sandbox,mdio";
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +02001816 #address-cells = <1>;
1817 #size-cells = <0>;
1818
1819 ethphy1: ethernet-phy@1 {
1820 reg = <1>;
1821 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001822 };
Sean Andersonb7860542020-06-24 06:41:12 -04001823
1824 pm-bus-test {
1825 compatible = "simple-pm-bus";
1826 clocks = <&clk_sandbox 4>;
1827 power-domains = <&pwrdom 1>;
1828 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001829
1830 resetc2: syscon-reset {
1831 compatible = "syscon-reset";
1832 #reset-cells = <1>;
1833 regmap = <&syscon0>;
1834 offset = <1>;
1835 mask = <0x27FFFFFF>;
1836 assert-high = <0>;
1837 };
1838
1839 syscon-reset-test {
1840 compatible = "sandbox,misc_sandbox";
1841 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1842 reset-names = "valid", "no_mask", "out_of_range";
1843 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301844
Simon Glass458b66a2020-11-05 06:32:05 -07001845 sysinfo {
1846 compatible = "sandbox,sysinfo-sandbox";
1847 };
1848
Sean Anderson1c830672021-04-20 10:50:58 -04001849 sysinfo-gpio {
1850 compatible = "gpio-sysinfo";
1851 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1852 revisions = <19>, <5>;
1853 names = "rev_a", "foo";
1854 };
1855
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301856 some_regmapped-bus {
1857 #address-cells = <0x1>;
1858 #size-cells = <0x1>;
1859
1860 ranges = <0x0 0x0 0x10>;
1861 compatible = "simple-bus";
1862
1863 regmap-test_0 {
1864 reg = <0 0x10>;
1865 compatible = "sandbox,regmap_test";
1866 };
1867 };
Robert Marko9cf87122022-09-06 13:30:35 +02001868
1869 thermal {
1870 compatible = "sandbox,thermal";
1871 };
Sughosh Ganu77079e72022-10-21 18:16:05 +05301872
1873 fwu-mdata {
1874 compatible = "u-boot,fwu-mdata-gpt";
1875 fwu-mdata-store = <&mmc0>;
1876 };
Abdellatif El Khlifi6b005872023-04-17 10:11:55 +01001877
1878 nvmxip-qspi1@08000000 {
1879 compatible = "nvmxip,qspi";
1880 reg = <0x08000000 0x00200000>;
1881 lba_shift = <9>;
1882 lba = <4096>;
1883 };
1884
1885 nvmxip-qspi2@08200000 {
1886 compatible = "nvmxip,qspi";
1887 reg = <0x08200000 0x00100000>;
1888 lba_shift = <9>;
1889 lba = <2048>;
1890 };
Svyatoslav Ryhel669f5c82023-04-25 10:57:21 +03001891
1892 extcon {
1893 compatible = "sandbox,extcon";
1894 };
Abdellatif El Khlifi4970d5b2023-08-04 14:33:41 +01001895
1896 arm-ffa-emul {
1897 compatible = "sandbox,arm-ffa-emul";
1898
1899 sandbox-arm-ffa {
1900 compatible = "sandbox,arm-ffa";
1901 };
1902 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001903};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001904
1905#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001906#include "cros-ec-keyboard.dtsi"
Simon Glass5e135d32022-10-20 18:23:15 -06001907
1908#ifdef CONFIG_SANDBOX_VPL
1909#include "sandbox_vpl.dtsi"
1910#endif
Simon Glass61300722023-06-01 10:23:01 -06001911
1912#include "cedit.dtsi"