blob: 2cea4a43c8772453423427270fa2043ec7304dff [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay23aee612020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010017
Simon Glassb2c1cac2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070023
Simon Glassfef72b72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -060031 gpio1 = &gpio_a;
32 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010033 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070034 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060035 mmc0 = "/mmc0";
36 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070037 pci0 = &pci0;
38 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070039 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020040 remoteproc0 = &rproc_1;
41 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060042 rtc0 = &rtc_0;
43 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060044 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020045 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070046 testbus3 = "/some-bus";
47 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070048 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070049 testfdt3 = "/b-test";
50 testfdt5 = "/some-bus/c-test@5";
51 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070052 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020053 fdt-dummy0 = "/translation-test@8000/dev@0,0";
54 fdt-dummy1 = "/translation-test@8000/dev@1,100";
55 fdt-dummy2 = "/translation-test@8000/dev@2,200";
56 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060057 usb0 = &usb_0;
58 usb1 = &usb_1;
59 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020060 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020061 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060062 };
63
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020064 config {
Simon Glass0034d962021-08-07 07:24:01 -060065 testing-bool;
66 testing-int = <123>;
67 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020068 environment {
69 from_fdt = "yes";
70 fdt_env_path = "";
71 };
72 };
73
Nandor Han6521e5d2021-06-10 16:56:44 +030074 reboot-mode0 {
75 compatible = "reboot-mode-gpio";
76 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
77 u-boot,env-variable = "bootstatus";
78 mode-test = <0x01>;
79 mode-download = <0x03>;
80 };
81
Nandor Han7e4067a2021-06-10 16:56:45 +030082 reboot_mode1: reboot-mode@14 {
83 compatible = "reboot-mode-rtc";
84 rtc = <&rtc_0>;
85 reg = <0x30 4>;
86 u-boot,env-variable = "bootstatus";
87 big-endian;
88 mode-test = <0x21969147>;
89 mode-download = <0x51939147>;
90 };
91
Simon Glassed96cde2018-12-10 10:37:33 -070092 audio: audio-codec {
93 compatible = "sandbox,audio-codec";
94 #sound-dai-cells = <1>;
95 };
96
Philippe Reynes1ee26482020-07-24 18:19:51 +020097 buttons {
98 compatible = "gpio-keys";
99
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200100 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200101 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200102 label = "button1";
Philippe Reynes1ee26482020-07-24 18:19:51 +0200103 };
104
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200105 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200106 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200107 label = "button2";
Philippe Reynes1ee26482020-07-24 18:19:51 +0200108 };
109 };
110
Marek Szyprowskiad398592021-02-18 11:33:18 +0100111 buttons2 {
112 compatible = "adc-keys";
113 io-channels = <&adc 3>;
114 keyup-threshold-microvolt = <3000000>;
115
116 button-up {
117 label = "button3";
118 linux,code = <KEY_F3>;
119 press-threshold-microvolt = <1500000>;
120 };
121
122 button-down {
123 label = "button4";
124 linux,code = <KEY_F4>;
125 press-threshold-microvolt = <1000000>;
126 };
127
128 button-enter {
129 label = "button5";
130 linux,code = <KEY_F5>;
131 press-threshold-microvolt = <500000>;
132 };
133 };
134
Simon Glassc953aaf2018-12-10 10:37:34 -0700135 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600136 reg = <0 0>;
137 compatible = "google,cros-ec-sandbox";
138
139 /*
140 * This describes the flash memory within the EC. Note
141 * that the STM32L flash erases to 0, not 0xff.
142 */
143 flash {
144 image-pos = <0x08000000>;
145 size = <0x20000>;
146 erase-value = <0>;
147
148 /* Information for sandbox */
149 ro {
150 image-pos = <0>;
151 size = <0xf000>;
152 };
153 wp-ro {
154 image-pos = <0xf000>;
155 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700156 used = <0x884>;
157 compress = "lz4";
158 uncomp-size = <0xcf8>;
159 hash {
160 algo = "sha256";
161 value = [00 01 02 03 04 05 06 07
162 08 09 0a 0b 0c 0d 0e 0f
163 10 11 12 13 14 15 16 17
164 18 19 1a 1b 1c 1d 1e 1f];
165 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600166 };
167 rw {
168 image-pos = <0x10000>;
169 size = <0x10000>;
170 };
171 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300172
173 cros_ec_pwm: cros-ec-pwm {
174 compatible = "google,cros-ec-pwm";
175 #pwm-cells = <1>;
176 };
177
Simon Glass699c9ca2018-10-01 12:22:08 -0600178 };
179
Yannick Fertré9712c822019-10-07 15:29:05 +0200180 dsi_host: dsi_host {
181 compatible = "sandbox,dsi-host";
182 };
183
Simon Glassb2c1cac2014-02-26 15:59:21 -0700184 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600185 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700186 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600187 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700188 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600189 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100190 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
191 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700192 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100193 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
194 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
195 <&gpio_b 7 GPIO_IN 3 2 1>,
196 <&gpio_b 8 GPIO_OUT 3 2 1>,
197 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100198 test3-gpios =
199 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
200 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
201 <&gpio_c 2 GPIO_OUT>,
202 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
203 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200204 <&gpio_c 5 GPIO_IN>,
205 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
206 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530207 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
208 test5-gpios = <&gpio_a 19>;
209
Simon Glass6df01f92018-12-10 10:37:37 -0700210 int-value = <1234>;
211 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200212 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200213 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600214 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700215 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600216 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200217 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530218
219 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
220 <&muxcontroller0 2>, <&muxcontroller0 3>,
221 <&muxcontroller1>;
222 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
223 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100224 display-timings {
225 timing0: 240x320 {
226 clock-frequency = <6500000>;
227 hactive = <240>;
228 vactive = <320>;
229 hfront-porch = <6>;
230 hback-porch = <7>;
231 hsync-len = <1>;
232 vback-porch = <5>;
233 vfront-porch = <8>;
234 vsync-len = <2>;
235 hsync-active = <1>;
236 vsync-active = <0>;
237 de-active = <1>;
238 pixelclk-active = <1>;
239 interlaced;
240 doublescan;
241 doubleclk;
242 };
243 timing1: 480x800 {
244 clock-frequency = <9000000>;
245 hactive = <480>;
246 vactive = <800>;
247 hfront-porch = <10>;
248 hback-porch = <59>;
249 hsync-len = <12>;
250 vback-porch = <15>;
251 vfront-porch = <17>;
252 vsync-len = <16>;
253 hsync-active = <0>;
254 vsync-active = <1>;
255 de-active = <0>;
256 pixelclk-active = <0>;
257 };
258 timing2: 800x480 {
259 clock-frequency = <33500000>;
260 hactive = <800>;
261 vactive = <480>;
262 hback-porch = <89>;
263 hfront-porch = <164>;
264 vback-porch = <23>;
265 vfront-porch = <10>;
266 hsync-len = <11>;
267 vsync-len = <13>;
268 };
269 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700270 };
271
272 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600273 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700274 compatible = "not,compatible";
275 };
276
277 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600278 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700279 };
280
Simon Glass5620cf82018-10-01 12:22:40 -0600281 backlight: backlight {
282 compatible = "pwm-backlight";
283 enable-gpios = <&gpio_a 1>;
284 power-supply = <&ldo_1>;
285 pwms = <&pwm 0 1000>;
286 default-brightness-level = <5>;
287 brightness-levels = <0 16 32 64 128 170 202 234 255>;
288 };
289
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200290 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200291 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200292 bind-test-child1 {
293 compatible = "sandbox,phy";
294 #phy-cells = <1>;
295 };
296
297 bind-test-child2 {
298 compatible = "simple-bus";
299 };
300 };
301
Simon Glassb2c1cac2014-02-26 15:59:21 -0700302 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600303 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700304 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600305 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700306 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530307
308 mux-controls = <&muxcontroller0 0>;
309 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700310 };
311
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200312 phy_provider0: gen_phy@0 {
313 compatible = "sandbox,phy";
314 #phy-cells = <1>;
315 };
316
317 phy_provider1: gen_phy@1 {
318 compatible = "sandbox,phy";
319 #phy-cells = <0>;
320 broken;
321 };
322
developer71092972020-05-02 11:35:12 +0200323 phy_provider2: gen_phy@2 {
324 compatible = "sandbox,phy";
325 #phy-cells = <0>;
326 };
327
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200328 gen_phy_user: gen_phy_user {
329 compatible = "simple-bus";
330 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
331 phy-names = "phy1", "phy2", "phy3";
332 };
333
developer71092972020-05-02 11:35:12 +0200334 gen_phy_user1: gen_phy_user1 {
335 compatible = "simple-bus";
336 phys = <&phy_provider0 0>, <&phy_provider2>;
337 phy-names = "phy1", "phy2";
338 };
339
Simon Glassb2c1cac2014-02-26 15:59:21 -0700340 some-bus {
341 #address-cells = <1>;
342 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600343 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600344 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600345 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700346 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600347 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700348 compatible = "denx,u-boot-fdt-test";
349 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600350 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700351 ping-add = <5>;
352 };
Simon Glass40717422014-07-23 06:55:18 -0600353 c-test@0 {
354 compatible = "denx,u-boot-fdt-test";
355 reg = <0>;
356 ping-expect = <6>;
357 ping-add = <6>;
358 };
359 c-test@1 {
360 compatible = "denx,u-boot-fdt-test";
361 reg = <1>;
362 ping-expect = <7>;
363 ping-add = <7>;
364 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700365 };
366
367 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600368 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600369 ping-expect = <6>;
370 ping-add = <6>;
371 compatible = "google,another-fdt-test";
372 };
373
374 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600375 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600376 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700377 ping-add = <6>;
378 compatible = "google,another-fdt-test";
379 };
380
Simon Glass0ccb0972015-01-25 08:27:05 -0700381 f-test {
382 compatible = "denx,u-boot-fdt-test";
383 };
384
385 g-test {
386 compatible = "denx,u-boot-fdt-test";
387 };
388
Bin Mengd9d24782018-10-10 22:07:01 -0700389 h-test {
390 compatible = "denx,u-boot-fdt-test1";
391 };
392
developercf8bc132020-05-02 11:35:10 +0200393 i-test {
394 compatible = "mediatek,u-boot-fdt-test";
395 #address-cells = <1>;
396 #size-cells = <0>;
397
398 subnode@0 {
399 reg = <0>;
400 };
401
402 subnode@1 {
403 reg = <1>;
404 };
405
406 subnode@2 {
407 reg = <2>;
408 };
409 };
410
Simon Glass204675c2019-12-29 21:19:25 -0700411 devres-test {
412 compatible = "denx,u-boot-devres-test";
413 };
414
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530415 another-test {
416 reg = <0 2>;
417 compatible = "denx,u-boot-fdt-test";
418 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
419 test5-gpios = <&gpio_a 19>;
420 };
421
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100422 mmio-bus@0 {
423 #address-cells = <1>;
424 #size-cells = <1>;
425 compatible = "denx,u-boot-test-bus";
426 dma-ranges = <0x10000000 0x00000000 0x00040000>;
427
428 subnode@0 {
429 compatible = "denx,u-boot-fdt-test";
430 };
431 };
432
433 mmio-bus@1 {
434 #address-cells = <1>;
435 #size-cells = <1>;
436 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100437
438 subnode@0 {
439 compatible = "denx,u-boot-fdt-test";
440 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100441 };
442
Simon Glass3c601b12020-07-07 13:12:06 -0600443 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600444 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600445 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600446 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600447 child {
448 compatible = "denx,u-boot-acpi-test";
449 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600450 };
451
Simon Glass3c601b12020-07-07 13:12:06 -0600452 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600453 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600454 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600455 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600456 };
457
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200458 clocks {
459 clk_fixed: clk-fixed {
460 compatible = "fixed-clock";
461 #clock-cells = <0>;
462 clock-frequency = <1234>;
463 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000464
465 clk_fixed_factor: clk-fixed-factor {
466 compatible = "fixed-factor-clock";
467 #clock-cells = <0>;
468 clock-div = <3>;
469 clock-mult = <2>;
470 clocks = <&clk_fixed>;
471 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200472
473 osc {
474 compatible = "fixed-clock";
475 #clock-cells = <0>;
476 clock-frequency = <20000000>;
477 };
Stephen Warrena9622432016-06-17 09:44:00 -0600478 };
479
480 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600481 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600482 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200483 assigned-clocks = <&clk_sandbox 3>;
484 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600485 };
486
487 clk-test {
488 compatible = "sandbox,clk-test";
489 clocks = <&clk_fixed>,
490 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200491 <&clk_sandbox 0>,
492 <&clk_sandbox 3>,
493 <&clk_sandbox 2>;
494 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600495 };
496
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200497 ccf: clk-ccf {
498 compatible = "sandbox,clk-ccf";
499 };
500
Simon Glass507ab962021-12-04 08:56:31 -0700501 efi-media {
502 compatible = "sandbox,efi-media";
503 };
504
Simon Glass5b968632015-05-22 15:42:15 -0600505 eth@10002000 {
506 compatible = "sandbox,eth";
507 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500508 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600509 };
510
511 eth_5: eth@10003000 {
512 compatible = "sandbox,eth";
513 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500514 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600515 };
516
Bin Meng04a11cb2015-08-27 22:25:53 -0700517 eth_3: sbe5 {
518 compatible = "sandbox,eth";
519 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500520 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700521 };
522
Simon Glass5b968632015-05-22 15:42:15 -0600523 eth@10004000 {
524 compatible = "sandbox,eth";
525 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500526 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600527 };
528
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800529 dsa_eth0: dsa-test-eth {
530 compatible = "sandbox,eth";
531 reg = <0x10006000 0x1000>;
532 fake-host-hwaddr = [00 00 66 44 22 66];
533 };
534
535 dsa-test {
536 compatible = "sandbox,dsa";
537
538 ports {
539 #address-cells = <1>;
540 #size-cells = <0>;
541 swp_0: port@0 {
542 reg = <0>;
543 label = "lan0";
544 phy-mode = "rgmii-rxid";
545
546 fixed-link {
547 speed = <100>;
548 full-duplex;
549 };
550 };
551
552 swp_1: port@1 {
553 reg = <1>;
554 label = "lan1";
555 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800556 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800557 };
558
559 port@2 {
560 reg = <2>;
561 ethernet = <&dsa_eth0>;
562
563 fixed-link {
564 speed = <1000>;
565 full-duplex;
566 };
567 };
568 };
569 };
570
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700571 firmware {
572 sandbox_firmware: sandbox-firmware {
573 compatible = "sandbox,firmware";
574 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200575
576 sandbox-scmi-agent@0 {
577 compatible = "sandbox,scmi-agent";
578 #address-cells = <1>;
579 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200580
581 clk_scmi0: protocol@14 {
582 reg = <0x14>;
583 #clock-cells = <1>;
584 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200585
586 reset_scmi0: protocol@16 {
587 reg = <0x16>;
588 #reset-cells = <1>;
589 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100590
591 protocol@17 {
592 reg = <0x17>;
593
594 regulators {
595 #address-cells = <1>;
596 #size-cells = <0>;
597
598 regul0_scmi0: reg@0 {
599 reg = <0>;
600 regulator-name = "sandbox-voltd0";
601 regulator-min-microvolt = <1100000>;
602 regulator-max-microvolt = <3300000>;
603 };
604 regul1_scmi0: reg@1 {
605 reg = <0x1>;
606 regulator-name = "sandbox-voltd1";
607 regulator-min-microvolt = <1800000>;
608 };
609 };
610 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200611 };
612
613 sandbox-scmi-agent@1 {
614 compatible = "sandbox,scmi-agent";
615 #address-cells = <1>;
616 #size-cells = <0>;
617
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200618 clk_scmi1: protocol@14 {
619 reg = <0x14>;
620 #clock-cells = <1>;
621 };
622
Etienne Carriere02fd1262020-09-09 18:44:00 +0200623 protocol@10 {
624 reg = <0x10>;
625 };
626 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700627 };
628
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100629 pinctrl-gpio {
630 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700631
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100632 gpio_a: base-gpios {
633 compatible = "sandbox,gpio";
634 gpio-controller;
635 #gpio-cells = <1>;
636 gpio-bank-name = "a";
637 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200638 hog_input_active_low {
639 gpio-hog;
640 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200641 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200642 };
643 hog_input_active_high {
644 gpio-hog;
645 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200646 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200647 };
648 hog_output_low {
649 gpio-hog;
650 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200651 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200652 };
653 hog_output_high {
654 gpio-hog;
655 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200656 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200657 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100658 };
659
660 gpio_b: extra-gpios {
661 compatible = "sandbox,gpio";
662 gpio-controller;
663 #gpio-cells = <5>;
664 gpio-bank-name = "b";
665 sandbox,gpio-count = <10>;
666 };
Simon Glass25348a42014-10-13 23:42:11 -0600667
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100668 gpio_c: pinmux-gpios {
669 compatible = "sandbox,gpio";
670 gpio-controller;
671 #gpio-cells = <2>;
672 gpio-bank-name = "c";
673 sandbox,gpio-count = <10>;
674 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100675 };
676
Simon Glass7df766e2014-12-10 08:55:55 -0700677 i2c@0 {
678 #address-cells = <1>;
679 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600680 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700681 compatible = "sandbox,i2c";
682 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200683 pinctrl-names = "default";
684 pinctrl-0 = <&pinmux_i2c0_pins>;
685
Simon Glass7df766e2014-12-10 08:55:55 -0700686 eeprom@2c {
687 reg = <0x2c>;
688 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700689 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200690 partitions {
691 compatible = "fixed-partitions";
692 #address-cells = <1>;
693 #size-cells = <1>;
694 bootcount_i2c: bootcount@10 {
695 reg = <10 2>;
696 };
697 };
Simon Glass7df766e2014-12-10 08:55:55 -0700698 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200699
Simon Glass336b2952015-05-22 15:42:17 -0600700 rtc_0: rtc@43 {
701 reg = <0x43>;
702 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700703 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600704 };
705
706 rtc_1: rtc@61 {
707 reg = <0x61>;
708 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700709 sandbox,emul = <&emul1>;
710 };
711
712 i2c_emul: emul {
713 reg = <0xff>;
714 compatible = "sandbox,i2c-emul-parent";
715 emul_eeprom: emul-eeprom {
716 compatible = "sandbox,i2c-eeprom";
717 sandbox,filename = "i2c.bin";
718 sandbox,size = <256>;
719 };
720 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700721 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700722 };
723 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700724 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600725 };
726 };
727
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200728 sandbox_pmic: sandbox_pmic {
729 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700730 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200731 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200732
733 mc34708: pmic@41 {
734 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700735 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200736 };
Simon Glass7df766e2014-12-10 08:55:55 -0700737 };
738
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100739 bootcount@0 {
740 compatible = "u-boot,bootcount-rtc";
741 rtc = <&rtc_1>;
742 offset = <0x13>;
743 };
744
Michal Simek4f18f922020-05-28 11:48:55 +0200745 bootcount {
746 compatible = "u-boot,bootcount-i2c-eeprom";
747 i2c-eeprom = <&bootcount_i2c>;
748 };
749
Nandor Han88895812021-06-10 15:40:38 +0300750 bootcount_4@0 {
751 compatible = "u-boot,bootcount-syscon";
752 syscon = <&syscon0>;
753 reg = <0x0 0x04>, <0x0 0x04>;
754 reg-names = "syscon_reg", "offset";
755 };
756
757 bootcount_2@0 {
758 compatible = "u-boot,bootcount-syscon";
759 syscon = <&syscon0>;
760 reg = <0x0 0x04>, <0x0 0x02> ;
761 reg-names = "syscon_reg", "offset";
762 };
763
Marek Szyprowskiad398592021-02-18 11:33:18 +0100764 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100765 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100766 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100767 vdd-supply = <&buck2>;
768 vss-microvolts = <0>;
769 };
770
Mark Kettenis67748ee2021-10-23 16:58:02 +0200771 iommu: iommu@0 {
772 compatible = "sandbox,iommu";
773 #iommu-cells = <0>;
774 };
775
Simon Glass515dcff2020-02-06 09:55:00 -0700776 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700777 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700778 interrupt-controller;
779 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700780 };
781
Simon Glass90b6fef2016-01-18 19:52:26 -0700782 lcd {
783 u-boot,dm-pre-reloc;
784 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200785 pinctrl-names = "default";
786 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700787 xres = <1366>;
788 yres = <768>;
789 };
790
Simon Glassd783eb32015-07-06 12:54:34 -0600791 leds {
792 compatible = "gpio-leds";
793
794 iracibble {
795 gpios = <&gpio_a 1 0>;
796 label = "sandbox:red";
797 };
798
799 martinet {
800 gpios = <&gpio_a 2 0>;
801 label = "sandbox:green";
802 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200803
804 default_on {
805 gpios = <&gpio_a 5 0>;
806 label = "sandbox:default_on";
807 default-state = "on";
808 };
809
810 default_off {
811 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400812 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200813 default-state = "off";
814 };
Simon Glassd783eb32015-07-06 12:54:34 -0600815 };
816
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200817 gpio-wdt {
818 gpios = <&gpio_a 7 0>;
819 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +0200820 hw_margin_ms = <100>;
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200821 always-running;
822 };
823
Stephen Warren62f2c902016-05-16 17:41:37 -0600824 mbox: mbox {
825 compatible = "sandbox,mbox";
826 #mbox-cells = <1>;
827 };
828
829 mbox-test {
830 compatible = "sandbox,mbox-test";
831 mboxes = <&mbox 100>, <&mbox 1>;
832 mbox-names = "other", "test";
833 };
834
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900835 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200836 #address-cells = <1>;
837 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400838 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200839 cpu1: cpu@1 {
840 device_type = "cpu";
841 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400842 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900843 compatible = "sandbox,cpu_sandbox";
844 u-boot,dm-pre-reloc;
845 };
Mario Sixdea5df72018-08-06 10:23:44 +0200846
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200847 cpu2: cpu@2 {
848 device_type = "cpu";
849 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900850 compatible = "sandbox,cpu_sandbox";
851 u-boot,dm-pre-reloc;
852 };
Mario Sixdea5df72018-08-06 10:23:44 +0200853
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200854 cpu3: cpu@3 {
855 device_type = "cpu";
856 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900857 compatible = "sandbox,cpu_sandbox";
858 u-boot,dm-pre-reloc;
859 };
Mario Sixdea5df72018-08-06 10:23:44 +0200860 };
861
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500862 chipid: chipid {
863 compatible = "sandbox,soc";
864 };
865
Simon Glassc953aaf2018-12-10 10:37:34 -0700866 i2s: i2s {
867 compatible = "sandbox,i2s";
868 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700869 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700870 };
871
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200872 nop-test_0 {
873 compatible = "sandbox,nop_sandbox1";
874 nop-test_1 {
875 compatible = "sandbox,nop_sandbox2";
876 bind = "True";
877 };
878 nop-test_2 {
879 compatible = "sandbox,nop_sandbox2";
880 bind = "False";
881 };
882 };
883
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200884 misc-test {
885 compatible = "sandbox,misc_sandbox";
886 };
887
Simon Glasse4fef742017-04-23 20:02:07 -0600888 mmc2 {
889 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -0600890 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -0600891 };
892
893 mmc1 {
894 compatible = "sandbox,mmc";
895 };
896
897 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600898 compatible = "sandbox,mmc";
899 };
900
Simon Glass53a68b32019-02-16 20:24:50 -0700901 pch {
902 compatible = "sandbox,pch";
903 };
904
Tom Rini4a3ca482020-02-11 12:41:23 -0500905 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700906 compatible = "sandbox,pci";
907 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500908 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700909 #address-cells = <3>;
910 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600911 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700912 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700913 pci@0,0 {
914 compatible = "pci-generic";
915 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600916 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700917 };
Alex Margineanf1274432019-06-07 11:24:24 +0300918 pci@1,0 {
919 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600920 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
921 reg = <0x02000814 0 0 0 0
922 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600923 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300924 };
Simon Glass937bb472019-12-06 21:41:57 -0700925 p2sb-pci@2,0 {
926 compatible = "sandbox,p2sb";
927 reg = <0x02001010 0 0 0 0>;
928 sandbox,emul = <&p2sb_emul>;
929
930 adder {
931 intel,p2sb-port-id = <3>;
932 compatible = "sandbox,adder";
933 };
934 };
Simon Glass8c501022019-12-06 21:41:54 -0700935 pci@1e,0 {
936 compatible = "sandbox,pmc";
937 reg = <0xf000 0 0 0 0>;
938 sandbox,emul = <&pmc_emul1e>;
939 acpi-base = <0x400>;
940 gpe0-dwx-mask = <0xf>;
941 gpe0-dwx-shift-base = <4>;
942 gpe0-dw = <6 7 9>;
943 gpe0-sts = <0x20>;
944 gpe0-en = <0x30>;
945 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700946 pci@1f,0 {
947 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600948 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
949 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600950 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700951 };
952 };
953
Simon Glassb98ba4c2019-09-25 08:56:10 -0600954 pci-emul0 {
955 compatible = "sandbox,pci-emul-parent";
956 swap_case_emul0_0: emul0@0,0 {
957 compatible = "sandbox,swap-case";
958 };
959 swap_case_emul0_1: emul0@1,0 {
960 compatible = "sandbox,swap-case";
961 use-ea;
962 };
963 swap_case_emul0_1f: emul0@1f,0 {
964 compatible = "sandbox,swap-case";
965 };
Simon Glass937bb472019-12-06 21:41:57 -0700966 p2sb_emul: emul@2,0 {
967 compatible = "sandbox,p2sb-emul";
968 };
Simon Glass8c501022019-12-06 21:41:54 -0700969 pmc_emul1e: emul@1e,0 {
970 compatible = "sandbox,pmc-emul";
971 };
Simon Glassb98ba4c2019-09-25 08:56:10 -0600972 };
973
Tom Rini4a3ca482020-02-11 12:41:23 -0500974 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -0700975 compatible = "sandbox,pci";
976 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500977 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -0700978 #address-cells = <3>;
979 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -0700980 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
981 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
982 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700983 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200984 0x0c 0x00 0x1234 0x5678
985 0x10 0x00 0x1234 0x5678>;
986 pci@10,0 {
987 reg = <0x8000 0 0 0 0>;
988 };
Bin Meng408e5902018-08-03 01:14:41 -0700989 };
990
Tom Rini4a3ca482020-02-11 12:41:23 -0500991 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -0700992 compatible = "sandbox,pci";
993 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500994 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -0700995 #address-cells = <3>;
996 #size-cells = <2>;
997 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
998 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
999 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1000 pci@1f,0 {
1001 compatible = "pci-generic";
1002 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001003 sandbox,emul = <&swap_case_emul2_1f>;
1004 };
1005 };
1006
1007 pci-emul2 {
1008 compatible = "sandbox,pci-emul-parent";
1009 swap_case_emul2_1f: emul2@1f,0 {
1010 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001011 };
1012 };
1013
Ramon Friedc64f19b2019-04-27 11:15:23 +03001014 pci_ep: pci_ep {
1015 compatible = "sandbox,pci_ep";
1016 };
1017
Simon Glass9c433fe2017-04-23 20:10:44 -06001018 probing {
1019 compatible = "simple-bus";
1020 test1 {
1021 compatible = "denx,u-boot-probe-test";
1022 };
1023
1024 test2 {
1025 compatible = "denx,u-boot-probe-test";
1026 };
1027
1028 test3 {
1029 compatible = "denx,u-boot-probe-test";
1030 };
1031
1032 test4 {
1033 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001034 first-syscon = <&syscon0>;
1035 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001036 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001037 };
1038 };
1039
Stephen Warren92c67fa2016-07-13 13:45:31 -06001040 pwrdom: power-domain {
1041 compatible = "sandbox,power-domain";
1042 #power-domain-cells = <1>;
1043 };
1044
1045 power-domain-test {
1046 compatible = "sandbox,power-domain-test";
1047 power-domains = <&pwrdom 2>;
1048 };
1049
Simon Glass5620cf82018-10-01 12:22:40 -06001050 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001051 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001052 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001053 pinctrl-names = "default";
1054 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001055 };
1056
1057 pwm2 {
1058 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001059 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001060 };
1061
Simon Glass3d355e62015-07-06 12:54:31 -06001062 ram {
1063 compatible = "sandbox,ram";
1064 };
1065
Simon Glassd860f222015-07-06 12:54:29 -06001066 reset@0 {
1067 compatible = "sandbox,warm-reset";
1068 };
1069
1070 reset@1 {
1071 compatible = "sandbox,reset";
1072 };
1073
Stephen Warren6488e642016-06-17 09:43:59 -06001074 resetc: reset-ctl {
1075 compatible = "sandbox,reset-ctl";
1076 #reset-cells = <1>;
1077 };
1078
1079 reset-ctl-test {
1080 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001081 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1082 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001083 };
1084
Sughosh Ganu23e37512019-12-28 23:58:31 +05301085 rng {
1086 compatible = "sandbox,sandbox-rng";
1087 };
1088
Nishanth Menonedf85812015-09-17 15:42:41 -05001089 rproc_1: rproc@1 {
1090 compatible = "sandbox,test-processor";
1091 remoteproc-name = "remoteproc-test-dev1";
1092 };
1093
1094 rproc_2: rproc@2 {
1095 compatible = "sandbox,test-processor";
1096 internal-memory-mapped;
1097 remoteproc-name = "remoteproc-test-dev2";
1098 };
1099
Simon Glass5620cf82018-10-01 12:22:40 -06001100 panel {
1101 compatible = "simple-panel";
1102 backlight = <&backlight 0 100>;
1103 };
1104
Ramon Fried26ed32e2018-07-02 02:57:59 +03001105 smem@0 {
1106 compatible = "sandbox,smem";
1107 };
1108
Simon Glass76072ac2018-12-10 10:37:36 -07001109 sound {
1110 compatible = "sandbox,sound";
1111 cpu {
1112 sound-dai = <&i2s 0>;
1113 };
1114
1115 codec {
1116 sound-dai = <&audio 0>;
1117 };
1118 };
1119
Simon Glass25348a42014-10-13 23:42:11 -06001120 spi@0 {
1121 #address-cells = <1>;
1122 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001123 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001124 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001125 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001126 pinctrl-names = "default";
1127 pinctrl-0 = <&pinmux_spi0_pins>;
1128
Simon Glass25348a42014-10-13 23:42:11 -06001129 spi.bin@0 {
1130 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001131 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001132 spi-max-frequency = <40000000>;
1133 sandbox,filename = "spi.bin";
1134 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001135 spi.bin@1 {
1136 reg = <1>;
1137 compatible = "spansion,m25p16", "jedec,spi-nor";
1138 spi-max-frequency = <50000000>;
1139 sandbox,filename = "spi.bin";
1140 spi-cpol;
1141 spi-cpha;
1142 };
Simon Glass25348a42014-10-13 23:42:11 -06001143 };
1144
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001145 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001146 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001147 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001148 };
1149
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001150 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001151 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001152 reg = <0x20 5
1153 0x28 6
1154 0x30 7
1155 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001156 };
1157
Patrick Delaunayee010432019-03-07 09:57:13 +01001158 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001159 compatible = "simple-mfd", "syscon";
1160 reg = <0x40 5
1161 0x48 6
1162 0x50 7
1163 0x58 8>;
1164 };
1165
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301166 syscon3: syscon@3 {
1167 compatible = "simple-mfd", "syscon";
1168 reg = <0x000100 0x10>;
1169
1170 muxcontroller0: a-mux-controller {
1171 compatible = "mmio-mux";
1172 #mux-control-cells = <1>;
1173
1174 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1175 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1176 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1177 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1178 u-boot,mux-autoprobe;
1179 };
1180 };
1181
1182 muxcontroller1: emul-mux-controller {
1183 compatible = "mux-emul";
1184 #mux-control-cells = <0>;
1185 u-boot,mux-autoprobe;
1186 idle-state = <0xabcd>;
1187 };
1188
Simon Glass791a17f2020-12-16 21:20:27 -07001189 testfdtm0 {
1190 compatible = "denx,u-boot-fdtm-test";
1191 };
1192
1193 testfdtm1: testfdtm1 {
1194 compatible = "denx,u-boot-fdtm-test";
1195 };
1196
1197 testfdtm2 {
1198 compatible = "denx,u-boot-fdtm-test";
1199 };
1200
Sean Anderson79d3bba2020-09-28 10:52:23 -04001201 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001202 compatible = "sandbox,timer";
1203 clock-frequency = <1000000>;
1204 };
1205
Sean Anderson79d3bba2020-09-28 10:52:23 -04001206 timer@1 {
1207 compatible = "sandbox,timer";
1208 sandbox,timebase-frequency-fallback;
1209 };
1210
Miquel Raynal80938c12018-05-15 11:57:27 +02001211 tpm2 {
1212 compatible = "sandbox,tpm2";
1213 };
1214
Simon Glass5b968632015-05-22 15:42:15 -06001215 uart0: serial {
1216 compatible = "sandbox,serial";
1217 u-boot,dm-pre-reloc;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001218 pinctrl-names = "default";
1219 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001220 };
1221
Simon Glass31680482015-03-25 12:23:05 -06001222 usb_0: usb@0 {
1223 compatible = "sandbox,usb";
1224 status = "disabled";
1225 hub {
1226 compatible = "sandbox,usb-hub";
1227 #address-cells = <1>;
1228 #size-cells = <0>;
1229 flash-stick {
1230 reg = <0>;
1231 compatible = "sandbox,usb-flash";
1232 };
1233 };
1234 };
1235
1236 usb_1: usb@1 {
1237 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001238 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001239 hub {
1240 compatible = "usb-hub";
1241 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001242 #address-cells = <1>;
1243 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001244 hub-emul {
1245 compatible = "sandbox,usb-hub";
1246 #address-cells = <1>;
1247 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001248 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001249 reg = <0>;
1250 compatible = "sandbox,usb-flash";
1251 sandbox,filepath = "testflash.bin";
1252 };
1253
Simon Glass4700fe52015-11-08 23:48:01 -07001254 flash-stick@1 {
1255 reg = <1>;
1256 compatible = "sandbox,usb-flash";
1257 sandbox,filepath = "testflash1.bin";
1258 };
1259
1260 flash-stick@2 {
1261 reg = <2>;
1262 compatible = "sandbox,usb-flash";
1263 sandbox,filepath = "testflash2.bin";
1264 };
1265
Simon Glassc0ccc722015-11-08 23:48:08 -07001266 keyb@3 {
1267 reg = <3>;
1268 compatible = "sandbox,usb-keyb";
1269 };
1270
Simon Glass31680482015-03-25 12:23:05 -06001271 };
Michael Walle7c961322020-06-02 01:47:07 +02001272
1273 usbstor@1 {
1274 reg = <1>;
1275 };
1276 usbstor@3 {
1277 reg = <3>;
1278 };
Simon Glass31680482015-03-25 12:23:05 -06001279 };
1280 };
1281
1282 usb_2: usb@2 {
1283 compatible = "sandbox,usb";
1284 status = "disabled";
1285 };
1286
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001287 spmi: spmi@0 {
1288 compatible = "sandbox,spmi";
1289 #address-cells = <0x1>;
1290 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001291 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001292 pm8916@0 {
1293 compatible = "qcom,spmi-pmic";
1294 reg = <0x0 0x1>;
1295 #address-cells = <0x1>;
1296 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001297 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001298
1299 spmi_gpios: gpios@c000 {
1300 compatible = "qcom,pm8916-gpio";
1301 reg = <0xc000 0x400>;
1302 gpio-controller;
1303 gpio-count = <4>;
1304 #gpio-cells = <2>;
1305 gpio-bank-name="spmi";
1306 };
1307 };
1308 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001309
1310 wdt0: wdt@0 {
1311 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001312 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001313 };
Rob Clarka471b672018-01-10 11:33:30 +01001314
Mario Six95922152018-08-09 14:51:19 +02001315 axi: axi@0 {
1316 compatible = "sandbox,axi";
1317 #address-cells = <0x1>;
1318 #size-cells = <0x1>;
1319 store@0 {
1320 compatible = "sandbox,sandbox_store";
1321 reg = <0x0 0x400>;
1322 };
1323 };
1324
Rob Clarka471b672018-01-10 11:33:30 +01001325 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001326 #address-cells = <1>;
1327 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001328 setting = "sunrise ohoka";
1329 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001330 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001331 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001332 chosen-test {
1333 compatible = "denx,u-boot-fdt-test";
1334 reg = <9 1>;
1335 };
1336 };
Mario Six35616ef2018-03-12 14:53:33 +01001337
1338 translation-test@8000 {
1339 compatible = "simple-bus";
1340 reg = <0x8000 0x4000>;
1341
1342 #address-cells = <0x2>;
1343 #size-cells = <0x1>;
1344
1345 ranges = <0 0x0 0x8000 0x1000
1346 1 0x100 0x9000 0x1000
1347 2 0x200 0xA000 0x1000
1348 3 0x300 0xB000 0x1000
1349 >;
1350
Fabien Dessenne22236e02019-05-31 15:11:30 +02001351 dma-ranges = <0 0x000 0x10000000 0x1000
1352 1 0x100 0x20000000 0x1000
1353 >;
1354
Mario Six35616ef2018-03-12 14:53:33 +01001355 dev@0,0 {
1356 compatible = "denx,u-boot-fdt-dummy";
1357 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +01001358 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001359 };
1360
1361 dev@1,100 {
1362 compatible = "denx,u-boot-fdt-dummy";
1363 reg = <1 0x100 0x1000>;
1364
1365 };
1366
1367 dev@2,200 {
1368 compatible = "denx,u-boot-fdt-dummy";
1369 reg = <2 0x200 0x1000>;
1370 };
1371
1372
1373 noxlatebus@3,300 {
1374 compatible = "simple-bus";
1375 reg = <3 0x300 0x1000>;
1376
1377 #address-cells = <0x1>;
1378 #size-cells = <0x0>;
1379
1380 dev@42 {
1381 compatible = "denx,u-boot-fdt-dummy";
1382 reg = <0x42>;
1383 };
1384 };
1385 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001386
1387 osd {
1388 compatible = "sandbox,sandbox_osd";
1389 };
Tom Rinib93eea72018-09-30 18:16:51 -04001390
Jens Wiklander86afaa62018-09-25 16:40:16 +02001391 sandbox_tee {
1392 compatible = "sandbox,tee";
1393 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001394
1395 sandbox_virtio1 {
1396 compatible = "sandbox,virtio1";
1397 };
1398
1399 sandbox_virtio2 {
1400 compatible = "sandbox,virtio2";
1401 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001402
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001403 sandbox_scmi {
1404 compatible = "sandbox,scmi-devices";
1405 clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>;
Etienne Carriere8b9b6892020-09-09 18:44:07 +02001406 resets = <&reset_scmi0 3>;
Etienne Carriereb8f15cd2021-03-08 22:38:07 +01001407 regul0-supply = <&regul0_scmi0>;
1408 regul1-supply = <&regul1_scmi0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001409 };
1410
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001411 pinctrl {
1412 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001413
Sean Anderson3438e3b2020-09-14 11:01:57 -04001414 pinctrl-names = "default", "alternate";
1415 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1416 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001417
Sean Anderson3438e3b2020-09-14 11:01:57 -04001418 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001419 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001420 pins = "P5";
1421 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001422 bias-pull-up;
1423 input-disable;
1424 };
1425 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001426 pins = "P6";
1427 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001428 output-high;
1429 drive-open-drain;
1430 };
1431 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001432 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001433 bias-pull-down;
1434 input-enable;
1435 };
1436 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001437 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001438 bias-disable;
1439 };
1440 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001441
1442 pinctrl_i2c: i2c {
1443 groups {
1444 groups = "I2C_UART";
1445 function = "I2C";
1446 };
1447
1448 pins {
1449 pins = "P0", "P1";
1450 drive-open-drain;
1451 };
1452 };
1453
1454 pinctrl_i2s: i2s {
1455 groups = "SPI_I2S";
1456 function = "I2S";
1457 };
1458
1459 pinctrl_spi: spi {
1460 groups = "SPI_I2S";
1461 function = "SPI";
1462
1463 cs {
1464 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1465 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1466 };
1467 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001468 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001469
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001470 pinctrl-single-no-width {
1471 compatible = "pinctrl-single";
1472 reg = <0x0000 0x238>;
1473 #pinctrl-cells = <1>;
1474 pinctrl-single,function-mask = <0x7f>;
1475 };
1476
1477 pinctrl-single-pins {
1478 compatible = "pinctrl-single";
1479 reg = <0x0000 0x238>;
1480 #pinctrl-cells = <1>;
1481 pinctrl-single,register-width = <32>;
1482 pinctrl-single,function-mask = <0x7f>;
1483
1484 pinmux_pwm_pins: pinmux_pwm_pins {
1485 pinctrl-single,pins = < 0x48 0x06 >;
1486 };
1487
1488 pinmux_spi0_pins: pinmux_spi0_pins {
1489 pinctrl-single,pins = <
1490 0x190 0x0c
1491 0x194 0x0c
1492 0x198 0x23
1493 0x19c 0x0c
1494 >;
1495 };
1496
1497 pinmux_uart0_pins: pinmux_uart0_pins {
1498 pinctrl-single,pins = <
1499 0x70 0x30
1500 0x74 0x00
1501 >;
1502 };
1503 };
1504
1505 pinctrl-single-bits {
1506 compatible = "pinctrl-single";
1507 reg = <0x0000 0x50>;
1508 #pinctrl-cells = <2>;
1509 pinctrl-single,bit-per-mux;
1510 pinctrl-single,register-width = <32>;
1511 pinctrl-single,function-mask = <0xf>;
1512
1513 pinmux_i2c0_pins: pinmux_i2c0_pins {
1514 pinctrl-single,bits = <
1515 0x10 0x00002200 0x0000ff00
1516 >;
1517 };
1518
1519 pinmux_lcd_pins: pinmux_lcd_pins {
1520 pinctrl-single,bits = <
1521 0x40 0x22222200 0xffffff00
1522 0x44 0x22222222 0xffffffff
1523 0x48 0x00000022 0x000000ff
1524 0x48 0x02000000 0x0f000000
1525 0x4c 0x02000022 0x0f0000ff
1526 >;
1527 };
1528 };
1529
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001530 hwspinlock@0 {
1531 compatible = "sandbox,hwspinlock";
1532 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001533
1534 dma: dma {
1535 compatible = "sandbox,dma";
1536 #dma-cells = <1>;
1537
1538 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1539 dma-names = "m2m", "tx0", "rx0";
1540 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001541
Alex Marginean0649be52019-07-12 10:13:53 +03001542 /*
1543 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1544 * end of the test. If parent mdio is removed first, clean-up of the
1545 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1546 * active at the end of the test. That it turn doesn't allow the mdio
1547 * class to be destroyed, triggering an error.
1548 */
1549 mdio-mux-test {
1550 compatible = "sandbox,mdio-mux";
1551 #address-cells = <1>;
1552 #size-cells = <0>;
1553 mdio-parent-bus = <&mdio>;
1554
1555 mdio-ch-test@0 {
1556 reg = <0>;
1557 };
1558 mdio-ch-test@1 {
1559 reg = <1>;
1560 };
1561 };
1562
1563 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001564 compatible = "sandbox,mdio";
1565 };
Sean Andersonb7860542020-06-24 06:41:12 -04001566
1567 pm-bus-test {
1568 compatible = "simple-pm-bus";
1569 clocks = <&clk_sandbox 4>;
1570 power-domains = <&pwrdom 1>;
1571 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001572
1573 resetc2: syscon-reset {
1574 compatible = "syscon-reset";
1575 #reset-cells = <1>;
1576 regmap = <&syscon0>;
1577 offset = <1>;
1578 mask = <0x27FFFFFF>;
1579 assert-high = <0>;
1580 };
1581
1582 syscon-reset-test {
1583 compatible = "sandbox,misc_sandbox";
1584 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1585 reset-names = "valid", "no_mask", "out_of_range";
1586 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301587
Simon Glass458b66a2020-11-05 06:32:05 -07001588 sysinfo {
1589 compatible = "sandbox,sysinfo-sandbox";
1590 };
1591
Sean Anderson1c830672021-04-20 10:50:58 -04001592 sysinfo-gpio {
1593 compatible = "gpio-sysinfo";
1594 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1595 revisions = <19>, <5>;
1596 names = "rev_a", "foo";
1597 };
1598
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301599 some_regmapped-bus {
1600 #address-cells = <0x1>;
1601 #size-cells = <0x1>;
1602
1603 ranges = <0x0 0x0 0x10>;
1604 compatible = "simple-bus";
1605
1606 regmap-test_0 {
1607 reg = <0 0x10>;
1608 compatible = "sandbox,regmap_test";
1609 };
1610 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001611};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001612
1613#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001614#include "cros-ec-keyboard.dtsi"