blob: 8cd688e8d267aeae85568296fb9079f0d3fa2b1f [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay23aee612020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010017
Simon Glassb2c1cac2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070023
Simon Glassfef72b72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -060031 gpio1 = &gpio_a;
32 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010033 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070034 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060035 mmc0 = "/mmc0";
36 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070037 pci0 = &pci0;
38 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070039 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020040 remoteproc0 = &rproc_1;
41 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060042 rtc0 = &rtc_0;
43 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060044 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020045 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070046 testbus3 = "/some-bus";
47 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070048 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070049 testfdt3 = "/b-test";
50 testfdt5 = "/some-bus/c-test@5";
51 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070052 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020053 fdt-dummy0 = "/translation-test@8000/dev@0,0";
54 fdt-dummy1 = "/translation-test@8000/dev@1,100";
55 fdt-dummy2 = "/translation-test@8000/dev@2,200";
56 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060057 usb0 = &usb_0;
58 usb1 = &usb_1;
59 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020060 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020061 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060062 };
63
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020064 config {
Simon Glass0034d962021-08-07 07:24:01 -060065 testing-bool;
66 testing-int = <123>;
67 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020068 environment {
69 from_fdt = "yes";
70 fdt_env_path = "";
71 };
72 };
73
Nandor Han6521e5d2021-06-10 16:56:44 +030074 reboot-mode0 {
75 compatible = "reboot-mode-gpio";
76 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
77 u-boot,env-variable = "bootstatus";
78 mode-test = <0x01>;
79 mode-download = <0x03>;
80 };
81
Nandor Han7e4067a2021-06-10 16:56:45 +030082 reboot_mode1: reboot-mode@14 {
83 compatible = "reboot-mode-rtc";
84 rtc = <&rtc_0>;
85 reg = <0x30 4>;
86 u-boot,env-variable = "bootstatus";
87 big-endian;
88 mode-test = <0x21969147>;
89 mode-download = <0x51939147>;
90 };
91
Simon Glassed96cde2018-12-10 10:37:33 -070092 audio: audio-codec {
93 compatible = "sandbox,audio-codec";
94 #sound-dai-cells = <1>;
95 };
96
Philippe Reynes1ee26482020-07-24 18:19:51 +020097 buttons {
98 compatible = "gpio-keys";
99
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200100 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200101 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200102 label = "button1";
Philippe Reynes1ee26482020-07-24 18:19:51 +0200103 };
104
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200105 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200106 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200107 label = "button2";
Philippe Reynes1ee26482020-07-24 18:19:51 +0200108 };
109 };
110
Marek Szyprowskiad398592021-02-18 11:33:18 +0100111 buttons2 {
112 compatible = "adc-keys";
113 io-channels = <&adc 3>;
114 keyup-threshold-microvolt = <3000000>;
115
116 button-up {
117 label = "button3";
118 linux,code = <KEY_F3>;
119 press-threshold-microvolt = <1500000>;
120 };
121
122 button-down {
123 label = "button4";
124 linux,code = <KEY_F4>;
125 press-threshold-microvolt = <1000000>;
126 };
127
128 button-enter {
129 label = "button5";
130 linux,code = <KEY_F5>;
131 press-threshold-microvolt = <500000>;
132 };
133 };
134
Simon Glassc953aaf2018-12-10 10:37:34 -0700135 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600136 reg = <0 0>;
137 compatible = "google,cros-ec-sandbox";
138
139 /*
140 * This describes the flash memory within the EC. Note
141 * that the STM32L flash erases to 0, not 0xff.
142 */
143 flash {
144 image-pos = <0x08000000>;
145 size = <0x20000>;
146 erase-value = <0>;
147
148 /* Information for sandbox */
149 ro {
150 image-pos = <0>;
151 size = <0xf000>;
152 };
153 wp-ro {
154 image-pos = <0xf000>;
155 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700156 used = <0x884>;
157 compress = "lz4";
158 uncomp-size = <0xcf8>;
159 hash {
160 algo = "sha256";
161 value = [00 01 02 03 04 05 06 07
162 08 09 0a 0b 0c 0d 0e 0f
163 10 11 12 13 14 15 16 17
164 18 19 1a 1b 1c 1d 1e 1f];
165 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600166 };
167 rw {
168 image-pos = <0x10000>;
169 size = <0x10000>;
170 };
171 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300172
173 cros_ec_pwm: cros-ec-pwm {
174 compatible = "google,cros-ec-pwm";
175 #pwm-cells = <1>;
176 };
177
Simon Glass699c9ca2018-10-01 12:22:08 -0600178 };
179
Yannick Fertré9712c822019-10-07 15:29:05 +0200180 dsi_host: dsi_host {
181 compatible = "sandbox,dsi-host";
182 };
183
Simon Glassb2c1cac2014-02-26 15:59:21 -0700184 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600185 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700186 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600187 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700188 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600189 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100190 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
191 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700192 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100193 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
194 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
195 <&gpio_b 7 GPIO_IN 3 2 1>,
196 <&gpio_b 8 GPIO_OUT 3 2 1>,
197 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100198 test3-gpios =
199 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
200 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
201 <&gpio_c 2 GPIO_OUT>,
202 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
203 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200204 <&gpio_c 5 GPIO_IN>,
205 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
206 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530207 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
208 test5-gpios = <&gpio_a 19>;
209
Simon Glass6df01f92018-12-10 10:37:37 -0700210 int-value = <1234>;
211 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200212 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200213 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600214 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700215 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600216 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200217 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530218
219 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
220 <&muxcontroller0 2>, <&muxcontroller0 3>,
221 <&muxcontroller1>;
222 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
223 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100224 display-timings {
225 timing0: 240x320 {
226 clock-frequency = <6500000>;
227 hactive = <240>;
228 vactive = <320>;
229 hfront-porch = <6>;
230 hback-porch = <7>;
231 hsync-len = <1>;
232 vback-porch = <5>;
233 vfront-porch = <8>;
234 vsync-len = <2>;
235 hsync-active = <1>;
236 vsync-active = <0>;
237 de-active = <1>;
238 pixelclk-active = <1>;
239 interlaced;
240 doublescan;
241 doubleclk;
242 };
243 timing1: 480x800 {
244 clock-frequency = <9000000>;
245 hactive = <480>;
246 vactive = <800>;
247 hfront-porch = <10>;
248 hback-porch = <59>;
249 hsync-len = <12>;
250 vback-porch = <15>;
251 vfront-porch = <17>;
252 vsync-len = <16>;
253 hsync-active = <0>;
254 vsync-active = <1>;
255 de-active = <0>;
256 pixelclk-active = <0>;
257 };
258 timing2: 800x480 {
259 clock-frequency = <33500000>;
260 hactive = <800>;
261 vactive = <480>;
262 hback-porch = <89>;
263 hfront-porch = <164>;
264 vback-porch = <23>;
265 vfront-porch = <10>;
266 hsync-len = <11>;
267 vsync-len = <13>;
268 };
269 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700270 };
271
272 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600273 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700274 compatible = "not,compatible";
275 };
276
277 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600278 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700279 };
280
Simon Glass5620cf82018-10-01 12:22:40 -0600281 backlight: backlight {
282 compatible = "pwm-backlight";
283 enable-gpios = <&gpio_a 1>;
284 power-supply = <&ldo_1>;
285 pwms = <&pwm 0 1000>;
286 default-brightness-level = <5>;
287 brightness-levels = <0 16 32 64 128 170 202 234 255>;
288 };
289
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200290 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200291 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200292 bind-test-child1 {
293 compatible = "sandbox,phy";
294 #phy-cells = <1>;
295 };
296
297 bind-test-child2 {
298 compatible = "simple-bus";
299 };
300 };
301
Simon Glassb2c1cac2014-02-26 15:59:21 -0700302 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600303 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700304 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600305 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700306 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530307
308 mux-controls = <&muxcontroller0 0>;
309 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700310 };
311
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200312 phy_provider0: gen_phy@0 {
313 compatible = "sandbox,phy";
314 #phy-cells = <1>;
315 };
316
317 phy_provider1: gen_phy@1 {
318 compatible = "sandbox,phy";
319 #phy-cells = <0>;
320 broken;
321 };
322
developer71092972020-05-02 11:35:12 +0200323 phy_provider2: gen_phy@2 {
324 compatible = "sandbox,phy";
325 #phy-cells = <0>;
326 };
327
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200328 gen_phy_user: gen_phy_user {
329 compatible = "simple-bus";
330 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
331 phy-names = "phy1", "phy2", "phy3";
332 };
333
developer71092972020-05-02 11:35:12 +0200334 gen_phy_user1: gen_phy_user1 {
335 compatible = "simple-bus";
336 phys = <&phy_provider0 0>, <&phy_provider2>;
337 phy-names = "phy1", "phy2";
338 };
339
Simon Glassb2c1cac2014-02-26 15:59:21 -0700340 some-bus {
341 #address-cells = <1>;
342 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600343 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600344 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600345 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700346 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600347 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700348 compatible = "denx,u-boot-fdt-test";
349 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600350 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700351 ping-add = <5>;
352 };
Simon Glass40717422014-07-23 06:55:18 -0600353 c-test@0 {
354 compatible = "denx,u-boot-fdt-test";
355 reg = <0>;
356 ping-expect = <6>;
357 ping-add = <6>;
358 };
359 c-test@1 {
360 compatible = "denx,u-boot-fdt-test";
361 reg = <1>;
362 ping-expect = <7>;
363 ping-add = <7>;
364 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700365 };
366
367 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600368 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600369 ping-expect = <6>;
370 ping-add = <6>;
371 compatible = "google,another-fdt-test";
372 };
373
374 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600375 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600376 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700377 ping-add = <6>;
378 compatible = "google,another-fdt-test";
379 };
380
Simon Glass0ccb0972015-01-25 08:27:05 -0700381 f-test {
382 compatible = "denx,u-boot-fdt-test";
383 };
384
385 g-test {
386 compatible = "denx,u-boot-fdt-test";
387 };
388
Bin Mengd9d24782018-10-10 22:07:01 -0700389 h-test {
390 compatible = "denx,u-boot-fdt-test1";
391 };
392
developercf8bc132020-05-02 11:35:10 +0200393 i-test {
394 compatible = "mediatek,u-boot-fdt-test";
395 #address-cells = <1>;
396 #size-cells = <0>;
397
398 subnode@0 {
399 reg = <0>;
400 };
401
402 subnode@1 {
403 reg = <1>;
404 };
405
406 subnode@2 {
407 reg = <2>;
408 };
409 };
410
Simon Glass204675c2019-12-29 21:19:25 -0700411 devres-test {
412 compatible = "denx,u-boot-devres-test";
413 };
414
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530415 another-test {
416 reg = <0 2>;
417 compatible = "denx,u-boot-fdt-test";
418 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
419 test5-gpios = <&gpio_a 19>;
420 };
421
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100422 mmio-bus@0 {
423 #address-cells = <1>;
424 #size-cells = <1>;
425 compatible = "denx,u-boot-test-bus";
426 dma-ranges = <0x10000000 0x00000000 0x00040000>;
427
428 subnode@0 {
429 compatible = "denx,u-boot-fdt-test";
430 };
431 };
432
433 mmio-bus@1 {
434 #address-cells = <1>;
435 #size-cells = <1>;
436 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100437
438 subnode@0 {
439 compatible = "denx,u-boot-fdt-test";
440 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100441 };
442
Simon Glass3c601b12020-07-07 13:12:06 -0600443 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600444 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600445 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600446 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600447 child {
448 compatible = "denx,u-boot-acpi-test";
449 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600450 };
451
Simon Glass3c601b12020-07-07 13:12:06 -0600452 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600453 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600454 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600455 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600456 };
457
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200458 clocks {
459 clk_fixed: clk-fixed {
460 compatible = "fixed-clock";
461 #clock-cells = <0>;
462 clock-frequency = <1234>;
463 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000464
465 clk_fixed_factor: clk-fixed-factor {
466 compatible = "fixed-factor-clock";
467 #clock-cells = <0>;
468 clock-div = <3>;
469 clock-mult = <2>;
470 clocks = <&clk_fixed>;
471 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200472
473 osc {
474 compatible = "fixed-clock";
475 #clock-cells = <0>;
476 clock-frequency = <20000000>;
477 };
Stephen Warrena9622432016-06-17 09:44:00 -0600478 };
479
480 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600481 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600482 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200483 assigned-clocks = <&clk_sandbox 3>;
484 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600485 };
486
487 clk-test {
488 compatible = "sandbox,clk-test";
489 clocks = <&clk_fixed>,
490 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200491 <&clk_sandbox 0>,
492 <&clk_sandbox 3>,
493 <&clk_sandbox 2>;
494 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600495 };
496
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200497 ccf: clk-ccf {
498 compatible = "sandbox,clk-ccf";
499 };
500
Simon Glass5b968632015-05-22 15:42:15 -0600501 eth@10002000 {
502 compatible = "sandbox,eth";
503 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500504 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600505 };
506
507 eth_5: eth@10003000 {
508 compatible = "sandbox,eth";
509 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500510 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600511 };
512
Bin Meng04a11cb2015-08-27 22:25:53 -0700513 eth_3: sbe5 {
514 compatible = "sandbox,eth";
515 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500516 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700517 };
518
Simon Glass5b968632015-05-22 15:42:15 -0600519 eth@10004000 {
520 compatible = "sandbox,eth";
521 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500522 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600523 };
524
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800525 dsa_eth0: dsa-test-eth {
526 compatible = "sandbox,eth";
527 reg = <0x10006000 0x1000>;
528 fake-host-hwaddr = [00 00 66 44 22 66];
529 };
530
531 dsa-test {
532 compatible = "sandbox,dsa";
533
534 ports {
535 #address-cells = <1>;
536 #size-cells = <0>;
537 swp_0: port@0 {
538 reg = <0>;
539 label = "lan0";
540 phy-mode = "rgmii-rxid";
541
542 fixed-link {
543 speed = <100>;
544 full-duplex;
545 };
546 };
547
548 swp_1: port@1 {
549 reg = <1>;
550 label = "lan1";
551 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800552 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800553 };
554
555 port@2 {
556 reg = <2>;
557 ethernet = <&dsa_eth0>;
558
559 fixed-link {
560 speed = <1000>;
561 full-duplex;
562 };
563 };
564 };
565 };
566
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700567 firmware {
568 sandbox_firmware: sandbox-firmware {
569 compatible = "sandbox,firmware";
570 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200571
572 sandbox-scmi-agent@0 {
573 compatible = "sandbox,scmi-agent";
574 #address-cells = <1>;
575 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200576
577 clk_scmi0: protocol@14 {
578 reg = <0x14>;
579 #clock-cells = <1>;
580 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200581
582 reset_scmi0: protocol@16 {
583 reg = <0x16>;
584 #reset-cells = <1>;
585 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100586
587 protocol@17 {
588 reg = <0x17>;
589
590 regulators {
591 #address-cells = <1>;
592 #size-cells = <0>;
593
594 regul0_scmi0: reg@0 {
595 reg = <0>;
596 regulator-name = "sandbox-voltd0";
597 regulator-min-microvolt = <1100000>;
598 regulator-max-microvolt = <3300000>;
599 };
600 regul1_scmi0: reg@1 {
601 reg = <0x1>;
602 regulator-name = "sandbox-voltd1";
603 regulator-min-microvolt = <1800000>;
604 };
605 };
606 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200607 };
608
609 sandbox-scmi-agent@1 {
610 compatible = "sandbox,scmi-agent";
611 #address-cells = <1>;
612 #size-cells = <0>;
613
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200614 clk_scmi1: protocol@14 {
615 reg = <0x14>;
616 #clock-cells = <1>;
617 };
618
Etienne Carriere02fd1262020-09-09 18:44:00 +0200619 protocol@10 {
620 reg = <0x10>;
621 };
622 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700623 };
624
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100625 pinctrl-gpio {
626 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700627
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100628 gpio_a: base-gpios {
629 compatible = "sandbox,gpio";
630 gpio-controller;
631 #gpio-cells = <1>;
632 gpio-bank-name = "a";
633 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200634 hog_input_active_low {
635 gpio-hog;
636 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200637 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200638 };
639 hog_input_active_high {
640 gpio-hog;
641 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200642 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200643 };
644 hog_output_low {
645 gpio-hog;
646 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200647 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200648 };
649 hog_output_high {
650 gpio-hog;
651 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200652 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200653 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100654 };
655
656 gpio_b: extra-gpios {
657 compatible = "sandbox,gpio";
658 gpio-controller;
659 #gpio-cells = <5>;
660 gpio-bank-name = "b";
661 sandbox,gpio-count = <10>;
662 };
Simon Glass25348a42014-10-13 23:42:11 -0600663
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100664 gpio_c: pinmux-gpios {
665 compatible = "sandbox,gpio";
666 gpio-controller;
667 #gpio-cells = <2>;
668 gpio-bank-name = "c";
669 sandbox,gpio-count = <10>;
670 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100671 };
672
Simon Glass7df766e2014-12-10 08:55:55 -0700673 i2c@0 {
674 #address-cells = <1>;
675 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600676 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700677 compatible = "sandbox,i2c";
678 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200679 pinctrl-names = "default";
680 pinctrl-0 = <&pinmux_i2c0_pins>;
681
Simon Glass7df766e2014-12-10 08:55:55 -0700682 eeprom@2c {
683 reg = <0x2c>;
684 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700685 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200686 partitions {
687 compatible = "fixed-partitions";
688 #address-cells = <1>;
689 #size-cells = <1>;
690 bootcount_i2c: bootcount@10 {
691 reg = <10 2>;
692 };
693 };
Simon Glass7df766e2014-12-10 08:55:55 -0700694 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200695
Simon Glass336b2952015-05-22 15:42:17 -0600696 rtc_0: rtc@43 {
697 reg = <0x43>;
698 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700699 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600700 };
701
702 rtc_1: rtc@61 {
703 reg = <0x61>;
704 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700705 sandbox,emul = <&emul1>;
706 };
707
708 i2c_emul: emul {
709 reg = <0xff>;
710 compatible = "sandbox,i2c-emul-parent";
711 emul_eeprom: emul-eeprom {
712 compatible = "sandbox,i2c-eeprom";
713 sandbox,filename = "i2c.bin";
714 sandbox,size = <256>;
715 };
716 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700717 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700718 };
719 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700720 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600721 };
722 };
723
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200724 sandbox_pmic: sandbox_pmic {
725 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700726 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200727 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200728
729 mc34708: pmic@41 {
730 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700731 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200732 };
Simon Glass7df766e2014-12-10 08:55:55 -0700733 };
734
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100735 bootcount@0 {
736 compatible = "u-boot,bootcount-rtc";
737 rtc = <&rtc_1>;
738 offset = <0x13>;
739 };
740
Michal Simek4f18f922020-05-28 11:48:55 +0200741 bootcount {
742 compatible = "u-boot,bootcount-i2c-eeprom";
743 i2c-eeprom = <&bootcount_i2c>;
744 };
745
Nandor Han88895812021-06-10 15:40:38 +0300746 bootcount_4@0 {
747 compatible = "u-boot,bootcount-syscon";
748 syscon = <&syscon0>;
749 reg = <0x0 0x04>, <0x0 0x04>;
750 reg-names = "syscon_reg", "offset";
751 };
752
753 bootcount_2@0 {
754 compatible = "u-boot,bootcount-syscon";
755 syscon = <&syscon0>;
756 reg = <0x0 0x04>, <0x0 0x02> ;
757 reg-names = "syscon_reg", "offset";
758 };
759
Marek Szyprowskiad398592021-02-18 11:33:18 +0100760 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100761 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100762 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100763 vdd-supply = <&buck2>;
764 vss-microvolts = <0>;
765 };
766
Mark Kettenis67748ee2021-10-23 16:58:02 +0200767 iommu: iommu@0 {
768 compatible = "sandbox,iommu";
769 #iommu-cells = <0>;
770 };
771
Simon Glass515dcff2020-02-06 09:55:00 -0700772 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700773 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700774 interrupt-controller;
775 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700776 };
777
Simon Glass90b6fef2016-01-18 19:52:26 -0700778 lcd {
779 u-boot,dm-pre-reloc;
780 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200781 pinctrl-names = "default";
782 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700783 xres = <1366>;
784 yres = <768>;
785 };
786
Simon Glassd783eb32015-07-06 12:54:34 -0600787 leds {
788 compatible = "gpio-leds";
789
790 iracibble {
791 gpios = <&gpio_a 1 0>;
792 label = "sandbox:red";
793 };
794
795 martinet {
796 gpios = <&gpio_a 2 0>;
797 label = "sandbox:green";
798 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200799
800 default_on {
801 gpios = <&gpio_a 5 0>;
802 label = "sandbox:default_on";
803 default-state = "on";
804 };
805
806 default_off {
807 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400808 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200809 default-state = "off";
810 };
Simon Glassd783eb32015-07-06 12:54:34 -0600811 };
812
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200813 gpio-wdt {
814 gpios = <&gpio_a 7 0>;
815 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +0200816 hw_margin_ms = <100>;
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200817 always-running;
818 };
819
Stephen Warren62f2c902016-05-16 17:41:37 -0600820 mbox: mbox {
821 compatible = "sandbox,mbox";
822 #mbox-cells = <1>;
823 };
824
825 mbox-test {
826 compatible = "sandbox,mbox-test";
827 mboxes = <&mbox 100>, <&mbox 1>;
828 mbox-names = "other", "test";
829 };
830
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900831 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200832 #address-cells = <1>;
833 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400834 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200835 cpu1: cpu@1 {
836 device_type = "cpu";
837 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400838 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900839 compatible = "sandbox,cpu_sandbox";
840 u-boot,dm-pre-reloc;
841 };
Mario Sixdea5df72018-08-06 10:23:44 +0200842
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200843 cpu2: cpu@2 {
844 device_type = "cpu";
845 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900846 compatible = "sandbox,cpu_sandbox";
847 u-boot,dm-pre-reloc;
848 };
Mario Sixdea5df72018-08-06 10:23:44 +0200849
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200850 cpu3: cpu@3 {
851 device_type = "cpu";
852 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900853 compatible = "sandbox,cpu_sandbox";
854 u-boot,dm-pre-reloc;
855 };
Mario Sixdea5df72018-08-06 10:23:44 +0200856 };
857
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500858 chipid: chipid {
859 compatible = "sandbox,soc";
860 };
861
Simon Glassc953aaf2018-12-10 10:37:34 -0700862 i2s: i2s {
863 compatible = "sandbox,i2s";
864 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700865 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700866 };
867
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200868 nop-test_0 {
869 compatible = "sandbox,nop_sandbox1";
870 nop-test_1 {
871 compatible = "sandbox,nop_sandbox2";
872 bind = "True";
873 };
874 nop-test_2 {
875 compatible = "sandbox,nop_sandbox2";
876 bind = "False";
877 };
878 };
879
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200880 misc-test {
881 compatible = "sandbox,misc_sandbox";
882 };
883
Simon Glasse4fef742017-04-23 20:02:07 -0600884 mmc2 {
885 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -0600886 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -0600887 };
888
889 mmc1 {
890 compatible = "sandbox,mmc";
891 };
892
893 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600894 compatible = "sandbox,mmc";
895 };
896
Simon Glass53a68b32019-02-16 20:24:50 -0700897 pch {
898 compatible = "sandbox,pch";
899 };
900
Tom Rini4a3ca482020-02-11 12:41:23 -0500901 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700902 compatible = "sandbox,pci";
903 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500904 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700905 #address-cells = <3>;
906 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600907 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700908 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700909 pci@0,0 {
910 compatible = "pci-generic";
911 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600912 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700913 };
Alex Margineanf1274432019-06-07 11:24:24 +0300914 pci@1,0 {
915 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600916 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
917 reg = <0x02000814 0 0 0 0
918 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600919 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300920 };
Simon Glass937bb472019-12-06 21:41:57 -0700921 p2sb-pci@2,0 {
922 compatible = "sandbox,p2sb";
923 reg = <0x02001010 0 0 0 0>;
924 sandbox,emul = <&p2sb_emul>;
925
926 adder {
927 intel,p2sb-port-id = <3>;
928 compatible = "sandbox,adder";
929 };
930 };
Simon Glass8c501022019-12-06 21:41:54 -0700931 pci@1e,0 {
932 compatible = "sandbox,pmc";
933 reg = <0xf000 0 0 0 0>;
934 sandbox,emul = <&pmc_emul1e>;
935 acpi-base = <0x400>;
936 gpe0-dwx-mask = <0xf>;
937 gpe0-dwx-shift-base = <4>;
938 gpe0-dw = <6 7 9>;
939 gpe0-sts = <0x20>;
940 gpe0-en = <0x30>;
941 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700942 pci@1f,0 {
943 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600944 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
945 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600946 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700947 };
948 };
949
Simon Glassb98ba4c2019-09-25 08:56:10 -0600950 pci-emul0 {
951 compatible = "sandbox,pci-emul-parent";
952 swap_case_emul0_0: emul0@0,0 {
953 compatible = "sandbox,swap-case";
954 };
955 swap_case_emul0_1: emul0@1,0 {
956 compatible = "sandbox,swap-case";
957 use-ea;
958 };
959 swap_case_emul0_1f: emul0@1f,0 {
960 compatible = "sandbox,swap-case";
961 };
Simon Glass937bb472019-12-06 21:41:57 -0700962 p2sb_emul: emul@2,0 {
963 compatible = "sandbox,p2sb-emul";
964 };
Simon Glass8c501022019-12-06 21:41:54 -0700965 pmc_emul1e: emul@1e,0 {
966 compatible = "sandbox,pmc-emul";
967 };
Simon Glassb98ba4c2019-09-25 08:56:10 -0600968 };
969
Tom Rini4a3ca482020-02-11 12:41:23 -0500970 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -0700971 compatible = "sandbox,pci";
972 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500973 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -0700974 #address-cells = <3>;
975 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -0700976 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
977 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
978 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700979 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200980 0x0c 0x00 0x1234 0x5678
981 0x10 0x00 0x1234 0x5678>;
982 pci@10,0 {
983 reg = <0x8000 0 0 0 0>;
984 };
Bin Meng408e5902018-08-03 01:14:41 -0700985 };
986
Tom Rini4a3ca482020-02-11 12:41:23 -0500987 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -0700988 compatible = "sandbox,pci";
989 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500990 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -0700991 #address-cells = <3>;
992 #size-cells = <2>;
993 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
994 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
995 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
996 pci@1f,0 {
997 compatible = "pci-generic";
998 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600999 sandbox,emul = <&swap_case_emul2_1f>;
1000 };
1001 };
1002
1003 pci-emul2 {
1004 compatible = "sandbox,pci-emul-parent";
1005 swap_case_emul2_1f: emul2@1f,0 {
1006 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001007 };
1008 };
1009
Ramon Friedc64f19b2019-04-27 11:15:23 +03001010 pci_ep: pci_ep {
1011 compatible = "sandbox,pci_ep";
1012 };
1013
Simon Glass9c433fe2017-04-23 20:10:44 -06001014 probing {
1015 compatible = "simple-bus";
1016 test1 {
1017 compatible = "denx,u-boot-probe-test";
1018 };
1019
1020 test2 {
1021 compatible = "denx,u-boot-probe-test";
1022 };
1023
1024 test3 {
1025 compatible = "denx,u-boot-probe-test";
1026 };
1027
1028 test4 {
1029 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001030 first-syscon = <&syscon0>;
1031 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001032 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001033 };
1034 };
1035
Stephen Warren92c67fa2016-07-13 13:45:31 -06001036 pwrdom: power-domain {
1037 compatible = "sandbox,power-domain";
1038 #power-domain-cells = <1>;
1039 };
1040
1041 power-domain-test {
1042 compatible = "sandbox,power-domain-test";
1043 power-domains = <&pwrdom 2>;
1044 };
1045
Simon Glass5620cf82018-10-01 12:22:40 -06001046 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001047 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001048 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001049 pinctrl-names = "default";
1050 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001051 };
1052
1053 pwm2 {
1054 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001055 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001056 };
1057
Simon Glass3d355e62015-07-06 12:54:31 -06001058 ram {
1059 compatible = "sandbox,ram";
1060 };
1061
Simon Glassd860f222015-07-06 12:54:29 -06001062 reset@0 {
1063 compatible = "sandbox,warm-reset";
1064 };
1065
1066 reset@1 {
1067 compatible = "sandbox,reset";
1068 };
1069
Stephen Warren6488e642016-06-17 09:43:59 -06001070 resetc: reset-ctl {
1071 compatible = "sandbox,reset-ctl";
1072 #reset-cells = <1>;
1073 };
1074
1075 reset-ctl-test {
1076 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001077 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1078 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001079 };
1080
Sughosh Ganu23e37512019-12-28 23:58:31 +05301081 rng {
1082 compatible = "sandbox,sandbox-rng";
1083 };
1084
Nishanth Menonedf85812015-09-17 15:42:41 -05001085 rproc_1: rproc@1 {
1086 compatible = "sandbox,test-processor";
1087 remoteproc-name = "remoteproc-test-dev1";
1088 };
1089
1090 rproc_2: rproc@2 {
1091 compatible = "sandbox,test-processor";
1092 internal-memory-mapped;
1093 remoteproc-name = "remoteproc-test-dev2";
1094 };
1095
Simon Glass5620cf82018-10-01 12:22:40 -06001096 panel {
1097 compatible = "simple-panel";
1098 backlight = <&backlight 0 100>;
1099 };
1100
Ramon Fried26ed32e2018-07-02 02:57:59 +03001101 smem@0 {
1102 compatible = "sandbox,smem";
1103 };
1104
Simon Glass76072ac2018-12-10 10:37:36 -07001105 sound {
1106 compatible = "sandbox,sound";
1107 cpu {
1108 sound-dai = <&i2s 0>;
1109 };
1110
1111 codec {
1112 sound-dai = <&audio 0>;
1113 };
1114 };
1115
Simon Glass25348a42014-10-13 23:42:11 -06001116 spi@0 {
1117 #address-cells = <1>;
1118 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001119 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001120 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001121 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001122 pinctrl-names = "default";
1123 pinctrl-0 = <&pinmux_spi0_pins>;
1124
Simon Glass25348a42014-10-13 23:42:11 -06001125 spi.bin@0 {
1126 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001127 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001128 spi-max-frequency = <40000000>;
1129 sandbox,filename = "spi.bin";
1130 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001131 spi.bin@1 {
1132 reg = <1>;
1133 compatible = "spansion,m25p16", "jedec,spi-nor";
1134 spi-max-frequency = <50000000>;
1135 sandbox,filename = "spi.bin";
1136 spi-cpol;
1137 spi-cpha;
1138 };
Simon Glass25348a42014-10-13 23:42:11 -06001139 };
1140
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001141 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001142 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001143 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001144 };
1145
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001146 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001147 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001148 reg = <0x20 5
1149 0x28 6
1150 0x30 7
1151 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001152 };
1153
Patrick Delaunayee010432019-03-07 09:57:13 +01001154 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001155 compatible = "simple-mfd", "syscon";
1156 reg = <0x40 5
1157 0x48 6
1158 0x50 7
1159 0x58 8>;
1160 };
1161
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301162 syscon3: syscon@3 {
1163 compatible = "simple-mfd", "syscon";
1164 reg = <0x000100 0x10>;
1165
1166 muxcontroller0: a-mux-controller {
1167 compatible = "mmio-mux";
1168 #mux-control-cells = <1>;
1169
1170 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1171 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1172 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1173 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1174 u-boot,mux-autoprobe;
1175 };
1176 };
1177
1178 muxcontroller1: emul-mux-controller {
1179 compatible = "mux-emul";
1180 #mux-control-cells = <0>;
1181 u-boot,mux-autoprobe;
1182 idle-state = <0xabcd>;
1183 };
1184
Simon Glass791a17f2020-12-16 21:20:27 -07001185 testfdtm0 {
1186 compatible = "denx,u-boot-fdtm-test";
1187 };
1188
1189 testfdtm1: testfdtm1 {
1190 compatible = "denx,u-boot-fdtm-test";
1191 };
1192
1193 testfdtm2 {
1194 compatible = "denx,u-boot-fdtm-test";
1195 };
1196
Sean Anderson79d3bba2020-09-28 10:52:23 -04001197 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001198 compatible = "sandbox,timer";
1199 clock-frequency = <1000000>;
1200 };
1201
Sean Anderson79d3bba2020-09-28 10:52:23 -04001202 timer@1 {
1203 compatible = "sandbox,timer";
1204 sandbox,timebase-frequency-fallback;
1205 };
1206
Miquel Raynal80938c12018-05-15 11:57:27 +02001207 tpm2 {
1208 compatible = "sandbox,tpm2";
1209 };
1210
Simon Glass5b968632015-05-22 15:42:15 -06001211 uart0: serial {
1212 compatible = "sandbox,serial";
1213 u-boot,dm-pre-reloc;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001214 pinctrl-names = "default";
1215 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001216 };
1217
Simon Glass31680482015-03-25 12:23:05 -06001218 usb_0: usb@0 {
1219 compatible = "sandbox,usb";
1220 status = "disabled";
1221 hub {
1222 compatible = "sandbox,usb-hub";
1223 #address-cells = <1>;
1224 #size-cells = <0>;
1225 flash-stick {
1226 reg = <0>;
1227 compatible = "sandbox,usb-flash";
1228 };
1229 };
1230 };
1231
1232 usb_1: usb@1 {
1233 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001234 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001235 hub {
1236 compatible = "usb-hub";
1237 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001238 #address-cells = <1>;
1239 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001240 hub-emul {
1241 compatible = "sandbox,usb-hub";
1242 #address-cells = <1>;
1243 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001244 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001245 reg = <0>;
1246 compatible = "sandbox,usb-flash";
1247 sandbox,filepath = "testflash.bin";
1248 };
1249
Simon Glass4700fe52015-11-08 23:48:01 -07001250 flash-stick@1 {
1251 reg = <1>;
1252 compatible = "sandbox,usb-flash";
1253 sandbox,filepath = "testflash1.bin";
1254 };
1255
1256 flash-stick@2 {
1257 reg = <2>;
1258 compatible = "sandbox,usb-flash";
1259 sandbox,filepath = "testflash2.bin";
1260 };
1261
Simon Glassc0ccc722015-11-08 23:48:08 -07001262 keyb@3 {
1263 reg = <3>;
1264 compatible = "sandbox,usb-keyb";
1265 };
1266
Simon Glass31680482015-03-25 12:23:05 -06001267 };
Michael Walle7c961322020-06-02 01:47:07 +02001268
1269 usbstor@1 {
1270 reg = <1>;
1271 };
1272 usbstor@3 {
1273 reg = <3>;
1274 };
Simon Glass31680482015-03-25 12:23:05 -06001275 };
1276 };
1277
1278 usb_2: usb@2 {
1279 compatible = "sandbox,usb";
1280 status = "disabled";
1281 };
1282
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001283 spmi: spmi@0 {
1284 compatible = "sandbox,spmi";
1285 #address-cells = <0x1>;
1286 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001287 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001288 pm8916@0 {
1289 compatible = "qcom,spmi-pmic";
1290 reg = <0x0 0x1>;
1291 #address-cells = <0x1>;
1292 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001293 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001294
1295 spmi_gpios: gpios@c000 {
1296 compatible = "qcom,pm8916-gpio";
1297 reg = <0xc000 0x400>;
1298 gpio-controller;
1299 gpio-count = <4>;
1300 #gpio-cells = <2>;
1301 gpio-bank-name="spmi";
1302 };
1303 };
1304 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001305
1306 wdt0: wdt@0 {
1307 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001308 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001309 };
Rob Clarka471b672018-01-10 11:33:30 +01001310
Mario Six95922152018-08-09 14:51:19 +02001311 axi: axi@0 {
1312 compatible = "sandbox,axi";
1313 #address-cells = <0x1>;
1314 #size-cells = <0x1>;
1315 store@0 {
1316 compatible = "sandbox,sandbox_store";
1317 reg = <0x0 0x400>;
1318 };
1319 };
1320
Rob Clarka471b672018-01-10 11:33:30 +01001321 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001322 #address-cells = <1>;
1323 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001324 setting = "sunrise ohoka";
1325 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001326 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001327 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001328 chosen-test {
1329 compatible = "denx,u-boot-fdt-test";
1330 reg = <9 1>;
1331 };
1332 };
Mario Six35616ef2018-03-12 14:53:33 +01001333
1334 translation-test@8000 {
1335 compatible = "simple-bus";
1336 reg = <0x8000 0x4000>;
1337
1338 #address-cells = <0x2>;
1339 #size-cells = <0x1>;
1340
1341 ranges = <0 0x0 0x8000 0x1000
1342 1 0x100 0x9000 0x1000
1343 2 0x200 0xA000 0x1000
1344 3 0x300 0xB000 0x1000
1345 >;
1346
Fabien Dessenne22236e02019-05-31 15:11:30 +02001347 dma-ranges = <0 0x000 0x10000000 0x1000
1348 1 0x100 0x20000000 0x1000
1349 >;
1350
Mario Six35616ef2018-03-12 14:53:33 +01001351 dev@0,0 {
1352 compatible = "denx,u-boot-fdt-dummy";
1353 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +01001354 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001355 };
1356
1357 dev@1,100 {
1358 compatible = "denx,u-boot-fdt-dummy";
1359 reg = <1 0x100 0x1000>;
1360
1361 };
1362
1363 dev@2,200 {
1364 compatible = "denx,u-boot-fdt-dummy";
1365 reg = <2 0x200 0x1000>;
1366 };
1367
1368
1369 noxlatebus@3,300 {
1370 compatible = "simple-bus";
1371 reg = <3 0x300 0x1000>;
1372
1373 #address-cells = <0x1>;
1374 #size-cells = <0x0>;
1375
1376 dev@42 {
1377 compatible = "denx,u-boot-fdt-dummy";
1378 reg = <0x42>;
1379 };
1380 };
1381 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001382
1383 osd {
1384 compatible = "sandbox,sandbox_osd";
1385 };
Tom Rinib93eea72018-09-30 18:16:51 -04001386
Jens Wiklander86afaa62018-09-25 16:40:16 +02001387 sandbox_tee {
1388 compatible = "sandbox,tee";
1389 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001390
1391 sandbox_virtio1 {
1392 compatible = "sandbox,virtio1";
1393 };
1394
1395 sandbox_virtio2 {
1396 compatible = "sandbox,virtio2";
1397 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001398
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001399 sandbox_scmi {
1400 compatible = "sandbox,scmi-devices";
1401 clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>;
Etienne Carriere8b9b6892020-09-09 18:44:07 +02001402 resets = <&reset_scmi0 3>;
Etienne Carriereb8f15cd2021-03-08 22:38:07 +01001403 regul0-supply = <&regul0_scmi0>;
1404 regul1-supply = <&regul1_scmi0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001405 };
1406
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001407 pinctrl {
1408 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001409
Sean Anderson3438e3b2020-09-14 11:01:57 -04001410 pinctrl-names = "default", "alternate";
1411 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1412 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001413
Sean Anderson3438e3b2020-09-14 11:01:57 -04001414 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001415 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001416 pins = "P5";
1417 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001418 bias-pull-up;
1419 input-disable;
1420 };
1421 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001422 pins = "P6";
1423 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001424 output-high;
1425 drive-open-drain;
1426 };
1427 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001428 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001429 bias-pull-down;
1430 input-enable;
1431 };
1432 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001433 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001434 bias-disable;
1435 };
1436 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001437
1438 pinctrl_i2c: i2c {
1439 groups {
1440 groups = "I2C_UART";
1441 function = "I2C";
1442 };
1443
1444 pins {
1445 pins = "P0", "P1";
1446 drive-open-drain;
1447 };
1448 };
1449
1450 pinctrl_i2s: i2s {
1451 groups = "SPI_I2S";
1452 function = "I2S";
1453 };
1454
1455 pinctrl_spi: spi {
1456 groups = "SPI_I2S";
1457 function = "SPI";
1458
1459 cs {
1460 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1461 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1462 };
1463 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001464 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001465
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001466 pinctrl-single-no-width {
1467 compatible = "pinctrl-single";
1468 reg = <0x0000 0x238>;
1469 #pinctrl-cells = <1>;
1470 pinctrl-single,function-mask = <0x7f>;
1471 };
1472
1473 pinctrl-single-pins {
1474 compatible = "pinctrl-single";
1475 reg = <0x0000 0x238>;
1476 #pinctrl-cells = <1>;
1477 pinctrl-single,register-width = <32>;
1478 pinctrl-single,function-mask = <0x7f>;
1479
1480 pinmux_pwm_pins: pinmux_pwm_pins {
1481 pinctrl-single,pins = < 0x48 0x06 >;
1482 };
1483
1484 pinmux_spi0_pins: pinmux_spi0_pins {
1485 pinctrl-single,pins = <
1486 0x190 0x0c
1487 0x194 0x0c
1488 0x198 0x23
1489 0x19c 0x0c
1490 >;
1491 };
1492
1493 pinmux_uart0_pins: pinmux_uart0_pins {
1494 pinctrl-single,pins = <
1495 0x70 0x30
1496 0x74 0x00
1497 >;
1498 };
1499 };
1500
1501 pinctrl-single-bits {
1502 compatible = "pinctrl-single";
1503 reg = <0x0000 0x50>;
1504 #pinctrl-cells = <2>;
1505 pinctrl-single,bit-per-mux;
1506 pinctrl-single,register-width = <32>;
1507 pinctrl-single,function-mask = <0xf>;
1508
1509 pinmux_i2c0_pins: pinmux_i2c0_pins {
1510 pinctrl-single,bits = <
1511 0x10 0x00002200 0x0000ff00
1512 >;
1513 };
1514
1515 pinmux_lcd_pins: pinmux_lcd_pins {
1516 pinctrl-single,bits = <
1517 0x40 0x22222200 0xffffff00
1518 0x44 0x22222222 0xffffffff
1519 0x48 0x00000022 0x000000ff
1520 0x48 0x02000000 0x0f000000
1521 0x4c 0x02000022 0x0f0000ff
1522 >;
1523 };
1524 };
1525
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001526 hwspinlock@0 {
1527 compatible = "sandbox,hwspinlock";
1528 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001529
1530 dma: dma {
1531 compatible = "sandbox,dma";
1532 #dma-cells = <1>;
1533
1534 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1535 dma-names = "m2m", "tx0", "rx0";
1536 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001537
Alex Marginean0649be52019-07-12 10:13:53 +03001538 /*
1539 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1540 * end of the test. If parent mdio is removed first, clean-up of the
1541 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1542 * active at the end of the test. That it turn doesn't allow the mdio
1543 * class to be destroyed, triggering an error.
1544 */
1545 mdio-mux-test {
1546 compatible = "sandbox,mdio-mux";
1547 #address-cells = <1>;
1548 #size-cells = <0>;
1549 mdio-parent-bus = <&mdio>;
1550
1551 mdio-ch-test@0 {
1552 reg = <0>;
1553 };
1554 mdio-ch-test@1 {
1555 reg = <1>;
1556 };
1557 };
1558
1559 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001560 compatible = "sandbox,mdio";
1561 };
Sean Andersonb7860542020-06-24 06:41:12 -04001562
1563 pm-bus-test {
1564 compatible = "simple-pm-bus";
1565 clocks = <&clk_sandbox 4>;
1566 power-domains = <&pwrdom 1>;
1567 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001568
1569 resetc2: syscon-reset {
1570 compatible = "syscon-reset";
1571 #reset-cells = <1>;
1572 regmap = <&syscon0>;
1573 offset = <1>;
1574 mask = <0x27FFFFFF>;
1575 assert-high = <0>;
1576 };
1577
1578 syscon-reset-test {
1579 compatible = "sandbox,misc_sandbox";
1580 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1581 reset-names = "valid", "no_mask", "out_of_range";
1582 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301583
Simon Glass458b66a2020-11-05 06:32:05 -07001584 sysinfo {
1585 compatible = "sandbox,sysinfo-sandbox";
1586 };
1587
Sean Anderson1c830672021-04-20 10:50:58 -04001588 sysinfo-gpio {
1589 compatible = "gpio-sysinfo";
1590 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1591 revisions = <19>, <5>;
1592 names = "rev_a", "foo";
1593 };
1594
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301595 some_regmapped-bus {
1596 #address-cells = <0x1>;
1597 #size-cells = <0x1>;
1598
1599 ranges = <0x0 0x0 0x10>;
1600 compatible = "simple-bus";
1601
1602 regmap-test_0 {
1603 reg = <0 0x10>;
1604 compatible = "sandbox,regmap_test";
1605 };
1606 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001607};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001608
1609#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001610#include "cros-ec-keyboard.dtsi"