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Simon Glassb2c1cac2014-02-26 15:59:21 -07001/dts-v1/;
2
Patrick Delaunay23aee612020-01-13 11:35:13 +01003#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +01005#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -04006#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05307#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +01008
Simon Glassb2c1cac2014-02-26 15:59:21 -07009/ {
10 model = "sandbox";
11 compatible = "sandbox";
12 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060013 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070014
Simon Glassfef72b72014-07-23 06:55:03 -060015 aliases {
16 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -060017 eth0 = "/eth@10002000";
Claudiu Manoild9eaa922021-03-14 20:14:57 +080018 eth2 = &swp_0;
Bin Meng04a11cb2015-08-27 22:25:53 -070019 eth3 = &eth_3;
Claudiu Manoild9eaa922021-03-14 20:14:57 +080020 eth4 = &dsa_eth0;
Simon Glass5b968632015-05-22 15:42:15 -060021 eth5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -060022 gpio1 = &gpio_a;
23 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010024 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070025 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060026 mmc0 = "/mmc0";
27 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070028 pci0 = &pci0;
29 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070030 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020031 remoteproc0 = &rproc_1;
32 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060033 rtc0 = &rtc_0;
34 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060035 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020036 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070037 testbus3 = "/some-bus";
38 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070039 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070040 testfdt3 = "/b-test";
41 testfdt5 = "/some-bus/c-test@5";
42 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070043 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020044 fdt-dummy0 = "/translation-test@8000/dev@0,0";
45 fdt-dummy1 = "/translation-test@8000/dev@1,100";
46 fdt-dummy2 = "/translation-test@8000/dev@2,200";
47 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Dario Binacchib574d682020-12-30 00:16:21 +010048 fdt-dummy4 = "/translation-test@8000/xlatebus@4,400/devs/dev@19";
Simon Glass31680482015-03-25 12:23:05 -060049 usb0 = &usb_0;
50 usb1 = &usb_1;
51 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020052 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020053 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060054 };
55
Simon Glassed96cde2018-12-10 10:37:33 -070056 audio: audio-codec {
57 compatible = "sandbox,audio-codec";
58 #sound-dai-cells = <1>;
59 };
60
Philippe Reynes1ee26482020-07-24 18:19:51 +020061 buttons {
62 compatible = "gpio-keys";
63
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020064 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +020065 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020066 label = "button1";
Philippe Reynes1ee26482020-07-24 18:19:51 +020067 };
68
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020069 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +020070 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020071 label = "button2";
Philippe Reynes1ee26482020-07-24 18:19:51 +020072 };
73 };
74
Marek Szyprowskiad398592021-02-18 11:33:18 +010075 buttons2 {
76 compatible = "adc-keys";
77 io-channels = <&adc 3>;
78 keyup-threshold-microvolt = <3000000>;
79
80 button-up {
81 label = "button3";
82 linux,code = <KEY_F3>;
83 press-threshold-microvolt = <1500000>;
84 };
85
86 button-down {
87 label = "button4";
88 linux,code = <KEY_F4>;
89 press-threshold-microvolt = <1000000>;
90 };
91
92 button-enter {
93 label = "button5";
94 linux,code = <KEY_F5>;
95 press-threshold-microvolt = <500000>;
96 };
97 };
98
Simon Glassc953aaf2018-12-10 10:37:34 -070099 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600100 reg = <0 0>;
101 compatible = "google,cros-ec-sandbox";
102
103 /*
104 * This describes the flash memory within the EC. Note
105 * that the STM32L flash erases to 0, not 0xff.
106 */
107 flash {
108 image-pos = <0x08000000>;
109 size = <0x20000>;
110 erase-value = <0>;
111
112 /* Information for sandbox */
113 ro {
114 image-pos = <0>;
115 size = <0xf000>;
116 };
117 wp-ro {
118 image-pos = <0xf000>;
119 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700120 used = <0x884>;
121 compress = "lz4";
122 uncomp-size = <0xcf8>;
123 hash {
124 algo = "sha256";
125 value = [00 01 02 03 04 05 06 07
126 08 09 0a 0b 0c 0d 0e 0f
127 10 11 12 13 14 15 16 17
128 18 19 1a 1b 1c 1d 1e 1f];
129 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600130 };
131 rw {
132 image-pos = <0x10000>;
133 size = <0x10000>;
134 };
135 };
136 };
137
Yannick Fertré9712c822019-10-07 15:29:05 +0200138 dsi_host: dsi_host {
139 compatible = "sandbox,dsi-host";
140 };
141
Simon Glassb2c1cac2014-02-26 15:59:21 -0700142 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600143 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700144 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600145 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700146 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600147 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100148 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
149 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700150 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100151 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
152 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
153 <&gpio_b 7 GPIO_IN 3 2 1>,
154 <&gpio_b 8 GPIO_OUT 3 2 1>,
155 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100156 test3-gpios =
157 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
158 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
159 <&gpio_c 2 GPIO_OUT>,
160 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
161 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200162 <&gpio_c 5 GPIO_IN>,
163 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
164 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530165 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
166 test5-gpios = <&gpio_a 19>;
167
Simon Glass6df01f92018-12-10 10:37:37 -0700168 int-value = <1234>;
169 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200170 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200171 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600172 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700173 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600174 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200175 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530176
177 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
178 <&muxcontroller0 2>, <&muxcontroller0 3>,
179 <&muxcontroller1>;
180 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
181 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100182 display-timings {
183 timing0: 240x320 {
184 clock-frequency = <6500000>;
185 hactive = <240>;
186 vactive = <320>;
187 hfront-porch = <6>;
188 hback-porch = <7>;
189 hsync-len = <1>;
190 vback-porch = <5>;
191 vfront-porch = <8>;
192 vsync-len = <2>;
193 hsync-active = <1>;
194 vsync-active = <0>;
195 de-active = <1>;
196 pixelclk-active = <1>;
197 interlaced;
198 doublescan;
199 doubleclk;
200 };
201 timing1: 480x800 {
202 clock-frequency = <9000000>;
203 hactive = <480>;
204 vactive = <800>;
205 hfront-porch = <10>;
206 hback-porch = <59>;
207 hsync-len = <12>;
208 vback-porch = <15>;
209 vfront-porch = <17>;
210 vsync-len = <16>;
211 hsync-active = <0>;
212 vsync-active = <1>;
213 de-active = <0>;
214 pixelclk-active = <0>;
215 };
216 timing2: 800x480 {
217 clock-frequency = <33500000>;
218 hactive = <800>;
219 vactive = <480>;
220 hback-porch = <89>;
221 hfront-porch = <164>;
222 vback-porch = <23>;
223 vfront-porch = <10>;
224 hsync-len = <11>;
225 vsync-len = <13>;
226 };
227 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700228 };
229
230 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600231 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700232 compatible = "not,compatible";
233 };
234
235 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600236 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700237 };
238
Simon Glass5620cf82018-10-01 12:22:40 -0600239 backlight: backlight {
240 compatible = "pwm-backlight";
241 enable-gpios = <&gpio_a 1>;
242 power-supply = <&ldo_1>;
243 pwms = <&pwm 0 1000>;
244 default-brightness-level = <5>;
245 brightness-levels = <0 16 32 64 128 170 202 234 255>;
246 };
247
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200248 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200249 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200250 bind-test-child1 {
251 compatible = "sandbox,phy";
252 #phy-cells = <1>;
253 };
254
255 bind-test-child2 {
256 compatible = "simple-bus";
257 };
258 };
259
Simon Glassb2c1cac2014-02-26 15:59:21 -0700260 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600261 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700262 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600263 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700264 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530265
266 mux-controls = <&muxcontroller0 0>;
267 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700268 };
269
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200270 phy_provider0: gen_phy@0 {
271 compatible = "sandbox,phy";
272 #phy-cells = <1>;
273 };
274
275 phy_provider1: gen_phy@1 {
276 compatible = "sandbox,phy";
277 #phy-cells = <0>;
278 broken;
279 };
280
developer71092972020-05-02 11:35:12 +0200281 phy_provider2: gen_phy@2 {
282 compatible = "sandbox,phy";
283 #phy-cells = <0>;
284 };
285
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200286 gen_phy_user: gen_phy_user {
287 compatible = "simple-bus";
288 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
289 phy-names = "phy1", "phy2", "phy3";
290 };
291
developer71092972020-05-02 11:35:12 +0200292 gen_phy_user1: gen_phy_user1 {
293 compatible = "simple-bus";
294 phys = <&phy_provider0 0>, <&phy_provider2>;
295 phy-names = "phy1", "phy2";
296 };
297
Simon Glassb2c1cac2014-02-26 15:59:21 -0700298 some-bus {
299 #address-cells = <1>;
300 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600301 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600302 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600303 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700304 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600305 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700306 compatible = "denx,u-boot-fdt-test";
307 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600308 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700309 ping-add = <5>;
310 };
Simon Glass40717422014-07-23 06:55:18 -0600311 c-test@0 {
312 compatible = "denx,u-boot-fdt-test";
313 reg = <0>;
314 ping-expect = <6>;
315 ping-add = <6>;
316 };
317 c-test@1 {
318 compatible = "denx,u-boot-fdt-test";
319 reg = <1>;
320 ping-expect = <7>;
321 ping-add = <7>;
322 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700323 };
324
325 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600326 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600327 ping-expect = <6>;
328 ping-add = <6>;
329 compatible = "google,another-fdt-test";
330 };
331
332 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600333 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600334 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700335 ping-add = <6>;
336 compatible = "google,another-fdt-test";
337 };
338
Simon Glass0ccb0972015-01-25 08:27:05 -0700339 f-test {
340 compatible = "denx,u-boot-fdt-test";
341 };
342
343 g-test {
344 compatible = "denx,u-boot-fdt-test";
345 };
346
Bin Mengd9d24782018-10-10 22:07:01 -0700347 h-test {
348 compatible = "denx,u-boot-fdt-test1";
349 };
350
developercf8bc132020-05-02 11:35:10 +0200351 i-test {
352 compatible = "mediatek,u-boot-fdt-test";
353 #address-cells = <1>;
354 #size-cells = <0>;
355
356 subnode@0 {
357 reg = <0>;
358 };
359
360 subnode@1 {
361 reg = <1>;
362 };
363
364 subnode@2 {
365 reg = <2>;
366 };
367 };
368
Simon Glass204675c2019-12-29 21:19:25 -0700369 devres-test {
370 compatible = "denx,u-boot-devres-test";
371 };
372
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530373 another-test {
374 reg = <0 2>;
375 compatible = "denx,u-boot-fdt-test";
376 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
377 test5-gpios = <&gpio_a 19>;
378 };
379
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100380 mmio-bus@0 {
381 #address-cells = <1>;
382 #size-cells = <1>;
383 compatible = "denx,u-boot-test-bus";
384 dma-ranges = <0x10000000 0x00000000 0x00040000>;
385
386 subnode@0 {
387 compatible = "denx,u-boot-fdt-test";
388 };
389 };
390
391 mmio-bus@1 {
392 #address-cells = <1>;
393 #size-cells = <1>;
394 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100395
396 subnode@0 {
397 compatible = "denx,u-boot-fdt-test";
398 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100399 };
400
Simon Glass3c601b12020-07-07 13:12:06 -0600401 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600402 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600403 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600404 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600405 child {
406 compatible = "denx,u-boot-acpi-test";
407 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600408 };
409
Simon Glass3c601b12020-07-07 13:12:06 -0600410 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600411 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600412 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600413 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600414 };
415
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200416 clocks {
417 clk_fixed: clk-fixed {
418 compatible = "fixed-clock";
419 #clock-cells = <0>;
420 clock-frequency = <1234>;
421 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000422
423 clk_fixed_factor: clk-fixed-factor {
424 compatible = "fixed-factor-clock";
425 #clock-cells = <0>;
426 clock-div = <3>;
427 clock-mult = <2>;
428 clocks = <&clk_fixed>;
429 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200430
431 osc {
432 compatible = "fixed-clock";
433 #clock-cells = <0>;
434 clock-frequency = <20000000>;
435 };
Stephen Warrena9622432016-06-17 09:44:00 -0600436 };
437
438 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600439 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600440 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200441 assigned-clocks = <&clk_sandbox 3>;
442 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600443 };
444
445 clk-test {
446 compatible = "sandbox,clk-test";
447 clocks = <&clk_fixed>,
448 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200449 <&clk_sandbox 0>,
450 <&clk_sandbox 3>,
451 <&clk_sandbox 2>;
452 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600453 };
454
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200455 ccf: clk-ccf {
456 compatible = "sandbox,clk-ccf";
457 };
458
Simon Glass5b968632015-05-22 15:42:15 -0600459 eth@10002000 {
460 compatible = "sandbox,eth";
461 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500462 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600463 };
464
465 eth_5: eth@10003000 {
466 compatible = "sandbox,eth";
467 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500468 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600469 };
470
Bin Meng04a11cb2015-08-27 22:25:53 -0700471 eth_3: sbe5 {
472 compatible = "sandbox,eth";
473 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500474 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700475 };
476
Simon Glass5b968632015-05-22 15:42:15 -0600477 eth@10004000 {
478 compatible = "sandbox,eth";
479 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500480 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600481 };
482
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800483 dsa_eth0: dsa-test-eth {
484 compatible = "sandbox,eth";
485 reg = <0x10006000 0x1000>;
486 fake-host-hwaddr = [00 00 66 44 22 66];
487 };
488
489 dsa-test {
490 compatible = "sandbox,dsa";
491
492 ports {
493 #address-cells = <1>;
494 #size-cells = <0>;
495 swp_0: port@0 {
496 reg = <0>;
497 label = "lan0";
498 phy-mode = "rgmii-rxid";
499
500 fixed-link {
501 speed = <100>;
502 full-duplex;
503 };
504 };
505
506 swp_1: port@1 {
507 reg = <1>;
508 label = "lan1";
509 phy-mode = "rgmii-txid";
510
511 fixed-link {
512 speed = <100>;
513 full-duplex;
514 };
515 };
516
517 port@2 {
518 reg = <2>;
519 ethernet = <&dsa_eth0>;
520
521 fixed-link {
522 speed = <1000>;
523 full-duplex;
524 };
525 };
526 };
527 };
528
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700529 firmware {
530 sandbox_firmware: sandbox-firmware {
531 compatible = "sandbox,firmware";
532 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200533
534 sandbox-scmi-agent@0 {
535 compatible = "sandbox,scmi-agent";
536 #address-cells = <1>;
537 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200538
539 clk_scmi0: protocol@14 {
540 reg = <0x14>;
541 #clock-cells = <1>;
542 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200543
544 reset_scmi0: protocol@16 {
545 reg = <0x16>;
546 #reset-cells = <1>;
547 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100548
549 protocol@17 {
550 reg = <0x17>;
551
552 regulators {
553 #address-cells = <1>;
554 #size-cells = <0>;
555
556 regul0_scmi0: reg@0 {
557 reg = <0>;
558 regulator-name = "sandbox-voltd0";
559 regulator-min-microvolt = <1100000>;
560 regulator-max-microvolt = <3300000>;
561 };
562 regul1_scmi0: reg@1 {
563 reg = <0x1>;
564 regulator-name = "sandbox-voltd1";
565 regulator-min-microvolt = <1800000>;
566 };
567 };
568 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200569 };
570
571 sandbox-scmi-agent@1 {
572 compatible = "sandbox,scmi-agent";
573 #address-cells = <1>;
574 #size-cells = <0>;
575
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200576 clk_scmi1: protocol@14 {
577 reg = <0x14>;
578 #clock-cells = <1>;
579 };
580
Etienne Carriere02fd1262020-09-09 18:44:00 +0200581 protocol@10 {
582 reg = <0x10>;
583 };
584 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700585 };
586
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100587 pinctrl-gpio {
588 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700589
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100590 gpio_a: base-gpios {
591 compatible = "sandbox,gpio";
592 gpio-controller;
593 #gpio-cells = <1>;
594 gpio-bank-name = "a";
595 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200596 hog_input_active_low {
597 gpio-hog;
598 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200599 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200600 };
601 hog_input_active_high {
602 gpio-hog;
603 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200604 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200605 };
606 hog_output_low {
607 gpio-hog;
608 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200609 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200610 };
611 hog_output_high {
612 gpio-hog;
613 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200614 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200615 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100616 };
617
618 gpio_b: extra-gpios {
619 compatible = "sandbox,gpio";
620 gpio-controller;
621 #gpio-cells = <5>;
622 gpio-bank-name = "b";
623 sandbox,gpio-count = <10>;
624 };
Simon Glass25348a42014-10-13 23:42:11 -0600625
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100626 gpio_c: pinmux-gpios {
627 compatible = "sandbox,gpio";
628 gpio-controller;
629 #gpio-cells = <2>;
630 gpio-bank-name = "c";
631 sandbox,gpio-count = <10>;
632 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100633 };
634
Simon Glass7df766e2014-12-10 08:55:55 -0700635 i2c@0 {
636 #address-cells = <1>;
637 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600638 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700639 compatible = "sandbox,i2c";
640 clock-frequency = <100000>;
641 eeprom@2c {
642 reg = <0x2c>;
643 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700644 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200645 partitions {
646 compatible = "fixed-partitions";
647 #address-cells = <1>;
648 #size-cells = <1>;
649 bootcount_i2c: bootcount@10 {
650 reg = <10 2>;
651 };
652 };
Simon Glass7df766e2014-12-10 08:55:55 -0700653 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200654
Simon Glass336b2952015-05-22 15:42:17 -0600655 rtc_0: rtc@43 {
656 reg = <0x43>;
657 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700658 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600659 };
660
661 rtc_1: rtc@61 {
662 reg = <0x61>;
663 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700664 sandbox,emul = <&emul1>;
665 };
666
667 i2c_emul: emul {
668 reg = <0xff>;
669 compatible = "sandbox,i2c-emul-parent";
670 emul_eeprom: emul-eeprom {
671 compatible = "sandbox,i2c-eeprom";
672 sandbox,filename = "i2c.bin";
673 sandbox,size = <256>;
674 };
675 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700676 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700677 };
678 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700679 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600680 };
681 };
682
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200683 sandbox_pmic: sandbox_pmic {
684 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700685 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200686 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200687
688 mc34708: pmic@41 {
689 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700690 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200691 };
Simon Glass7df766e2014-12-10 08:55:55 -0700692 };
693
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100694 bootcount@0 {
695 compatible = "u-boot,bootcount-rtc";
696 rtc = <&rtc_1>;
697 offset = <0x13>;
698 };
699
Michal Simek4f18f922020-05-28 11:48:55 +0200700 bootcount {
701 compatible = "u-boot,bootcount-i2c-eeprom";
702 i2c-eeprom = <&bootcount_i2c>;
703 };
704
Marek Szyprowskiad398592021-02-18 11:33:18 +0100705 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100706 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100707 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100708 vdd-supply = <&buck2>;
709 vss-microvolts = <0>;
710 };
711
Simon Glass515dcff2020-02-06 09:55:00 -0700712 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700713 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700714 interrupt-controller;
715 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700716 };
717
Simon Glass90b6fef2016-01-18 19:52:26 -0700718 lcd {
719 u-boot,dm-pre-reloc;
720 compatible = "sandbox,lcd-sdl";
721 xres = <1366>;
722 yres = <768>;
723 };
724
Simon Glassd783eb32015-07-06 12:54:34 -0600725 leds {
726 compatible = "gpio-leds";
727
728 iracibble {
729 gpios = <&gpio_a 1 0>;
730 label = "sandbox:red";
731 };
732
733 martinet {
734 gpios = <&gpio_a 2 0>;
735 label = "sandbox:green";
736 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200737
738 default_on {
739 gpios = <&gpio_a 5 0>;
740 label = "sandbox:default_on";
741 default-state = "on";
742 };
743
744 default_off {
745 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400746 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200747 default-state = "off";
748 };
Simon Glassd783eb32015-07-06 12:54:34 -0600749 };
750
Stephen Warren62f2c902016-05-16 17:41:37 -0600751 mbox: mbox {
752 compatible = "sandbox,mbox";
753 #mbox-cells = <1>;
754 };
755
756 mbox-test {
757 compatible = "sandbox,mbox-test";
758 mboxes = <&mbox 100>, <&mbox 1>;
759 mbox-names = "other", "test";
760 };
761
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900762 cpus {
Sean Anderson79d3bba2020-09-28 10:52:23 -0400763 timebase-frequency = <2000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900764 cpu-test1 {
Sean Anderson79d3bba2020-09-28 10:52:23 -0400765 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900766 compatible = "sandbox,cpu_sandbox";
767 u-boot,dm-pre-reloc;
768 };
Mario Sixdea5df72018-08-06 10:23:44 +0200769
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900770 cpu-test2 {
771 compatible = "sandbox,cpu_sandbox";
772 u-boot,dm-pre-reloc;
773 };
Mario Sixdea5df72018-08-06 10:23:44 +0200774
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900775 cpu-test3 {
776 compatible = "sandbox,cpu_sandbox";
777 u-boot,dm-pre-reloc;
778 };
Mario Sixdea5df72018-08-06 10:23:44 +0200779 };
780
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500781 chipid: chipid {
782 compatible = "sandbox,soc";
783 };
784
Simon Glassc953aaf2018-12-10 10:37:34 -0700785 i2s: i2s {
786 compatible = "sandbox,i2s";
787 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700788 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700789 };
790
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200791 nop-test_0 {
792 compatible = "sandbox,nop_sandbox1";
793 nop-test_1 {
794 compatible = "sandbox,nop_sandbox2";
795 bind = "True";
796 };
797 nop-test_2 {
798 compatible = "sandbox,nop_sandbox2";
799 bind = "False";
800 };
801 };
802
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200803 misc-test {
804 compatible = "sandbox,misc_sandbox";
805 };
806
Simon Glasse4fef742017-04-23 20:02:07 -0600807 mmc2 {
808 compatible = "sandbox,mmc";
809 };
810
811 mmc1 {
812 compatible = "sandbox,mmc";
813 };
814
815 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600816 compatible = "sandbox,mmc";
817 };
818
Simon Glass53a68b32019-02-16 20:24:50 -0700819 pch {
820 compatible = "sandbox,pch";
821 };
822
Tom Rini4a3ca482020-02-11 12:41:23 -0500823 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700824 compatible = "sandbox,pci";
825 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500826 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700827 #address-cells = <3>;
828 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600829 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700830 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700831 pci@0,0 {
832 compatible = "pci-generic";
833 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600834 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700835 };
Alex Margineanf1274432019-06-07 11:24:24 +0300836 pci@1,0 {
837 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600838 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
839 reg = <0x02000814 0 0 0 0
840 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600841 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300842 };
Simon Glass937bb472019-12-06 21:41:57 -0700843 p2sb-pci@2,0 {
844 compatible = "sandbox,p2sb";
845 reg = <0x02001010 0 0 0 0>;
846 sandbox,emul = <&p2sb_emul>;
847
848 adder {
849 intel,p2sb-port-id = <3>;
850 compatible = "sandbox,adder";
851 };
852 };
Simon Glass8c501022019-12-06 21:41:54 -0700853 pci@1e,0 {
854 compatible = "sandbox,pmc";
855 reg = <0xf000 0 0 0 0>;
856 sandbox,emul = <&pmc_emul1e>;
857 acpi-base = <0x400>;
858 gpe0-dwx-mask = <0xf>;
859 gpe0-dwx-shift-base = <4>;
860 gpe0-dw = <6 7 9>;
861 gpe0-sts = <0x20>;
862 gpe0-en = <0x30>;
863 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700864 pci@1f,0 {
865 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600866 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
867 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600868 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700869 };
870 };
871
Simon Glassb98ba4c2019-09-25 08:56:10 -0600872 pci-emul0 {
873 compatible = "sandbox,pci-emul-parent";
874 swap_case_emul0_0: emul0@0,0 {
875 compatible = "sandbox,swap-case";
876 };
877 swap_case_emul0_1: emul0@1,0 {
878 compatible = "sandbox,swap-case";
879 use-ea;
880 };
881 swap_case_emul0_1f: emul0@1f,0 {
882 compatible = "sandbox,swap-case";
883 };
Simon Glass937bb472019-12-06 21:41:57 -0700884 p2sb_emul: emul@2,0 {
885 compatible = "sandbox,p2sb-emul";
886 };
Simon Glass8c501022019-12-06 21:41:54 -0700887 pmc_emul1e: emul@1e,0 {
888 compatible = "sandbox,pmc-emul";
889 };
Simon Glassb98ba4c2019-09-25 08:56:10 -0600890 };
891
Tom Rini4a3ca482020-02-11 12:41:23 -0500892 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -0700893 compatible = "sandbox,pci";
894 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500895 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -0700896 #address-cells = <3>;
897 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -0700898 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
899 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
900 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700901 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200902 0x0c 0x00 0x1234 0x5678
903 0x10 0x00 0x1234 0x5678>;
904 pci@10,0 {
905 reg = <0x8000 0 0 0 0>;
906 };
Bin Meng408e5902018-08-03 01:14:41 -0700907 };
908
Tom Rini4a3ca482020-02-11 12:41:23 -0500909 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -0700910 compatible = "sandbox,pci";
911 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500912 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -0700913 #address-cells = <3>;
914 #size-cells = <2>;
915 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
916 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
917 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
918 pci@1f,0 {
919 compatible = "pci-generic";
920 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600921 sandbox,emul = <&swap_case_emul2_1f>;
922 };
923 };
924
925 pci-emul2 {
926 compatible = "sandbox,pci-emul-parent";
927 swap_case_emul2_1f: emul2@1f,0 {
928 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -0700929 };
930 };
931
Ramon Friedc64f19b2019-04-27 11:15:23 +0300932 pci_ep: pci_ep {
933 compatible = "sandbox,pci_ep";
934 };
935
Simon Glass9c433fe2017-04-23 20:10:44 -0600936 probing {
937 compatible = "simple-bus";
938 test1 {
939 compatible = "denx,u-boot-probe-test";
940 };
941
942 test2 {
943 compatible = "denx,u-boot-probe-test";
944 };
945
946 test3 {
947 compatible = "denx,u-boot-probe-test";
948 };
949
950 test4 {
951 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100952 first-syscon = <&syscon0>;
953 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +0100954 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -0600955 };
956 };
957
Stephen Warren92c67fa2016-07-13 13:45:31 -0600958 pwrdom: power-domain {
959 compatible = "sandbox,power-domain";
960 #power-domain-cells = <1>;
961 };
962
963 power-domain-test {
964 compatible = "sandbox,power-domain-test";
965 power-domains = <&pwrdom 2>;
966 };
967
Simon Glass5620cf82018-10-01 12:22:40 -0600968 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -0600969 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600970 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600971 };
972
973 pwm2 {
974 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600975 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600976 };
977
Simon Glass3d355e62015-07-06 12:54:31 -0600978 ram {
979 compatible = "sandbox,ram";
980 };
981
Simon Glassd860f222015-07-06 12:54:29 -0600982 reset@0 {
983 compatible = "sandbox,warm-reset";
984 };
985
986 reset@1 {
987 compatible = "sandbox,reset";
988 };
989
Stephen Warren6488e642016-06-17 09:43:59 -0600990 resetc: reset-ctl {
991 compatible = "sandbox,reset-ctl";
992 #reset-cells = <1>;
993 };
994
995 reset-ctl-test {
996 compatible = "sandbox,reset-ctl-test";
997 resets = <&resetc 100>, <&resetc 2>;
998 reset-names = "other", "test";
999 };
1000
Sughosh Ganu23e37512019-12-28 23:58:31 +05301001 rng {
1002 compatible = "sandbox,sandbox-rng";
1003 };
1004
Nishanth Menonedf85812015-09-17 15:42:41 -05001005 rproc_1: rproc@1 {
1006 compatible = "sandbox,test-processor";
1007 remoteproc-name = "remoteproc-test-dev1";
1008 };
1009
1010 rproc_2: rproc@2 {
1011 compatible = "sandbox,test-processor";
1012 internal-memory-mapped;
1013 remoteproc-name = "remoteproc-test-dev2";
1014 };
1015
Simon Glass5620cf82018-10-01 12:22:40 -06001016 panel {
1017 compatible = "simple-panel";
1018 backlight = <&backlight 0 100>;
1019 };
1020
Ramon Fried26ed32e2018-07-02 02:57:59 +03001021 smem@0 {
1022 compatible = "sandbox,smem";
1023 };
1024
Simon Glass76072ac2018-12-10 10:37:36 -07001025 sound {
1026 compatible = "sandbox,sound";
1027 cpu {
1028 sound-dai = <&i2s 0>;
1029 };
1030
1031 codec {
1032 sound-dai = <&audio 0>;
1033 };
1034 };
1035
Simon Glass25348a42014-10-13 23:42:11 -06001036 spi@0 {
1037 #address-cells = <1>;
1038 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001039 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001040 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001041 cs-gpios = <0>, <0>, <&gpio_a 0>;
Simon Glass25348a42014-10-13 23:42:11 -06001042 spi.bin@0 {
1043 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001044 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001045 spi-max-frequency = <40000000>;
1046 sandbox,filename = "spi.bin";
1047 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001048 spi.bin@1 {
1049 reg = <1>;
1050 compatible = "spansion,m25p16", "jedec,spi-nor";
1051 spi-max-frequency = <50000000>;
1052 sandbox,filename = "spi.bin";
1053 spi-cpol;
1054 spi-cpha;
1055 };
Simon Glass25348a42014-10-13 23:42:11 -06001056 };
1057
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001058 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001059 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001060 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001061 };
1062
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001063 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001064 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001065 reg = <0x20 5
1066 0x28 6
1067 0x30 7
1068 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001069 };
1070
Patrick Delaunayee010432019-03-07 09:57:13 +01001071 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001072 compatible = "simple-mfd", "syscon";
1073 reg = <0x40 5
1074 0x48 6
1075 0x50 7
1076 0x58 8>;
1077 };
1078
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301079 syscon3: syscon@3 {
1080 compatible = "simple-mfd", "syscon";
1081 reg = <0x000100 0x10>;
1082
1083 muxcontroller0: a-mux-controller {
1084 compatible = "mmio-mux";
1085 #mux-control-cells = <1>;
1086
1087 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1088 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1089 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1090 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1091 u-boot,mux-autoprobe;
1092 };
1093 };
1094
1095 muxcontroller1: emul-mux-controller {
1096 compatible = "mux-emul";
1097 #mux-control-cells = <0>;
1098 u-boot,mux-autoprobe;
1099 idle-state = <0xabcd>;
1100 };
1101
Simon Glass791a17f2020-12-16 21:20:27 -07001102 testfdtm0 {
1103 compatible = "denx,u-boot-fdtm-test";
1104 };
1105
1106 testfdtm1: testfdtm1 {
1107 compatible = "denx,u-boot-fdtm-test";
1108 };
1109
1110 testfdtm2 {
1111 compatible = "denx,u-boot-fdtm-test";
1112 };
1113
Sean Anderson79d3bba2020-09-28 10:52:23 -04001114 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001115 compatible = "sandbox,timer";
1116 clock-frequency = <1000000>;
1117 };
1118
Sean Anderson79d3bba2020-09-28 10:52:23 -04001119 timer@1 {
1120 compatible = "sandbox,timer";
1121 sandbox,timebase-frequency-fallback;
1122 };
1123
Miquel Raynal80938c12018-05-15 11:57:27 +02001124 tpm2 {
1125 compatible = "sandbox,tpm2";
1126 };
1127
Simon Glass5b968632015-05-22 15:42:15 -06001128 uart0: serial {
1129 compatible = "sandbox,serial";
1130 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -05001131 };
1132
Simon Glass31680482015-03-25 12:23:05 -06001133 usb_0: usb@0 {
1134 compatible = "sandbox,usb";
1135 status = "disabled";
1136 hub {
1137 compatible = "sandbox,usb-hub";
1138 #address-cells = <1>;
1139 #size-cells = <0>;
1140 flash-stick {
1141 reg = <0>;
1142 compatible = "sandbox,usb-flash";
1143 };
1144 };
1145 };
1146
1147 usb_1: usb@1 {
1148 compatible = "sandbox,usb";
1149 hub {
1150 compatible = "usb-hub";
1151 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001152 #address-cells = <1>;
1153 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001154 hub-emul {
1155 compatible = "sandbox,usb-hub";
1156 #address-cells = <1>;
1157 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001158 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001159 reg = <0>;
1160 compatible = "sandbox,usb-flash";
1161 sandbox,filepath = "testflash.bin";
1162 };
1163
Simon Glass4700fe52015-11-08 23:48:01 -07001164 flash-stick@1 {
1165 reg = <1>;
1166 compatible = "sandbox,usb-flash";
1167 sandbox,filepath = "testflash1.bin";
1168 };
1169
1170 flash-stick@2 {
1171 reg = <2>;
1172 compatible = "sandbox,usb-flash";
1173 sandbox,filepath = "testflash2.bin";
1174 };
1175
Simon Glassc0ccc722015-11-08 23:48:08 -07001176 keyb@3 {
1177 reg = <3>;
1178 compatible = "sandbox,usb-keyb";
1179 };
1180
Simon Glass31680482015-03-25 12:23:05 -06001181 };
Michael Walle7c961322020-06-02 01:47:07 +02001182
1183 usbstor@1 {
1184 reg = <1>;
1185 };
1186 usbstor@3 {
1187 reg = <3>;
1188 };
Simon Glass31680482015-03-25 12:23:05 -06001189 };
1190 };
1191
1192 usb_2: usb@2 {
1193 compatible = "sandbox,usb";
1194 status = "disabled";
1195 };
1196
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001197 spmi: spmi@0 {
1198 compatible = "sandbox,spmi";
1199 #address-cells = <0x1>;
1200 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001201 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001202 pm8916@0 {
1203 compatible = "qcom,spmi-pmic";
1204 reg = <0x0 0x1>;
1205 #address-cells = <0x1>;
1206 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001207 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001208
1209 spmi_gpios: gpios@c000 {
1210 compatible = "qcom,pm8916-gpio";
1211 reg = <0xc000 0x400>;
1212 gpio-controller;
1213 gpio-count = <4>;
1214 #gpio-cells = <2>;
1215 gpio-bank-name="spmi";
1216 };
1217 };
1218 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001219
1220 wdt0: wdt@0 {
1221 compatible = "sandbox,wdt";
1222 };
Rob Clarka471b672018-01-10 11:33:30 +01001223
Mario Six95922152018-08-09 14:51:19 +02001224 axi: axi@0 {
1225 compatible = "sandbox,axi";
1226 #address-cells = <0x1>;
1227 #size-cells = <0x1>;
1228 store@0 {
1229 compatible = "sandbox,sandbox_store";
1230 reg = <0x0 0x400>;
1231 };
1232 };
1233
Rob Clarka471b672018-01-10 11:33:30 +01001234 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001235 #address-cells = <1>;
1236 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001237 setting = "sunrise ohoka";
1238 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001239 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001240 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001241 chosen-test {
1242 compatible = "denx,u-boot-fdt-test";
1243 reg = <9 1>;
1244 };
1245 };
Mario Six35616ef2018-03-12 14:53:33 +01001246
1247 translation-test@8000 {
1248 compatible = "simple-bus";
1249 reg = <0x8000 0x4000>;
1250
1251 #address-cells = <0x2>;
1252 #size-cells = <0x1>;
1253
1254 ranges = <0 0x0 0x8000 0x1000
1255 1 0x100 0x9000 0x1000
1256 2 0x200 0xA000 0x1000
1257 3 0x300 0xB000 0x1000
Dario Binacchib574d682020-12-30 00:16:21 +01001258 4 0x400 0xC000 0x1000
Mario Six35616ef2018-03-12 14:53:33 +01001259 >;
1260
Fabien Dessenne22236e02019-05-31 15:11:30 +02001261 dma-ranges = <0 0x000 0x10000000 0x1000
1262 1 0x100 0x20000000 0x1000
1263 >;
1264
Mario Six35616ef2018-03-12 14:53:33 +01001265 dev@0,0 {
1266 compatible = "denx,u-boot-fdt-dummy";
1267 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +01001268 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001269 };
1270
1271 dev@1,100 {
1272 compatible = "denx,u-boot-fdt-dummy";
1273 reg = <1 0x100 0x1000>;
1274
1275 };
1276
1277 dev@2,200 {
1278 compatible = "denx,u-boot-fdt-dummy";
1279 reg = <2 0x200 0x1000>;
1280 };
1281
1282
1283 noxlatebus@3,300 {
1284 compatible = "simple-bus";
1285 reg = <3 0x300 0x1000>;
1286
1287 #address-cells = <0x1>;
1288 #size-cells = <0x0>;
1289
1290 dev@42 {
1291 compatible = "denx,u-boot-fdt-dummy";
1292 reg = <0x42>;
1293 };
1294 };
Dario Binacchib574d682020-12-30 00:16:21 +01001295
1296 xlatebus@4,400 {
1297 compatible = "sandbox,zero-size-cells-bus";
1298 reg = <4 0x400 0x1000>;
1299 #address-cells = <1>;
1300 #size-cells = <1>;
1301 ranges = <0 4 0x400 0x1000>;
1302
1303 devs {
1304 #address-cells = <1>;
1305 #size-cells = <0>;
1306
1307 dev@19 {
1308 compatible = "denx,u-boot-fdt-dummy";
1309 reg = <0x19>;
1310 };
1311 };
1312 };
1313
Mario Six35616ef2018-03-12 14:53:33 +01001314 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001315
1316 osd {
1317 compatible = "sandbox,sandbox_osd";
1318 };
Tom Rinib93eea72018-09-30 18:16:51 -04001319
Jens Wiklander86afaa62018-09-25 16:40:16 +02001320 sandbox_tee {
1321 compatible = "sandbox,tee";
1322 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001323
1324 sandbox_virtio1 {
1325 compatible = "sandbox,virtio1";
1326 };
1327
1328 sandbox_virtio2 {
1329 compatible = "sandbox,virtio2";
1330 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001331
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001332 sandbox_scmi {
1333 compatible = "sandbox,scmi-devices";
1334 clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>;
Etienne Carriere8b9b6892020-09-09 18:44:07 +02001335 resets = <&reset_scmi0 3>;
Etienne Carriereb8f15cd2021-03-08 22:38:07 +01001336 regul0-supply = <&regul0_scmi0>;
1337 regul1-supply = <&regul1_scmi0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001338 };
1339
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001340 pinctrl {
1341 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001342
Sean Anderson3438e3b2020-09-14 11:01:57 -04001343 pinctrl-names = "default", "alternate";
1344 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1345 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001346
Sean Anderson3438e3b2020-09-14 11:01:57 -04001347 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001348 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001349 pins = "P5";
1350 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001351 bias-pull-up;
1352 input-disable;
1353 };
1354 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001355 pins = "P6";
1356 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001357 output-high;
1358 drive-open-drain;
1359 };
1360 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001361 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001362 bias-pull-down;
1363 input-enable;
1364 };
1365 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001366 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001367 bias-disable;
1368 };
1369 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001370
1371 pinctrl_i2c: i2c {
1372 groups {
1373 groups = "I2C_UART";
1374 function = "I2C";
1375 };
1376
1377 pins {
1378 pins = "P0", "P1";
1379 drive-open-drain;
1380 };
1381 };
1382
1383 pinctrl_i2s: i2s {
1384 groups = "SPI_I2S";
1385 function = "I2S";
1386 };
1387
1388 pinctrl_spi: spi {
1389 groups = "SPI_I2S";
1390 function = "SPI";
1391
1392 cs {
1393 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1394 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1395 };
1396 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001397 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001398
1399 hwspinlock@0 {
1400 compatible = "sandbox,hwspinlock";
1401 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001402
1403 dma: dma {
1404 compatible = "sandbox,dma";
1405 #dma-cells = <1>;
1406
1407 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1408 dma-names = "m2m", "tx0", "rx0";
1409 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001410
Alex Marginean0649be52019-07-12 10:13:53 +03001411 /*
1412 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1413 * end of the test. If parent mdio is removed first, clean-up of the
1414 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1415 * active at the end of the test. That it turn doesn't allow the mdio
1416 * class to be destroyed, triggering an error.
1417 */
1418 mdio-mux-test {
1419 compatible = "sandbox,mdio-mux";
1420 #address-cells = <1>;
1421 #size-cells = <0>;
1422 mdio-parent-bus = <&mdio>;
1423
1424 mdio-ch-test@0 {
1425 reg = <0>;
1426 };
1427 mdio-ch-test@1 {
1428 reg = <1>;
1429 };
1430 };
1431
1432 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001433 compatible = "sandbox,mdio";
1434 };
Sean Andersonb7860542020-06-24 06:41:12 -04001435
1436 pm-bus-test {
1437 compatible = "simple-pm-bus";
1438 clocks = <&clk_sandbox 4>;
1439 power-domains = <&pwrdom 1>;
1440 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001441
1442 resetc2: syscon-reset {
1443 compatible = "syscon-reset";
1444 #reset-cells = <1>;
1445 regmap = <&syscon0>;
1446 offset = <1>;
1447 mask = <0x27FFFFFF>;
1448 assert-high = <0>;
1449 };
1450
1451 syscon-reset-test {
1452 compatible = "sandbox,misc_sandbox";
1453 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1454 reset-names = "valid", "no_mask", "out_of_range";
1455 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301456
Simon Glass458b66a2020-11-05 06:32:05 -07001457 sysinfo {
1458 compatible = "sandbox,sysinfo-sandbox";
1459 };
1460
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301461 some_regmapped-bus {
1462 #address-cells = <0x1>;
1463 #size-cells = <0x1>;
1464
1465 ranges = <0x0 0x0 0x10>;
1466 compatible = "simple-bus";
1467
1468 regmap-test_0 {
1469 reg = <0 0x10>;
1470 compatible = "sandbox,regmap_test";
1471 };
1472 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001473};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001474
1475#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001476#include "cros-ec-keyboard.dtsi"