blob: b48456aebee33d1d932ab94ee93226f731c03fc0 [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay23aee612020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010017
Simon Glassb2c1cac2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070023
Simon Glassfef72b72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Sean Anderson67d93a42022-05-05 13:11:30 -040031 ethernet6 = "/eth@10004000";
32 ethernet7 = &swp_1;
33 ethernet8 = &phy_eth0;
Simon Glass5620cf82018-10-01 12:22:40 -060034 gpio1 = &gpio_a;
35 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010036 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070037 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060038 mmc0 = "/mmc0";
39 mmc1 = "/mmc1";
Simon Glassf1eba352022-10-20 18:23:20 -060040 mmc2 = "/mmc2";
41 mmc3 = "/mmc3";
Simon Glassfff928c2023-08-24 13:55:41 -060042 mmc4 = "/mmc4";
43 mmc5 = "/mmc5";
Bin Meng408e5902018-08-03 01:14:41 -070044 pci0 = &pci0;
45 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070046 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020047 remoteproc0 = &rproc_1;
48 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060049 rtc0 = &rtc_0;
50 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060051 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020052 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070053 testbus3 = "/some-bus";
54 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070055 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070056 testfdt3 = "/b-test";
57 testfdt5 = "/some-bus/c-test@5";
58 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070059 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020060 fdt-dummy0 = "/translation-test@8000/dev@0,0";
61 fdt-dummy1 = "/translation-test@8000/dev@1,100";
62 fdt-dummy2 = "/translation-test@8000/dev@2,200";
63 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060064 usb0 = &usb_0;
65 usb1 = &usb_1;
66 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020067 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020068 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060069 };
70
Simon Glass5e135d32022-10-20 18:23:15 -060071 binman: binman {
Philippe Reynes462d1632022-03-28 22:56:53 +020072 };
73
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020074 config {
Simon Glass0034d962021-08-07 07:24:01 -060075 testing-bool;
76 testing-int = <123>;
77 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020078 environment {
79 from_fdt = "yes";
80 fdt_env_path = "";
81 };
82 };
83
Simon Glassb255efc2022-04-24 23:31:24 -060084 bootstd {
Simon Glassd3a98cb2023-02-13 08:56:33 -070085 bootph-verify;
Simon Glassb255efc2022-04-24 23:31:24 -060086 compatible = "u-boot,boot-std";
87
88 filename-prefixes = "/", "/boot/";
89 bootdev-order = "mmc2", "mmc1";
90
Simon Glassb71d7f72023-05-10 16:34:46 -060091 extlinux {
92 compatible = "u-boot,extlinux";
Simon Glassb255efc2022-04-24 23:31:24 -060093 };
94
95 efi {
96 compatible = "u-boot,distro-efi";
97 };
Simon Glassa9289612022-10-20 18:23:14 -060098
Simon Glassd2bc33ed2023-01-06 08:52:41 -060099 theme {
100 font-size = <30>;
Simon Glass86f1ac52023-06-01 10:23:00 -0600101 menu-inset = <3>;
102 menuitem-gap-y = <1>;
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600103 };
104
Simon Glass82adc292023-08-14 16:40:30 -0600105 cedit-theme {
106 font-size = <30>;
107 menu-inset = <3>;
108 menuitem-gap-y = <1>;
109 };
110
Simon Glassf1eba352022-10-20 18:23:20 -0600111 /*
112 * This is used for the VBE OS-request tests. A FAT filesystem
113 * created in a partition with the VBE information appearing
114 * before the parititon starts
115 */
Simon Glassa9289612022-10-20 18:23:14 -0600116 firmware0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700117 bootph-verify;
Simon Glassa9289612022-10-20 18:23:14 -0600118 compatible = "fwupd,vbe-simple";
119 storage = "mmc1";
120 skip-offset = <0x200>;
121 area-start = <0x400>;
122 area-size = <0x1000>;
123 state-offset = <0x400>;
124 state-size = <0x40>;
125 version-offset = <0x800>;
126 version-size = <0x100>;
127 };
Simon Glassf1eba352022-10-20 18:23:20 -0600128
129 /*
130 * This is used for the VBE VPL tests. The MMC device holds the
131 * binman image.bin file. The test progresses through each phase
132 * of U-Boot, loading each in turn from MMC.
133 *
134 * Note that the test enables this node (and mmc3) before
135 * running U-Boot
136 */
137 firmware1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700138 bootph-verify;
Simon Glassf1eba352022-10-20 18:23:20 -0600139 status = "disabled";
140 compatible = "fwupd,vbe-simple";
141 storage = "mmc3";
Simon Glass9bb73e32023-04-02 14:01:24 +1200142 skip-offset = <0x800000>;
Simon Glassf1eba352022-10-20 18:23:20 -0600143 area-start = <0>;
144 area-size = <0xe00000>;
145 state-offset = <0xdffc00>;
146 state-size = <0x40>;
147 version-offset = <0xdffe00>;
148 version-size = <0x100>;
149 };
Simon Glassb255efc2022-04-24 23:31:24 -0600150 };
151
Simon Glass61300722023-06-01 10:23:01 -0600152 cedit: cedit {
153 };
154
Andrew Scull451b8b12022-05-30 10:00:12 +0000155 fuzzing-engine {
156 compatible = "sandbox,fuzzing-engine";
157 };
158
Nandor Han6521e5d2021-06-10 16:56:44 +0300159 reboot-mode0 {
160 compatible = "reboot-mode-gpio";
161 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
162 u-boot,env-variable = "bootstatus";
163 mode-test = <0x01>;
164 mode-download = <0x03>;
165 };
166
Nandor Han7e4067a2021-06-10 16:56:45 +0300167 reboot_mode1: reboot-mode@14 {
168 compatible = "reboot-mode-rtc";
169 rtc = <&rtc_0>;
170 reg = <0x30 4>;
171 u-boot,env-variable = "bootstatus";
172 big-endian;
173 mode-test = <0x21969147>;
174 mode-download = <0x51939147>;
175 };
176
Simon Glassed96cde2018-12-10 10:37:33 -0700177 audio: audio-codec {
178 compatible = "sandbox,audio-codec";
179 #sound-dai-cells = <1>;
180 };
181
Philippe Reynes1ee26482020-07-24 18:19:51 +0200182 buttons {
183 compatible = "gpio-keys";
184
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200185 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200186 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200187 label = "button1";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300188 linux,code = <BTN_1>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200189 };
190
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200191 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200192 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200193 label = "button2";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300194 linux,code = <BTN_2>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200195 };
196 };
197
Marek Szyprowskiad398592021-02-18 11:33:18 +0100198 buttons2 {
199 compatible = "adc-keys";
200 io-channels = <&adc 3>;
201 keyup-threshold-microvolt = <3000000>;
202
203 button-up {
204 label = "button3";
205 linux,code = <KEY_F3>;
206 press-threshold-microvolt = <1500000>;
207 };
208
209 button-down {
210 label = "button4";
211 linux,code = <KEY_F4>;
212 press-threshold-microvolt = <1000000>;
213 };
214
215 button-enter {
216 label = "button5";
217 linux,code = <KEY_F5>;
218 press-threshold-microvolt = <500000>;
219 };
220 };
221
Simon Glassc953aaf2018-12-10 10:37:34 -0700222 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600223 reg = <0 0>;
224 compatible = "google,cros-ec-sandbox";
225
226 /*
227 * This describes the flash memory within the EC. Note
228 * that the STM32L flash erases to 0, not 0xff.
229 */
230 flash {
231 image-pos = <0x08000000>;
232 size = <0x20000>;
233 erase-value = <0>;
234
235 /* Information for sandbox */
236 ro {
237 image-pos = <0>;
238 size = <0xf000>;
239 };
240 wp-ro {
241 image-pos = <0xf000>;
242 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700243 used = <0x884>;
244 compress = "lz4";
245 uncomp-size = <0xcf8>;
246 hash {
247 algo = "sha256";
248 value = [00 01 02 03 04 05 06 07
249 08 09 0a 0b 0c 0d 0e 0f
250 10 11 12 13 14 15 16 17
251 18 19 1a 1b 1c 1d 1e 1f];
252 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600253 };
254 rw {
255 image-pos = <0x10000>;
256 size = <0x10000>;
257 };
258 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300259
260 cros_ec_pwm: cros-ec-pwm {
261 compatible = "google,cros-ec-pwm";
262 #pwm-cells = <1>;
263 };
264
Simon Glass699c9ca2018-10-01 12:22:08 -0600265 };
266
Yannick Fertré9712c822019-10-07 15:29:05 +0200267 dsi_host: dsi_host {
268 compatible = "sandbox,dsi-host";
269 };
270
Simon Glassb2c1cac2014-02-26 15:59:21 -0700271 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600272 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700273 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600274 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700275 ping-add = <0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700276 bootph-all;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100277 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
278 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700279 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100280 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
281 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
282 <&gpio_b 7 GPIO_IN 3 2 1>,
283 <&gpio_b 8 GPIO_OUT 3 2 1>,
284 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100285 test3-gpios =
286 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
287 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
288 <&gpio_c 2 GPIO_OUT>,
289 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
290 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200291 <&gpio_c 5 GPIO_IN>,
292 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
293 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530294 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
295 test5-gpios = <&gpio_a 19>;
296
Simon Glass73025392021-10-23 17:26:04 -0600297 bool-value;
Stefan Herbrechtsmeier1b090e62022-06-14 15:21:30 +0200298 int8-value = /bits/ 8 <0x12>;
299 int16-value = /bits/ 16 <0x1234>;
Simon Glass6df01f92018-12-10 10:37:37 -0700300 int-value = <1234>;
301 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200302 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200303 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600304 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700305 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600306 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200307 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530308
309 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
310 <&muxcontroller0 2>, <&muxcontroller0 3>,
311 <&muxcontroller1>;
312 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
313 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100314 display-timings {
315 timing0: 240x320 {
316 clock-frequency = <6500000>;
317 hactive = <240>;
318 vactive = <320>;
319 hfront-porch = <6>;
320 hback-porch = <7>;
321 hsync-len = <1>;
322 vback-porch = <5>;
323 vfront-porch = <8>;
324 vsync-len = <2>;
325 hsync-active = <1>;
326 vsync-active = <0>;
327 de-active = <1>;
328 pixelclk-active = <1>;
329 interlaced;
330 doublescan;
331 doubleclk;
332 };
333 timing1: 480x800 {
334 clock-frequency = <9000000>;
335 hactive = <480>;
336 vactive = <800>;
337 hfront-porch = <10>;
338 hback-porch = <59>;
339 hsync-len = <12>;
340 vback-porch = <15>;
341 vfront-porch = <17>;
342 vsync-len = <16>;
343 hsync-active = <0>;
344 vsync-active = <1>;
345 de-active = <0>;
346 pixelclk-active = <0>;
347 };
348 timing2: 800x480 {
349 clock-frequency = <33500000>;
350 hactive = <800>;
351 vactive = <480>;
352 hback-porch = <89>;
353 hfront-porch = <164>;
354 vback-porch = <23>;
355 vfront-porch = <10>;
356 hsync-len = <11>;
357 vsync-len = <13>;
358 };
359 };
Raphael Gallais-Poua853b922023-05-11 16:36:52 +0200360 panel-timing {
Nikhil M Jainbb9d1312023-01-31 15:35:15 +0530361 clock-frequency = <6500000>;
362 hactive = <240>;
363 vactive = <320>;
364 hfront-porch = <6>;
365 hback-porch = <7>;
366 hsync-len = <1>;
367 vback-porch = <5>;
368 vfront-porch = <8>;
369 vsync-len = <2>;
370 hsync-active = <1>;
371 vsync-active = <0>;
372 de-active = <1>;
373 pixelclk-active = <1>;
374 interlaced;
375 doublescan;
376 doubleclk;
377 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700378 };
379
380 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600381 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700382 compatible = "not,compatible";
383 };
384
385 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600386 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700387 };
388
Simon Glass5620cf82018-10-01 12:22:40 -0600389 backlight: backlight {
390 compatible = "pwm-backlight";
391 enable-gpios = <&gpio_a 1>;
392 power-supply = <&ldo_1>;
393 pwms = <&pwm 0 1000>;
394 default-brightness-level = <5>;
395 brightness-levels = <0 16 32 64 128 170 202 234 255>;
396 };
397
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200398 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200399 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200400 bind-test-child1 {
401 compatible = "sandbox,phy";
402 #phy-cells = <1>;
403 };
404
405 bind-test-child2 {
406 compatible = "simple-bus";
407 };
408 };
409
Simon Glassb2c1cac2014-02-26 15:59:21 -0700410 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600411 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700412 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600413 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700414 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530415
416 mux-controls = <&muxcontroller0 0>;
417 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700418 };
419
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200420 phy_provider0: gen_phy@0 {
421 compatible = "sandbox,phy";
422 #phy-cells = <1>;
423 };
424
425 phy_provider1: gen_phy@1 {
426 compatible = "sandbox,phy";
427 #phy-cells = <0>;
428 broken;
429 };
430
developer71092972020-05-02 11:35:12 +0200431 phy_provider2: gen_phy@2 {
432 compatible = "sandbox,phy";
433 #phy-cells = <0>;
434 };
435
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200436 gen_phy_user: gen_phy_user {
437 compatible = "simple-bus";
438 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
439 phy-names = "phy1", "phy2", "phy3";
440 };
441
developer71092972020-05-02 11:35:12 +0200442 gen_phy_user1: gen_phy_user1 {
443 compatible = "simple-bus";
444 phys = <&phy_provider0 0>, <&phy_provider2>;
445 phy-names = "phy1", "phy2";
446 };
447
Simon Glassb2c1cac2014-02-26 15:59:21 -0700448 some-bus {
449 #address-cells = <1>;
450 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600451 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600452 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600453 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700454 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600455 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700456 compatible = "denx,u-boot-fdt-test";
457 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600458 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700459 ping-add = <5>;
460 };
Simon Glass40717422014-07-23 06:55:18 -0600461 c-test@0 {
462 compatible = "denx,u-boot-fdt-test";
463 reg = <0>;
464 ping-expect = <6>;
465 ping-add = <6>;
466 };
467 c-test@1 {
468 compatible = "denx,u-boot-fdt-test";
469 reg = <1>;
470 ping-expect = <7>;
471 ping-add = <7>;
472 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700473 };
474
475 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600476 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600477 ping-expect = <6>;
478 ping-add = <6>;
479 compatible = "google,another-fdt-test";
480 };
481
482 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600483 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600484 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700485 ping-add = <6>;
486 compatible = "google,another-fdt-test";
487 };
488
Simon Glass0ccb0972015-01-25 08:27:05 -0700489 f-test {
490 compatible = "denx,u-boot-fdt-test";
491 };
492
493 g-test {
494 compatible = "denx,u-boot-fdt-test";
495 };
496
Bin Mengd9d24782018-10-10 22:07:01 -0700497 h-test {
498 compatible = "denx,u-boot-fdt-test1";
499 };
500
developercf8bc132020-05-02 11:35:10 +0200501 i-test {
502 compatible = "mediatek,u-boot-fdt-test";
503 #address-cells = <1>;
504 #size-cells = <0>;
505
506 subnode@0 {
507 reg = <0>;
508 };
509
510 subnode@1 {
511 reg = <1>;
512 };
513
514 subnode@2 {
515 reg = <2>;
516 };
517 };
518
Simon Glass204675c2019-12-29 21:19:25 -0700519 devres-test {
520 compatible = "denx,u-boot-devres-test";
521 };
522
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530523 another-test {
524 reg = <0 2>;
525 compatible = "denx,u-boot-fdt-test";
526 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
527 test5-gpios = <&gpio_a 19>;
528 };
529
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100530 mmio-bus@0 {
531 #address-cells = <1>;
532 #size-cells = <1>;
533 compatible = "denx,u-boot-test-bus";
534 dma-ranges = <0x10000000 0x00000000 0x00040000>;
535
536 subnode@0 {
537 compatible = "denx,u-boot-fdt-test";
538 };
539 };
540
541 mmio-bus@1 {
542 #address-cells = <1>;
543 #size-cells = <1>;
544 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100545
546 subnode@0 {
547 compatible = "denx,u-boot-fdt-test";
548 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100549 };
550
Simon Glass3c601b12020-07-07 13:12:06 -0600551 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600552 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600553 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600554 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600555 child {
556 compatible = "denx,u-boot-acpi-test";
557 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600558 };
559
Simon Glass3c601b12020-07-07 13:12:06 -0600560 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600561 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600562 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600563 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600564 };
565
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200566 clocks {
567 clk_fixed: clk-fixed {
568 compatible = "fixed-clock";
569 #clock-cells = <0>;
570 clock-frequency = <1234>;
571 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000572
573 clk_fixed_factor: clk-fixed-factor {
574 compatible = "fixed-factor-clock";
575 #clock-cells = <0>;
576 clock-div = <3>;
577 clock-mult = <2>;
578 clocks = <&clk_fixed>;
579 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200580
581 osc {
582 compatible = "fixed-clock";
583 #clock-cells = <0>;
584 clock-frequency = <20000000>;
585 };
Stephen Warrena9622432016-06-17 09:44:00 -0600586 };
587
588 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600589 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600590 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200591 assigned-clocks = <&clk_sandbox 3>;
592 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600593 };
594
595 clk-test {
596 compatible = "sandbox,clk-test";
597 clocks = <&clk_fixed>,
598 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200599 <&clk_sandbox 0>,
600 <&clk_sandbox 3>,
601 <&clk_sandbox 2>;
602 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600603 };
604
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200605 ccf: clk-ccf {
606 compatible = "sandbox,clk-ccf";
607 };
608
Simon Glass507ab962021-12-04 08:56:31 -0700609 efi-media {
610 compatible = "sandbox,efi-media";
611 };
612
Simon Glass5b968632015-05-22 15:42:15 -0600613 eth@10002000 {
614 compatible = "sandbox,eth";
615 reg = <0x10002000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600616 };
617
618 eth_5: eth@10003000 {
619 compatible = "sandbox,eth";
620 reg = <0x10003000 0x1000>;
Sean Anderson13652b82022-05-05 13:11:44 -0400621 nvmem-cells = <&eth5_addr>;
622 nvmem-cell-names = "mac-address";
Simon Glass5b968632015-05-22 15:42:15 -0600623 };
624
Bin Meng04a11cb2015-08-27 22:25:53 -0700625 eth_3: sbe5 {
626 compatible = "sandbox,eth";
627 reg = <0x10005000 0x1000>;
Sean Andersone2dc0e62022-05-05 13:11:42 -0400628 nvmem-cells = <&eth3_addr>;
629 nvmem-cell-names = "mac-address";
Bin Meng04a11cb2015-08-27 22:25:53 -0700630 };
631
Simon Glass5b968632015-05-22 15:42:15 -0600632 eth@10004000 {
633 compatible = "sandbox,eth";
634 reg = <0x10004000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600635 };
636
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200637 phy_eth0: phy-test-eth {
638 compatible = "sandbox,eth";
639 reg = <0x10007000 0x1000>;
Sean Anderson24b1b8d2022-05-05 13:11:35 -0400640 mac-address = [ 02 00 11 22 33 49 ];
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200641 phy-handle = <&ethphy1>;
Marek BehĂșnbc194772022-04-07 00:33:01 +0200642 phy-mode = "2500base-x";
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200643 };
644
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800645 dsa_eth0: dsa-test-eth {
646 compatible = "sandbox,eth";
647 reg = <0x10006000 0x1000>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400648 nvmem-cells = <&eth4_addr>;
649 nvmem-cell-names = "mac-address";
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800650 };
651
652 dsa-test {
653 compatible = "sandbox,dsa";
654
655 ports {
656 #address-cells = <1>;
657 #size-cells = <0>;
658 swp_0: port@0 {
659 reg = <0>;
660 label = "lan0";
661 phy-mode = "rgmii-rxid";
662
663 fixed-link {
664 speed = <100>;
665 full-duplex;
666 };
667 };
668
669 swp_1: port@1 {
670 reg = <1>;
671 label = "lan1";
672 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800673 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800674 };
675
676 port@2 {
677 reg = <2>;
678 ethernet = <&dsa_eth0>;
679
680 fixed-link {
681 speed = <1000>;
682 full-duplex;
683 };
684 };
685 };
686 };
687
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700688 firmware {
689 sandbox_firmware: sandbox-firmware {
690 compatible = "sandbox,firmware";
691 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200692
Etienne Carriere09665cb2022-02-21 09:22:39 +0100693 scmi {
Etienne Carriere02fd1262020-09-09 18:44:00 +0200694 compatible = "sandbox,scmi-agent";
695 #address-cells = <1>;
696 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200697
Etienne Carriere09665cb2022-02-21 09:22:39 +0100698 protocol@10 {
699 reg = <0x10>;
700 };
701
702 clk_scmi: protocol@14 {
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200703 reg = <0x14>;
704 #clock-cells = <1>;
705 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200706
Etienne Carriere09665cb2022-02-21 09:22:39 +0100707 reset_scmi: protocol@16 {
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200708 reg = <0x16>;
709 #reset-cells = <1>;
710 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100711
712 protocol@17 {
713 reg = <0x17>;
714
715 regulators {
716 #address-cells = <1>;
717 #size-cells = <0>;
718
Etienne Carriere09665cb2022-02-21 09:22:39 +0100719 regul0_scmi: reg@0 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100720 reg = <0>;
721 regulator-name = "sandbox-voltd0";
722 regulator-min-microvolt = <1100000>;
723 regulator-max-microvolt = <3300000>;
724 };
Etienne Carriere09665cb2022-02-21 09:22:39 +0100725 regul1_scmi: reg@1 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100726 reg = <0x1>;
727 regulator-name = "sandbox-voltd1";
728 regulator-min-microvolt = <1800000>;
729 };
730 };
731 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200732 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700733 };
734
Alexander Dahl6ac319d2022-09-30 14:04:30 +0200735 fpga {
736 compatible = "sandbox,fpga";
737 };
738
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100739 pinctrl-gpio {
740 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700741
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100742 gpio_a: base-gpios {
743 compatible = "sandbox,gpio";
744 gpio-controller;
745 #gpio-cells = <1>;
746 gpio-bank-name = "a";
747 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200748 hog_input_active_low {
749 gpio-hog;
750 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200751 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200752 };
753 hog_input_active_high {
754 gpio-hog;
755 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200756 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200757 };
758 hog_output_low {
759 gpio-hog;
760 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200761 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200762 };
763 hog_output_high {
764 gpio-hog;
765 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200766 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200767 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100768 };
769
770 gpio_b: extra-gpios {
771 compatible = "sandbox,gpio";
772 gpio-controller;
773 #gpio-cells = <5>;
774 gpio-bank-name = "b";
775 sandbox,gpio-count = <10>;
776 };
Simon Glass25348a42014-10-13 23:42:11 -0600777
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100778 gpio_c: pinmux-gpios {
779 compatible = "sandbox,gpio";
780 gpio-controller;
781 #gpio-cells = <2>;
782 gpio-bank-name = "c";
783 sandbox,gpio-count = <10>;
784 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100785 };
786
Simon Glass7df766e2014-12-10 08:55:55 -0700787 i2c@0 {
788 #address-cells = <1>;
789 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600790 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700791 compatible = "sandbox,i2c";
792 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200793 pinctrl-names = "default";
794 pinctrl-0 = <&pinmux_i2c0_pins>;
795
Simon Glass7df766e2014-12-10 08:55:55 -0700796 eeprom@2c {
Sean Andersone2dc0e62022-05-05 13:11:42 -0400797 #address-cells = <1>;
798 #size-cells = <1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700799 reg = <0x2c>;
800 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700801 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200802 partitions {
803 compatible = "fixed-partitions";
804 #address-cells = <1>;
805 #size-cells = <1>;
806 bootcount_i2c: bootcount@10 {
807 reg = <10 2>;
808 };
809 };
Sean Andersone2dc0e62022-05-05 13:11:42 -0400810
811 eth3_addr: mac-address@24 {
812 reg = <24 6>;
813 };
Simon Glass7df766e2014-12-10 08:55:55 -0700814 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200815
Simon Glass336b2952015-05-22 15:42:17 -0600816 rtc_0: rtc@43 {
Sean Anderson5768e8b2022-05-05 13:11:43 -0400817 #address-cells = <1>;
818 #size-cells = <1>;
Simon Glass336b2952015-05-22 15:42:17 -0600819 reg = <0x43>;
820 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700821 sandbox,emul = <&emul0>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400822
823 eth4_addr: mac-address@40 {
824 reg = <0x40 6>;
825 };
Simon Glass336b2952015-05-22 15:42:17 -0600826 };
827
828 rtc_1: rtc@61 {
829 reg = <0x61>;
830 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700831 sandbox,emul = <&emul1>;
832 };
833
834 i2c_emul: emul {
835 reg = <0xff>;
836 compatible = "sandbox,i2c-emul-parent";
837 emul_eeprom: emul-eeprom {
838 compatible = "sandbox,i2c-eeprom";
839 sandbox,filename = "i2c.bin";
840 sandbox,size = <256>;
841 };
842 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700843 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700844 };
845 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700846 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600847 };
848 };
849
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200850 sandbox_pmic: sandbox_pmic {
851 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700852 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200853 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200854
855 mc34708: pmic@41 {
856 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700857 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200858 };
Simon Glass7df766e2014-12-10 08:55:55 -0700859 };
860
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100861 bootcount@0 {
862 compatible = "u-boot,bootcount-rtc";
863 rtc = <&rtc_1>;
864 offset = <0x13>;
865 };
866
Michal Simek4f18f922020-05-28 11:48:55 +0200867 bootcount {
868 compatible = "u-boot,bootcount-i2c-eeprom";
869 i2c-eeprom = <&bootcount_i2c>;
870 };
871
Nandor Han88895812021-06-10 15:40:38 +0300872 bootcount_4@0 {
873 compatible = "u-boot,bootcount-syscon";
874 syscon = <&syscon0>;
875 reg = <0x0 0x04>, <0x0 0x04>;
876 reg-names = "syscon_reg", "offset";
877 };
878
879 bootcount_2@0 {
880 compatible = "u-boot,bootcount-syscon";
881 syscon = <&syscon0>;
882 reg = <0x0 0x04>, <0x0 0x02> ;
883 reg-names = "syscon_reg", "offset";
884 };
885
Marek Szyprowskiad398592021-02-18 11:33:18 +0100886 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100887 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100888 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100889 vdd-supply = <&buck2>;
890 vss-microvolts = <0>;
891 };
892
Mark Kettenis67748ee2021-10-23 16:58:02 +0200893 iommu: iommu@0 {
894 compatible = "sandbox,iommu";
895 #iommu-cells = <0>;
896 };
897
Simon Glass515dcff2020-02-06 09:55:00 -0700898 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700899 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700900 interrupt-controller;
901 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700902 };
903
Simon Glass90b6fef2016-01-18 19:52:26 -0700904 lcd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700905 bootph-all;
Simon Glass90b6fef2016-01-18 19:52:26 -0700906 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200907 pinctrl-names = "default";
908 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700909 xres = <1366>;
910 yres = <768>;
911 };
912
Simon Glassd783eb32015-07-06 12:54:34 -0600913 leds {
914 compatible = "gpio-leds";
915
916 iracibble {
917 gpios = <&gpio_a 1 0>;
918 label = "sandbox:red";
919 };
920
921 martinet {
922 gpios = <&gpio_a 2 0>;
923 label = "sandbox:green";
924 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200925
926 default_on {
927 gpios = <&gpio_a 5 0>;
928 label = "sandbox:default_on";
929 default-state = "on";
930 };
931
932 default_off {
933 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400934 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200935 default-state = "off";
936 };
Simon Glassd783eb32015-07-06 12:54:34 -0600937 };
938
Paul Doelle709f0372022-07-04 09:00:25 +0000939 wdt-gpio-toggle {
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200940 gpios = <&gpio_a 7 0>;
941 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +0200942 hw_margin_ms = <100>;
Paul Doelle709f0372022-07-04 09:00:25 +0000943 hw_algo = "toggle";
944 always-running;
945 };
946
947 wdt-gpio-level {
948 gpios = <&gpio_a 7 0>;
949 compatible = "linux,wdt-gpio";
950 hw_margin_ms = <100>;
951 hw_algo = "level";
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200952 always-running;
953 };
954
Stephen Warren62f2c902016-05-16 17:41:37 -0600955 mbox: mbox {
956 compatible = "sandbox,mbox";
957 #mbox-cells = <1>;
958 };
959
960 mbox-test {
961 compatible = "sandbox,mbox-test";
962 mboxes = <&mbox 100>, <&mbox 1>;
963 mbox-names = "other", "test";
964 };
965
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900966 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200967 #address-cells = <1>;
968 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400969 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200970 cpu1: cpu@1 {
971 device_type = "cpu";
972 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400973 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900974 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700975 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900976 };
Mario Sixdea5df72018-08-06 10:23:44 +0200977
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200978 cpu2: cpu@2 {
979 device_type = "cpu";
980 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900981 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700982 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900983 };
Mario Sixdea5df72018-08-06 10:23:44 +0200984
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200985 cpu3: cpu@3 {
986 device_type = "cpu";
987 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900988 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700989 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900990 };
Mario Sixdea5df72018-08-06 10:23:44 +0200991 };
992
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500993 chipid: chipid {
994 compatible = "sandbox,soc";
995 };
996
Simon Glassc953aaf2018-12-10 10:37:34 -0700997 i2s: i2s {
998 compatible = "sandbox,i2s";
999 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -07001000 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -07001001 };
1002
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +02001003 nop-test_0 {
1004 compatible = "sandbox,nop_sandbox1";
1005 nop-test_1 {
1006 compatible = "sandbox,nop_sandbox2";
1007 bind = "True";
1008 };
1009 nop-test_2 {
1010 compatible = "sandbox,nop_sandbox2";
1011 bind = "False";
1012 };
1013 };
1014
Roger Quadrosb0679a72022-10-20 16:30:46 +03001015 memory-controller {
1016 compatible = "sandbox,memory";
1017 };
1018
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001019 misc-test {
Sean Anderson13652b82022-05-05 13:11:44 -04001020 #address-cells = <1>;
1021 #size-cells = <1>;
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001022 compatible = "sandbox,misc_sandbox";
Sean Anderson13652b82022-05-05 13:11:44 -04001023
1024 eth5_addr: mac-address@10 {
1025 reg = <0x10 6>;
1026 };
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001027 };
1028
Simon Glasse4fef742017-04-23 20:02:07 -06001029 mmc2 {
1030 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -06001031 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -06001032 };
1033
Simon Glassb255efc2022-04-24 23:31:24 -06001034 /* This is used for the bootdev tests */
Simon Glasse4fef742017-04-23 20:02:07 -06001035 mmc1 {
1036 compatible = "sandbox,mmc";
Simon Glassb255efc2022-04-24 23:31:24 -06001037 filename = "mmc1.img";
Simon Glasse4fef742017-04-23 20:02:07 -06001038 };
1039
Simon Glassb255efc2022-04-24 23:31:24 -06001040 /* This is used for the fastboot tests */
Sughosh Ganu77079e72022-10-21 18:16:05 +05301041 mmc0: mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -06001042 compatible = "sandbox,mmc";
1043 };
1044
Simon Glassf1eba352022-10-20 18:23:20 -06001045 /* This is used for VBE VPL tests */
1046 mmc3 {
1047 status = "disabled";
1048 compatible = "sandbox,mmc";
1049 filename = "image.bin";
1050 non-removable;
1051 };
1052
Simon Glassd2bc33ed2023-01-06 08:52:41 -06001053 /* This is used for bootstd bootmenu tests */
1054 mmc4 {
1055 status = "disabled";
1056 compatible = "sandbox,mmc";
1057 filename = "mmc4.img";
1058 };
1059
Simon Glassfff928c2023-08-24 13:55:41 -06001060 /* This is used for ChromiumOS tests */
1061 mmc5 {
1062 status = "disabled";
1063 compatible = "sandbox,mmc";
1064 filename = "mmc5.img";
1065 };
1066
Simon Glass53a68b32019-02-16 20:24:50 -07001067 pch {
1068 compatible = "sandbox,pch";
1069 };
1070
Tom Rini4a3ca482020-02-11 12:41:23 -05001071 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -07001072 compatible = "sandbox,pci";
1073 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001074 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001075 #address-cells = <3>;
1076 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -06001077 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -07001078 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Mark Kettenis5dfd4ec2023-01-21 20:27:57 +01001079 iommu-map = <0x0010 &iommu 0 1>;
1080 iommu-map-mask = <0xfffffff8>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001081 pci@0,0 {
1082 compatible = "pci-generic";
1083 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001084 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001085 };
Alex Margineanf1274432019-06-07 11:24:24 +03001086 pci@1,0 {
1087 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001088 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
1089 reg = <0x02000814 0 0 0 0
1090 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001091 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +03001092 };
Simon Glass937bb472019-12-06 21:41:57 -07001093 p2sb-pci@2,0 {
1094 compatible = "sandbox,p2sb";
1095 reg = <0x02001010 0 0 0 0>;
1096 sandbox,emul = <&p2sb_emul>;
1097
1098 adder {
1099 intel,p2sb-port-id = <3>;
1100 compatible = "sandbox,adder";
1101 };
1102 };
Simon Glass8c501022019-12-06 21:41:54 -07001103 pci@1e,0 {
1104 compatible = "sandbox,pmc";
1105 reg = <0xf000 0 0 0 0>;
1106 sandbox,emul = <&pmc_emul1e>;
1107 acpi-base = <0x400>;
1108 gpe0-dwx-mask = <0xf>;
1109 gpe0-dwx-shift-base = <4>;
1110 gpe0-dw = <6 7 9>;
1111 gpe0-sts = <0x20>;
1112 gpe0-en = <0x30>;
1113 };
Simon Glass3a6eae62015-03-05 12:25:34 -07001114 pci@1f,0 {
1115 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001116 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
1117 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001118 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001119 };
1120 };
1121
Simon Glassb98ba4c2019-09-25 08:56:10 -06001122 pci-emul0 {
1123 compatible = "sandbox,pci-emul-parent";
1124 swap_case_emul0_0: emul0@0,0 {
1125 compatible = "sandbox,swap-case";
1126 };
1127 swap_case_emul0_1: emul0@1,0 {
1128 compatible = "sandbox,swap-case";
1129 use-ea;
1130 };
1131 swap_case_emul0_1f: emul0@1f,0 {
1132 compatible = "sandbox,swap-case";
1133 };
Simon Glass937bb472019-12-06 21:41:57 -07001134 p2sb_emul: emul@2,0 {
1135 compatible = "sandbox,p2sb-emul";
1136 };
Simon Glass8c501022019-12-06 21:41:54 -07001137 pmc_emul1e: emul@1e,0 {
1138 compatible = "sandbox,pmc-emul";
1139 };
Simon Glassb98ba4c2019-09-25 08:56:10 -06001140 };
1141
Tom Rini4a3ca482020-02-11 12:41:23 -05001142 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -07001143 compatible = "sandbox,pci";
1144 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001145 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -07001146 #address-cells = <3>;
1147 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001148 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scullc7456a42022-04-21 16:11:09 +00001149 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001150 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -07001151 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +02001152 0x0c 0x00 0x1234 0x5678
1153 0x10 0x00 0x1234 0x5678>;
1154 pci@10,0 {
1155 reg = <0x8000 0 0 0 0>;
1156 };
Bin Meng408e5902018-08-03 01:14:41 -07001157 };
1158
Tom Rini4a3ca482020-02-11 12:41:23 -05001159 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -07001160 compatible = "sandbox,pci";
1161 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001162 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -07001163 #address-cells = <3>;
1164 #size-cells = <2>;
1165 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1166 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1167 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1168 pci@1f,0 {
1169 compatible = "pci-generic";
1170 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001171 sandbox,emul = <&swap_case_emul2_1f>;
1172 };
1173 };
1174
1175 pci-emul2 {
1176 compatible = "sandbox,pci-emul-parent";
1177 swap_case_emul2_1f: emul2@1f,0 {
1178 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001179 };
1180 };
1181
Ramon Friedc64f19b2019-04-27 11:15:23 +03001182 pci_ep: pci_ep {
1183 compatible = "sandbox,pci_ep";
1184 };
1185
Simon Glass9c433fe2017-04-23 20:10:44 -06001186 probing {
1187 compatible = "simple-bus";
1188 test1 {
1189 compatible = "denx,u-boot-probe-test";
1190 };
1191
1192 test2 {
1193 compatible = "denx,u-boot-probe-test";
1194 };
1195
1196 test3 {
1197 compatible = "denx,u-boot-probe-test";
1198 };
1199
1200 test4 {
1201 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001202 first-syscon = <&syscon0>;
1203 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001204 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001205 };
1206 };
1207
Stephen Warren92c67fa2016-07-13 13:45:31 -06001208 pwrdom: power-domain {
1209 compatible = "sandbox,power-domain";
1210 #power-domain-cells = <1>;
1211 };
1212
1213 power-domain-test {
1214 compatible = "sandbox,power-domain-test";
1215 power-domains = <&pwrdom 2>;
1216 };
1217
Simon Glass5620cf82018-10-01 12:22:40 -06001218 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001219 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001220 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001221 pinctrl-names = "default";
1222 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001223 };
1224
1225 pwm2 {
1226 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001227 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001228 };
1229
Simon Glass3d355e62015-07-06 12:54:31 -06001230 ram {
1231 compatible = "sandbox,ram";
1232 };
1233
Simon Glassd860f222015-07-06 12:54:29 -06001234 reset@0 {
1235 compatible = "sandbox,warm-reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001236 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001237 };
1238
1239 reset@1 {
1240 compatible = "sandbox,reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001241 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001242 };
1243
Stephen Warren6488e642016-06-17 09:43:59 -06001244 resetc: reset-ctl {
1245 compatible = "sandbox,reset-ctl";
1246 #reset-cells = <1>;
1247 };
1248
1249 reset-ctl-test {
1250 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001251 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1252 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001253 };
1254
Sughosh Ganu23e37512019-12-28 23:58:31 +05301255 rng {
1256 compatible = "sandbox,sandbox-rng";
1257 };
1258
Nishanth Menonedf85812015-09-17 15:42:41 -05001259 rproc_1: rproc@1 {
1260 compatible = "sandbox,test-processor";
1261 remoteproc-name = "remoteproc-test-dev1";
1262 };
1263
1264 rproc_2: rproc@2 {
1265 compatible = "sandbox,test-processor";
1266 internal-memory-mapped;
1267 remoteproc-name = "remoteproc-test-dev2";
1268 };
1269
Simon Glass5620cf82018-10-01 12:22:40 -06001270 panel {
1271 compatible = "simple-panel";
1272 backlight = <&backlight 0 100>;
1273 };
1274
Simon Glass509f32e2022-09-21 16:21:47 +02001275 scsi {
1276 compatible = "sandbox,scsi";
1277 sandbox,filepath = "scsi.img";
1278 };
1279
Ramon Fried26ed32e2018-07-02 02:57:59 +03001280 smem@0 {
1281 compatible = "sandbox,smem";
1282 };
1283
Simon Glass76072ac2018-12-10 10:37:36 -07001284 sound {
1285 compatible = "sandbox,sound";
1286 cpu {
1287 sound-dai = <&i2s 0>;
1288 };
1289
1290 codec {
1291 sound-dai = <&audio 0>;
1292 };
1293 };
1294
Simon Glass25348a42014-10-13 23:42:11 -06001295 spi@0 {
1296 #address-cells = <1>;
1297 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001298 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001299 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001300 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001301 pinctrl-names = "default";
1302 pinctrl-0 = <&pinmux_spi0_pins>;
1303
Simon Glass25348a42014-10-13 23:42:11 -06001304 spi.bin@0 {
1305 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001306 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001307 spi-max-frequency = <40000000>;
1308 sandbox,filename = "spi.bin";
1309 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001310 spi.bin@1 {
1311 reg = <1>;
1312 compatible = "spansion,m25p16", "jedec,spi-nor";
1313 spi-max-frequency = <50000000>;
1314 sandbox,filename = "spi.bin";
1315 spi-cpol;
1316 spi-cpha;
1317 };
Simon Glass25348a42014-10-13 23:42:11 -06001318 };
1319
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001320 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001321 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001322 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001323 };
1324
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001325 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001326 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001327 reg = <0x20 5
1328 0x28 6
1329 0x30 7
1330 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001331 };
1332
Patrick Delaunayee010432019-03-07 09:57:13 +01001333 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001334 compatible = "simple-mfd", "syscon";
1335 reg = <0x40 5
1336 0x48 6
1337 0x50 7
1338 0x58 8>;
1339 };
1340
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301341 syscon3: syscon@3 {
1342 compatible = "simple-mfd", "syscon";
1343 reg = <0x000100 0x10>;
1344
1345 muxcontroller0: a-mux-controller {
1346 compatible = "mmio-mux";
1347 #mux-control-cells = <1>;
1348
1349 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1350 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1351 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1352 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1353 u-boot,mux-autoprobe;
1354 };
1355 };
1356
1357 muxcontroller1: emul-mux-controller {
1358 compatible = "mux-emul";
1359 #mux-control-cells = <0>;
1360 u-boot,mux-autoprobe;
1361 idle-state = <0xabcd>;
1362 };
1363
Simon Glass791a17f2020-12-16 21:20:27 -07001364 testfdtm0 {
1365 compatible = "denx,u-boot-fdtm-test";
1366 };
1367
1368 testfdtm1: testfdtm1 {
1369 compatible = "denx,u-boot-fdtm-test";
1370 };
1371
1372 testfdtm2 {
1373 compatible = "denx,u-boot-fdtm-test";
1374 };
1375
Sean Anderson79d3bba2020-09-28 10:52:23 -04001376 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001377 compatible = "sandbox,timer";
1378 clock-frequency = <1000000>;
1379 };
1380
Sean Anderson79d3bba2020-09-28 10:52:23 -04001381 timer@1 {
1382 compatible = "sandbox,timer";
1383 sandbox,timebase-frequency-fallback;
1384 };
1385
Miquel Raynal80938c12018-05-15 11:57:27 +02001386 tpm2 {
1387 compatible = "sandbox,tpm2";
1388 };
1389
Simon Glasseef107e2023-02-21 06:24:51 -07001390 tpm {
1391 compatible = "google,sandbox-tpm";
1392 };
1393
Simon Glass5b968632015-05-22 15:42:15 -06001394 uart0: serial {
1395 compatible = "sandbox,serial";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001396 bootph-all;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001397 pinctrl-names = "default";
1398 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001399 };
1400
Simon Glass31680482015-03-25 12:23:05 -06001401 usb_0: usb@0 {
1402 compatible = "sandbox,usb";
1403 status = "disabled";
1404 hub {
1405 compatible = "sandbox,usb-hub";
1406 #address-cells = <1>;
1407 #size-cells = <0>;
1408 flash-stick {
1409 reg = <0>;
1410 compatible = "sandbox,usb-flash";
1411 };
1412 };
1413 };
1414
1415 usb_1: usb@1 {
1416 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001417 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001418 hub {
1419 compatible = "usb-hub";
1420 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001421 #address-cells = <1>;
1422 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001423 hub-emul {
1424 compatible = "sandbox,usb-hub";
1425 #address-cells = <1>;
1426 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001427 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001428 reg = <0>;
1429 compatible = "sandbox,usb-flash";
1430 sandbox,filepath = "testflash.bin";
1431 };
1432
Simon Glass4700fe52015-11-08 23:48:01 -07001433 flash-stick@1 {
1434 reg = <1>;
1435 compatible = "sandbox,usb-flash";
1436 sandbox,filepath = "testflash1.bin";
1437 };
1438
1439 flash-stick@2 {
1440 reg = <2>;
1441 compatible = "sandbox,usb-flash";
1442 sandbox,filepath = "testflash2.bin";
1443 };
1444
Simon Glassc0ccc722015-11-08 23:48:08 -07001445 keyb@3 {
1446 reg = <3>;
1447 compatible = "sandbox,usb-keyb";
1448 };
1449
Simon Glass31680482015-03-25 12:23:05 -06001450 };
Michael Walle7c961322020-06-02 01:47:07 +02001451
1452 usbstor@1 {
1453 reg = <1>;
1454 };
1455 usbstor@3 {
1456 reg = <3>;
1457 };
Simon Glass31680482015-03-25 12:23:05 -06001458 };
1459 };
1460
1461 usb_2: usb@2 {
1462 compatible = "sandbox,usb";
1463 status = "disabled";
1464 };
1465
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001466 spmi: spmi@0 {
1467 compatible = "sandbox,spmi";
1468 #address-cells = <0x1>;
1469 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001470 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001471 pm8916@0 {
1472 compatible = "qcom,spmi-pmic";
1473 reg = <0x0 0x1>;
1474 #address-cells = <0x1>;
1475 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001476 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001477
1478 spmi_gpios: gpios@c000 {
1479 compatible = "qcom,pm8916-gpio";
1480 reg = <0xc000 0x400>;
1481 gpio-controller;
1482 gpio-count = <4>;
1483 #gpio-cells = <2>;
1484 gpio-bank-name="spmi";
1485 };
1486 };
1487 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001488
1489 wdt0: wdt@0 {
1490 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001491 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001492 };
Rob Clarka471b672018-01-10 11:33:30 +01001493
Mario Six95922152018-08-09 14:51:19 +02001494 axi: axi@0 {
1495 compatible = "sandbox,axi";
1496 #address-cells = <0x1>;
1497 #size-cells = <0x1>;
1498 store@0 {
1499 compatible = "sandbox,sandbox_store";
1500 reg = <0x0 0x400>;
1501 };
1502 };
1503
Rob Clarka471b672018-01-10 11:33:30 +01001504 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001505 #address-cells = <1>;
1506 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001507 setting = "sunrise ohoka";
1508 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001509 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001510 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001511 chosen-test {
1512 compatible = "denx,u-boot-fdt-test";
1513 reg = <9 1>;
1514 };
1515 };
Mario Six35616ef2018-03-12 14:53:33 +01001516
1517 translation-test@8000 {
1518 compatible = "simple-bus";
1519 reg = <0x8000 0x4000>;
1520
1521 #address-cells = <0x2>;
1522 #size-cells = <0x1>;
1523
1524 ranges = <0 0x0 0x8000 0x1000
1525 1 0x100 0x9000 0x1000
1526 2 0x200 0xA000 0x1000
1527 3 0x300 0xB000 0x1000
1528 >;
1529
Fabien Dessenne22236e02019-05-31 15:11:30 +02001530 dma-ranges = <0 0x000 0x10000000 0x1000
1531 1 0x100 0x20000000 0x1000
1532 >;
1533
Mario Six35616ef2018-03-12 14:53:33 +01001534 dev@0,0 {
1535 compatible = "denx,u-boot-fdt-dummy";
1536 reg = <0 0x0 0x1000>;
Álvaro Fernåndez Rojasa3181152018-12-03 19:37:09 +01001537 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001538 };
1539
1540 dev@1,100 {
1541 compatible = "denx,u-boot-fdt-dummy";
1542 reg = <1 0x100 0x1000>;
1543
1544 };
1545
1546 dev@2,200 {
1547 compatible = "denx,u-boot-fdt-dummy";
1548 reg = <2 0x200 0x1000>;
1549 };
1550
1551
1552 noxlatebus@3,300 {
1553 compatible = "simple-bus";
1554 reg = <3 0x300 0x1000>;
1555
1556 #address-cells = <0x1>;
1557 #size-cells = <0x0>;
1558
1559 dev@42 {
1560 compatible = "denx,u-boot-fdt-dummy";
1561 reg = <0x42>;
1562 };
1563 };
1564 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001565
Dzmitry Sankouski54f4c832023-01-22 18:21:23 +03001566 ofnode-foreach {
1567 compatible = "foreach";
1568
1569 first {
1570 prop1 = <1>;
1571 prop2 = <2>;
1572 };
1573
1574 second {
1575 prop1 = <1>;
1576 prop2 = <2>;
1577 };
1578 };
1579
Mario Six02ad6fb2018-09-27 09:19:31 +02001580 osd {
1581 compatible = "sandbox,sandbox_osd";
1582 };
Tom Rinib93eea72018-09-30 18:16:51 -04001583
Jens Wiklander86afaa62018-09-25 16:40:16 +02001584 sandbox_tee {
1585 compatible = "sandbox,tee";
1586 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001587
1588 sandbox_virtio1 {
1589 compatible = "sandbox,virtio1";
Simon Glass8de5a542023-01-17 10:47:51 -07001590 virtio-type = <4>; /* rng */
Bin Meng1bb290d2018-10-15 02:21:26 -07001591 };
1592
1593 sandbox_virtio2 {
1594 compatible = "sandbox,virtio2";
1595 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001596
Simon Glass8de5a542023-01-17 10:47:51 -07001597 sandbox-virtio-blk {
1598 compatible = "sandbox,virtio1";
1599 virtio-type = <2>; /* block */
1600 };
1601
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001602 sandbox_scmi {
1603 compatible = "sandbox,scmi-devices";
Etienne Carrierebf1f1322022-02-21 09:22:41 +01001604 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere09665cb2022-02-21 09:22:39 +01001605 resets = <&reset_scmi 3>;
1606 regul0-supply = <&regul0_scmi>;
1607 regul1-supply = <&regul1_scmi>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001608 };
1609
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001610 pinctrl {
1611 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001612
Sean Anderson3438e3b2020-09-14 11:01:57 -04001613 pinctrl-names = "default", "alternate";
1614 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1615 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001616
Sean Anderson3438e3b2020-09-14 11:01:57 -04001617 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001618 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001619 pins = "P5";
1620 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001621 bias-pull-up;
1622 input-disable;
1623 };
1624 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001625 pins = "P6";
1626 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001627 output-high;
1628 drive-open-drain;
1629 };
1630 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001631 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001632 bias-pull-down;
1633 input-enable;
1634 };
1635 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001636 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001637 bias-disable;
1638 };
1639 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001640
1641 pinctrl_i2c: i2c {
1642 groups {
1643 groups = "I2C_UART";
1644 function = "I2C";
1645 };
1646
1647 pins {
1648 pins = "P0", "P1";
1649 drive-open-drain;
1650 };
1651 };
1652
1653 pinctrl_i2s: i2s {
1654 groups = "SPI_I2S";
1655 function = "I2S";
1656 };
1657
1658 pinctrl_spi: spi {
1659 groups = "SPI_I2S";
1660 function = "SPI";
1661
1662 cs {
1663 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1664 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1665 };
1666 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001667 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001668
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001669 pinctrl-single-no-width {
1670 compatible = "pinctrl-single";
1671 reg = <0x0000 0x238>;
1672 #pinctrl-cells = <1>;
1673 pinctrl-single,function-mask = <0x7f>;
1674 };
1675
1676 pinctrl-single-pins {
1677 compatible = "pinctrl-single";
1678 reg = <0x0000 0x238>;
1679 #pinctrl-cells = <1>;
1680 pinctrl-single,register-width = <32>;
1681 pinctrl-single,function-mask = <0x7f>;
1682
1683 pinmux_pwm_pins: pinmux_pwm_pins {
1684 pinctrl-single,pins = < 0x48 0x06 >;
1685 };
1686
1687 pinmux_spi0_pins: pinmux_spi0_pins {
1688 pinctrl-single,pins = <
1689 0x190 0x0c
1690 0x194 0x0c
1691 0x198 0x23
1692 0x19c 0x0c
1693 >;
1694 };
1695
1696 pinmux_uart0_pins: pinmux_uart0_pins {
1697 pinctrl-single,pins = <
1698 0x70 0x30
1699 0x74 0x00
1700 >;
1701 };
1702 };
1703
1704 pinctrl-single-bits {
1705 compatible = "pinctrl-single";
1706 reg = <0x0000 0x50>;
1707 #pinctrl-cells = <2>;
1708 pinctrl-single,bit-per-mux;
1709 pinctrl-single,register-width = <32>;
1710 pinctrl-single,function-mask = <0xf>;
1711
1712 pinmux_i2c0_pins: pinmux_i2c0_pins {
1713 pinctrl-single,bits = <
1714 0x10 0x00002200 0x0000ff00
1715 >;
1716 };
1717
1718 pinmux_lcd_pins: pinmux_lcd_pins {
1719 pinctrl-single,bits = <
1720 0x40 0x22222200 0xffffff00
1721 0x44 0x22222222 0xffffffff
1722 0x48 0x00000022 0x000000ff
1723 0x48 0x02000000 0x0f000000
1724 0x4c 0x02000022 0x0f0000ff
1725 >;
1726 };
1727 };
1728
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001729 hwspinlock@0 {
1730 compatible = "sandbox,hwspinlock";
1731 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001732
1733 dma: dma {
1734 compatible = "sandbox,dma";
1735 #dma-cells = <1>;
1736
1737 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1738 dma-names = "m2m", "tx0", "rx0";
1739 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001740
Alex Marginean0649be52019-07-12 10:13:53 +03001741 /*
1742 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1743 * end of the test. If parent mdio is removed first, clean-up of the
1744 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1745 * active at the end of the test. That it turn doesn't allow the mdio
1746 * class to be destroyed, triggering an error.
1747 */
1748 mdio-mux-test {
1749 compatible = "sandbox,mdio-mux";
1750 #address-cells = <1>;
1751 #size-cells = <0>;
1752 mdio-parent-bus = <&mdio>;
1753
1754 mdio-ch-test@0 {
1755 reg = <0>;
1756 };
1757 mdio-ch-test@1 {
1758 reg = <1>;
1759 };
1760 };
1761
1762 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001763 compatible = "sandbox,mdio";
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +02001764 #address-cells = <1>;
1765 #size-cells = <0>;
1766
1767 ethphy1: ethernet-phy@1 {
1768 reg = <1>;
1769 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001770 };
Sean Andersonb7860542020-06-24 06:41:12 -04001771
1772 pm-bus-test {
1773 compatible = "simple-pm-bus";
1774 clocks = <&clk_sandbox 4>;
1775 power-domains = <&pwrdom 1>;
1776 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001777
1778 resetc2: syscon-reset {
1779 compatible = "syscon-reset";
1780 #reset-cells = <1>;
1781 regmap = <&syscon0>;
1782 offset = <1>;
1783 mask = <0x27FFFFFF>;
1784 assert-high = <0>;
1785 };
1786
1787 syscon-reset-test {
1788 compatible = "sandbox,misc_sandbox";
1789 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1790 reset-names = "valid", "no_mask", "out_of_range";
1791 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301792
Simon Glass458b66a2020-11-05 06:32:05 -07001793 sysinfo {
1794 compatible = "sandbox,sysinfo-sandbox";
1795 };
1796
Sean Anderson1c830672021-04-20 10:50:58 -04001797 sysinfo-gpio {
1798 compatible = "gpio-sysinfo";
1799 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1800 revisions = <19>, <5>;
1801 names = "rev_a", "foo";
1802 };
1803
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301804 some_regmapped-bus {
1805 #address-cells = <0x1>;
1806 #size-cells = <0x1>;
1807
1808 ranges = <0x0 0x0 0x10>;
1809 compatible = "simple-bus";
1810
1811 regmap-test_0 {
1812 reg = <0 0x10>;
1813 compatible = "sandbox,regmap_test";
1814 };
1815 };
Robert Marko9cf87122022-09-06 13:30:35 +02001816
1817 thermal {
1818 compatible = "sandbox,thermal";
1819 };
Sughosh Ganu77079e72022-10-21 18:16:05 +05301820
1821 fwu-mdata {
1822 compatible = "u-boot,fwu-mdata-gpt";
1823 fwu-mdata-store = <&mmc0>;
1824 };
Abdellatif El Khlifi6b005872023-04-17 10:11:55 +01001825
1826 nvmxip-qspi1@08000000 {
1827 compatible = "nvmxip,qspi";
1828 reg = <0x08000000 0x00200000>;
1829 lba_shift = <9>;
1830 lba = <4096>;
1831 };
1832
1833 nvmxip-qspi2@08200000 {
1834 compatible = "nvmxip,qspi";
1835 reg = <0x08200000 0x00100000>;
1836 lba_shift = <9>;
1837 lba = <2048>;
1838 };
Svyatoslav Ryhel669f5c82023-04-25 10:57:21 +03001839
1840 extcon {
1841 compatible = "sandbox,extcon";
1842 };
Abdellatif El Khlifi4970d5b2023-08-04 14:33:41 +01001843
1844 arm-ffa-emul {
1845 compatible = "sandbox,arm-ffa-emul";
1846
1847 sandbox-arm-ffa {
1848 compatible = "sandbox,arm-ffa";
1849 };
1850 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001851};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001852
1853#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001854#include "cros-ec-keyboard.dtsi"
Simon Glass5e135d32022-10-20 18:23:15 -06001855
1856#ifdef CONFIG_SANDBOX_VPL
1857#include "sandbox_vpl.dtsi"
1858#endif
Simon Glass61300722023-06-01 10:23:01 -06001859
1860#include "cedit.dtsi"