blob: 30874b038bb429dd3aebfb0211f1bfea4dd9d135 [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay23aee612020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010017
Simon Glassb2c1cac2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070023
Simon Glassfef72b72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -060031 gpio1 = &gpio_a;
32 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010033 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070034 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060035 mmc0 = "/mmc0";
36 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070037 pci0 = &pci0;
38 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070039 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020040 remoteproc0 = &rproc_1;
41 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060042 rtc0 = &rtc_0;
43 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060044 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020045 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070046 testbus3 = "/some-bus";
47 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070048 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070049 testfdt3 = "/b-test";
50 testfdt5 = "/some-bus/c-test@5";
51 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070052 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020053 fdt-dummy0 = "/translation-test@8000/dev@0,0";
54 fdt-dummy1 = "/translation-test@8000/dev@1,100";
55 fdt-dummy2 = "/translation-test@8000/dev@2,200";
56 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060057 usb0 = &usb_0;
58 usb1 = &usb_1;
59 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020060 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020061 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060062 };
63
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020064 config {
Simon Glass0034d962021-08-07 07:24:01 -060065 testing-bool;
66 testing-int = <123>;
67 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020068 environment {
69 from_fdt = "yes";
70 fdt_env_path = "";
71 };
72 };
73
Nandor Han6521e5d2021-06-10 16:56:44 +030074 reboot-mode0 {
75 compatible = "reboot-mode-gpio";
76 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
77 u-boot,env-variable = "bootstatus";
78 mode-test = <0x01>;
79 mode-download = <0x03>;
80 };
81
Nandor Han7e4067a2021-06-10 16:56:45 +030082 reboot_mode1: reboot-mode@14 {
83 compatible = "reboot-mode-rtc";
84 rtc = <&rtc_0>;
85 reg = <0x30 4>;
86 u-boot,env-variable = "bootstatus";
87 big-endian;
88 mode-test = <0x21969147>;
89 mode-download = <0x51939147>;
90 };
91
Simon Glassed96cde2018-12-10 10:37:33 -070092 audio: audio-codec {
93 compatible = "sandbox,audio-codec";
94 #sound-dai-cells = <1>;
95 };
96
Philippe Reynes1ee26482020-07-24 18:19:51 +020097 buttons {
98 compatible = "gpio-keys";
99
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200100 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200101 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200102 label = "button1";
Philippe Reynes1ee26482020-07-24 18:19:51 +0200103 };
104
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200105 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200106 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200107 label = "button2";
Philippe Reynes1ee26482020-07-24 18:19:51 +0200108 };
109 };
110
Marek Szyprowskiad398592021-02-18 11:33:18 +0100111 buttons2 {
112 compatible = "adc-keys";
113 io-channels = <&adc 3>;
114 keyup-threshold-microvolt = <3000000>;
115
116 button-up {
117 label = "button3";
118 linux,code = <KEY_F3>;
119 press-threshold-microvolt = <1500000>;
120 };
121
122 button-down {
123 label = "button4";
124 linux,code = <KEY_F4>;
125 press-threshold-microvolt = <1000000>;
126 };
127
128 button-enter {
129 label = "button5";
130 linux,code = <KEY_F5>;
131 press-threshold-microvolt = <500000>;
132 };
133 };
134
Simon Glassc953aaf2018-12-10 10:37:34 -0700135 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600136 reg = <0 0>;
137 compatible = "google,cros-ec-sandbox";
138
139 /*
140 * This describes the flash memory within the EC. Note
141 * that the STM32L flash erases to 0, not 0xff.
142 */
143 flash {
144 image-pos = <0x08000000>;
145 size = <0x20000>;
146 erase-value = <0>;
147
148 /* Information for sandbox */
149 ro {
150 image-pos = <0>;
151 size = <0xf000>;
152 };
153 wp-ro {
154 image-pos = <0xf000>;
155 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700156 used = <0x884>;
157 compress = "lz4";
158 uncomp-size = <0xcf8>;
159 hash {
160 algo = "sha256";
161 value = [00 01 02 03 04 05 06 07
162 08 09 0a 0b 0c 0d 0e 0f
163 10 11 12 13 14 15 16 17
164 18 19 1a 1b 1c 1d 1e 1f];
165 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600166 };
167 rw {
168 image-pos = <0x10000>;
169 size = <0x10000>;
170 };
171 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300172
173 cros_ec_pwm: cros-ec-pwm {
174 compatible = "google,cros-ec-pwm";
175 #pwm-cells = <1>;
176 };
177
Simon Glass699c9ca2018-10-01 12:22:08 -0600178 };
179
Yannick Fertré9712c822019-10-07 15:29:05 +0200180 dsi_host: dsi_host {
181 compatible = "sandbox,dsi-host";
182 };
183
Simon Glassb2c1cac2014-02-26 15:59:21 -0700184 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600185 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700186 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600187 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700188 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600189 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100190 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
191 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700192 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100193 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
194 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
195 <&gpio_b 7 GPIO_IN 3 2 1>,
196 <&gpio_b 8 GPIO_OUT 3 2 1>,
197 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100198 test3-gpios =
199 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
200 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
201 <&gpio_c 2 GPIO_OUT>,
202 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
203 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200204 <&gpio_c 5 GPIO_IN>,
205 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
206 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530207 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
208 test5-gpios = <&gpio_a 19>;
209
Simon Glass73025392021-10-23 17:26:04 -0600210 bool-value;
Simon Glass6df01f92018-12-10 10:37:37 -0700211 int-value = <1234>;
212 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200213 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200214 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600215 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700216 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600217 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200218 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530219
220 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
221 <&muxcontroller0 2>, <&muxcontroller0 3>,
222 <&muxcontroller1>;
223 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
224 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100225 display-timings {
226 timing0: 240x320 {
227 clock-frequency = <6500000>;
228 hactive = <240>;
229 vactive = <320>;
230 hfront-porch = <6>;
231 hback-porch = <7>;
232 hsync-len = <1>;
233 vback-porch = <5>;
234 vfront-porch = <8>;
235 vsync-len = <2>;
236 hsync-active = <1>;
237 vsync-active = <0>;
238 de-active = <1>;
239 pixelclk-active = <1>;
240 interlaced;
241 doublescan;
242 doubleclk;
243 };
244 timing1: 480x800 {
245 clock-frequency = <9000000>;
246 hactive = <480>;
247 vactive = <800>;
248 hfront-porch = <10>;
249 hback-porch = <59>;
250 hsync-len = <12>;
251 vback-porch = <15>;
252 vfront-porch = <17>;
253 vsync-len = <16>;
254 hsync-active = <0>;
255 vsync-active = <1>;
256 de-active = <0>;
257 pixelclk-active = <0>;
258 };
259 timing2: 800x480 {
260 clock-frequency = <33500000>;
261 hactive = <800>;
262 vactive = <480>;
263 hback-porch = <89>;
264 hfront-porch = <164>;
265 vback-porch = <23>;
266 vfront-porch = <10>;
267 hsync-len = <11>;
268 vsync-len = <13>;
269 };
270 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700271 };
272
273 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600274 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700275 compatible = "not,compatible";
276 };
277
278 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600279 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700280 };
281
Simon Glass5620cf82018-10-01 12:22:40 -0600282 backlight: backlight {
283 compatible = "pwm-backlight";
284 enable-gpios = <&gpio_a 1>;
285 power-supply = <&ldo_1>;
286 pwms = <&pwm 0 1000>;
287 default-brightness-level = <5>;
288 brightness-levels = <0 16 32 64 128 170 202 234 255>;
289 };
290
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200291 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200292 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200293 bind-test-child1 {
294 compatible = "sandbox,phy";
295 #phy-cells = <1>;
296 };
297
298 bind-test-child2 {
299 compatible = "simple-bus";
300 };
301 };
302
Simon Glassb2c1cac2014-02-26 15:59:21 -0700303 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600304 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700305 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600306 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700307 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530308
309 mux-controls = <&muxcontroller0 0>;
310 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700311 };
312
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200313 phy_provider0: gen_phy@0 {
314 compatible = "sandbox,phy";
315 #phy-cells = <1>;
316 };
317
318 phy_provider1: gen_phy@1 {
319 compatible = "sandbox,phy";
320 #phy-cells = <0>;
321 broken;
322 };
323
developer71092972020-05-02 11:35:12 +0200324 phy_provider2: gen_phy@2 {
325 compatible = "sandbox,phy";
326 #phy-cells = <0>;
327 };
328
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200329 gen_phy_user: gen_phy_user {
330 compatible = "simple-bus";
331 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
332 phy-names = "phy1", "phy2", "phy3";
333 };
334
developer71092972020-05-02 11:35:12 +0200335 gen_phy_user1: gen_phy_user1 {
336 compatible = "simple-bus";
337 phys = <&phy_provider0 0>, <&phy_provider2>;
338 phy-names = "phy1", "phy2";
339 };
340
Simon Glassb2c1cac2014-02-26 15:59:21 -0700341 some-bus {
342 #address-cells = <1>;
343 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600344 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600345 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600346 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700347 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600348 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700349 compatible = "denx,u-boot-fdt-test";
350 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600351 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700352 ping-add = <5>;
353 };
Simon Glass40717422014-07-23 06:55:18 -0600354 c-test@0 {
355 compatible = "denx,u-boot-fdt-test";
356 reg = <0>;
357 ping-expect = <6>;
358 ping-add = <6>;
359 };
360 c-test@1 {
361 compatible = "denx,u-boot-fdt-test";
362 reg = <1>;
363 ping-expect = <7>;
364 ping-add = <7>;
365 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700366 };
367
368 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600369 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600370 ping-expect = <6>;
371 ping-add = <6>;
372 compatible = "google,another-fdt-test";
373 };
374
375 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600376 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600377 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700378 ping-add = <6>;
379 compatible = "google,another-fdt-test";
380 };
381
Simon Glass0ccb0972015-01-25 08:27:05 -0700382 f-test {
383 compatible = "denx,u-boot-fdt-test";
384 };
385
386 g-test {
387 compatible = "denx,u-boot-fdt-test";
388 };
389
Bin Mengd9d24782018-10-10 22:07:01 -0700390 h-test {
391 compatible = "denx,u-boot-fdt-test1";
392 };
393
developercf8bc132020-05-02 11:35:10 +0200394 i-test {
395 compatible = "mediatek,u-boot-fdt-test";
396 #address-cells = <1>;
397 #size-cells = <0>;
398
399 subnode@0 {
400 reg = <0>;
401 };
402
403 subnode@1 {
404 reg = <1>;
405 };
406
407 subnode@2 {
408 reg = <2>;
409 };
410 };
411
Simon Glass204675c2019-12-29 21:19:25 -0700412 devres-test {
413 compatible = "denx,u-boot-devres-test";
414 };
415
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530416 another-test {
417 reg = <0 2>;
418 compatible = "denx,u-boot-fdt-test";
419 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
420 test5-gpios = <&gpio_a 19>;
421 };
422
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100423 mmio-bus@0 {
424 #address-cells = <1>;
425 #size-cells = <1>;
426 compatible = "denx,u-boot-test-bus";
427 dma-ranges = <0x10000000 0x00000000 0x00040000>;
428
429 subnode@0 {
430 compatible = "denx,u-boot-fdt-test";
431 };
432 };
433
434 mmio-bus@1 {
435 #address-cells = <1>;
436 #size-cells = <1>;
437 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100438
439 subnode@0 {
440 compatible = "denx,u-boot-fdt-test";
441 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100442 };
443
Simon Glass3c601b12020-07-07 13:12:06 -0600444 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600445 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600446 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600447 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600448 child {
449 compatible = "denx,u-boot-acpi-test";
450 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600451 };
452
Simon Glass3c601b12020-07-07 13:12:06 -0600453 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600454 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600455 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600456 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600457 };
458
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200459 clocks {
460 clk_fixed: clk-fixed {
461 compatible = "fixed-clock";
462 #clock-cells = <0>;
463 clock-frequency = <1234>;
464 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000465
466 clk_fixed_factor: clk-fixed-factor {
467 compatible = "fixed-factor-clock";
468 #clock-cells = <0>;
469 clock-div = <3>;
470 clock-mult = <2>;
471 clocks = <&clk_fixed>;
472 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200473
474 osc {
475 compatible = "fixed-clock";
476 #clock-cells = <0>;
477 clock-frequency = <20000000>;
478 };
Stephen Warrena9622432016-06-17 09:44:00 -0600479 };
480
481 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600482 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600483 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200484 assigned-clocks = <&clk_sandbox 3>;
485 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600486 };
487
488 clk-test {
489 compatible = "sandbox,clk-test";
490 clocks = <&clk_fixed>,
491 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200492 <&clk_sandbox 0>,
493 <&clk_sandbox 3>,
494 <&clk_sandbox 2>;
495 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600496 };
497
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200498 ccf: clk-ccf {
499 compatible = "sandbox,clk-ccf";
500 };
501
Simon Glass507ab962021-12-04 08:56:31 -0700502 efi-media {
503 compatible = "sandbox,efi-media";
504 };
505
Simon Glass5b968632015-05-22 15:42:15 -0600506 eth@10002000 {
507 compatible = "sandbox,eth";
508 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500509 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600510 };
511
512 eth_5: eth@10003000 {
513 compatible = "sandbox,eth";
514 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500515 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600516 };
517
Bin Meng04a11cb2015-08-27 22:25:53 -0700518 eth_3: sbe5 {
519 compatible = "sandbox,eth";
520 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500521 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700522 };
523
Simon Glass5b968632015-05-22 15:42:15 -0600524 eth@10004000 {
525 compatible = "sandbox,eth";
526 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500527 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600528 };
529
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800530 dsa_eth0: dsa-test-eth {
531 compatible = "sandbox,eth";
532 reg = <0x10006000 0x1000>;
533 fake-host-hwaddr = [00 00 66 44 22 66];
534 };
535
536 dsa-test {
537 compatible = "sandbox,dsa";
538
539 ports {
540 #address-cells = <1>;
541 #size-cells = <0>;
542 swp_0: port@0 {
543 reg = <0>;
544 label = "lan0";
545 phy-mode = "rgmii-rxid";
546
547 fixed-link {
548 speed = <100>;
549 full-duplex;
550 };
551 };
552
553 swp_1: port@1 {
554 reg = <1>;
555 label = "lan1";
556 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800557 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800558 };
559
560 port@2 {
561 reg = <2>;
562 ethernet = <&dsa_eth0>;
563
564 fixed-link {
565 speed = <1000>;
566 full-duplex;
567 };
568 };
569 };
570 };
571
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700572 firmware {
573 sandbox_firmware: sandbox-firmware {
574 compatible = "sandbox,firmware";
575 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200576
Etienne Carriere09665cb2022-02-21 09:22:39 +0100577 scmi {
Etienne Carriere02fd1262020-09-09 18:44:00 +0200578 compatible = "sandbox,scmi-agent";
579 #address-cells = <1>;
580 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200581
Etienne Carriere09665cb2022-02-21 09:22:39 +0100582 protocol@10 {
583 reg = <0x10>;
584 };
585
586 clk_scmi: protocol@14 {
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200587 reg = <0x14>;
588 #clock-cells = <1>;
589 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200590
Etienne Carriere09665cb2022-02-21 09:22:39 +0100591 reset_scmi: protocol@16 {
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200592 reg = <0x16>;
593 #reset-cells = <1>;
594 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100595
596 protocol@17 {
597 reg = <0x17>;
598
599 regulators {
600 #address-cells = <1>;
601 #size-cells = <0>;
602
Etienne Carriere09665cb2022-02-21 09:22:39 +0100603 regul0_scmi: reg@0 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100604 reg = <0>;
605 regulator-name = "sandbox-voltd0";
606 regulator-min-microvolt = <1100000>;
607 regulator-max-microvolt = <3300000>;
608 };
Etienne Carriere09665cb2022-02-21 09:22:39 +0100609 regul1_scmi: reg@1 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100610 reg = <0x1>;
611 regulator-name = "sandbox-voltd1";
612 regulator-min-microvolt = <1800000>;
613 };
614 };
615 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200616 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700617 };
618
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100619 pinctrl-gpio {
620 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700621
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100622 gpio_a: base-gpios {
623 compatible = "sandbox,gpio";
624 gpio-controller;
625 #gpio-cells = <1>;
626 gpio-bank-name = "a";
627 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200628 hog_input_active_low {
629 gpio-hog;
630 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200631 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200632 };
633 hog_input_active_high {
634 gpio-hog;
635 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200636 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200637 };
638 hog_output_low {
639 gpio-hog;
640 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200641 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200642 };
643 hog_output_high {
644 gpio-hog;
645 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200646 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200647 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100648 };
649
650 gpio_b: extra-gpios {
651 compatible = "sandbox,gpio";
652 gpio-controller;
653 #gpio-cells = <5>;
654 gpio-bank-name = "b";
655 sandbox,gpio-count = <10>;
656 };
Simon Glass25348a42014-10-13 23:42:11 -0600657
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100658 gpio_c: pinmux-gpios {
659 compatible = "sandbox,gpio";
660 gpio-controller;
661 #gpio-cells = <2>;
662 gpio-bank-name = "c";
663 sandbox,gpio-count = <10>;
664 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100665 };
666
Simon Glass7df766e2014-12-10 08:55:55 -0700667 i2c@0 {
668 #address-cells = <1>;
669 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600670 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700671 compatible = "sandbox,i2c";
672 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200673 pinctrl-names = "default";
674 pinctrl-0 = <&pinmux_i2c0_pins>;
675
Simon Glass7df766e2014-12-10 08:55:55 -0700676 eeprom@2c {
677 reg = <0x2c>;
678 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700679 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200680 partitions {
681 compatible = "fixed-partitions";
682 #address-cells = <1>;
683 #size-cells = <1>;
684 bootcount_i2c: bootcount@10 {
685 reg = <10 2>;
686 };
687 };
Simon Glass7df766e2014-12-10 08:55:55 -0700688 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200689
Simon Glass336b2952015-05-22 15:42:17 -0600690 rtc_0: rtc@43 {
691 reg = <0x43>;
692 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700693 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600694 };
695
696 rtc_1: rtc@61 {
697 reg = <0x61>;
698 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700699 sandbox,emul = <&emul1>;
700 };
701
702 i2c_emul: emul {
703 reg = <0xff>;
704 compatible = "sandbox,i2c-emul-parent";
705 emul_eeprom: emul-eeprom {
706 compatible = "sandbox,i2c-eeprom";
707 sandbox,filename = "i2c.bin";
708 sandbox,size = <256>;
709 };
710 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700711 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700712 };
713 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700714 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600715 };
716 };
717
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200718 sandbox_pmic: sandbox_pmic {
719 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700720 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200721 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200722
723 mc34708: pmic@41 {
724 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700725 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200726 };
Simon Glass7df766e2014-12-10 08:55:55 -0700727 };
728
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100729 bootcount@0 {
730 compatible = "u-boot,bootcount-rtc";
731 rtc = <&rtc_1>;
732 offset = <0x13>;
733 };
734
Michal Simek4f18f922020-05-28 11:48:55 +0200735 bootcount {
736 compatible = "u-boot,bootcount-i2c-eeprom";
737 i2c-eeprom = <&bootcount_i2c>;
738 };
739
Nandor Han88895812021-06-10 15:40:38 +0300740 bootcount_4@0 {
741 compatible = "u-boot,bootcount-syscon";
742 syscon = <&syscon0>;
743 reg = <0x0 0x04>, <0x0 0x04>;
744 reg-names = "syscon_reg", "offset";
745 };
746
747 bootcount_2@0 {
748 compatible = "u-boot,bootcount-syscon";
749 syscon = <&syscon0>;
750 reg = <0x0 0x04>, <0x0 0x02> ;
751 reg-names = "syscon_reg", "offset";
752 };
753
Marek Szyprowskiad398592021-02-18 11:33:18 +0100754 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100755 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100756 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100757 vdd-supply = <&buck2>;
758 vss-microvolts = <0>;
759 };
760
Mark Kettenis67748ee2021-10-23 16:58:02 +0200761 iommu: iommu@0 {
762 compatible = "sandbox,iommu";
763 #iommu-cells = <0>;
764 };
765
Simon Glass515dcff2020-02-06 09:55:00 -0700766 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700767 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700768 interrupt-controller;
769 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700770 };
771
Simon Glass90b6fef2016-01-18 19:52:26 -0700772 lcd {
773 u-boot,dm-pre-reloc;
774 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200775 pinctrl-names = "default";
776 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700777 xres = <1366>;
778 yres = <768>;
779 };
780
Simon Glassd783eb32015-07-06 12:54:34 -0600781 leds {
782 compatible = "gpio-leds";
783
784 iracibble {
785 gpios = <&gpio_a 1 0>;
786 label = "sandbox:red";
787 };
788
789 martinet {
790 gpios = <&gpio_a 2 0>;
791 label = "sandbox:green";
792 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200793
794 default_on {
795 gpios = <&gpio_a 5 0>;
796 label = "sandbox:default_on";
797 default-state = "on";
798 };
799
800 default_off {
801 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400802 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200803 default-state = "off";
804 };
Simon Glassd783eb32015-07-06 12:54:34 -0600805 };
806
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200807 gpio-wdt {
808 gpios = <&gpio_a 7 0>;
809 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +0200810 hw_margin_ms = <100>;
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200811 always-running;
812 };
813
Stephen Warren62f2c902016-05-16 17:41:37 -0600814 mbox: mbox {
815 compatible = "sandbox,mbox";
816 #mbox-cells = <1>;
817 };
818
819 mbox-test {
820 compatible = "sandbox,mbox-test";
821 mboxes = <&mbox 100>, <&mbox 1>;
822 mbox-names = "other", "test";
823 };
824
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900825 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200826 #address-cells = <1>;
827 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400828 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200829 cpu1: cpu@1 {
830 device_type = "cpu";
831 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400832 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900833 compatible = "sandbox,cpu_sandbox";
834 u-boot,dm-pre-reloc;
835 };
Mario Sixdea5df72018-08-06 10:23:44 +0200836
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200837 cpu2: cpu@2 {
838 device_type = "cpu";
839 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900840 compatible = "sandbox,cpu_sandbox";
841 u-boot,dm-pre-reloc;
842 };
Mario Sixdea5df72018-08-06 10:23:44 +0200843
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200844 cpu3: cpu@3 {
845 device_type = "cpu";
846 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900847 compatible = "sandbox,cpu_sandbox";
848 u-boot,dm-pre-reloc;
849 };
Mario Sixdea5df72018-08-06 10:23:44 +0200850 };
851
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500852 chipid: chipid {
853 compatible = "sandbox,soc";
854 };
855
Simon Glassc953aaf2018-12-10 10:37:34 -0700856 i2s: i2s {
857 compatible = "sandbox,i2s";
858 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700859 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700860 };
861
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200862 nop-test_0 {
863 compatible = "sandbox,nop_sandbox1";
864 nop-test_1 {
865 compatible = "sandbox,nop_sandbox2";
866 bind = "True";
867 };
868 nop-test_2 {
869 compatible = "sandbox,nop_sandbox2";
870 bind = "False";
871 };
872 };
873
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200874 misc-test {
875 compatible = "sandbox,misc_sandbox";
876 };
877
Simon Glasse4fef742017-04-23 20:02:07 -0600878 mmc2 {
879 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -0600880 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -0600881 };
882
883 mmc1 {
884 compatible = "sandbox,mmc";
885 };
886
887 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600888 compatible = "sandbox,mmc";
889 };
890
Simon Glass53a68b32019-02-16 20:24:50 -0700891 pch {
892 compatible = "sandbox,pch";
893 };
894
Tom Rini4a3ca482020-02-11 12:41:23 -0500895 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700896 compatible = "sandbox,pci";
897 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500898 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700899 #address-cells = <3>;
900 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600901 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700902 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700903 pci@0,0 {
904 compatible = "pci-generic";
905 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600906 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700907 };
Alex Margineanf1274432019-06-07 11:24:24 +0300908 pci@1,0 {
909 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600910 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
911 reg = <0x02000814 0 0 0 0
912 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600913 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300914 };
Simon Glass937bb472019-12-06 21:41:57 -0700915 p2sb-pci@2,0 {
916 compatible = "sandbox,p2sb";
917 reg = <0x02001010 0 0 0 0>;
918 sandbox,emul = <&p2sb_emul>;
919
920 adder {
921 intel,p2sb-port-id = <3>;
922 compatible = "sandbox,adder";
923 };
924 };
Simon Glass8c501022019-12-06 21:41:54 -0700925 pci@1e,0 {
926 compatible = "sandbox,pmc";
927 reg = <0xf000 0 0 0 0>;
928 sandbox,emul = <&pmc_emul1e>;
929 acpi-base = <0x400>;
930 gpe0-dwx-mask = <0xf>;
931 gpe0-dwx-shift-base = <4>;
932 gpe0-dw = <6 7 9>;
933 gpe0-sts = <0x20>;
934 gpe0-en = <0x30>;
935 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700936 pci@1f,0 {
937 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600938 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
939 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600940 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700941 };
942 };
943
Simon Glassb98ba4c2019-09-25 08:56:10 -0600944 pci-emul0 {
945 compatible = "sandbox,pci-emul-parent";
946 swap_case_emul0_0: emul0@0,0 {
947 compatible = "sandbox,swap-case";
948 };
949 swap_case_emul0_1: emul0@1,0 {
950 compatible = "sandbox,swap-case";
951 use-ea;
952 };
953 swap_case_emul0_1f: emul0@1f,0 {
954 compatible = "sandbox,swap-case";
955 };
Simon Glass937bb472019-12-06 21:41:57 -0700956 p2sb_emul: emul@2,0 {
957 compatible = "sandbox,p2sb-emul";
958 };
Simon Glass8c501022019-12-06 21:41:54 -0700959 pmc_emul1e: emul@1e,0 {
960 compatible = "sandbox,pmc-emul";
961 };
Simon Glassb98ba4c2019-09-25 08:56:10 -0600962 };
963
Tom Rini4a3ca482020-02-11 12:41:23 -0500964 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -0700965 compatible = "sandbox,pci";
966 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500967 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -0700968 #address-cells = <3>;
969 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -0700970 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
971 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
972 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700973 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200974 0x0c 0x00 0x1234 0x5678
975 0x10 0x00 0x1234 0x5678>;
976 pci@10,0 {
977 reg = <0x8000 0 0 0 0>;
978 };
Bin Meng408e5902018-08-03 01:14:41 -0700979 };
980
Tom Rini4a3ca482020-02-11 12:41:23 -0500981 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -0700982 compatible = "sandbox,pci";
983 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500984 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -0700985 #address-cells = <3>;
986 #size-cells = <2>;
987 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
988 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
989 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
990 pci@1f,0 {
991 compatible = "pci-generic";
992 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600993 sandbox,emul = <&swap_case_emul2_1f>;
994 };
995 };
996
997 pci-emul2 {
998 compatible = "sandbox,pci-emul-parent";
999 swap_case_emul2_1f: emul2@1f,0 {
1000 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001001 };
1002 };
1003
Ramon Friedc64f19b2019-04-27 11:15:23 +03001004 pci_ep: pci_ep {
1005 compatible = "sandbox,pci_ep";
1006 };
1007
Simon Glass9c433fe2017-04-23 20:10:44 -06001008 probing {
1009 compatible = "simple-bus";
1010 test1 {
1011 compatible = "denx,u-boot-probe-test";
1012 };
1013
1014 test2 {
1015 compatible = "denx,u-boot-probe-test";
1016 };
1017
1018 test3 {
1019 compatible = "denx,u-boot-probe-test";
1020 };
1021
1022 test4 {
1023 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001024 first-syscon = <&syscon0>;
1025 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001026 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001027 };
1028 };
1029
Stephen Warren92c67fa2016-07-13 13:45:31 -06001030 pwrdom: power-domain {
1031 compatible = "sandbox,power-domain";
1032 #power-domain-cells = <1>;
1033 };
1034
1035 power-domain-test {
1036 compatible = "sandbox,power-domain-test";
1037 power-domains = <&pwrdom 2>;
1038 };
1039
Simon Glass5620cf82018-10-01 12:22:40 -06001040 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001041 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001042 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001043 pinctrl-names = "default";
1044 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001045 };
1046
1047 pwm2 {
1048 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001049 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001050 };
1051
Simon Glass3d355e62015-07-06 12:54:31 -06001052 ram {
1053 compatible = "sandbox,ram";
1054 };
1055
Simon Glassd860f222015-07-06 12:54:29 -06001056 reset@0 {
1057 compatible = "sandbox,warm-reset";
1058 };
1059
1060 reset@1 {
1061 compatible = "sandbox,reset";
1062 };
1063
Stephen Warren6488e642016-06-17 09:43:59 -06001064 resetc: reset-ctl {
1065 compatible = "sandbox,reset-ctl";
1066 #reset-cells = <1>;
1067 };
1068
1069 reset-ctl-test {
1070 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001071 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1072 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001073 };
1074
Sughosh Ganu23e37512019-12-28 23:58:31 +05301075 rng {
1076 compatible = "sandbox,sandbox-rng";
1077 };
1078
Nishanth Menonedf85812015-09-17 15:42:41 -05001079 rproc_1: rproc@1 {
1080 compatible = "sandbox,test-processor";
1081 remoteproc-name = "remoteproc-test-dev1";
1082 };
1083
1084 rproc_2: rproc@2 {
1085 compatible = "sandbox,test-processor";
1086 internal-memory-mapped;
1087 remoteproc-name = "remoteproc-test-dev2";
1088 };
1089
Simon Glass5620cf82018-10-01 12:22:40 -06001090 panel {
1091 compatible = "simple-panel";
1092 backlight = <&backlight 0 100>;
1093 };
1094
Ramon Fried26ed32e2018-07-02 02:57:59 +03001095 smem@0 {
1096 compatible = "sandbox,smem";
1097 };
1098
Simon Glass76072ac2018-12-10 10:37:36 -07001099 sound {
1100 compatible = "sandbox,sound";
1101 cpu {
1102 sound-dai = <&i2s 0>;
1103 };
1104
1105 codec {
1106 sound-dai = <&audio 0>;
1107 };
1108 };
1109
Simon Glass25348a42014-10-13 23:42:11 -06001110 spi@0 {
1111 #address-cells = <1>;
1112 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001113 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001114 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001115 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001116 pinctrl-names = "default";
1117 pinctrl-0 = <&pinmux_spi0_pins>;
1118
Simon Glass25348a42014-10-13 23:42:11 -06001119 spi.bin@0 {
1120 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001121 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001122 spi-max-frequency = <40000000>;
1123 sandbox,filename = "spi.bin";
1124 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001125 spi.bin@1 {
1126 reg = <1>;
1127 compatible = "spansion,m25p16", "jedec,spi-nor";
1128 spi-max-frequency = <50000000>;
1129 sandbox,filename = "spi.bin";
1130 spi-cpol;
1131 spi-cpha;
1132 };
Simon Glass25348a42014-10-13 23:42:11 -06001133 };
1134
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001135 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001136 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001137 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001138 };
1139
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001140 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001141 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001142 reg = <0x20 5
1143 0x28 6
1144 0x30 7
1145 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001146 };
1147
Patrick Delaunayee010432019-03-07 09:57:13 +01001148 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001149 compatible = "simple-mfd", "syscon";
1150 reg = <0x40 5
1151 0x48 6
1152 0x50 7
1153 0x58 8>;
1154 };
1155
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301156 syscon3: syscon@3 {
1157 compatible = "simple-mfd", "syscon";
1158 reg = <0x000100 0x10>;
1159
1160 muxcontroller0: a-mux-controller {
1161 compatible = "mmio-mux";
1162 #mux-control-cells = <1>;
1163
1164 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1165 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1166 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1167 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1168 u-boot,mux-autoprobe;
1169 };
1170 };
1171
1172 muxcontroller1: emul-mux-controller {
1173 compatible = "mux-emul";
1174 #mux-control-cells = <0>;
1175 u-boot,mux-autoprobe;
1176 idle-state = <0xabcd>;
1177 };
1178
Simon Glass791a17f2020-12-16 21:20:27 -07001179 testfdtm0 {
1180 compatible = "denx,u-boot-fdtm-test";
1181 };
1182
1183 testfdtm1: testfdtm1 {
1184 compatible = "denx,u-boot-fdtm-test";
1185 };
1186
1187 testfdtm2 {
1188 compatible = "denx,u-boot-fdtm-test";
1189 };
1190
Sean Anderson79d3bba2020-09-28 10:52:23 -04001191 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001192 compatible = "sandbox,timer";
1193 clock-frequency = <1000000>;
1194 };
1195
Sean Anderson79d3bba2020-09-28 10:52:23 -04001196 timer@1 {
1197 compatible = "sandbox,timer";
1198 sandbox,timebase-frequency-fallback;
1199 };
1200
Miquel Raynal80938c12018-05-15 11:57:27 +02001201 tpm2 {
1202 compatible = "sandbox,tpm2";
1203 };
1204
Simon Glass5b968632015-05-22 15:42:15 -06001205 uart0: serial {
1206 compatible = "sandbox,serial";
1207 u-boot,dm-pre-reloc;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001208 pinctrl-names = "default";
1209 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001210 };
1211
Simon Glass31680482015-03-25 12:23:05 -06001212 usb_0: usb@0 {
1213 compatible = "sandbox,usb";
1214 status = "disabled";
1215 hub {
1216 compatible = "sandbox,usb-hub";
1217 #address-cells = <1>;
1218 #size-cells = <0>;
1219 flash-stick {
1220 reg = <0>;
1221 compatible = "sandbox,usb-flash";
1222 };
1223 };
1224 };
1225
1226 usb_1: usb@1 {
1227 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001228 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001229 hub {
1230 compatible = "usb-hub";
1231 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001232 #address-cells = <1>;
1233 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001234 hub-emul {
1235 compatible = "sandbox,usb-hub";
1236 #address-cells = <1>;
1237 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001238 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001239 reg = <0>;
1240 compatible = "sandbox,usb-flash";
1241 sandbox,filepath = "testflash.bin";
1242 };
1243
Simon Glass4700fe52015-11-08 23:48:01 -07001244 flash-stick@1 {
1245 reg = <1>;
1246 compatible = "sandbox,usb-flash";
1247 sandbox,filepath = "testflash1.bin";
1248 };
1249
1250 flash-stick@2 {
1251 reg = <2>;
1252 compatible = "sandbox,usb-flash";
1253 sandbox,filepath = "testflash2.bin";
1254 };
1255
Simon Glassc0ccc722015-11-08 23:48:08 -07001256 keyb@3 {
1257 reg = <3>;
1258 compatible = "sandbox,usb-keyb";
1259 };
1260
Simon Glass31680482015-03-25 12:23:05 -06001261 };
Michael Walle7c961322020-06-02 01:47:07 +02001262
1263 usbstor@1 {
1264 reg = <1>;
1265 };
1266 usbstor@3 {
1267 reg = <3>;
1268 };
Simon Glass31680482015-03-25 12:23:05 -06001269 };
1270 };
1271
1272 usb_2: usb@2 {
1273 compatible = "sandbox,usb";
1274 status = "disabled";
1275 };
1276
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001277 spmi: spmi@0 {
1278 compatible = "sandbox,spmi";
1279 #address-cells = <0x1>;
1280 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001281 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001282 pm8916@0 {
1283 compatible = "qcom,spmi-pmic";
1284 reg = <0x0 0x1>;
1285 #address-cells = <0x1>;
1286 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001287 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001288
1289 spmi_gpios: gpios@c000 {
1290 compatible = "qcom,pm8916-gpio";
1291 reg = <0xc000 0x400>;
1292 gpio-controller;
1293 gpio-count = <4>;
1294 #gpio-cells = <2>;
1295 gpio-bank-name="spmi";
1296 };
1297 };
1298 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001299
1300 wdt0: wdt@0 {
1301 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001302 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001303 };
Rob Clarka471b672018-01-10 11:33:30 +01001304
Mario Six95922152018-08-09 14:51:19 +02001305 axi: axi@0 {
1306 compatible = "sandbox,axi";
1307 #address-cells = <0x1>;
1308 #size-cells = <0x1>;
1309 store@0 {
1310 compatible = "sandbox,sandbox_store";
1311 reg = <0x0 0x400>;
1312 };
1313 };
1314
Rob Clarka471b672018-01-10 11:33:30 +01001315 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001316 #address-cells = <1>;
1317 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001318 setting = "sunrise ohoka";
1319 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001320 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001321 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001322 chosen-test {
1323 compatible = "denx,u-boot-fdt-test";
1324 reg = <9 1>;
1325 };
1326 };
Mario Six35616ef2018-03-12 14:53:33 +01001327
1328 translation-test@8000 {
1329 compatible = "simple-bus";
1330 reg = <0x8000 0x4000>;
1331
1332 #address-cells = <0x2>;
1333 #size-cells = <0x1>;
1334
1335 ranges = <0 0x0 0x8000 0x1000
1336 1 0x100 0x9000 0x1000
1337 2 0x200 0xA000 0x1000
1338 3 0x300 0xB000 0x1000
1339 >;
1340
Fabien Dessenne22236e02019-05-31 15:11:30 +02001341 dma-ranges = <0 0x000 0x10000000 0x1000
1342 1 0x100 0x20000000 0x1000
1343 >;
1344
Mario Six35616ef2018-03-12 14:53:33 +01001345 dev@0,0 {
1346 compatible = "denx,u-boot-fdt-dummy";
1347 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +01001348 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001349 };
1350
1351 dev@1,100 {
1352 compatible = "denx,u-boot-fdt-dummy";
1353 reg = <1 0x100 0x1000>;
1354
1355 };
1356
1357 dev@2,200 {
1358 compatible = "denx,u-boot-fdt-dummy";
1359 reg = <2 0x200 0x1000>;
1360 };
1361
1362
1363 noxlatebus@3,300 {
1364 compatible = "simple-bus";
1365 reg = <3 0x300 0x1000>;
1366
1367 #address-cells = <0x1>;
1368 #size-cells = <0x0>;
1369
1370 dev@42 {
1371 compatible = "denx,u-boot-fdt-dummy";
1372 reg = <0x42>;
1373 };
1374 };
1375 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001376
1377 osd {
1378 compatible = "sandbox,sandbox_osd";
1379 };
Tom Rinib93eea72018-09-30 18:16:51 -04001380
Jens Wiklander86afaa62018-09-25 16:40:16 +02001381 sandbox_tee {
1382 compatible = "sandbox,tee";
1383 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001384
1385 sandbox_virtio1 {
1386 compatible = "sandbox,virtio1";
1387 };
1388
1389 sandbox_virtio2 {
1390 compatible = "sandbox,virtio2";
1391 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001392
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001393 sandbox_scmi {
1394 compatible = "sandbox,scmi-devices";
Etienne Carriere09665cb2022-02-21 09:22:39 +01001395 clocks = <&clk_scmi 7>, <&clk_scmi 3>;
1396 resets = <&reset_scmi 3>;
1397 regul0-supply = <&regul0_scmi>;
1398 regul1-supply = <&regul1_scmi>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001399 };
1400
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001401 pinctrl {
1402 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001403
Sean Anderson3438e3b2020-09-14 11:01:57 -04001404 pinctrl-names = "default", "alternate";
1405 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1406 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001407
Sean Anderson3438e3b2020-09-14 11:01:57 -04001408 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001409 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001410 pins = "P5";
1411 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001412 bias-pull-up;
1413 input-disable;
1414 };
1415 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001416 pins = "P6";
1417 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001418 output-high;
1419 drive-open-drain;
1420 };
1421 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001422 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001423 bias-pull-down;
1424 input-enable;
1425 };
1426 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001427 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001428 bias-disable;
1429 };
1430 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001431
1432 pinctrl_i2c: i2c {
1433 groups {
1434 groups = "I2C_UART";
1435 function = "I2C";
1436 };
1437
1438 pins {
1439 pins = "P0", "P1";
1440 drive-open-drain;
1441 };
1442 };
1443
1444 pinctrl_i2s: i2s {
1445 groups = "SPI_I2S";
1446 function = "I2S";
1447 };
1448
1449 pinctrl_spi: spi {
1450 groups = "SPI_I2S";
1451 function = "SPI";
1452
1453 cs {
1454 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1455 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1456 };
1457 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001458 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001459
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001460 pinctrl-single-no-width {
1461 compatible = "pinctrl-single";
1462 reg = <0x0000 0x238>;
1463 #pinctrl-cells = <1>;
1464 pinctrl-single,function-mask = <0x7f>;
1465 };
1466
1467 pinctrl-single-pins {
1468 compatible = "pinctrl-single";
1469 reg = <0x0000 0x238>;
1470 #pinctrl-cells = <1>;
1471 pinctrl-single,register-width = <32>;
1472 pinctrl-single,function-mask = <0x7f>;
1473
1474 pinmux_pwm_pins: pinmux_pwm_pins {
1475 pinctrl-single,pins = < 0x48 0x06 >;
1476 };
1477
1478 pinmux_spi0_pins: pinmux_spi0_pins {
1479 pinctrl-single,pins = <
1480 0x190 0x0c
1481 0x194 0x0c
1482 0x198 0x23
1483 0x19c 0x0c
1484 >;
1485 };
1486
1487 pinmux_uart0_pins: pinmux_uart0_pins {
1488 pinctrl-single,pins = <
1489 0x70 0x30
1490 0x74 0x00
1491 >;
1492 };
1493 };
1494
1495 pinctrl-single-bits {
1496 compatible = "pinctrl-single";
1497 reg = <0x0000 0x50>;
1498 #pinctrl-cells = <2>;
1499 pinctrl-single,bit-per-mux;
1500 pinctrl-single,register-width = <32>;
1501 pinctrl-single,function-mask = <0xf>;
1502
1503 pinmux_i2c0_pins: pinmux_i2c0_pins {
1504 pinctrl-single,bits = <
1505 0x10 0x00002200 0x0000ff00
1506 >;
1507 };
1508
1509 pinmux_lcd_pins: pinmux_lcd_pins {
1510 pinctrl-single,bits = <
1511 0x40 0x22222200 0xffffff00
1512 0x44 0x22222222 0xffffffff
1513 0x48 0x00000022 0x000000ff
1514 0x48 0x02000000 0x0f000000
1515 0x4c 0x02000022 0x0f0000ff
1516 >;
1517 };
1518 };
1519
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001520 hwspinlock@0 {
1521 compatible = "sandbox,hwspinlock";
1522 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001523
1524 dma: dma {
1525 compatible = "sandbox,dma";
1526 #dma-cells = <1>;
1527
1528 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1529 dma-names = "m2m", "tx0", "rx0";
1530 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001531
Alex Marginean0649be52019-07-12 10:13:53 +03001532 /*
1533 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1534 * end of the test. If parent mdio is removed first, clean-up of the
1535 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1536 * active at the end of the test. That it turn doesn't allow the mdio
1537 * class to be destroyed, triggering an error.
1538 */
1539 mdio-mux-test {
1540 compatible = "sandbox,mdio-mux";
1541 #address-cells = <1>;
1542 #size-cells = <0>;
1543 mdio-parent-bus = <&mdio>;
1544
1545 mdio-ch-test@0 {
1546 reg = <0>;
1547 };
1548 mdio-ch-test@1 {
1549 reg = <1>;
1550 };
1551 };
1552
1553 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001554 compatible = "sandbox,mdio";
1555 };
Sean Andersonb7860542020-06-24 06:41:12 -04001556
1557 pm-bus-test {
1558 compatible = "simple-pm-bus";
1559 clocks = <&clk_sandbox 4>;
1560 power-domains = <&pwrdom 1>;
1561 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001562
1563 resetc2: syscon-reset {
1564 compatible = "syscon-reset";
1565 #reset-cells = <1>;
1566 regmap = <&syscon0>;
1567 offset = <1>;
1568 mask = <0x27FFFFFF>;
1569 assert-high = <0>;
1570 };
1571
1572 syscon-reset-test {
1573 compatible = "sandbox,misc_sandbox";
1574 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1575 reset-names = "valid", "no_mask", "out_of_range";
1576 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301577
Simon Glass458b66a2020-11-05 06:32:05 -07001578 sysinfo {
1579 compatible = "sandbox,sysinfo-sandbox";
1580 };
1581
Sean Anderson1c830672021-04-20 10:50:58 -04001582 sysinfo-gpio {
1583 compatible = "gpio-sysinfo";
1584 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1585 revisions = <19>, <5>;
1586 names = "rev_a", "foo";
1587 };
1588
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301589 some_regmapped-bus {
1590 #address-cells = <0x1>;
1591 #size-cells = <0x1>;
1592
1593 ranges = <0x0 0x0 0x10>;
1594 compatible = "simple-bus";
1595
1596 regmap-test_0 {
1597 reg = <0 0x10>;
1598 compatible = "sandbox,regmap_test";
1599 };
1600 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001601};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001602
1603#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001604#include "cros-ec-keyboard.dtsi"