blob: e5261bb9fa26923c49c827bc5b8bb501df864b51 [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay23aee612020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010017
Simon Glassb2c1cac2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070023
Simon Glassfef72b72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -060031 gpio1 = &gpio_a;
32 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010033 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070034 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060035 mmc0 = "/mmc0";
36 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070037 pci0 = &pci0;
38 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070039 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020040 remoteproc0 = &rproc_1;
41 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060042 rtc0 = &rtc_0;
43 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060044 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020045 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070046 testbus3 = "/some-bus";
47 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070048 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070049 testfdt3 = "/b-test";
50 testfdt5 = "/some-bus/c-test@5";
51 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070052 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020053 fdt-dummy0 = "/translation-test@8000/dev@0,0";
54 fdt-dummy1 = "/translation-test@8000/dev@1,100";
55 fdt-dummy2 = "/translation-test@8000/dev@2,200";
56 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060057 usb0 = &usb_0;
58 usb1 = &usb_1;
59 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020060 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020061 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060062 };
63
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020064 config {
Simon Glass0034d962021-08-07 07:24:01 -060065 testing-bool;
66 testing-int = <123>;
67 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020068 environment {
69 from_fdt = "yes";
70 fdt_env_path = "";
71 };
72 };
73
Nandor Han6521e5d2021-06-10 16:56:44 +030074 reboot-mode0 {
75 compatible = "reboot-mode-gpio";
76 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
77 u-boot,env-variable = "bootstatus";
78 mode-test = <0x01>;
79 mode-download = <0x03>;
80 };
81
Nandor Han7e4067a2021-06-10 16:56:45 +030082 reboot_mode1: reboot-mode@14 {
83 compatible = "reboot-mode-rtc";
84 rtc = <&rtc_0>;
85 reg = <0x30 4>;
86 u-boot,env-variable = "bootstatus";
87 big-endian;
88 mode-test = <0x21969147>;
89 mode-download = <0x51939147>;
90 };
91
Simon Glassed96cde2018-12-10 10:37:33 -070092 audio: audio-codec {
93 compatible = "sandbox,audio-codec";
94 #sound-dai-cells = <1>;
95 };
96
Philippe Reynes1ee26482020-07-24 18:19:51 +020097 buttons {
98 compatible = "gpio-keys";
99
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200100 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200101 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200102 label = "button1";
Philippe Reynes1ee26482020-07-24 18:19:51 +0200103 };
104
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200105 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200106 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200107 label = "button2";
Philippe Reynes1ee26482020-07-24 18:19:51 +0200108 };
109 };
110
Marek Szyprowskiad398592021-02-18 11:33:18 +0100111 buttons2 {
112 compatible = "adc-keys";
113 io-channels = <&adc 3>;
114 keyup-threshold-microvolt = <3000000>;
115
116 button-up {
117 label = "button3";
118 linux,code = <KEY_F3>;
119 press-threshold-microvolt = <1500000>;
120 };
121
122 button-down {
123 label = "button4";
124 linux,code = <KEY_F4>;
125 press-threshold-microvolt = <1000000>;
126 };
127
128 button-enter {
129 label = "button5";
130 linux,code = <KEY_F5>;
131 press-threshold-microvolt = <500000>;
132 };
133 };
134
Simon Glassc953aaf2018-12-10 10:37:34 -0700135 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600136 reg = <0 0>;
137 compatible = "google,cros-ec-sandbox";
138
139 /*
140 * This describes the flash memory within the EC. Note
141 * that the STM32L flash erases to 0, not 0xff.
142 */
143 flash {
144 image-pos = <0x08000000>;
145 size = <0x20000>;
146 erase-value = <0>;
147
148 /* Information for sandbox */
149 ro {
150 image-pos = <0>;
151 size = <0xf000>;
152 };
153 wp-ro {
154 image-pos = <0xf000>;
155 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700156 used = <0x884>;
157 compress = "lz4";
158 uncomp-size = <0xcf8>;
159 hash {
160 algo = "sha256";
161 value = [00 01 02 03 04 05 06 07
162 08 09 0a 0b 0c 0d 0e 0f
163 10 11 12 13 14 15 16 17
164 18 19 1a 1b 1c 1d 1e 1f];
165 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600166 };
167 rw {
168 image-pos = <0x10000>;
169 size = <0x10000>;
170 };
171 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300172
173 cros_ec_pwm: cros-ec-pwm {
174 compatible = "google,cros-ec-pwm";
175 #pwm-cells = <1>;
176 };
177
Simon Glass699c9ca2018-10-01 12:22:08 -0600178 };
179
Yannick Fertré9712c822019-10-07 15:29:05 +0200180 dsi_host: dsi_host {
181 compatible = "sandbox,dsi-host";
182 };
183
Simon Glassb2c1cac2014-02-26 15:59:21 -0700184 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600185 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700186 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600187 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700188 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600189 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100190 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
191 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700192 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100193 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
194 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
195 <&gpio_b 7 GPIO_IN 3 2 1>,
196 <&gpio_b 8 GPIO_OUT 3 2 1>,
197 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100198 test3-gpios =
199 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
200 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
201 <&gpio_c 2 GPIO_OUT>,
202 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
203 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200204 <&gpio_c 5 GPIO_IN>,
205 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
206 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530207 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
208 test5-gpios = <&gpio_a 19>;
209
Simon Glass73025392021-10-23 17:26:04 -0600210 bool-value;
Simon Glass6df01f92018-12-10 10:37:37 -0700211 int-value = <1234>;
212 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200213 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200214 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600215 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700216 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600217 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200218 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530219
220 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
221 <&muxcontroller0 2>, <&muxcontroller0 3>,
222 <&muxcontroller1>;
223 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
224 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100225 display-timings {
226 timing0: 240x320 {
227 clock-frequency = <6500000>;
228 hactive = <240>;
229 vactive = <320>;
230 hfront-porch = <6>;
231 hback-porch = <7>;
232 hsync-len = <1>;
233 vback-porch = <5>;
234 vfront-porch = <8>;
235 vsync-len = <2>;
236 hsync-active = <1>;
237 vsync-active = <0>;
238 de-active = <1>;
239 pixelclk-active = <1>;
240 interlaced;
241 doublescan;
242 doubleclk;
243 };
244 timing1: 480x800 {
245 clock-frequency = <9000000>;
246 hactive = <480>;
247 vactive = <800>;
248 hfront-porch = <10>;
249 hback-porch = <59>;
250 hsync-len = <12>;
251 vback-porch = <15>;
252 vfront-porch = <17>;
253 vsync-len = <16>;
254 hsync-active = <0>;
255 vsync-active = <1>;
256 de-active = <0>;
257 pixelclk-active = <0>;
258 };
259 timing2: 800x480 {
260 clock-frequency = <33500000>;
261 hactive = <800>;
262 vactive = <480>;
263 hback-porch = <89>;
264 hfront-porch = <164>;
265 vback-porch = <23>;
266 vfront-porch = <10>;
267 hsync-len = <11>;
268 vsync-len = <13>;
269 };
270 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700271 };
272
273 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600274 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700275 compatible = "not,compatible";
276 };
277
278 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600279 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700280 };
281
Simon Glass5620cf82018-10-01 12:22:40 -0600282 backlight: backlight {
283 compatible = "pwm-backlight";
284 enable-gpios = <&gpio_a 1>;
285 power-supply = <&ldo_1>;
286 pwms = <&pwm 0 1000>;
287 default-brightness-level = <5>;
288 brightness-levels = <0 16 32 64 128 170 202 234 255>;
289 };
290
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200291 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200292 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200293 bind-test-child1 {
294 compatible = "sandbox,phy";
295 #phy-cells = <1>;
296 };
297
298 bind-test-child2 {
299 compatible = "simple-bus";
300 };
301 };
302
Simon Glassb2c1cac2014-02-26 15:59:21 -0700303 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600304 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700305 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600306 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700307 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530308
309 mux-controls = <&muxcontroller0 0>;
310 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700311 };
312
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200313 phy_provider0: gen_phy@0 {
314 compatible = "sandbox,phy";
315 #phy-cells = <1>;
316 };
317
318 phy_provider1: gen_phy@1 {
319 compatible = "sandbox,phy";
320 #phy-cells = <0>;
321 broken;
322 };
323
developer71092972020-05-02 11:35:12 +0200324 phy_provider2: gen_phy@2 {
325 compatible = "sandbox,phy";
326 #phy-cells = <0>;
327 };
328
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200329 gen_phy_user: gen_phy_user {
330 compatible = "simple-bus";
331 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
332 phy-names = "phy1", "phy2", "phy3";
333 };
334
developer71092972020-05-02 11:35:12 +0200335 gen_phy_user1: gen_phy_user1 {
336 compatible = "simple-bus";
337 phys = <&phy_provider0 0>, <&phy_provider2>;
338 phy-names = "phy1", "phy2";
339 };
340
Simon Glassb2c1cac2014-02-26 15:59:21 -0700341 some-bus {
342 #address-cells = <1>;
343 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600344 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600345 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600346 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700347 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600348 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700349 compatible = "denx,u-boot-fdt-test";
350 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600351 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700352 ping-add = <5>;
353 };
Simon Glass40717422014-07-23 06:55:18 -0600354 c-test@0 {
355 compatible = "denx,u-boot-fdt-test";
356 reg = <0>;
357 ping-expect = <6>;
358 ping-add = <6>;
359 };
360 c-test@1 {
361 compatible = "denx,u-boot-fdt-test";
362 reg = <1>;
363 ping-expect = <7>;
364 ping-add = <7>;
365 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700366 };
367
368 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600369 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600370 ping-expect = <6>;
371 ping-add = <6>;
372 compatible = "google,another-fdt-test";
373 };
374
375 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600376 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600377 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700378 ping-add = <6>;
379 compatible = "google,another-fdt-test";
380 };
381
Simon Glass0ccb0972015-01-25 08:27:05 -0700382 f-test {
383 compatible = "denx,u-boot-fdt-test";
384 };
385
386 g-test {
387 compatible = "denx,u-boot-fdt-test";
388 };
389
Bin Mengd9d24782018-10-10 22:07:01 -0700390 h-test {
391 compatible = "denx,u-boot-fdt-test1";
392 };
393
developercf8bc132020-05-02 11:35:10 +0200394 i-test {
395 compatible = "mediatek,u-boot-fdt-test";
396 #address-cells = <1>;
397 #size-cells = <0>;
398
399 subnode@0 {
400 reg = <0>;
401 };
402
403 subnode@1 {
404 reg = <1>;
405 };
406
407 subnode@2 {
408 reg = <2>;
409 };
410 };
411
Simon Glass204675c2019-12-29 21:19:25 -0700412 devres-test {
413 compatible = "denx,u-boot-devres-test";
414 };
415
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530416 another-test {
417 reg = <0 2>;
418 compatible = "denx,u-boot-fdt-test";
419 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
420 test5-gpios = <&gpio_a 19>;
421 };
422
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100423 mmio-bus@0 {
424 #address-cells = <1>;
425 #size-cells = <1>;
426 compatible = "denx,u-boot-test-bus";
427 dma-ranges = <0x10000000 0x00000000 0x00040000>;
428
429 subnode@0 {
430 compatible = "denx,u-boot-fdt-test";
431 };
432 };
433
434 mmio-bus@1 {
435 #address-cells = <1>;
436 #size-cells = <1>;
437 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100438
439 subnode@0 {
440 compatible = "denx,u-boot-fdt-test";
441 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100442 };
443
Simon Glass3c601b12020-07-07 13:12:06 -0600444 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600445 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600446 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600447 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600448 child {
449 compatible = "denx,u-boot-acpi-test";
450 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600451 };
452
Simon Glass3c601b12020-07-07 13:12:06 -0600453 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600454 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600455 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600456 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600457 };
458
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200459 clocks {
460 clk_fixed: clk-fixed {
461 compatible = "fixed-clock";
462 #clock-cells = <0>;
463 clock-frequency = <1234>;
464 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000465
466 clk_fixed_factor: clk-fixed-factor {
467 compatible = "fixed-factor-clock";
468 #clock-cells = <0>;
469 clock-div = <3>;
470 clock-mult = <2>;
471 clocks = <&clk_fixed>;
472 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200473
474 osc {
475 compatible = "fixed-clock";
476 #clock-cells = <0>;
477 clock-frequency = <20000000>;
478 };
Stephen Warrena9622432016-06-17 09:44:00 -0600479 };
480
481 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600482 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600483 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200484 assigned-clocks = <&clk_sandbox 3>;
485 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600486 };
487
488 clk-test {
489 compatible = "sandbox,clk-test";
490 clocks = <&clk_fixed>,
491 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200492 <&clk_sandbox 0>,
493 <&clk_sandbox 3>,
494 <&clk_sandbox 2>;
495 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600496 };
497
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200498 ccf: clk-ccf {
499 compatible = "sandbox,clk-ccf";
500 };
501
Simon Glass5b968632015-05-22 15:42:15 -0600502 eth@10002000 {
503 compatible = "sandbox,eth";
504 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500505 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600506 };
507
508 eth_5: eth@10003000 {
509 compatible = "sandbox,eth";
510 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500511 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600512 };
513
Bin Meng04a11cb2015-08-27 22:25:53 -0700514 eth_3: sbe5 {
515 compatible = "sandbox,eth";
516 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500517 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700518 };
519
Simon Glass5b968632015-05-22 15:42:15 -0600520 eth@10004000 {
521 compatible = "sandbox,eth";
522 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500523 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600524 };
525
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800526 dsa_eth0: dsa-test-eth {
527 compatible = "sandbox,eth";
528 reg = <0x10006000 0x1000>;
529 fake-host-hwaddr = [00 00 66 44 22 66];
530 };
531
532 dsa-test {
533 compatible = "sandbox,dsa";
534
535 ports {
536 #address-cells = <1>;
537 #size-cells = <0>;
538 swp_0: port@0 {
539 reg = <0>;
540 label = "lan0";
541 phy-mode = "rgmii-rxid";
542
543 fixed-link {
544 speed = <100>;
545 full-duplex;
546 };
547 };
548
549 swp_1: port@1 {
550 reg = <1>;
551 label = "lan1";
552 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800553 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800554 };
555
556 port@2 {
557 reg = <2>;
558 ethernet = <&dsa_eth0>;
559
560 fixed-link {
561 speed = <1000>;
562 full-duplex;
563 };
564 };
565 };
566 };
567
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700568 firmware {
569 sandbox_firmware: sandbox-firmware {
570 compatible = "sandbox,firmware";
571 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200572
573 sandbox-scmi-agent@0 {
574 compatible = "sandbox,scmi-agent";
575 #address-cells = <1>;
576 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200577
578 clk_scmi0: protocol@14 {
579 reg = <0x14>;
580 #clock-cells = <1>;
581 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200582
583 reset_scmi0: protocol@16 {
584 reg = <0x16>;
585 #reset-cells = <1>;
586 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100587
588 protocol@17 {
589 reg = <0x17>;
590
591 regulators {
592 #address-cells = <1>;
593 #size-cells = <0>;
594
595 regul0_scmi0: reg@0 {
596 reg = <0>;
597 regulator-name = "sandbox-voltd0";
598 regulator-min-microvolt = <1100000>;
599 regulator-max-microvolt = <3300000>;
600 };
601 regul1_scmi0: reg@1 {
602 reg = <0x1>;
603 regulator-name = "sandbox-voltd1";
604 regulator-min-microvolt = <1800000>;
605 };
606 };
607 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200608 };
609
610 sandbox-scmi-agent@1 {
611 compatible = "sandbox,scmi-agent";
612 #address-cells = <1>;
613 #size-cells = <0>;
614
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200615 clk_scmi1: protocol@14 {
616 reg = <0x14>;
617 #clock-cells = <1>;
618 };
619
Etienne Carriere02fd1262020-09-09 18:44:00 +0200620 protocol@10 {
621 reg = <0x10>;
622 };
623 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700624 };
625
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100626 pinctrl-gpio {
627 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700628
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100629 gpio_a: base-gpios {
630 compatible = "sandbox,gpio";
631 gpio-controller;
632 #gpio-cells = <1>;
633 gpio-bank-name = "a";
634 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200635 hog_input_active_low {
636 gpio-hog;
637 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200638 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200639 };
640 hog_input_active_high {
641 gpio-hog;
642 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200643 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200644 };
645 hog_output_low {
646 gpio-hog;
647 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200648 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200649 };
650 hog_output_high {
651 gpio-hog;
652 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200653 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200654 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100655 };
656
657 gpio_b: extra-gpios {
658 compatible = "sandbox,gpio";
659 gpio-controller;
660 #gpio-cells = <5>;
661 gpio-bank-name = "b";
662 sandbox,gpio-count = <10>;
663 };
Simon Glass25348a42014-10-13 23:42:11 -0600664
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100665 gpio_c: pinmux-gpios {
666 compatible = "sandbox,gpio";
667 gpio-controller;
668 #gpio-cells = <2>;
669 gpio-bank-name = "c";
670 sandbox,gpio-count = <10>;
671 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100672 };
673
Simon Glass7df766e2014-12-10 08:55:55 -0700674 i2c@0 {
675 #address-cells = <1>;
676 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600677 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700678 compatible = "sandbox,i2c";
679 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200680 pinctrl-names = "default";
681 pinctrl-0 = <&pinmux_i2c0_pins>;
682
Simon Glass7df766e2014-12-10 08:55:55 -0700683 eeprom@2c {
684 reg = <0x2c>;
685 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700686 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200687 partitions {
688 compatible = "fixed-partitions";
689 #address-cells = <1>;
690 #size-cells = <1>;
691 bootcount_i2c: bootcount@10 {
692 reg = <10 2>;
693 };
694 };
Simon Glass7df766e2014-12-10 08:55:55 -0700695 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200696
Simon Glass336b2952015-05-22 15:42:17 -0600697 rtc_0: rtc@43 {
698 reg = <0x43>;
699 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700700 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600701 };
702
703 rtc_1: rtc@61 {
704 reg = <0x61>;
705 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700706 sandbox,emul = <&emul1>;
707 };
708
709 i2c_emul: emul {
710 reg = <0xff>;
711 compatible = "sandbox,i2c-emul-parent";
712 emul_eeprom: emul-eeprom {
713 compatible = "sandbox,i2c-eeprom";
714 sandbox,filename = "i2c.bin";
715 sandbox,size = <256>;
716 };
717 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700718 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700719 };
720 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700721 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600722 };
723 };
724
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200725 sandbox_pmic: sandbox_pmic {
726 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700727 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200728 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200729
730 mc34708: pmic@41 {
731 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700732 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200733 };
Simon Glass7df766e2014-12-10 08:55:55 -0700734 };
735
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100736 bootcount@0 {
737 compatible = "u-boot,bootcount-rtc";
738 rtc = <&rtc_1>;
739 offset = <0x13>;
740 };
741
Michal Simek4f18f922020-05-28 11:48:55 +0200742 bootcount {
743 compatible = "u-boot,bootcount-i2c-eeprom";
744 i2c-eeprom = <&bootcount_i2c>;
745 };
746
Nandor Han88895812021-06-10 15:40:38 +0300747 bootcount_4@0 {
748 compatible = "u-boot,bootcount-syscon";
749 syscon = <&syscon0>;
750 reg = <0x0 0x04>, <0x0 0x04>;
751 reg-names = "syscon_reg", "offset";
752 };
753
754 bootcount_2@0 {
755 compatible = "u-boot,bootcount-syscon";
756 syscon = <&syscon0>;
757 reg = <0x0 0x04>, <0x0 0x02> ;
758 reg-names = "syscon_reg", "offset";
759 };
760
Marek Szyprowskiad398592021-02-18 11:33:18 +0100761 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100762 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100763 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100764 vdd-supply = <&buck2>;
765 vss-microvolts = <0>;
766 };
767
Mark Kettenis67748ee2021-10-23 16:58:02 +0200768 iommu: iommu@0 {
769 compatible = "sandbox,iommu";
770 #iommu-cells = <0>;
771 };
772
Simon Glass515dcff2020-02-06 09:55:00 -0700773 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700774 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700775 interrupt-controller;
776 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700777 };
778
Simon Glass90b6fef2016-01-18 19:52:26 -0700779 lcd {
780 u-boot,dm-pre-reloc;
781 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200782 pinctrl-names = "default";
783 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700784 xres = <1366>;
785 yres = <768>;
786 };
787
Simon Glassd783eb32015-07-06 12:54:34 -0600788 leds {
789 compatible = "gpio-leds";
790
791 iracibble {
792 gpios = <&gpio_a 1 0>;
793 label = "sandbox:red";
794 };
795
796 martinet {
797 gpios = <&gpio_a 2 0>;
798 label = "sandbox:green";
799 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200800
801 default_on {
802 gpios = <&gpio_a 5 0>;
803 label = "sandbox:default_on";
804 default-state = "on";
805 };
806
807 default_off {
808 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400809 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200810 default-state = "off";
811 };
Simon Glassd783eb32015-07-06 12:54:34 -0600812 };
813
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200814 gpio-wdt {
815 gpios = <&gpio_a 7 0>;
816 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +0200817 hw_margin_ms = <100>;
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200818 always-running;
819 };
820
Stephen Warren62f2c902016-05-16 17:41:37 -0600821 mbox: mbox {
822 compatible = "sandbox,mbox";
823 #mbox-cells = <1>;
824 };
825
826 mbox-test {
827 compatible = "sandbox,mbox-test";
828 mboxes = <&mbox 100>, <&mbox 1>;
829 mbox-names = "other", "test";
830 };
831
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900832 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200833 #address-cells = <1>;
834 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400835 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200836 cpu1: cpu@1 {
837 device_type = "cpu";
838 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400839 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900840 compatible = "sandbox,cpu_sandbox";
841 u-boot,dm-pre-reloc;
842 };
Mario Sixdea5df72018-08-06 10:23:44 +0200843
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200844 cpu2: cpu@2 {
845 device_type = "cpu";
846 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900847 compatible = "sandbox,cpu_sandbox";
848 u-boot,dm-pre-reloc;
849 };
Mario Sixdea5df72018-08-06 10:23:44 +0200850
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200851 cpu3: cpu@3 {
852 device_type = "cpu";
853 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900854 compatible = "sandbox,cpu_sandbox";
855 u-boot,dm-pre-reloc;
856 };
Mario Sixdea5df72018-08-06 10:23:44 +0200857 };
858
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500859 chipid: chipid {
860 compatible = "sandbox,soc";
861 };
862
Simon Glassc953aaf2018-12-10 10:37:34 -0700863 i2s: i2s {
864 compatible = "sandbox,i2s";
865 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700866 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700867 };
868
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200869 nop-test_0 {
870 compatible = "sandbox,nop_sandbox1";
871 nop-test_1 {
872 compatible = "sandbox,nop_sandbox2";
873 bind = "True";
874 };
875 nop-test_2 {
876 compatible = "sandbox,nop_sandbox2";
877 bind = "False";
878 };
879 };
880
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200881 misc-test {
882 compatible = "sandbox,misc_sandbox";
883 };
884
Simon Glasse4fef742017-04-23 20:02:07 -0600885 mmc2 {
886 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -0600887 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -0600888 };
889
890 mmc1 {
891 compatible = "sandbox,mmc";
892 };
893
894 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600895 compatible = "sandbox,mmc";
896 };
897
Simon Glass53a68b32019-02-16 20:24:50 -0700898 pch {
899 compatible = "sandbox,pch";
900 };
901
Tom Rini4a3ca482020-02-11 12:41:23 -0500902 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700903 compatible = "sandbox,pci";
904 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500905 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700906 #address-cells = <3>;
907 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600908 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700909 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700910 pci@0,0 {
911 compatible = "pci-generic";
912 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600913 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700914 };
Alex Margineanf1274432019-06-07 11:24:24 +0300915 pci@1,0 {
916 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600917 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
918 reg = <0x02000814 0 0 0 0
919 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600920 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300921 };
Simon Glass937bb472019-12-06 21:41:57 -0700922 p2sb-pci@2,0 {
923 compatible = "sandbox,p2sb";
924 reg = <0x02001010 0 0 0 0>;
925 sandbox,emul = <&p2sb_emul>;
926
927 adder {
928 intel,p2sb-port-id = <3>;
929 compatible = "sandbox,adder";
930 };
931 };
Simon Glass8c501022019-12-06 21:41:54 -0700932 pci@1e,0 {
933 compatible = "sandbox,pmc";
934 reg = <0xf000 0 0 0 0>;
935 sandbox,emul = <&pmc_emul1e>;
936 acpi-base = <0x400>;
937 gpe0-dwx-mask = <0xf>;
938 gpe0-dwx-shift-base = <4>;
939 gpe0-dw = <6 7 9>;
940 gpe0-sts = <0x20>;
941 gpe0-en = <0x30>;
942 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700943 pci@1f,0 {
944 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600945 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
946 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600947 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700948 };
949 };
950
Simon Glassb98ba4c2019-09-25 08:56:10 -0600951 pci-emul0 {
952 compatible = "sandbox,pci-emul-parent";
953 swap_case_emul0_0: emul0@0,0 {
954 compatible = "sandbox,swap-case";
955 };
956 swap_case_emul0_1: emul0@1,0 {
957 compatible = "sandbox,swap-case";
958 use-ea;
959 };
960 swap_case_emul0_1f: emul0@1f,0 {
961 compatible = "sandbox,swap-case";
962 };
Simon Glass937bb472019-12-06 21:41:57 -0700963 p2sb_emul: emul@2,0 {
964 compatible = "sandbox,p2sb-emul";
965 };
Simon Glass8c501022019-12-06 21:41:54 -0700966 pmc_emul1e: emul@1e,0 {
967 compatible = "sandbox,pmc-emul";
968 };
Simon Glassb98ba4c2019-09-25 08:56:10 -0600969 };
970
Tom Rini4a3ca482020-02-11 12:41:23 -0500971 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -0700972 compatible = "sandbox,pci";
973 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500974 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -0700975 #address-cells = <3>;
976 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -0700977 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
978 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
979 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700980 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200981 0x0c 0x00 0x1234 0x5678
982 0x10 0x00 0x1234 0x5678>;
983 pci@10,0 {
984 reg = <0x8000 0 0 0 0>;
985 };
Bin Meng408e5902018-08-03 01:14:41 -0700986 };
987
Tom Rini4a3ca482020-02-11 12:41:23 -0500988 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -0700989 compatible = "sandbox,pci";
990 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500991 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -0700992 #address-cells = <3>;
993 #size-cells = <2>;
994 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
995 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
996 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
997 pci@1f,0 {
998 compatible = "pci-generic";
999 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001000 sandbox,emul = <&swap_case_emul2_1f>;
1001 };
1002 };
1003
1004 pci-emul2 {
1005 compatible = "sandbox,pci-emul-parent";
1006 swap_case_emul2_1f: emul2@1f,0 {
1007 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001008 };
1009 };
1010
Ramon Friedc64f19b2019-04-27 11:15:23 +03001011 pci_ep: pci_ep {
1012 compatible = "sandbox,pci_ep";
1013 };
1014
Simon Glass9c433fe2017-04-23 20:10:44 -06001015 probing {
1016 compatible = "simple-bus";
1017 test1 {
1018 compatible = "denx,u-boot-probe-test";
1019 };
1020
1021 test2 {
1022 compatible = "denx,u-boot-probe-test";
1023 };
1024
1025 test3 {
1026 compatible = "denx,u-boot-probe-test";
1027 };
1028
1029 test4 {
1030 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001031 first-syscon = <&syscon0>;
1032 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001033 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001034 };
1035 };
1036
Stephen Warren92c67fa2016-07-13 13:45:31 -06001037 pwrdom: power-domain {
1038 compatible = "sandbox,power-domain";
1039 #power-domain-cells = <1>;
1040 };
1041
1042 power-domain-test {
1043 compatible = "sandbox,power-domain-test";
1044 power-domains = <&pwrdom 2>;
1045 };
1046
Simon Glass5620cf82018-10-01 12:22:40 -06001047 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001048 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001049 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001050 pinctrl-names = "default";
1051 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001052 };
1053
1054 pwm2 {
1055 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001056 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001057 };
1058
Simon Glass3d355e62015-07-06 12:54:31 -06001059 ram {
1060 compatible = "sandbox,ram";
1061 };
1062
Simon Glassd860f222015-07-06 12:54:29 -06001063 reset@0 {
1064 compatible = "sandbox,warm-reset";
1065 };
1066
1067 reset@1 {
1068 compatible = "sandbox,reset";
1069 };
1070
Stephen Warren6488e642016-06-17 09:43:59 -06001071 resetc: reset-ctl {
1072 compatible = "sandbox,reset-ctl";
1073 #reset-cells = <1>;
1074 };
1075
1076 reset-ctl-test {
1077 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001078 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1079 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001080 };
1081
Sughosh Ganu23e37512019-12-28 23:58:31 +05301082 rng {
1083 compatible = "sandbox,sandbox-rng";
1084 };
1085
Nishanth Menonedf85812015-09-17 15:42:41 -05001086 rproc_1: rproc@1 {
1087 compatible = "sandbox,test-processor";
1088 remoteproc-name = "remoteproc-test-dev1";
1089 };
1090
1091 rproc_2: rproc@2 {
1092 compatible = "sandbox,test-processor";
1093 internal-memory-mapped;
1094 remoteproc-name = "remoteproc-test-dev2";
1095 };
1096
Simon Glass5620cf82018-10-01 12:22:40 -06001097 panel {
1098 compatible = "simple-panel";
1099 backlight = <&backlight 0 100>;
1100 };
1101
Ramon Fried26ed32e2018-07-02 02:57:59 +03001102 smem@0 {
1103 compatible = "sandbox,smem";
1104 };
1105
Simon Glass76072ac2018-12-10 10:37:36 -07001106 sound {
1107 compatible = "sandbox,sound";
1108 cpu {
1109 sound-dai = <&i2s 0>;
1110 };
1111
1112 codec {
1113 sound-dai = <&audio 0>;
1114 };
1115 };
1116
Simon Glass25348a42014-10-13 23:42:11 -06001117 spi@0 {
1118 #address-cells = <1>;
1119 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001120 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001121 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001122 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001123 pinctrl-names = "default";
1124 pinctrl-0 = <&pinmux_spi0_pins>;
1125
Simon Glass25348a42014-10-13 23:42:11 -06001126 spi.bin@0 {
1127 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001128 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001129 spi-max-frequency = <40000000>;
1130 sandbox,filename = "spi.bin";
1131 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001132 spi.bin@1 {
1133 reg = <1>;
1134 compatible = "spansion,m25p16", "jedec,spi-nor";
1135 spi-max-frequency = <50000000>;
1136 sandbox,filename = "spi.bin";
1137 spi-cpol;
1138 spi-cpha;
1139 };
Simon Glass25348a42014-10-13 23:42:11 -06001140 };
1141
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001142 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001143 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001144 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001145 };
1146
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001147 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001148 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001149 reg = <0x20 5
1150 0x28 6
1151 0x30 7
1152 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001153 };
1154
Patrick Delaunayee010432019-03-07 09:57:13 +01001155 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001156 compatible = "simple-mfd", "syscon";
1157 reg = <0x40 5
1158 0x48 6
1159 0x50 7
1160 0x58 8>;
1161 };
1162
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301163 syscon3: syscon@3 {
1164 compatible = "simple-mfd", "syscon";
1165 reg = <0x000100 0x10>;
1166
1167 muxcontroller0: a-mux-controller {
1168 compatible = "mmio-mux";
1169 #mux-control-cells = <1>;
1170
1171 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1172 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1173 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1174 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1175 u-boot,mux-autoprobe;
1176 };
1177 };
1178
1179 muxcontroller1: emul-mux-controller {
1180 compatible = "mux-emul";
1181 #mux-control-cells = <0>;
1182 u-boot,mux-autoprobe;
1183 idle-state = <0xabcd>;
1184 };
1185
Simon Glass791a17f2020-12-16 21:20:27 -07001186 testfdtm0 {
1187 compatible = "denx,u-boot-fdtm-test";
1188 };
1189
1190 testfdtm1: testfdtm1 {
1191 compatible = "denx,u-boot-fdtm-test";
1192 };
1193
1194 testfdtm2 {
1195 compatible = "denx,u-boot-fdtm-test";
1196 };
1197
Sean Anderson79d3bba2020-09-28 10:52:23 -04001198 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001199 compatible = "sandbox,timer";
1200 clock-frequency = <1000000>;
1201 };
1202
Sean Anderson79d3bba2020-09-28 10:52:23 -04001203 timer@1 {
1204 compatible = "sandbox,timer";
1205 sandbox,timebase-frequency-fallback;
1206 };
1207
Miquel Raynal80938c12018-05-15 11:57:27 +02001208 tpm2 {
1209 compatible = "sandbox,tpm2";
1210 };
1211
Simon Glass5b968632015-05-22 15:42:15 -06001212 uart0: serial {
1213 compatible = "sandbox,serial";
1214 u-boot,dm-pre-reloc;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001215 pinctrl-names = "default";
1216 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001217 };
1218
Simon Glass31680482015-03-25 12:23:05 -06001219 usb_0: usb@0 {
1220 compatible = "sandbox,usb";
1221 status = "disabled";
1222 hub {
1223 compatible = "sandbox,usb-hub";
1224 #address-cells = <1>;
1225 #size-cells = <0>;
1226 flash-stick {
1227 reg = <0>;
1228 compatible = "sandbox,usb-flash";
1229 };
1230 };
1231 };
1232
1233 usb_1: usb@1 {
1234 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001235 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001236 hub {
1237 compatible = "usb-hub";
1238 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001239 #address-cells = <1>;
1240 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001241 hub-emul {
1242 compatible = "sandbox,usb-hub";
1243 #address-cells = <1>;
1244 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001245 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001246 reg = <0>;
1247 compatible = "sandbox,usb-flash";
1248 sandbox,filepath = "testflash.bin";
1249 };
1250
Simon Glass4700fe52015-11-08 23:48:01 -07001251 flash-stick@1 {
1252 reg = <1>;
1253 compatible = "sandbox,usb-flash";
1254 sandbox,filepath = "testflash1.bin";
1255 };
1256
1257 flash-stick@2 {
1258 reg = <2>;
1259 compatible = "sandbox,usb-flash";
1260 sandbox,filepath = "testflash2.bin";
1261 };
1262
Simon Glassc0ccc722015-11-08 23:48:08 -07001263 keyb@3 {
1264 reg = <3>;
1265 compatible = "sandbox,usb-keyb";
1266 };
1267
Simon Glass31680482015-03-25 12:23:05 -06001268 };
Michael Walle7c961322020-06-02 01:47:07 +02001269
1270 usbstor@1 {
1271 reg = <1>;
1272 };
1273 usbstor@3 {
1274 reg = <3>;
1275 };
Simon Glass31680482015-03-25 12:23:05 -06001276 };
1277 };
1278
1279 usb_2: usb@2 {
1280 compatible = "sandbox,usb";
1281 status = "disabled";
1282 };
1283
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001284 spmi: spmi@0 {
1285 compatible = "sandbox,spmi";
1286 #address-cells = <0x1>;
1287 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001288 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001289 pm8916@0 {
1290 compatible = "qcom,spmi-pmic";
1291 reg = <0x0 0x1>;
1292 #address-cells = <0x1>;
1293 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001294 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001295
1296 spmi_gpios: gpios@c000 {
1297 compatible = "qcom,pm8916-gpio";
1298 reg = <0xc000 0x400>;
1299 gpio-controller;
1300 gpio-count = <4>;
1301 #gpio-cells = <2>;
1302 gpio-bank-name="spmi";
1303 };
1304 };
1305 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001306
1307 wdt0: wdt@0 {
1308 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001309 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001310 };
Rob Clarka471b672018-01-10 11:33:30 +01001311
Mario Six95922152018-08-09 14:51:19 +02001312 axi: axi@0 {
1313 compatible = "sandbox,axi";
1314 #address-cells = <0x1>;
1315 #size-cells = <0x1>;
1316 store@0 {
1317 compatible = "sandbox,sandbox_store";
1318 reg = <0x0 0x400>;
1319 };
1320 };
1321
Rob Clarka471b672018-01-10 11:33:30 +01001322 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001323 #address-cells = <1>;
1324 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001325 setting = "sunrise ohoka";
1326 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001327 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001328 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001329 chosen-test {
1330 compatible = "denx,u-boot-fdt-test";
1331 reg = <9 1>;
1332 };
1333 };
Mario Six35616ef2018-03-12 14:53:33 +01001334
1335 translation-test@8000 {
1336 compatible = "simple-bus";
1337 reg = <0x8000 0x4000>;
1338
1339 #address-cells = <0x2>;
1340 #size-cells = <0x1>;
1341
1342 ranges = <0 0x0 0x8000 0x1000
1343 1 0x100 0x9000 0x1000
1344 2 0x200 0xA000 0x1000
1345 3 0x300 0xB000 0x1000
1346 >;
1347
Fabien Dessenne22236e02019-05-31 15:11:30 +02001348 dma-ranges = <0 0x000 0x10000000 0x1000
1349 1 0x100 0x20000000 0x1000
1350 >;
1351
Mario Six35616ef2018-03-12 14:53:33 +01001352 dev@0,0 {
1353 compatible = "denx,u-boot-fdt-dummy";
1354 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +01001355 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001356 };
1357
1358 dev@1,100 {
1359 compatible = "denx,u-boot-fdt-dummy";
1360 reg = <1 0x100 0x1000>;
1361
1362 };
1363
1364 dev@2,200 {
1365 compatible = "denx,u-boot-fdt-dummy";
1366 reg = <2 0x200 0x1000>;
1367 };
1368
1369
1370 noxlatebus@3,300 {
1371 compatible = "simple-bus";
1372 reg = <3 0x300 0x1000>;
1373
1374 #address-cells = <0x1>;
1375 #size-cells = <0x0>;
1376
1377 dev@42 {
1378 compatible = "denx,u-boot-fdt-dummy";
1379 reg = <0x42>;
1380 };
1381 };
1382 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001383
1384 osd {
1385 compatible = "sandbox,sandbox_osd";
1386 };
Tom Rinib93eea72018-09-30 18:16:51 -04001387
Jens Wiklander86afaa62018-09-25 16:40:16 +02001388 sandbox_tee {
1389 compatible = "sandbox,tee";
1390 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001391
1392 sandbox_virtio1 {
1393 compatible = "sandbox,virtio1";
1394 };
1395
1396 sandbox_virtio2 {
1397 compatible = "sandbox,virtio2";
1398 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001399
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001400 sandbox_scmi {
1401 compatible = "sandbox,scmi-devices";
1402 clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>;
Etienne Carriere8b9b6892020-09-09 18:44:07 +02001403 resets = <&reset_scmi0 3>;
Etienne Carriereb8f15cd2021-03-08 22:38:07 +01001404 regul0-supply = <&regul0_scmi0>;
1405 regul1-supply = <&regul1_scmi0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001406 };
1407
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001408 pinctrl {
1409 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001410
Sean Anderson3438e3b2020-09-14 11:01:57 -04001411 pinctrl-names = "default", "alternate";
1412 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1413 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001414
Sean Anderson3438e3b2020-09-14 11:01:57 -04001415 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001416 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001417 pins = "P5";
1418 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001419 bias-pull-up;
1420 input-disable;
1421 };
1422 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001423 pins = "P6";
1424 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001425 output-high;
1426 drive-open-drain;
1427 };
1428 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001429 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001430 bias-pull-down;
1431 input-enable;
1432 };
1433 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001434 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001435 bias-disable;
1436 };
1437 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001438
1439 pinctrl_i2c: i2c {
1440 groups {
1441 groups = "I2C_UART";
1442 function = "I2C";
1443 };
1444
1445 pins {
1446 pins = "P0", "P1";
1447 drive-open-drain;
1448 };
1449 };
1450
1451 pinctrl_i2s: i2s {
1452 groups = "SPI_I2S";
1453 function = "I2S";
1454 };
1455
1456 pinctrl_spi: spi {
1457 groups = "SPI_I2S";
1458 function = "SPI";
1459
1460 cs {
1461 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1462 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1463 };
1464 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001465 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001466
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001467 pinctrl-single-no-width {
1468 compatible = "pinctrl-single";
1469 reg = <0x0000 0x238>;
1470 #pinctrl-cells = <1>;
1471 pinctrl-single,function-mask = <0x7f>;
1472 };
1473
1474 pinctrl-single-pins {
1475 compatible = "pinctrl-single";
1476 reg = <0x0000 0x238>;
1477 #pinctrl-cells = <1>;
1478 pinctrl-single,register-width = <32>;
1479 pinctrl-single,function-mask = <0x7f>;
1480
1481 pinmux_pwm_pins: pinmux_pwm_pins {
1482 pinctrl-single,pins = < 0x48 0x06 >;
1483 };
1484
1485 pinmux_spi0_pins: pinmux_spi0_pins {
1486 pinctrl-single,pins = <
1487 0x190 0x0c
1488 0x194 0x0c
1489 0x198 0x23
1490 0x19c 0x0c
1491 >;
1492 };
1493
1494 pinmux_uart0_pins: pinmux_uart0_pins {
1495 pinctrl-single,pins = <
1496 0x70 0x30
1497 0x74 0x00
1498 >;
1499 };
1500 };
1501
1502 pinctrl-single-bits {
1503 compatible = "pinctrl-single";
1504 reg = <0x0000 0x50>;
1505 #pinctrl-cells = <2>;
1506 pinctrl-single,bit-per-mux;
1507 pinctrl-single,register-width = <32>;
1508 pinctrl-single,function-mask = <0xf>;
1509
1510 pinmux_i2c0_pins: pinmux_i2c0_pins {
1511 pinctrl-single,bits = <
1512 0x10 0x00002200 0x0000ff00
1513 >;
1514 };
1515
1516 pinmux_lcd_pins: pinmux_lcd_pins {
1517 pinctrl-single,bits = <
1518 0x40 0x22222200 0xffffff00
1519 0x44 0x22222222 0xffffffff
1520 0x48 0x00000022 0x000000ff
1521 0x48 0x02000000 0x0f000000
1522 0x4c 0x02000022 0x0f0000ff
1523 >;
1524 };
1525 };
1526
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001527 hwspinlock@0 {
1528 compatible = "sandbox,hwspinlock";
1529 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001530
1531 dma: dma {
1532 compatible = "sandbox,dma";
1533 #dma-cells = <1>;
1534
1535 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1536 dma-names = "m2m", "tx0", "rx0";
1537 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001538
Alex Marginean0649be52019-07-12 10:13:53 +03001539 /*
1540 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1541 * end of the test. If parent mdio is removed first, clean-up of the
1542 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1543 * active at the end of the test. That it turn doesn't allow the mdio
1544 * class to be destroyed, triggering an error.
1545 */
1546 mdio-mux-test {
1547 compatible = "sandbox,mdio-mux";
1548 #address-cells = <1>;
1549 #size-cells = <0>;
1550 mdio-parent-bus = <&mdio>;
1551
1552 mdio-ch-test@0 {
1553 reg = <0>;
1554 };
1555 mdio-ch-test@1 {
1556 reg = <1>;
1557 };
1558 };
1559
1560 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001561 compatible = "sandbox,mdio";
1562 };
Sean Andersonb7860542020-06-24 06:41:12 -04001563
1564 pm-bus-test {
1565 compatible = "simple-pm-bus";
1566 clocks = <&clk_sandbox 4>;
1567 power-domains = <&pwrdom 1>;
1568 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001569
1570 resetc2: syscon-reset {
1571 compatible = "syscon-reset";
1572 #reset-cells = <1>;
1573 regmap = <&syscon0>;
1574 offset = <1>;
1575 mask = <0x27FFFFFF>;
1576 assert-high = <0>;
1577 };
1578
1579 syscon-reset-test {
1580 compatible = "sandbox,misc_sandbox";
1581 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1582 reset-names = "valid", "no_mask", "out_of_range";
1583 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301584
Simon Glass458b66a2020-11-05 06:32:05 -07001585 sysinfo {
1586 compatible = "sandbox,sysinfo-sandbox";
1587 };
1588
Sean Anderson1c830672021-04-20 10:50:58 -04001589 sysinfo-gpio {
1590 compatible = "gpio-sysinfo";
1591 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1592 revisions = <19>, <5>;
1593 names = "rev_a", "foo";
1594 };
1595
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301596 some_regmapped-bus {
1597 #address-cells = <0x1>;
1598 #size-cells = <0x1>;
1599
1600 ranges = <0x0 0x0 0x10>;
1601 compatible = "simple-bus";
1602
1603 regmap-test_0 {
1604 reg = <0 0x10>;
1605 compatible = "sandbox,regmap_test";
1606 };
1607 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001608};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001609
1610#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001611#include "cros-ec-keyboard.dtsi"