blob: 9599a8db9c5a365697b990e96641298a03afbc83 [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Eddie James1a55a7a2023-10-24 10:43:51 -050012#include <config.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010013#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010015#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040016#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053017#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010018
Simon Glassb2c1cac2014-02-26 15:59:21 -070019/ {
20 model = "sandbox";
21 compatible = "sandbox";
22 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060023 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070024
Simon Glassfef72b72014-07-23 06:55:03 -060025 aliases {
26 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010027 ethernet0 = "/eth@10002000";
28 ethernet2 = &swp_0;
29 ethernet3 = &eth_3;
30 ethernet4 = &dsa_eth0;
31 ethernet5 = &eth_5;
Sean Anderson67d93a42022-05-05 13:11:30 -040032 ethernet6 = "/eth@10004000";
33 ethernet7 = &swp_1;
34 ethernet8 = &phy_eth0;
Simon Glass5620cf82018-10-01 12:22:40 -060035 gpio1 = &gpio_a;
36 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010037 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070038 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060039 mmc0 = "/mmc0";
40 mmc1 = "/mmc1";
Simon Glassf1eba352022-10-20 18:23:20 -060041 mmc2 = "/mmc2";
42 mmc3 = "/mmc3";
Simon Glassfff928c2023-08-24 13:55:41 -060043 mmc4 = "/mmc4";
44 mmc5 = "/mmc5";
Alexander Gendin038cb022023-10-09 01:24:36 +000045 mmc6 = "/mmc6";
Mattijs Korpershoekd77f8152024-07-10 10:40:06 +020046 mmc7 = "/mmc7";
Bin Meng408e5902018-08-03 01:14:41 -070047 pci0 = &pci0;
48 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070049 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020050 remoteproc0 = &rproc_1;
51 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060052 rtc0 = &rtc_0;
53 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060054 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020055 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070056 testbus3 = "/some-bus";
57 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070058 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070059 testfdt3 = "/b-test";
60 testfdt5 = "/some-bus/c-test@5";
61 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070062 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020063 fdt-dummy0 = "/translation-test@8000/dev@0,0";
64 fdt-dummy1 = "/translation-test@8000/dev@1,100";
65 fdt-dummy2 = "/translation-test@8000/dev@2,200";
66 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060067 usb0 = &usb_0;
68 usb1 = &usb_1;
69 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020070 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020071 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060072 };
73
Eddie James1a55a7a2023-10-24 10:43:51 -050074 reserved-memory {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 ranges;
78
79 event_log: tcg_event_log {
80 no-map;
Sughosh Ganu3f768682024-08-26 17:29:32 +053081 reg = <(CFG_SYS_SDRAM_BASE + 0x100000) 0x2000>;
Eddie James1a55a7a2023-10-24 10:43:51 -050082 };
83 };
84
Simon Glass5e135d32022-10-20 18:23:15 -060085 binman: binman {
Philippe Reynes462d1632022-03-28 22:56:53 +020086 };
87
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020088 config {
Simon Glass0034d962021-08-07 07:24:01 -060089 testing-bool;
90 testing-int = <123>;
91 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020092 environment {
93 from_fdt = "yes";
94 fdt_env_path = "";
95 };
96 };
97
Michal Simek43c42bd2023-08-31 08:59:05 +020098 options {
99 u-boot {
100 compatible = "u-boot,config";
101 bootscr-ram-offset = /bits/ 64 <0x12345678>;
Michal Simek6a7c1ce2023-08-31 09:04:27 +0200102 bootscr-flash-offset = /bits/ 64 <0>;
103 bootscr-flash-size = /bits/ 64 <0x2000>;
Michal Simek43c42bd2023-08-31 08:59:05 +0200104 };
105 };
106
Simon Glassb255efc2022-04-24 23:31:24 -0600107 bootstd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700108 bootph-verify;
Simon Glassb255efc2022-04-24 23:31:24 -0600109 compatible = "u-boot,boot-std";
110
111 filename-prefixes = "/", "/boot/";
112 bootdev-order = "mmc2", "mmc1";
113
Simon Glassb71d7f72023-05-10 16:34:46 -0600114 extlinux {
115 compatible = "u-boot,extlinux";
Simon Glassb255efc2022-04-24 23:31:24 -0600116 };
117
118 efi {
119 compatible = "u-boot,distro-efi";
120 };
Simon Glassa9289612022-10-20 18:23:14 -0600121
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600122 theme {
123 font-size = <30>;
Simon Glass86f1ac52023-06-01 10:23:00 -0600124 menu-inset = <3>;
125 menuitem-gap-y = <1>;
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600126 };
127
Simon Glass82adc292023-08-14 16:40:30 -0600128 cedit-theme {
129 font-size = <30>;
130 menu-inset = <3>;
131 menuitem-gap-y = <1>;
132 };
133
Simon Glassf1eba352022-10-20 18:23:20 -0600134 /*
135 * This is used for the VBE OS-request tests. A FAT filesystem
136 * created in a partition with the VBE information appearing
Michal Simek33224372023-09-07 14:55:48 +0200137 * before the partition starts
Simon Glassf1eba352022-10-20 18:23:20 -0600138 */
Simon Glassa9289612022-10-20 18:23:14 -0600139 firmware0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700140 bootph-verify;
Simon Glassa9289612022-10-20 18:23:14 -0600141 compatible = "fwupd,vbe-simple";
142 storage = "mmc1";
143 skip-offset = <0x200>;
144 area-start = <0x400>;
145 area-size = <0x1000>;
146 state-offset = <0x400>;
147 state-size = <0x40>;
148 version-offset = <0x800>;
149 version-size = <0x100>;
150 };
Simon Glassf1eba352022-10-20 18:23:20 -0600151
152 /*
153 * This is used for the VBE VPL tests. The MMC device holds the
154 * binman image.bin file. The test progresses through each phase
155 * of U-Boot, loading each in turn from MMC.
156 *
157 * Note that the test enables this node (and mmc3) before
158 * running U-Boot
159 */
160 firmware1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700161 bootph-verify;
Simon Glassf1eba352022-10-20 18:23:20 -0600162 status = "disabled";
163 compatible = "fwupd,vbe-simple";
164 storage = "mmc3";
Simon Glass9bb73e32023-04-02 14:01:24 +1200165 skip-offset = <0x800000>;
Simon Glassf1eba352022-10-20 18:23:20 -0600166 area-start = <0>;
167 area-size = <0xe00000>;
168 state-offset = <0xdffc00>;
169 state-size = <0x40>;
170 version-offset = <0xdffe00>;
171 version-size = <0x100>;
172 };
Simon Glassb255efc2022-04-24 23:31:24 -0600173 };
174
Simon Glass61300722023-06-01 10:23:01 -0600175 cedit: cedit {
176 };
177
Andrew Scull451b8b12022-05-30 10:00:12 +0000178 fuzzing-engine {
179 compatible = "sandbox,fuzzing-engine";
180 };
181
Nandor Han6521e5d2021-06-10 16:56:44 +0300182 reboot-mode0 {
183 compatible = "reboot-mode-gpio";
184 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
185 u-boot,env-variable = "bootstatus";
186 mode-test = <0x01>;
187 mode-download = <0x03>;
188 };
189
Nandor Han7e4067a2021-06-10 16:56:45 +0300190 reboot_mode1: reboot-mode@14 {
191 compatible = "reboot-mode-rtc";
192 rtc = <&rtc_0>;
193 reg = <0x30 4>;
194 u-boot,env-variable = "bootstatus";
195 big-endian;
196 mode-test = <0x21969147>;
197 mode-download = <0x51939147>;
198 };
199
Simon Glassed96cde2018-12-10 10:37:33 -0700200 audio: audio-codec {
201 compatible = "sandbox,audio-codec";
202 #sound-dai-cells = <1>;
203 };
204
Philippe Reynes1ee26482020-07-24 18:19:51 +0200205 buttons {
206 compatible = "gpio-keys";
207
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200208 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200209 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200210 label = "button1";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300211 linux,code = <BTN_1>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200212 };
213
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200214 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200215 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200216 label = "button2";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300217 linux,code = <BTN_2>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200218 };
219 };
220
Marek Szyprowskiad398592021-02-18 11:33:18 +0100221 buttons2 {
222 compatible = "adc-keys";
223 io-channels = <&adc 3>;
224 keyup-threshold-microvolt = <3000000>;
225
226 button-up {
227 label = "button3";
228 linux,code = <KEY_F3>;
229 press-threshold-microvolt = <1500000>;
230 };
231
232 button-down {
233 label = "button4";
234 linux,code = <KEY_F4>;
235 press-threshold-microvolt = <1000000>;
236 };
237
238 button-enter {
239 label = "button5";
240 linux,code = <KEY_F5>;
241 press-threshold-microvolt = <500000>;
242 };
243 };
244
Simon Glassc953aaf2018-12-10 10:37:34 -0700245 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600246 reg = <0 0>;
247 compatible = "google,cros-ec-sandbox";
248
249 /*
250 * This describes the flash memory within the EC. Note
251 * that the STM32L flash erases to 0, not 0xff.
252 */
253 flash {
254 image-pos = <0x08000000>;
255 size = <0x20000>;
256 erase-value = <0>;
257
258 /* Information for sandbox */
259 ro {
260 image-pos = <0>;
261 size = <0xf000>;
262 };
263 wp-ro {
264 image-pos = <0xf000>;
265 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700266 used = <0x884>;
267 compress = "lz4";
268 uncomp-size = <0xcf8>;
269 hash {
270 algo = "sha256";
271 value = [00 01 02 03 04 05 06 07
272 08 09 0a 0b 0c 0d 0e 0f
273 10 11 12 13 14 15 16 17
274 18 19 1a 1b 1c 1d 1e 1f];
275 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600276 };
277 rw {
278 image-pos = <0x10000>;
279 size = <0x10000>;
280 };
281 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300282
283 cros_ec_pwm: cros-ec-pwm {
284 compatible = "google,cros-ec-pwm";
285 #pwm-cells = <1>;
286 };
287
Simon Glass699c9ca2018-10-01 12:22:08 -0600288 };
289
Yannick Fertré9712c822019-10-07 15:29:05 +0200290 dsi_host: dsi_host {
291 compatible = "sandbox,dsi-host";
292 };
293
Simon Glassb2c1cac2014-02-26 15:59:21 -0700294 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600295 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700296 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600297 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700298 ping-add = <0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700299 bootph-all;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100300 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
301 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700302 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100303 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
304 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
305 <&gpio_b 7 GPIO_IN 3 2 1>,
306 <&gpio_b 8 GPIO_OUT 3 2 1>,
307 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100308 test3-gpios =
309 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
310 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
311 <&gpio_c 2 GPIO_OUT>,
312 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
313 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200314 <&gpio_c 5 GPIO_IN>,
315 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
316 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530317 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
318 test5-gpios = <&gpio_a 19>;
319
Simon Glass73025392021-10-23 17:26:04 -0600320 bool-value;
Stefan Herbrechtsmeier1b090e62022-06-14 15:21:30 +0200321 int8-value = /bits/ 8 <0x12>;
322 int16-value = /bits/ 16 <0x1234>;
Simon Glass6df01f92018-12-10 10:37:37 -0700323 int-value = <1234>;
324 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200325 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200326 int-array = <5678 9123 4567>;
Michal Simek08a194e2023-08-25 11:37:46 +0200327 int64-array = /bits/ 64 <0x1111222233334444 0x4444333322221111>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600328 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700329 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600330 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200331 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530332
333 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
334 <&muxcontroller0 2>, <&muxcontroller0 3>,
335 <&muxcontroller1>;
336 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
337 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100338 display-timings {
339 timing0: 240x320 {
340 clock-frequency = <6500000>;
341 hactive = <240>;
342 vactive = <320>;
343 hfront-porch = <6>;
344 hback-porch = <7>;
345 hsync-len = <1>;
346 vback-porch = <5>;
347 vfront-porch = <8>;
348 vsync-len = <2>;
349 hsync-active = <1>;
350 vsync-active = <0>;
351 de-active = <1>;
352 pixelclk-active = <1>;
353 interlaced;
354 doublescan;
355 doubleclk;
356 };
357 timing1: 480x800 {
358 clock-frequency = <9000000>;
359 hactive = <480>;
360 vactive = <800>;
361 hfront-porch = <10>;
362 hback-porch = <59>;
363 hsync-len = <12>;
364 vback-porch = <15>;
365 vfront-porch = <17>;
366 vsync-len = <16>;
367 hsync-active = <0>;
368 vsync-active = <1>;
369 de-active = <0>;
370 pixelclk-active = <0>;
371 };
372 timing2: 800x480 {
373 clock-frequency = <33500000>;
374 hactive = <800>;
375 vactive = <480>;
376 hback-porch = <89>;
377 hfront-porch = <164>;
378 vback-porch = <23>;
379 vfront-porch = <10>;
380 hsync-len = <11>;
381 vsync-len = <13>;
382 };
383 };
Raphael Gallais-Poua853b922023-05-11 16:36:52 +0200384 panel-timing {
Nikhil M Jainbb9d1312023-01-31 15:35:15 +0530385 clock-frequency = <6500000>;
386 hactive = <240>;
387 vactive = <320>;
388 hfront-porch = <6>;
389 hback-porch = <7>;
390 hsync-len = <1>;
391 vback-porch = <5>;
392 vfront-porch = <8>;
393 vsync-len = <2>;
394 hsync-active = <1>;
395 vsync-active = <0>;
396 de-active = <1>;
397 pixelclk-active = <1>;
398 interlaced;
399 doublescan;
400 doubleclk;
401 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700402 };
403
404 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600405 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700406 compatible = "not,compatible";
407 };
408
409 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600410 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700411 };
412
Simon Glass5620cf82018-10-01 12:22:40 -0600413 backlight: backlight {
414 compatible = "pwm-backlight";
415 enable-gpios = <&gpio_a 1>;
416 power-supply = <&ldo_1>;
417 pwms = <&pwm 0 1000>;
418 default-brightness-level = <5>;
419 brightness-levels = <0 16 32 64 128 170 202 234 255>;
420 };
421
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200422 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200423 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200424 bind-test-child1 {
425 compatible = "sandbox,phy";
426 #phy-cells = <1>;
427 };
428
429 bind-test-child2 {
430 compatible = "simple-bus";
431 };
432 };
433
Simon Glassb2c1cac2014-02-26 15:59:21 -0700434 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600435 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700436 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600437 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700438 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530439
440 mux-controls = <&muxcontroller0 0>;
441 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700442 };
443
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200444 phy_provider0: gen_phy@0 {
445 compatible = "sandbox,phy";
446 #phy-cells = <1>;
447 };
448
449 phy_provider1: gen_phy@1 {
450 compatible = "sandbox,phy";
451 #phy-cells = <0>;
452 broken;
453 };
454
developer71092972020-05-02 11:35:12 +0200455 phy_provider2: gen_phy@2 {
456 compatible = "sandbox,phy";
457 #phy-cells = <0>;
458 };
459
Jonas Karlman9f89e682023-08-31 22:16:35 +0000460 phy_provider3: gen_phy@3 {
461 compatible = "sandbox,phy";
462 #phy-cells = <2>;
463 };
464
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200465 gen_phy_user: gen_phy_user {
466 compatible = "simple-bus";
467 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
468 phy-names = "phy1", "phy2", "phy3";
469 };
470
developer71092972020-05-02 11:35:12 +0200471 gen_phy_user1: gen_phy_user1 {
472 compatible = "simple-bus";
473 phys = <&phy_provider0 0>, <&phy_provider2>;
474 phy-names = "phy1", "phy2";
475 };
476
Jonas Karlman9f89e682023-08-31 22:16:35 +0000477 gen_phy_user2: gen_phy_user2 {
478 compatible = "simple-bus";
479 phys = <&phy_provider3 0 0>;
480 phy-names = "phy1";
481 };
482
Simon Glassb2c1cac2014-02-26 15:59:21 -0700483 some-bus {
484 #address-cells = <1>;
485 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600486 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600487 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600488 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700489 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600490 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700491 compatible = "denx,u-boot-fdt-test";
492 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600493 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700494 ping-add = <5>;
495 };
Simon Glass40717422014-07-23 06:55:18 -0600496 c-test@0 {
497 compatible = "denx,u-boot-fdt-test";
498 reg = <0>;
499 ping-expect = <6>;
500 ping-add = <6>;
501 };
502 c-test@1 {
503 compatible = "denx,u-boot-fdt-test";
504 reg = <1>;
505 ping-expect = <7>;
506 ping-add = <7>;
507 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700508 };
509
510 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600511 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600512 ping-expect = <6>;
513 ping-add = <6>;
514 compatible = "google,another-fdt-test";
515 };
516
517 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600518 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600519 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700520 ping-add = <6>;
521 compatible = "google,another-fdt-test";
522 };
523
Simon Glass0ccb0972015-01-25 08:27:05 -0700524 f-test {
Patrick Rudolph0fe88cc2024-10-23 15:20:05 +0200525 #interrupt-cells = <2>;
526 interrupt-parent = <&irq>;
527 interrupts = <4 0>;
Simon Glass0ccb0972015-01-25 08:27:05 -0700528 compatible = "denx,u-boot-fdt-test";
529 };
530
531 g-test {
532 compatible = "denx,u-boot-fdt-test";
533 };
534
Bin Mengd9d24782018-10-10 22:07:01 -0700535 h-test {
536 compatible = "denx,u-boot-fdt-test1";
537 };
538
developercf8bc132020-05-02 11:35:10 +0200539 i-test {
540 compatible = "mediatek,u-boot-fdt-test";
541 #address-cells = <1>;
542 #size-cells = <0>;
543
544 subnode@0 {
545 reg = <0>;
546 };
547
548 subnode@1 {
549 reg = <1>;
550 };
551
552 subnode@2 {
553 reg = <2>;
554 };
555 };
556
Simon Glass204675c2019-12-29 21:19:25 -0700557 devres-test {
558 compatible = "denx,u-boot-devres-test";
559 };
560
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530561 another-test {
562 reg = <0 2>;
563 compatible = "denx,u-boot-fdt-test";
564 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
565 test5-gpios = <&gpio_a 19>;
566 };
567
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100568 mmio-bus@0 {
569 #address-cells = <1>;
570 #size-cells = <1>;
571 compatible = "denx,u-boot-test-bus";
572 dma-ranges = <0x10000000 0x00000000 0x00040000>;
573
574 subnode@0 {
575 compatible = "denx,u-boot-fdt-test";
576 };
577 };
578
579 mmio-bus@1 {
580 #address-cells = <1>;
581 #size-cells = <1>;
582 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100583
584 subnode@0 {
585 compatible = "denx,u-boot-fdt-test";
586 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100587 };
588
Simon Glass3c601b12020-07-07 13:12:06 -0600589 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600590 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600591 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600592 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600593 child {
594 compatible = "denx,u-boot-acpi-test";
595 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600596 };
597
Simon Glass3c601b12020-07-07 13:12:06 -0600598 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600599 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600600 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600601 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600602 };
603
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200604 clocks {
605 clk_fixed: clk-fixed {
606 compatible = "fixed-clock";
607 #clock-cells = <0>;
608 clock-frequency = <1234>;
609 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000610
611 clk_fixed_factor: clk-fixed-factor {
612 compatible = "fixed-factor-clock";
613 #clock-cells = <0>;
614 clock-div = <3>;
615 clock-mult = <2>;
616 clocks = <&clk_fixed>;
617 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200618
619 osc {
620 compatible = "fixed-clock";
621 #clock-cells = <0>;
622 clock-frequency = <20000000>;
623 };
Stephen Warrena9622432016-06-17 09:44:00 -0600624 };
625
626 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600627 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600628 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200629 assigned-clocks = <&clk_sandbox 3>;
630 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600631 };
632
633 clk-test {
634 compatible = "sandbox,clk-test";
635 clocks = <&clk_fixed>,
636 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200637 <&clk_sandbox 0>,
Yang Xiwene89289c2023-12-16 02:28:52 +0800638 <&ccf 11>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200639 <&clk_sandbox 3>,
640 <&clk_sandbox 2>;
Yang Xiwene89289c2023-12-16 02:28:52 +0800641 clock-names = "fixed", "i2c", "spi", "i2c_root", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600642 };
643
Ashok Reddy Soma8f03cef2023-08-30 10:31:42 +0200644 clk-test2 {
645 compatible = "sandbox,clk-test";
646 assigned-clock-rates = <321>;
647 };
648
649 clk-test3 {
650 compatible = "sandbox,clk-test";
651 assigned-clocks = <&clk_sandbox 1>;
652 };
653
654 clk-test4 {
655 compatible = "sandbox,clk-test";
656 assigned-clock-rates = <654>, <321>;
657 assigned-clocks = <&clk_sandbox 1>;
658 };
659
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200660 ccf: clk-ccf {
661 compatible = "sandbox,clk-ccf";
Yang Xiwene89289c2023-12-16 02:28:52 +0800662 #clock-cells = <1>;
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200663 };
664
Simon Glass507ab962021-12-04 08:56:31 -0700665 efi-media {
666 compatible = "sandbox,efi-media";
667 };
668
Simon Glass5b968632015-05-22 15:42:15 -0600669 eth@10002000 {
670 compatible = "sandbox,eth";
671 reg = <0x10002000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600672 };
673
674 eth_5: eth@10003000 {
675 compatible = "sandbox,eth";
676 reg = <0x10003000 0x1000>;
Sean Anderson13652b82022-05-05 13:11:44 -0400677 nvmem-cells = <&eth5_addr>;
678 nvmem-cell-names = "mac-address";
Simon Glass5b968632015-05-22 15:42:15 -0600679 };
680
Bin Meng04a11cb2015-08-27 22:25:53 -0700681 eth_3: sbe5 {
682 compatible = "sandbox,eth";
683 reg = <0x10005000 0x1000>;
Sean Andersone2dc0e62022-05-05 13:11:42 -0400684 nvmem-cells = <&eth3_addr>;
685 nvmem-cell-names = "mac-address";
Bin Meng04a11cb2015-08-27 22:25:53 -0700686 };
687
Simon Glass5b968632015-05-22 15:42:15 -0600688 eth@10004000 {
689 compatible = "sandbox,eth";
690 reg = <0x10004000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600691 };
692
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200693 phy_eth0: phy-test-eth {
694 compatible = "sandbox,eth";
695 reg = <0x10007000 0x1000>;
Sean Anderson24b1b8d2022-05-05 13:11:35 -0400696 mac-address = [ 02 00 11 22 33 49 ];
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200697 phy-handle = <&ethphy1>;
Marek Behúnbc194772022-04-07 00:33:01 +0200698 phy-mode = "2500base-x";
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200699 };
700
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800701 dsa_eth0: dsa-test-eth {
702 compatible = "sandbox,eth";
703 reg = <0x10006000 0x1000>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400704 nvmem-cells = <&eth4_addr>;
705 nvmem-cell-names = "mac-address";
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800706 };
707
708 dsa-test {
709 compatible = "sandbox,dsa";
710
711 ports {
712 #address-cells = <1>;
713 #size-cells = <0>;
714 swp_0: port@0 {
715 reg = <0>;
716 label = "lan0";
717 phy-mode = "rgmii-rxid";
718
719 fixed-link {
720 speed = <100>;
721 full-duplex;
722 };
723 };
724
725 swp_1: port@1 {
726 reg = <1>;
727 label = "lan1";
728 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800729 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800730 };
731
732 port@2 {
733 reg = <2>;
734 ethernet = <&dsa_eth0>;
735
736 fixed-link {
737 speed = <1000>;
738 full-duplex;
739 };
740 };
741 };
742 };
743
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700744 firmware {
745 sandbox_firmware: sandbox-firmware {
746 compatible = "sandbox,firmware";
747 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200748
Etienne Carriere09665cb2022-02-21 09:22:39 +0100749 scmi {
Etienne Carriere02fd1262020-09-09 18:44:00 +0200750 compatible = "sandbox,scmi-agent";
751 #address-cells = <1>;
752 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200753
AKASHI Takahiro535a7bd2023-10-16 14:39:45 +0900754 pwrdom_scmi: protocol@11 {
755 reg = <0x11>;
756 #power-domain-cells = <1>;
757 };
758
Etienne Carriere09665cb2022-02-21 09:22:39 +0100759 clk_scmi: protocol@14 {
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200760 reg = <0x14>;
761 #clock-cells = <1>;
AKASHI Takahirocc4ecda2023-10-11 19:06:59 +0900762 linaro,sandbox-channel-id = <0x14>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200763 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200764
Etienne Carriere09665cb2022-02-21 09:22:39 +0100765 reset_scmi: protocol@16 {
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200766 reg = <0x16>;
767 #reset-cells = <1>;
768 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100769
770 protocol@17 {
771 reg = <0x17>;
772
773 regulators {
774 #address-cells = <1>;
775 #size-cells = <0>;
776
Etienne Carriere09665cb2022-02-21 09:22:39 +0100777 regul0_scmi: reg@0 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100778 reg = <0>;
779 regulator-name = "sandbox-voltd0";
780 regulator-min-microvolt = <1100000>;
781 regulator-max-microvolt = <3300000>;
782 };
Etienne Carriere09665cb2022-02-21 09:22:39 +0100783 regul1_scmi: reg@1 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100784 reg = <0x1>;
785 regulator-name = "sandbox-voltd1";
786 regulator-min-microvolt = <1800000>;
787 };
788 };
789 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200790 };
Alexey Romanov9dc617d2023-09-21 11:13:36 +0300791
792 sm: secure-monitor {
793 compatible = "sandbox,sm";
794 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700795 };
796
Alexander Dahl6ac319d2022-09-30 14:04:30 +0200797 fpga {
798 compatible = "sandbox,fpga";
799 };
800
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100801 pinctrl-gpio {
802 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700803
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100804 gpio_a: base-gpios {
805 compatible = "sandbox,gpio";
806 gpio-controller;
807 #gpio-cells = <1>;
808 gpio-bank-name = "a";
809 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200810 hog_input_active_low {
811 gpio-hog;
812 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200813 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200814 };
815 hog_input_active_high {
816 gpio-hog;
817 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200818 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200819 };
820 hog_output_low {
821 gpio-hog;
822 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200823 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200824 };
825 hog_output_high {
826 gpio-hog;
827 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200828 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200829 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100830 };
831
832 gpio_b: extra-gpios {
833 compatible = "sandbox,gpio";
834 gpio-controller;
835 #gpio-cells = <5>;
836 gpio-bank-name = "b";
837 sandbox,gpio-count = <10>;
838 };
Simon Glass25348a42014-10-13 23:42:11 -0600839
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100840 gpio_c: pinmux-gpios {
841 compatible = "sandbox,gpio";
842 gpio-controller;
843 #gpio-cells = <2>;
844 gpio-bank-name = "c";
845 sandbox,gpio-count = <10>;
846 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100847 };
848
Simon Glass7df766e2014-12-10 08:55:55 -0700849 i2c@0 {
850 #address-cells = <1>;
851 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600852 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700853 compatible = "sandbox,i2c";
854 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200855 pinctrl-names = "default";
856 pinctrl-0 = <&pinmux_i2c0_pins>;
857
Simon Glass7df766e2014-12-10 08:55:55 -0700858 eeprom@2c {
Sean Andersone2dc0e62022-05-05 13:11:42 -0400859 #address-cells = <1>;
860 #size-cells = <1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700861 reg = <0x2c>;
862 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700863 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200864 partitions {
865 compatible = "fixed-partitions";
866 #address-cells = <1>;
867 #size-cells = <1>;
868 bootcount_i2c: bootcount@10 {
869 reg = <10 2>;
870 };
871 };
Sean Andersone2dc0e62022-05-05 13:11:42 -0400872
873 eth3_addr: mac-address@24 {
874 reg = <24 6>;
875 };
Simon Glass7df766e2014-12-10 08:55:55 -0700876 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200877
Simon Glass336b2952015-05-22 15:42:17 -0600878 rtc_0: rtc@43 {
Sean Anderson5768e8b2022-05-05 13:11:43 -0400879 #address-cells = <1>;
880 #size-cells = <1>;
Simon Glass336b2952015-05-22 15:42:17 -0600881 reg = <0x43>;
882 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700883 sandbox,emul = <&emul0>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400884
885 eth4_addr: mac-address@40 {
886 reg = <0x40 6>;
887 };
Simon Glass336b2952015-05-22 15:42:17 -0600888 };
889
890 rtc_1: rtc@61 {
891 reg = <0x61>;
892 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700893 sandbox,emul = <&emul1>;
894 };
895
896 i2c_emul: emul {
897 reg = <0xff>;
898 compatible = "sandbox,i2c-emul-parent";
899 emul_eeprom: emul-eeprom {
900 compatible = "sandbox,i2c-eeprom";
901 sandbox,filename = "i2c.bin";
902 sandbox,size = <256>;
903 };
904 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700905 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700906 };
907 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700908 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600909 };
910 };
911
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200912 sandbox_pmic: sandbox_pmic {
913 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700914 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200915 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200916
917 mc34708: pmic@41 {
918 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700919 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200920 };
Simon Glass7df766e2014-12-10 08:55:55 -0700921 };
922
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100923 bootcount@0 {
924 compatible = "u-boot,bootcount-rtc";
925 rtc = <&rtc_1>;
926 offset = <0x13>;
927 };
928
Michal Simek4f18f922020-05-28 11:48:55 +0200929 bootcount {
930 compatible = "u-boot,bootcount-i2c-eeprom";
931 i2c-eeprom = <&bootcount_i2c>;
932 };
933
Nandor Han88895812021-06-10 15:40:38 +0300934 bootcount_4@0 {
935 compatible = "u-boot,bootcount-syscon";
936 syscon = <&syscon0>;
937 reg = <0x0 0x04>, <0x0 0x04>;
938 reg-names = "syscon_reg", "offset";
939 };
940
941 bootcount_2@0 {
942 compatible = "u-boot,bootcount-syscon";
943 syscon = <&syscon0>;
944 reg = <0x0 0x04>, <0x0 0x02> ;
945 reg-names = "syscon_reg", "offset";
946 };
947
Marek Szyprowskiad398592021-02-18 11:33:18 +0100948 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100949 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100950 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100951 vdd-supply = <&buck2>;
952 vss-microvolts = <0>;
953 };
954
Mark Kettenis67748ee2021-10-23 16:58:02 +0200955 iommu: iommu@0 {
956 compatible = "sandbox,iommu";
957 #iommu-cells = <0>;
958 };
959
Simon Glass515dcff2020-02-06 09:55:00 -0700960 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700961 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700962 interrupt-controller;
963 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700964 };
965
Simon Glass90b6fef2016-01-18 19:52:26 -0700966 lcd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700967 bootph-all;
Simon Glass90b6fef2016-01-18 19:52:26 -0700968 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200969 pinctrl-names = "default";
970 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700971 xres = <1366>;
972 yres = <768>;
973 };
974
Simon Glassd783eb32015-07-06 12:54:34 -0600975 leds {
976 compatible = "gpio-leds";
977
978 iracibble {
979 gpios = <&gpio_a 1 0>;
980 label = "sandbox:red";
981 };
982
983 martinet {
984 gpios = <&gpio_a 2 0>;
985 label = "sandbox:green";
986 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200987
988 default_on {
989 gpios = <&gpio_a 5 0>;
990 label = "sandbox:default_on";
991 default-state = "on";
992 };
993
994 default_off {
995 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400996 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200997 default-state = "off";
998 };
Simon Glassd783eb32015-07-06 12:54:34 -0600999 };
1000
Paul Doelle709f0372022-07-04 09:00:25 +00001001 wdt-gpio-toggle {
Simon Glasse0f8cd22023-08-10 09:53:13 -06001002 gpios = <&gpio_a 8 0>;
Rasmus Villemoes2b673872021-08-19 11:57:05 +02001003 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001004 hw_margin_ms = <100>;
Paul Doelle709f0372022-07-04 09:00:25 +00001005 hw_algo = "toggle";
1006 always-running;
1007 };
1008
1009 wdt-gpio-level {
1010 gpios = <&gpio_a 7 0>;
1011 compatible = "linux,wdt-gpio";
1012 hw_margin_ms = <100>;
1013 hw_algo = "level";
Rasmus Villemoes2b673872021-08-19 11:57:05 +02001014 always-running;
1015 };
1016
Stephen Warren62f2c902016-05-16 17:41:37 -06001017 mbox: mbox {
1018 compatible = "sandbox,mbox";
1019 #mbox-cells = <1>;
1020 };
1021
1022 mbox-test {
1023 compatible = "sandbox,mbox-test";
1024 mboxes = <&mbox 100>, <&mbox 1>;
1025 mbox-names = "other", "test";
1026 };
1027
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001028 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001029 #address-cells = <1>;
1030 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -04001031 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001032 cpu1: cpu@1 {
1033 device_type = "cpu";
1034 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -04001035 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001036 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001037 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001038 };
Mario Sixdea5df72018-08-06 10:23:44 +02001039
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001040 cpu2: cpu@2 {
1041 device_type = "cpu";
1042 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001043 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001044 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001045 };
Mario Sixdea5df72018-08-06 10:23:44 +02001046
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001047 cpu3: cpu@3 {
1048 device_type = "cpu";
1049 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001050 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001051 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001052 };
Mario Sixdea5df72018-08-06 10:23:44 +02001053 };
1054
Dave Gerlach75dbdfc2020-07-15 23:39:58 -05001055 chipid: chipid {
1056 compatible = "sandbox,soc";
1057 };
1058
Simon Glassc953aaf2018-12-10 10:37:34 -07001059 i2s: i2s {
1060 compatible = "sandbox,i2s";
1061 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -07001062 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -07001063 };
1064
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +02001065 nop-test_0 {
1066 compatible = "sandbox,nop_sandbox1";
1067 nop-test_1 {
1068 compatible = "sandbox,nop_sandbox2";
1069 bind = "True";
1070 };
1071 nop-test_2 {
1072 compatible = "sandbox,nop_sandbox2";
1073 bind = "False";
1074 };
1075 };
1076
Roger Quadrosb0679a72022-10-20 16:30:46 +03001077 memory-controller {
1078 compatible = "sandbox,memory";
1079 };
1080
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001081 misc-test {
Sean Anderson13652b82022-05-05 13:11:44 -04001082 #address-cells = <1>;
1083 #size-cells = <1>;
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001084 compatible = "sandbox,misc_sandbox";
Sean Anderson13652b82022-05-05 13:11:44 -04001085
1086 eth5_addr: mac-address@10 {
1087 reg = <0x10 6>;
1088 };
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001089 };
1090
Simon Glasse4fef742017-04-23 20:02:07 -06001091 mmc2 {
1092 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -06001093 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -06001094 };
1095
Simon Glassb255efc2022-04-24 23:31:24 -06001096 /* This is used for the bootdev tests */
Simon Glasse4fef742017-04-23 20:02:07 -06001097 mmc1 {
1098 compatible = "sandbox,mmc";
Simon Glassb255efc2022-04-24 23:31:24 -06001099 filename = "mmc1.img";
Simon Glasse4fef742017-04-23 20:02:07 -06001100 };
1101
Simon Glassb255efc2022-04-24 23:31:24 -06001102 /* This is used for the fastboot tests */
Sughosh Ganu77079e72022-10-21 18:16:05 +05301103 mmc0: mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -06001104 compatible = "sandbox,mmc";
1105 };
1106
Simon Glassf1eba352022-10-20 18:23:20 -06001107 /* This is used for VBE VPL tests */
1108 mmc3 {
1109 status = "disabled";
1110 compatible = "sandbox,mmc";
1111 filename = "image.bin";
1112 non-removable;
1113 };
1114
Simon Glassd2bc33ed2023-01-06 08:52:41 -06001115 /* This is used for bootstd bootmenu tests */
1116 mmc4 {
1117 status = "disabled";
1118 compatible = "sandbox,mmc";
1119 filename = "mmc4.img";
1120 };
1121
Simon Glassfff928c2023-08-24 13:55:41 -06001122 /* This is used for ChromiumOS tests */
1123 mmc5 {
1124 status = "disabled";
1125 compatible = "sandbox,mmc";
1126 filename = "mmc5.img";
1127 };
1128
Alexander Gendin038cb022023-10-09 01:24:36 +00001129 /* This is used for mbr tests */
1130 mmc6 {
1131 status = "disabled";
1132 compatible = "sandbox,mmc";
1133 filename = "mmc6.img";
1134 };
1135
Mattijs Korpershoekd77f8152024-07-10 10:40:06 +02001136 /* This is used for Android tests */
1137 mmc7 {
1138 status = "disabled";
1139 compatible = "sandbox,mmc";
1140 filename = "mmc7.img";
1141 };
1142
Simon Glass53a68b32019-02-16 20:24:50 -07001143 pch {
1144 compatible = "sandbox,pch";
1145 };
1146
Tom Rini4a3ca482020-02-11 12:41:23 -05001147 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -07001148 compatible = "sandbox,pci";
1149 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001150 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001151 #address-cells = <3>;
1152 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -06001153 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -07001154 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Mark Kettenis5dfd4ec2023-01-21 20:27:57 +01001155 iommu-map = <0x0010 &iommu 0 1>;
1156 iommu-map-mask = <0xfffffff8>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001157 pci@0,0 {
1158 compatible = "pci-generic";
1159 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001160 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001161 };
Alex Margineanf1274432019-06-07 11:24:24 +03001162 pci@1,0 {
1163 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001164 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
Simon Glass4289c262023-09-26 08:14:58 -06001165 reg = <0x02000814 0 0 0x80 0
1166 0x01000810 0 0 0xc0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001167 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +03001168 };
Simon Glass937bb472019-12-06 21:41:57 -07001169 p2sb-pci@2,0 {
1170 compatible = "sandbox,p2sb";
1171 reg = <0x02001010 0 0 0 0>;
1172 sandbox,emul = <&p2sb_emul>;
1173
1174 adder {
1175 intel,p2sb-port-id = <3>;
1176 compatible = "sandbox,adder";
1177 };
1178 };
Simon Glass8c501022019-12-06 21:41:54 -07001179 pci@1e,0 {
1180 compatible = "sandbox,pmc";
1181 reg = <0xf000 0 0 0 0>;
1182 sandbox,emul = <&pmc_emul1e>;
1183 acpi-base = <0x400>;
1184 gpe0-dwx-mask = <0xf>;
1185 gpe0-dwx-shift-base = <4>;
1186 gpe0-dw = <6 7 9>;
1187 gpe0-sts = <0x20>;
1188 gpe0-en = <0x30>;
1189 };
Simon Glass3a6eae62015-03-05 12:25:34 -07001190 pci@1f,0 {
1191 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001192 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
Simon Glass4289c262023-09-26 08:14:58 -06001193 reg = <0x0100f810 0 0 0x100 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001194 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001195 };
1196 };
1197
Simon Glassb98ba4c2019-09-25 08:56:10 -06001198 pci-emul0 {
1199 compatible = "sandbox,pci-emul-parent";
1200 swap_case_emul0_0: emul0@0,0 {
1201 compatible = "sandbox,swap-case";
1202 };
1203 swap_case_emul0_1: emul0@1,0 {
1204 compatible = "sandbox,swap-case";
1205 use-ea;
1206 };
1207 swap_case_emul0_1f: emul0@1f,0 {
1208 compatible = "sandbox,swap-case";
1209 };
Simon Glass937bb472019-12-06 21:41:57 -07001210 p2sb_emul: emul@2,0 {
1211 compatible = "sandbox,p2sb-emul";
1212 };
Simon Glass8c501022019-12-06 21:41:54 -07001213 pmc_emul1e: emul@1e,0 {
1214 compatible = "sandbox,pmc-emul";
1215 };
Simon Glassb98ba4c2019-09-25 08:56:10 -06001216 };
1217
Tom Rini4a3ca482020-02-11 12:41:23 -05001218 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -07001219 compatible = "sandbox,pci";
1220 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001221 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -07001222 #address-cells = <3>;
1223 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001224 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scullc7456a42022-04-21 16:11:09 +00001225 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001226 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -07001227 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +02001228 0x0c 0x00 0x1234 0x5678
1229 0x10 0x00 0x1234 0x5678>;
1230 pci@10,0 {
1231 reg = <0x8000 0 0 0 0>;
1232 };
Bin Meng408e5902018-08-03 01:14:41 -07001233 };
1234
Tom Rini4a3ca482020-02-11 12:41:23 -05001235 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -07001236 compatible = "sandbox,pci";
1237 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001238 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -07001239 #address-cells = <3>;
1240 #size-cells = <2>;
1241 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1242 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1243 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1244 pci@1f,0 {
1245 compatible = "pci-generic";
1246 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001247 sandbox,emul = <&swap_case_emul2_1f>;
1248 };
1249 };
1250
1251 pci-emul2 {
1252 compatible = "sandbox,pci-emul-parent";
1253 swap_case_emul2_1f: emul2@1f,0 {
1254 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001255 };
1256 };
1257
Ramon Friedc64f19b2019-04-27 11:15:23 +03001258 pci_ep: pci_ep {
1259 compatible = "sandbox,pci_ep";
1260 };
1261
Simon Glass9c433fe2017-04-23 20:10:44 -06001262 probing {
1263 compatible = "simple-bus";
1264 test1 {
1265 compatible = "denx,u-boot-probe-test";
1266 };
1267
1268 test2 {
1269 compatible = "denx,u-boot-probe-test";
1270 };
1271
1272 test3 {
1273 compatible = "denx,u-boot-probe-test";
1274 };
1275
1276 test4 {
1277 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001278 first-syscon = <&syscon0>;
1279 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001280 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001281 };
1282 };
1283
Stephen Warren92c67fa2016-07-13 13:45:31 -06001284 pwrdom: power-domain {
1285 compatible = "sandbox,power-domain";
1286 #power-domain-cells = <1>;
1287 };
1288
1289 power-domain-test {
1290 compatible = "sandbox,power-domain-test";
1291 power-domains = <&pwrdom 2>;
1292 };
1293
Simon Glass5620cf82018-10-01 12:22:40 -06001294 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001295 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001296 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001297 pinctrl-names = "default";
1298 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001299 };
1300
1301 pwm2 {
1302 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001303 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001304 };
1305
Simon Glass3d355e62015-07-06 12:54:31 -06001306 ram {
1307 compatible = "sandbox,ram";
1308 };
1309
Simon Glassd860f222015-07-06 12:54:29 -06001310 reset@0 {
1311 compatible = "sandbox,warm-reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001312 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001313 };
1314
1315 reset@1 {
1316 compatible = "sandbox,reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001317 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001318 };
1319
Stephen Warren6488e642016-06-17 09:43:59 -06001320 resetc: reset-ctl {
1321 compatible = "sandbox,reset-ctl";
1322 #reset-cells = <1>;
1323 };
1324
1325 reset-ctl-test {
1326 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001327 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1328 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001329 };
1330
Sughosh Ganu23e37512019-12-28 23:58:31 +05301331 rng {
1332 compatible = "sandbox,sandbox-rng";
1333 };
1334
Nishanth Menonedf85812015-09-17 15:42:41 -05001335 rproc_1: rproc@1 {
1336 compatible = "sandbox,test-processor";
1337 remoteproc-name = "remoteproc-test-dev1";
1338 };
1339
1340 rproc_2: rproc@2 {
1341 compatible = "sandbox,test-processor";
1342 internal-memory-mapped;
1343 remoteproc-name = "remoteproc-test-dev2";
1344 };
1345
Simon Glass5620cf82018-10-01 12:22:40 -06001346 panel {
1347 compatible = "simple-panel";
1348 backlight = <&backlight 0 100>;
1349 };
1350
Simon Glass509f32e2022-09-21 16:21:47 +02001351 scsi {
1352 compatible = "sandbox,scsi";
1353 sandbox,filepath = "scsi.img";
1354 };
1355
Ramon Fried26ed32e2018-07-02 02:57:59 +03001356 smem@0 {
1357 compatible = "sandbox,smem";
1358 };
1359
Simon Glass76072ac2018-12-10 10:37:36 -07001360 sound {
1361 compatible = "sandbox,sound";
1362 cpu {
1363 sound-dai = <&i2s 0>;
1364 };
1365
1366 codec {
1367 sound-dai = <&audio 0>;
1368 };
1369 };
1370
Simon Glass25348a42014-10-13 23:42:11 -06001371 spi@0 {
1372 #address-cells = <1>;
1373 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001374 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001375 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001376 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001377 pinctrl-names = "default";
1378 pinctrl-0 = <&pinmux_spi0_pins>;
1379
Simon Glass25348a42014-10-13 23:42:11 -06001380 spi.bin@0 {
1381 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001382 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001383 spi-max-frequency = <40000000>;
1384 sandbox,filename = "spi.bin";
1385 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001386 spi.bin@1 {
1387 reg = <1>;
1388 compatible = "spansion,m25p16", "jedec,spi-nor";
1389 spi-max-frequency = <50000000>;
1390 sandbox,filename = "spi.bin";
1391 spi-cpol;
1392 spi-cpha;
1393 };
Simon Glass25348a42014-10-13 23:42:11 -06001394 };
1395
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001396 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001397 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001398 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001399 };
1400
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001401 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001402 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001403 reg = <0x20 5
1404 0x28 6
1405 0x30 7
1406 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001407 };
1408
Patrick Delaunayee010432019-03-07 09:57:13 +01001409 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001410 compatible = "simple-mfd", "syscon";
1411 reg = <0x40 5
1412 0x48 6
1413 0x50 7
1414 0x58 8>;
1415 };
1416
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301417 syscon3: syscon@3 {
1418 compatible = "simple-mfd", "syscon";
1419 reg = <0x000100 0x10>;
1420
1421 muxcontroller0: a-mux-controller {
1422 compatible = "mmio-mux";
1423 #mux-control-cells = <1>;
1424
1425 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1426 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1427 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1428 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1429 u-boot,mux-autoprobe;
1430 };
1431 };
1432
1433 muxcontroller1: emul-mux-controller {
1434 compatible = "mux-emul";
1435 #mux-control-cells = <0>;
1436 u-boot,mux-autoprobe;
1437 idle-state = <0xabcd>;
1438 };
1439
Simon Glass791a17f2020-12-16 21:20:27 -07001440 testfdtm0 {
1441 compatible = "denx,u-boot-fdtm-test";
1442 };
1443
1444 testfdtm1: testfdtm1 {
1445 compatible = "denx,u-boot-fdtm-test";
1446 };
1447
1448 testfdtm2 {
1449 compatible = "denx,u-boot-fdtm-test";
1450 };
1451
Sean Anderson79d3bba2020-09-28 10:52:23 -04001452 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001453 compatible = "sandbox,timer";
1454 clock-frequency = <1000000>;
1455 };
1456
Sean Anderson79d3bba2020-09-28 10:52:23 -04001457 timer@1 {
1458 compatible = "sandbox,timer";
1459 sandbox,timebase-frequency-fallback;
1460 };
1461
Miquel Raynal80938c12018-05-15 11:57:27 +02001462 tpm2 {
1463 compatible = "sandbox,tpm2";
Eddie James1a55a7a2023-10-24 10:43:51 -05001464 memory-region = <&event_log>;
Miquel Raynal80938c12018-05-15 11:57:27 +02001465 };
1466
Simon Glasseef107e2023-02-21 06:24:51 -07001467 tpm {
1468 compatible = "google,sandbox-tpm";
1469 };
1470
Simon Glass5b968632015-05-22 15:42:15 -06001471 uart0: serial {
1472 compatible = "sandbox,serial";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001473 bootph-all;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001474 pinctrl-names = "default";
1475 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001476 };
1477
Simon Glass31680482015-03-25 12:23:05 -06001478 usb_0: usb@0 {
1479 compatible = "sandbox,usb";
1480 status = "disabled";
1481 hub {
1482 compatible = "sandbox,usb-hub";
1483 #address-cells = <1>;
1484 #size-cells = <0>;
1485 flash-stick {
1486 reg = <0>;
1487 compatible = "sandbox,usb-flash";
1488 };
1489 };
1490 };
1491
1492 usb_1: usb@1 {
1493 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001494 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001495 hub {
1496 compatible = "usb-hub";
1497 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001498 #address-cells = <1>;
1499 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001500 hub-emul {
1501 compatible = "sandbox,usb-hub";
1502 #address-cells = <1>;
1503 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001504 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001505 reg = <0>;
1506 compatible = "sandbox,usb-flash";
1507 sandbox,filepath = "testflash.bin";
1508 };
1509
Simon Glass4700fe52015-11-08 23:48:01 -07001510 flash-stick@1 {
1511 reg = <1>;
1512 compatible = "sandbox,usb-flash";
1513 sandbox,filepath = "testflash1.bin";
1514 };
1515
1516 flash-stick@2 {
1517 reg = <2>;
1518 compatible = "sandbox,usb-flash";
1519 sandbox,filepath = "testflash2.bin";
1520 };
1521
Simon Glassc0ccc722015-11-08 23:48:08 -07001522 keyb@3 {
1523 reg = <3>;
1524 compatible = "sandbox,usb-keyb";
1525 };
1526
Simon Glass31680482015-03-25 12:23:05 -06001527 };
Michael Walle7c961322020-06-02 01:47:07 +02001528
1529 usbstor@1 {
1530 reg = <1>;
1531 };
1532 usbstor@3 {
1533 reg = <3>;
1534 };
Simon Glass31680482015-03-25 12:23:05 -06001535 };
1536 };
1537
1538 usb_2: usb@2 {
1539 compatible = "sandbox,usb";
1540 status = "disabled";
1541 };
1542
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001543 spmi: spmi@0 {
1544 compatible = "sandbox,spmi";
1545 #address-cells = <0x1>;
1546 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001547 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001548 pm8916@0 {
1549 compatible = "qcom,spmi-pmic";
1550 reg = <0x0 0x1>;
1551 #address-cells = <0x1>;
1552 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001553 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001554
1555 spmi_gpios: gpios@c000 {
1556 compatible = "qcom,pm8916-gpio";
1557 reg = <0xc000 0x400>;
Caleb Connolly1edc45f2024-01-08 15:30:51 +00001558 gpio-ranges = <&spmi_gpios 0 0 4>;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001559 gpio-controller;
1560 gpio-count = <4>;
1561 #gpio-cells = <2>;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001562 };
1563 };
1564 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001565
1566 wdt0: wdt@0 {
1567 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001568 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001569 };
Rob Clarka471b672018-01-10 11:33:30 +01001570
Mario Six95922152018-08-09 14:51:19 +02001571 axi: axi@0 {
1572 compatible = "sandbox,axi";
1573 #address-cells = <0x1>;
1574 #size-cells = <0x1>;
1575 store@0 {
1576 compatible = "sandbox,sandbox_store";
1577 reg = <0x0 0x400>;
1578 };
1579 };
1580
Rob Clarka471b672018-01-10 11:33:30 +01001581 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001582 #address-cells = <1>;
1583 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001584 setting = "sunrise ohoka";
1585 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001586 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001587 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Algapally Santosh Sagardf178992023-09-21 16:50:43 +05301588 stdout-path = "serial0:115200n8";
Rob Clarka471b672018-01-10 11:33:30 +01001589 chosen-test {
1590 compatible = "denx,u-boot-fdt-test";
1591 reg = <9 1>;
1592 };
1593 };
Mario Six35616ef2018-03-12 14:53:33 +01001594
1595 translation-test@8000 {
1596 compatible = "simple-bus";
1597 reg = <0x8000 0x4000>;
1598
1599 #address-cells = <0x2>;
1600 #size-cells = <0x1>;
1601
1602 ranges = <0 0x0 0x8000 0x1000
1603 1 0x100 0x9000 0x1000
1604 2 0x200 0xA000 0x1000
1605 3 0x300 0xB000 0x1000
1606 >;
1607
Fabien Dessenne22236e02019-05-31 15:11:30 +02001608 dma-ranges = <0 0x000 0x10000000 0x1000
1609 1 0x100 0x20000000 0x1000
1610 >;
1611
Mario Six35616ef2018-03-12 14:53:33 +01001612 dev@0,0 {
1613 compatible = "denx,u-boot-fdt-dummy";
1614 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +01001615 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001616 };
1617
1618 dev@1,100 {
1619 compatible = "denx,u-boot-fdt-dummy";
1620 reg = <1 0x100 0x1000>;
1621
1622 };
1623
1624 dev@2,200 {
1625 compatible = "denx,u-boot-fdt-dummy";
1626 reg = <2 0x200 0x1000>;
1627 };
1628
1629
1630 noxlatebus@3,300 {
1631 compatible = "simple-bus";
1632 reg = <3 0x300 0x1000>;
1633
1634 #address-cells = <0x1>;
1635 #size-cells = <0x0>;
1636
1637 dev@42 {
1638 compatible = "denx,u-boot-fdt-dummy";
1639 reg = <0x42>;
1640 };
1641 };
1642 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001643
Dzmitry Sankouski54f4c832023-01-22 18:21:23 +03001644 ofnode-foreach {
1645 compatible = "foreach";
1646
1647 first {
1648 prop1 = <1>;
1649 prop2 = <2>;
1650 };
1651
1652 second {
1653 prop1 = <1>;
1654 prop2 = <2>;
1655 };
1656 };
1657
Mario Six02ad6fb2018-09-27 09:19:31 +02001658 osd {
1659 compatible = "sandbox,sandbox_osd";
1660 };
Tom Rinib93eea72018-09-30 18:16:51 -04001661
Jens Wiklander86afaa62018-09-25 16:40:16 +02001662 sandbox_tee {
1663 compatible = "sandbox,tee";
1664 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001665
1666 sandbox_virtio1 {
1667 compatible = "sandbox,virtio1";
Simon Glass8de5a542023-01-17 10:47:51 -07001668 virtio-type = <4>; /* rng */
Bin Meng1bb290d2018-10-15 02:21:26 -07001669 };
1670
1671 sandbox_virtio2 {
1672 compatible = "sandbox,virtio2";
1673 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001674
Simon Glass8de5a542023-01-17 10:47:51 -07001675 sandbox-virtio-blk {
1676 compatible = "sandbox,virtio1";
1677 virtio-type = <2>; /* block */
1678 };
1679
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001680 sandbox_scmi {
1681 compatible = "sandbox,scmi-devices";
AKASHI Takahiro535a7bd2023-10-16 14:39:45 +09001682 power-domains = <&pwrdom_scmi 2>;
Etienne Carrierebf1f1322022-02-21 09:22:41 +01001683 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere09665cb2022-02-21 09:22:39 +01001684 resets = <&reset_scmi 3>;
1685 regul0-supply = <&regul0_scmi>;
1686 regul1-supply = <&regul1_scmi>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001687 };
1688
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001689 pinctrl {
1690 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001691
Sean Anderson3438e3b2020-09-14 11:01:57 -04001692 pinctrl-names = "default", "alternate";
1693 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1694 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001695
Sean Anderson3438e3b2020-09-14 11:01:57 -04001696 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001697 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001698 pins = "P5";
1699 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001700 bias-pull-up;
1701 input-disable;
1702 };
1703 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001704 pins = "P6";
1705 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001706 output-high;
1707 drive-open-drain;
1708 };
1709 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001710 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001711 bias-pull-down;
1712 input-enable;
1713 };
1714 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001715 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001716 bias-disable;
1717 };
1718 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001719
1720 pinctrl_i2c: i2c {
1721 groups {
1722 groups = "I2C_UART";
1723 function = "I2C";
1724 };
1725
1726 pins {
1727 pins = "P0", "P1";
1728 drive-open-drain;
1729 };
1730 };
1731
1732 pinctrl_i2s: i2s {
1733 groups = "SPI_I2S";
1734 function = "I2S";
1735 };
1736
1737 pinctrl_spi: spi {
1738 groups = "SPI_I2S";
1739 function = "SPI";
1740
1741 cs {
1742 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1743 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1744 };
1745 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001746 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001747
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001748 pinctrl-single-no-width {
1749 compatible = "pinctrl-single";
1750 reg = <0x0000 0x238>;
1751 #pinctrl-cells = <1>;
1752 pinctrl-single,function-mask = <0x7f>;
1753 };
1754
1755 pinctrl-single-pins {
1756 compatible = "pinctrl-single";
1757 reg = <0x0000 0x238>;
1758 #pinctrl-cells = <1>;
1759 pinctrl-single,register-width = <32>;
1760 pinctrl-single,function-mask = <0x7f>;
1761
1762 pinmux_pwm_pins: pinmux_pwm_pins {
1763 pinctrl-single,pins = < 0x48 0x06 >;
1764 };
1765
1766 pinmux_spi0_pins: pinmux_spi0_pins {
1767 pinctrl-single,pins = <
1768 0x190 0x0c
1769 0x194 0x0c
1770 0x198 0x23
1771 0x19c 0x0c
1772 >;
1773 };
1774
1775 pinmux_uart0_pins: pinmux_uart0_pins {
1776 pinctrl-single,pins = <
1777 0x70 0x30
1778 0x74 0x00
1779 >;
1780 };
1781 };
1782
1783 pinctrl-single-bits {
1784 compatible = "pinctrl-single";
1785 reg = <0x0000 0x50>;
1786 #pinctrl-cells = <2>;
1787 pinctrl-single,bit-per-mux;
1788 pinctrl-single,register-width = <32>;
1789 pinctrl-single,function-mask = <0xf>;
1790
1791 pinmux_i2c0_pins: pinmux_i2c0_pins {
1792 pinctrl-single,bits = <
1793 0x10 0x00002200 0x0000ff00
1794 >;
1795 };
1796
1797 pinmux_lcd_pins: pinmux_lcd_pins {
1798 pinctrl-single,bits = <
1799 0x40 0x22222200 0xffffff00
1800 0x44 0x22222222 0xffffffff
1801 0x48 0x00000022 0x000000ff
1802 0x48 0x02000000 0x0f000000
1803 0x4c 0x02000022 0x0f0000ff
1804 >;
1805 };
1806 };
1807
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001808 hwspinlock@0 {
1809 compatible = "sandbox,hwspinlock";
1810 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001811
1812 dma: dma {
1813 compatible = "sandbox,dma";
1814 #dma-cells = <1>;
1815
1816 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1817 dma-names = "m2m", "tx0", "rx0";
1818 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001819
Alex Marginean0649be52019-07-12 10:13:53 +03001820 /*
1821 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1822 * end of the test. If parent mdio is removed first, clean-up of the
1823 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1824 * active at the end of the test. That it turn doesn't allow the mdio
1825 * class to be destroyed, triggering an error.
1826 */
1827 mdio-mux-test {
1828 compatible = "sandbox,mdio-mux";
1829 #address-cells = <1>;
1830 #size-cells = <0>;
1831 mdio-parent-bus = <&mdio>;
1832
1833 mdio-ch-test@0 {
1834 reg = <0>;
1835 };
1836 mdio-ch-test@1 {
1837 reg = <1>;
1838 };
1839 };
1840
1841 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001842 compatible = "sandbox,mdio";
Marek Behúnf4f1ddc2022-04-07 00:32:57 +02001843 #address-cells = <1>;
1844 #size-cells = <0>;
1845
1846 ethphy1: ethernet-phy@1 {
1847 reg = <1>;
1848 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001849 };
Sean Andersonb7860542020-06-24 06:41:12 -04001850
1851 pm-bus-test {
1852 compatible = "simple-pm-bus";
1853 clocks = <&clk_sandbox 4>;
1854 power-domains = <&pwrdom 1>;
1855 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001856
1857 resetc2: syscon-reset {
1858 compatible = "syscon-reset";
1859 #reset-cells = <1>;
1860 regmap = <&syscon0>;
1861 offset = <1>;
1862 mask = <0x27FFFFFF>;
1863 assert-high = <0>;
1864 };
1865
1866 syscon-reset-test {
1867 compatible = "sandbox,misc_sandbox";
1868 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1869 reset-names = "valid", "no_mask", "out_of_range";
1870 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301871
Simon Glass458b66a2020-11-05 06:32:05 -07001872 sysinfo {
1873 compatible = "sandbox,sysinfo-sandbox";
1874 };
1875
Sean Anderson1c830672021-04-20 10:50:58 -04001876 sysinfo-gpio {
1877 compatible = "gpio-sysinfo";
1878 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1879 revisions = <19>, <5>;
1880 names = "rev_a", "foo";
1881 };
1882
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301883 some_regmapped-bus {
1884 #address-cells = <0x1>;
1885 #size-cells = <0x1>;
1886
1887 ranges = <0x0 0x0 0x10>;
1888 compatible = "simple-bus";
1889
1890 regmap-test_0 {
1891 reg = <0 0x10>;
1892 compatible = "sandbox,regmap_test";
1893 };
1894 };
Robert Marko9cf87122022-09-06 13:30:35 +02001895
1896 thermal {
1897 compatible = "sandbox,thermal";
1898 };
Sughosh Ganu77079e72022-10-21 18:16:05 +05301899
1900 fwu-mdata {
1901 compatible = "u-boot,fwu-mdata-gpt";
1902 fwu-mdata-store = <&mmc0>;
1903 };
Abdellatif El Khlifi6b005872023-04-17 10:11:55 +01001904
1905 nvmxip-qspi1@08000000 {
1906 compatible = "nvmxip,qspi";
1907 reg = <0x08000000 0x00200000>;
1908 lba_shift = <9>;
1909 lba = <4096>;
1910 };
1911
1912 nvmxip-qspi2@08200000 {
1913 compatible = "nvmxip,qspi";
1914 reg = <0x08200000 0x00100000>;
1915 lba_shift = <9>;
1916 lba = <2048>;
1917 };
Svyatoslav Ryhel669f5c82023-04-25 10:57:21 +03001918
1919 extcon {
1920 compatible = "sandbox,extcon";
1921 };
Abdellatif El Khlifi4970d5b2023-08-04 14:33:41 +01001922
1923 arm-ffa-emul {
1924 compatible = "sandbox,arm-ffa-emul";
1925
1926 sandbox-arm-ffa {
1927 compatible = "sandbox,arm-ffa";
1928 };
1929 };
Sean Anderson326422b2023-11-04 16:37:52 -04001930
1931 nand-controller {
1932 #address-cells = <1>;
1933 #size-cells = <0>;
1934 compatible = "sandbox,nand";
1935
1936 nand@0 {
1937 reg = <0>;
1938 nand-ecc-mode = "soft";
1939 sandbox,id = [00 e3];
1940 sandbox,erasesize = <(8 * 1024)>;
1941 sandbox,oobsize = <16>;
1942 sandbox,pagesize = <512>;
1943 sandbox,pages = <0x2000>;
1944 sandbox,err-count = <1>;
1945 sandbox,err-step-size = <512>;
1946 };
1947
1948 /* MT29F64G08AKABA */
1949 nand@1 {
1950 reg = <1>;
1951 nand-ecc-mode = "soft_bch";
1952 sandbox,id = [2C 48 00 26 89 00 00 00];
1953 sandbox,onfi = [
1954 4f 4e 46 49 0e 00 5a 00
1955 ff 01 00 00 00 00 03 00
1956 00 00 00 00 00 00 00 00
1957 00 00 00 00 00 00 00 00
1958 4d 49 43 52 4f 4e 20 20
1959 20 20 20 20 4d 54 32 39
1960 46 36 34 47 30 38 41 4b
1961 41 42 41 43 35 20 20 20
1962 2c 00 00 00 00 00 00 00
1963 00 00 00 00 00 00 00 00
1964 00 10 00 00 e0 00 00 02
1965 00 00 1c 00 80 00 00 00
1966 00 10 00 00 02 23 01 50
1967 00 01 05 01 00 00 04 00
1968 04 01 1e 00 00 00 00 00
1969 00 00 00 00 00 00 00 00
1970 0e 1f 00 1f 00 f4 01 ac
1971 0d 19 00 c8 00 00 00 00
1972 00 00 00 00 00 00 0a 07
1973 19 00 00 00 00 00 00 00
1974 00 00 00 00 01 00 01 00
1975 00 00 04 10 01 81 04 02
1976 02 01 1e 90 00 00 00 00
1977 00 00 00 00 00 00 00 00
1978 00 00 00 00 00 00 00 00
1979 00 00 00 00 00 00 00 00
1980 00 00 00 00 00 00 00 00
1981 00 00 00 00 00 00 00 00
1982 00 00 00 00 00 00 00 00
1983 00 00 00 00 00 00 00 00
1984 00 00 00 00 00 00 00 00
1985 00 00 00 00 00 03 20 7d
1986 ];
1987 sandbox,erasesize = <(512 * 1024)>;
1988 sandbox,oobsize = <224>;
1989 sandbox,pagesize = <4096>;
1990 sandbox,pages = <0x200000>;
1991 sandbox,err-count = <3>;
1992 sandbox,err-step-size = <512>;
1993 };
1994 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001995};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001996
1997#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001998#include "cros-ec-keyboard.dtsi"
Simon Glass5e135d32022-10-20 18:23:15 -06001999
2000#ifdef CONFIG_SANDBOX_VPL
2001#include "sandbox_vpl.dtsi"
2002#endif
Simon Glass61300722023-06-01 10:23:01 -06002003
Sughosh Ganu05137922024-03-27 16:19:00 +05302004#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
2005#include "sandbox_capsule.dtsi"
2006#endif
2007
Simon Glass61300722023-06-01 10:23:01 -06002008#include "cedit.dtsi"