blob: 6fd62fcdf8d718e8fc8b979f7666b5dc46083030 [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Eddie James1a55a7a2023-10-24 10:43:51 -050012#include <config.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010013#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010015#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040016#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053017#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010018
Simon Glassb2c1cac2014-02-26 15:59:21 -070019/ {
20 model = "sandbox";
21 compatible = "sandbox";
22 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060023 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070024
Simon Glassfef72b72014-07-23 06:55:03 -060025 aliases {
26 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010027 ethernet0 = "/eth@10002000";
28 ethernet2 = &swp_0;
29 ethernet3 = &eth_3;
30 ethernet4 = &dsa_eth0;
31 ethernet5 = &eth_5;
Sean Anderson67d93a42022-05-05 13:11:30 -040032 ethernet6 = "/eth@10004000";
33 ethernet7 = &swp_1;
34 ethernet8 = &phy_eth0;
Simon Glass5620cf82018-10-01 12:22:40 -060035 gpio1 = &gpio_a;
36 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010037 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070038 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060039 mmc0 = "/mmc0";
40 mmc1 = "/mmc1";
Simon Glassf1eba352022-10-20 18:23:20 -060041 mmc2 = "/mmc2";
42 mmc3 = "/mmc3";
Simon Glassfff928c2023-08-24 13:55:41 -060043 mmc4 = "/mmc4";
44 mmc5 = "/mmc5";
Alexander Gendin038cb022023-10-09 01:24:36 +000045 mmc6 = "/mmc6";
Bin Meng408e5902018-08-03 01:14:41 -070046 pci0 = &pci0;
47 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070048 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020049 remoteproc0 = &rproc_1;
50 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060051 rtc0 = &rtc_0;
52 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060053 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020054 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070055 testbus3 = "/some-bus";
56 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070057 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070058 testfdt3 = "/b-test";
59 testfdt5 = "/some-bus/c-test@5";
60 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070061 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020062 fdt-dummy0 = "/translation-test@8000/dev@0,0";
63 fdt-dummy1 = "/translation-test@8000/dev@1,100";
64 fdt-dummy2 = "/translation-test@8000/dev@2,200";
65 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060066 usb0 = &usb_0;
67 usb1 = &usb_1;
68 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020069 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020070 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060071 };
72
Eddie James1a55a7a2023-10-24 10:43:51 -050073 reserved-memory {
74 #address-cells = <1>;
75 #size-cells = <1>;
76 ranges;
77
78 event_log: tcg_event_log {
79 no-map;
80 reg = <(CFG_SYS_SDRAM_SIZE - 0x2000) 0x2000>;
81 };
82 };
83
Simon Glass5e135d32022-10-20 18:23:15 -060084 binman: binman {
Philippe Reynes462d1632022-03-28 22:56:53 +020085 };
86
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020087 config {
Simon Glass0034d962021-08-07 07:24:01 -060088 testing-bool;
89 testing-int = <123>;
90 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020091 environment {
92 from_fdt = "yes";
93 fdt_env_path = "";
94 };
95 };
96
Michal Simek43c42bd2023-08-31 08:59:05 +020097 options {
98 u-boot {
99 compatible = "u-boot,config";
100 bootscr-ram-offset = /bits/ 64 <0x12345678>;
Michal Simek6a7c1ce2023-08-31 09:04:27 +0200101 bootscr-flash-offset = /bits/ 64 <0>;
102 bootscr-flash-size = /bits/ 64 <0x2000>;
Michal Simek43c42bd2023-08-31 08:59:05 +0200103 };
104 };
105
Simon Glassb255efc2022-04-24 23:31:24 -0600106 bootstd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700107 bootph-verify;
Simon Glassb255efc2022-04-24 23:31:24 -0600108 compatible = "u-boot,boot-std";
109
110 filename-prefixes = "/", "/boot/";
111 bootdev-order = "mmc2", "mmc1";
112
Simon Glassb71d7f72023-05-10 16:34:46 -0600113 extlinux {
114 compatible = "u-boot,extlinux";
Simon Glassb255efc2022-04-24 23:31:24 -0600115 };
116
117 efi {
118 compatible = "u-boot,distro-efi";
119 };
Simon Glassa9289612022-10-20 18:23:14 -0600120
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600121 theme {
122 font-size = <30>;
Simon Glass86f1ac52023-06-01 10:23:00 -0600123 menu-inset = <3>;
124 menuitem-gap-y = <1>;
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600125 };
126
Simon Glass82adc292023-08-14 16:40:30 -0600127 cedit-theme {
128 font-size = <30>;
129 menu-inset = <3>;
130 menuitem-gap-y = <1>;
131 };
132
Simon Glassf1eba352022-10-20 18:23:20 -0600133 /*
134 * This is used for the VBE OS-request tests. A FAT filesystem
135 * created in a partition with the VBE information appearing
Michal Simek33224372023-09-07 14:55:48 +0200136 * before the partition starts
Simon Glassf1eba352022-10-20 18:23:20 -0600137 */
Simon Glassa9289612022-10-20 18:23:14 -0600138 firmware0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700139 bootph-verify;
Simon Glassa9289612022-10-20 18:23:14 -0600140 compatible = "fwupd,vbe-simple";
141 storage = "mmc1";
142 skip-offset = <0x200>;
143 area-start = <0x400>;
144 area-size = <0x1000>;
145 state-offset = <0x400>;
146 state-size = <0x40>;
147 version-offset = <0x800>;
148 version-size = <0x100>;
149 };
Simon Glassf1eba352022-10-20 18:23:20 -0600150
151 /*
152 * This is used for the VBE VPL tests. The MMC device holds the
153 * binman image.bin file. The test progresses through each phase
154 * of U-Boot, loading each in turn from MMC.
155 *
156 * Note that the test enables this node (and mmc3) before
157 * running U-Boot
158 */
159 firmware1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700160 bootph-verify;
Simon Glassf1eba352022-10-20 18:23:20 -0600161 status = "disabled";
162 compatible = "fwupd,vbe-simple";
163 storage = "mmc3";
Simon Glass9bb73e32023-04-02 14:01:24 +1200164 skip-offset = <0x800000>;
Simon Glassf1eba352022-10-20 18:23:20 -0600165 area-start = <0>;
166 area-size = <0xe00000>;
167 state-offset = <0xdffc00>;
168 state-size = <0x40>;
169 version-offset = <0xdffe00>;
170 version-size = <0x100>;
171 };
Simon Glassb255efc2022-04-24 23:31:24 -0600172 };
173
Simon Glass61300722023-06-01 10:23:01 -0600174 cedit: cedit {
175 };
176
Andrew Scull451b8b12022-05-30 10:00:12 +0000177 fuzzing-engine {
178 compatible = "sandbox,fuzzing-engine";
179 };
180
Nandor Han6521e5d2021-06-10 16:56:44 +0300181 reboot-mode0 {
182 compatible = "reboot-mode-gpio";
183 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
184 u-boot,env-variable = "bootstatus";
185 mode-test = <0x01>;
186 mode-download = <0x03>;
187 };
188
Nandor Han7e4067a2021-06-10 16:56:45 +0300189 reboot_mode1: reboot-mode@14 {
190 compatible = "reboot-mode-rtc";
191 rtc = <&rtc_0>;
192 reg = <0x30 4>;
193 u-boot,env-variable = "bootstatus";
194 big-endian;
195 mode-test = <0x21969147>;
196 mode-download = <0x51939147>;
197 };
198
Simon Glassed96cde2018-12-10 10:37:33 -0700199 audio: audio-codec {
200 compatible = "sandbox,audio-codec";
201 #sound-dai-cells = <1>;
202 };
203
Philippe Reynes1ee26482020-07-24 18:19:51 +0200204 buttons {
205 compatible = "gpio-keys";
206
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200207 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200208 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200209 label = "button1";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300210 linux,code = <BTN_1>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200211 };
212
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200213 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200214 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200215 label = "button2";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300216 linux,code = <BTN_2>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200217 };
218 };
219
Marek Szyprowskiad398592021-02-18 11:33:18 +0100220 buttons2 {
221 compatible = "adc-keys";
222 io-channels = <&adc 3>;
223 keyup-threshold-microvolt = <3000000>;
224
225 button-up {
226 label = "button3";
227 linux,code = <KEY_F3>;
228 press-threshold-microvolt = <1500000>;
229 };
230
231 button-down {
232 label = "button4";
233 linux,code = <KEY_F4>;
234 press-threshold-microvolt = <1000000>;
235 };
236
237 button-enter {
238 label = "button5";
239 linux,code = <KEY_F5>;
240 press-threshold-microvolt = <500000>;
241 };
242 };
243
Simon Glassc953aaf2018-12-10 10:37:34 -0700244 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600245 reg = <0 0>;
246 compatible = "google,cros-ec-sandbox";
247
248 /*
249 * This describes the flash memory within the EC. Note
250 * that the STM32L flash erases to 0, not 0xff.
251 */
252 flash {
253 image-pos = <0x08000000>;
254 size = <0x20000>;
255 erase-value = <0>;
256
257 /* Information for sandbox */
258 ro {
259 image-pos = <0>;
260 size = <0xf000>;
261 };
262 wp-ro {
263 image-pos = <0xf000>;
264 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700265 used = <0x884>;
266 compress = "lz4";
267 uncomp-size = <0xcf8>;
268 hash {
269 algo = "sha256";
270 value = [00 01 02 03 04 05 06 07
271 08 09 0a 0b 0c 0d 0e 0f
272 10 11 12 13 14 15 16 17
273 18 19 1a 1b 1c 1d 1e 1f];
274 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600275 };
276 rw {
277 image-pos = <0x10000>;
278 size = <0x10000>;
279 };
280 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300281
282 cros_ec_pwm: cros-ec-pwm {
283 compatible = "google,cros-ec-pwm";
284 #pwm-cells = <1>;
285 };
286
Simon Glass699c9ca2018-10-01 12:22:08 -0600287 };
288
Yannick Fertré9712c822019-10-07 15:29:05 +0200289 dsi_host: dsi_host {
290 compatible = "sandbox,dsi-host";
291 };
292
Simon Glassb2c1cac2014-02-26 15:59:21 -0700293 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600294 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700295 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600296 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700297 ping-add = <0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700298 bootph-all;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100299 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
300 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700301 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100302 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
303 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
304 <&gpio_b 7 GPIO_IN 3 2 1>,
305 <&gpio_b 8 GPIO_OUT 3 2 1>,
306 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100307 test3-gpios =
308 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
309 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
310 <&gpio_c 2 GPIO_OUT>,
311 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
312 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200313 <&gpio_c 5 GPIO_IN>,
314 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
315 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530316 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
317 test5-gpios = <&gpio_a 19>;
318
Simon Glass73025392021-10-23 17:26:04 -0600319 bool-value;
Stefan Herbrechtsmeier1b090e62022-06-14 15:21:30 +0200320 int8-value = /bits/ 8 <0x12>;
321 int16-value = /bits/ 16 <0x1234>;
Simon Glass6df01f92018-12-10 10:37:37 -0700322 int-value = <1234>;
323 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200324 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200325 int-array = <5678 9123 4567>;
Michal Simek08a194e2023-08-25 11:37:46 +0200326 int64-array = /bits/ 64 <0x1111222233334444 0x4444333322221111>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600327 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700328 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600329 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200330 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530331
332 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
333 <&muxcontroller0 2>, <&muxcontroller0 3>,
334 <&muxcontroller1>;
335 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
336 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100337 display-timings {
338 timing0: 240x320 {
339 clock-frequency = <6500000>;
340 hactive = <240>;
341 vactive = <320>;
342 hfront-porch = <6>;
343 hback-porch = <7>;
344 hsync-len = <1>;
345 vback-porch = <5>;
346 vfront-porch = <8>;
347 vsync-len = <2>;
348 hsync-active = <1>;
349 vsync-active = <0>;
350 de-active = <1>;
351 pixelclk-active = <1>;
352 interlaced;
353 doublescan;
354 doubleclk;
355 };
356 timing1: 480x800 {
357 clock-frequency = <9000000>;
358 hactive = <480>;
359 vactive = <800>;
360 hfront-porch = <10>;
361 hback-porch = <59>;
362 hsync-len = <12>;
363 vback-porch = <15>;
364 vfront-porch = <17>;
365 vsync-len = <16>;
366 hsync-active = <0>;
367 vsync-active = <1>;
368 de-active = <0>;
369 pixelclk-active = <0>;
370 };
371 timing2: 800x480 {
372 clock-frequency = <33500000>;
373 hactive = <800>;
374 vactive = <480>;
375 hback-porch = <89>;
376 hfront-porch = <164>;
377 vback-porch = <23>;
378 vfront-porch = <10>;
379 hsync-len = <11>;
380 vsync-len = <13>;
381 };
382 };
Raphael Gallais-Poua853b922023-05-11 16:36:52 +0200383 panel-timing {
Nikhil M Jainbb9d1312023-01-31 15:35:15 +0530384 clock-frequency = <6500000>;
385 hactive = <240>;
386 vactive = <320>;
387 hfront-porch = <6>;
388 hback-porch = <7>;
389 hsync-len = <1>;
390 vback-porch = <5>;
391 vfront-porch = <8>;
392 vsync-len = <2>;
393 hsync-active = <1>;
394 vsync-active = <0>;
395 de-active = <1>;
396 pixelclk-active = <1>;
397 interlaced;
398 doublescan;
399 doubleclk;
400 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700401 };
402
403 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600404 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700405 compatible = "not,compatible";
406 };
407
408 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600409 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700410 };
411
Simon Glass5620cf82018-10-01 12:22:40 -0600412 backlight: backlight {
413 compatible = "pwm-backlight";
414 enable-gpios = <&gpio_a 1>;
415 power-supply = <&ldo_1>;
416 pwms = <&pwm 0 1000>;
417 default-brightness-level = <5>;
418 brightness-levels = <0 16 32 64 128 170 202 234 255>;
419 };
420
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200421 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200422 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200423 bind-test-child1 {
424 compatible = "sandbox,phy";
425 #phy-cells = <1>;
426 };
427
428 bind-test-child2 {
429 compatible = "simple-bus";
430 };
431 };
432
Simon Glassb2c1cac2014-02-26 15:59:21 -0700433 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600434 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700435 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600436 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700437 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530438
439 mux-controls = <&muxcontroller0 0>;
440 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700441 };
442
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200443 phy_provider0: gen_phy@0 {
444 compatible = "sandbox,phy";
445 #phy-cells = <1>;
446 };
447
448 phy_provider1: gen_phy@1 {
449 compatible = "sandbox,phy";
450 #phy-cells = <0>;
451 broken;
452 };
453
developer71092972020-05-02 11:35:12 +0200454 phy_provider2: gen_phy@2 {
455 compatible = "sandbox,phy";
456 #phy-cells = <0>;
457 };
458
Jonas Karlman9f89e682023-08-31 22:16:35 +0000459 phy_provider3: gen_phy@3 {
460 compatible = "sandbox,phy";
461 #phy-cells = <2>;
462 };
463
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200464 gen_phy_user: gen_phy_user {
465 compatible = "simple-bus";
466 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
467 phy-names = "phy1", "phy2", "phy3";
468 };
469
developer71092972020-05-02 11:35:12 +0200470 gen_phy_user1: gen_phy_user1 {
471 compatible = "simple-bus";
472 phys = <&phy_provider0 0>, <&phy_provider2>;
473 phy-names = "phy1", "phy2";
474 };
475
Jonas Karlman9f89e682023-08-31 22:16:35 +0000476 gen_phy_user2: gen_phy_user2 {
477 compatible = "simple-bus";
478 phys = <&phy_provider3 0 0>;
479 phy-names = "phy1";
480 };
481
Simon Glassb2c1cac2014-02-26 15:59:21 -0700482 some-bus {
483 #address-cells = <1>;
484 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600485 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600486 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600487 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700488 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600489 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700490 compatible = "denx,u-boot-fdt-test";
491 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600492 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700493 ping-add = <5>;
494 };
Simon Glass40717422014-07-23 06:55:18 -0600495 c-test@0 {
496 compatible = "denx,u-boot-fdt-test";
497 reg = <0>;
498 ping-expect = <6>;
499 ping-add = <6>;
500 };
501 c-test@1 {
502 compatible = "denx,u-boot-fdt-test";
503 reg = <1>;
504 ping-expect = <7>;
505 ping-add = <7>;
506 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700507 };
508
509 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600510 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600511 ping-expect = <6>;
512 ping-add = <6>;
513 compatible = "google,another-fdt-test";
514 };
515
516 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600517 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600518 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700519 ping-add = <6>;
520 compatible = "google,another-fdt-test";
521 };
522
Simon Glass0ccb0972015-01-25 08:27:05 -0700523 f-test {
524 compatible = "denx,u-boot-fdt-test";
525 };
526
527 g-test {
528 compatible = "denx,u-boot-fdt-test";
529 };
530
Bin Mengd9d24782018-10-10 22:07:01 -0700531 h-test {
532 compatible = "denx,u-boot-fdt-test1";
533 };
534
developercf8bc132020-05-02 11:35:10 +0200535 i-test {
536 compatible = "mediatek,u-boot-fdt-test";
537 #address-cells = <1>;
538 #size-cells = <0>;
539
540 subnode@0 {
541 reg = <0>;
542 };
543
544 subnode@1 {
545 reg = <1>;
546 };
547
548 subnode@2 {
549 reg = <2>;
550 };
551 };
552
Simon Glass204675c2019-12-29 21:19:25 -0700553 devres-test {
554 compatible = "denx,u-boot-devres-test";
555 };
556
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530557 another-test {
558 reg = <0 2>;
559 compatible = "denx,u-boot-fdt-test";
560 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
561 test5-gpios = <&gpio_a 19>;
562 };
563
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100564 mmio-bus@0 {
565 #address-cells = <1>;
566 #size-cells = <1>;
567 compatible = "denx,u-boot-test-bus";
568 dma-ranges = <0x10000000 0x00000000 0x00040000>;
569
570 subnode@0 {
571 compatible = "denx,u-boot-fdt-test";
572 };
573 };
574
575 mmio-bus@1 {
576 #address-cells = <1>;
577 #size-cells = <1>;
578 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100579
580 subnode@0 {
581 compatible = "denx,u-boot-fdt-test";
582 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100583 };
584
Simon Glass3c601b12020-07-07 13:12:06 -0600585 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600586 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600587 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600588 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600589 child {
590 compatible = "denx,u-boot-acpi-test";
591 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600592 };
593
Simon Glass3c601b12020-07-07 13:12:06 -0600594 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600595 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600596 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600597 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600598 };
599
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200600 clocks {
601 clk_fixed: clk-fixed {
602 compatible = "fixed-clock";
603 #clock-cells = <0>;
604 clock-frequency = <1234>;
605 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000606
607 clk_fixed_factor: clk-fixed-factor {
608 compatible = "fixed-factor-clock";
609 #clock-cells = <0>;
610 clock-div = <3>;
611 clock-mult = <2>;
612 clocks = <&clk_fixed>;
613 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200614
615 osc {
616 compatible = "fixed-clock";
617 #clock-cells = <0>;
618 clock-frequency = <20000000>;
619 };
Stephen Warrena9622432016-06-17 09:44:00 -0600620 };
621
622 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600623 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600624 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200625 assigned-clocks = <&clk_sandbox 3>;
626 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600627 };
628
629 clk-test {
630 compatible = "sandbox,clk-test";
631 clocks = <&clk_fixed>,
632 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200633 <&clk_sandbox 0>,
634 <&clk_sandbox 3>,
635 <&clk_sandbox 2>;
636 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600637 };
638
Ashok Reddy Soma8f03cef2023-08-30 10:31:42 +0200639 clk-test2 {
640 compatible = "sandbox,clk-test";
641 assigned-clock-rates = <321>;
642 };
643
644 clk-test3 {
645 compatible = "sandbox,clk-test";
646 assigned-clocks = <&clk_sandbox 1>;
647 };
648
649 clk-test4 {
650 compatible = "sandbox,clk-test";
651 assigned-clock-rates = <654>, <321>;
652 assigned-clocks = <&clk_sandbox 1>;
653 };
654
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200655 ccf: clk-ccf {
656 compatible = "sandbox,clk-ccf";
657 };
658
Simon Glass507ab962021-12-04 08:56:31 -0700659 efi-media {
660 compatible = "sandbox,efi-media";
661 };
662
Simon Glass5b968632015-05-22 15:42:15 -0600663 eth@10002000 {
664 compatible = "sandbox,eth";
665 reg = <0x10002000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600666 };
667
668 eth_5: eth@10003000 {
669 compatible = "sandbox,eth";
670 reg = <0x10003000 0x1000>;
Sean Anderson13652b82022-05-05 13:11:44 -0400671 nvmem-cells = <&eth5_addr>;
672 nvmem-cell-names = "mac-address";
Simon Glass5b968632015-05-22 15:42:15 -0600673 };
674
Bin Meng04a11cb2015-08-27 22:25:53 -0700675 eth_3: sbe5 {
676 compatible = "sandbox,eth";
677 reg = <0x10005000 0x1000>;
Sean Andersone2dc0e62022-05-05 13:11:42 -0400678 nvmem-cells = <&eth3_addr>;
679 nvmem-cell-names = "mac-address";
Bin Meng04a11cb2015-08-27 22:25:53 -0700680 };
681
Simon Glass5b968632015-05-22 15:42:15 -0600682 eth@10004000 {
683 compatible = "sandbox,eth";
684 reg = <0x10004000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600685 };
686
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200687 phy_eth0: phy-test-eth {
688 compatible = "sandbox,eth";
689 reg = <0x10007000 0x1000>;
Sean Anderson24b1b8d2022-05-05 13:11:35 -0400690 mac-address = [ 02 00 11 22 33 49 ];
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200691 phy-handle = <&ethphy1>;
Marek Behúnbc194772022-04-07 00:33:01 +0200692 phy-mode = "2500base-x";
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200693 };
694
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800695 dsa_eth0: dsa-test-eth {
696 compatible = "sandbox,eth";
697 reg = <0x10006000 0x1000>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400698 nvmem-cells = <&eth4_addr>;
699 nvmem-cell-names = "mac-address";
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800700 };
701
702 dsa-test {
703 compatible = "sandbox,dsa";
704
705 ports {
706 #address-cells = <1>;
707 #size-cells = <0>;
708 swp_0: port@0 {
709 reg = <0>;
710 label = "lan0";
711 phy-mode = "rgmii-rxid";
712
713 fixed-link {
714 speed = <100>;
715 full-duplex;
716 };
717 };
718
719 swp_1: port@1 {
720 reg = <1>;
721 label = "lan1";
722 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800723 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800724 };
725
726 port@2 {
727 reg = <2>;
728 ethernet = <&dsa_eth0>;
729
730 fixed-link {
731 speed = <1000>;
732 full-duplex;
733 };
734 };
735 };
736 };
737
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700738 firmware {
739 sandbox_firmware: sandbox-firmware {
740 compatible = "sandbox,firmware";
741 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200742
Etienne Carriere09665cb2022-02-21 09:22:39 +0100743 scmi {
Etienne Carriere02fd1262020-09-09 18:44:00 +0200744 compatible = "sandbox,scmi-agent";
745 #address-cells = <1>;
746 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200747
AKASHI Takahiro535a7bd2023-10-16 14:39:45 +0900748 pwrdom_scmi: protocol@11 {
749 reg = <0x11>;
750 #power-domain-cells = <1>;
751 };
752
Etienne Carriere09665cb2022-02-21 09:22:39 +0100753 clk_scmi: protocol@14 {
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200754 reg = <0x14>;
755 #clock-cells = <1>;
AKASHI Takahirocc4ecda2023-10-11 19:06:59 +0900756 linaro,sandbox-channel-id = <0x14>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200757 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200758
Etienne Carriere09665cb2022-02-21 09:22:39 +0100759 reset_scmi: protocol@16 {
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200760 reg = <0x16>;
761 #reset-cells = <1>;
762 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100763
764 protocol@17 {
765 reg = <0x17>;
766
767 regulators {
768 #address-cells = <1>;
769 #size-cells = <0>;
770
Etienne Carriere09665cb2022-02-21 09:22:39 +0100771 regul0_scmi: reg@0 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100772 reg = <0>;
773 regulator-name = "sandbox-voltd0";
774 regulator-min-microvolt = <1100000>;
775 regulator-max-microvolt = <3300000>;
776 };
Etienne Carriere09665cb2022-02-21 09:22:39 +0100777 regul1_scmi: reg@1 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100778 reg = <0x1>;
779 regulator-name = "sandbox-voltd1";
780 regulator-min-microvolt = <1800000>;
781 };
782 };
783 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200784 };
Alexey Romanov9dc617d2023-09-21 11:13:36 +0300785
786 sm: secure-monitor {
787 compatible = "sandbox,sm";
788 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700789 };
790
Alexander Dahl6ac319d2022-09-30 14:04:30 +0200791 fpga {
792 compatible = "sandbox,fpga";
793 };
794
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100795 pinctrl-gpio {
796 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700797
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100798 gpio_a: base-gpios {
799 compatible = "sandbox,gpio";
800 gpio-controller;
801 #gpio-cells = <1>;
802 gpio-bank-name = "a";
803 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200804 hog_input_active_low {
805 gpio-hog;
806 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200807 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200808 };
809 hog_input_active_high {
810 gpio-hog;
811 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200812 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200813 };
814 hog_output_low {
815 gpio-hog;
816 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200817 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200818 };
819 hog_output_high {
820 gpio-hog;
821 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200822 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200823 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100824 };
825
826 gpio_b: extra-gpios {
827 compatible = "sandbox,gpio";
828 gpio-controller;
829 #gpio-cells = <5>;
830 gpio-bank-name = "b";
831 sandbox,gpio-count = <10>;
832 };
Simon Glass25348a42014-10-13 23:42:11 -0600833
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100834 gpio_c: pinmux-gpios {
835 compatible = "sandbox,gpio";
836 gpio-controller;
837 #gpio-cells = <2>;
838 gpio-bank-name = "c";
839 sandbox,gpio-count = <10>;
840 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100841 };
842
Simon Glass7df766e2014-12-10 08:55:55 -0700843 i2c@0 {
844 #address-cells = <1>;
845 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600846 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700847 compatible = "sandbox,i2c";
848 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200849 pinctrl-names = "default";
850 pinctrl-0 = <&pinmux_i2c0_pins>;
851
Simon Glass7df766e2014-12-10 08:55:55 -0700852 eeprom@2c {
Sean Andersone2dc0e62022-05-05 13:11:42 -0400853 #address-cells = <1>;
854 #size-cells = <1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700855 reg = <0x2c>;
856 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700857 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200858 partitions {
859 compatible = "fixed-partitions";
860 #address-cells = <1>;
861 #size-cells = <1>;
862 bootcount_i2c: bootcount@10 {
863 reg = <10 2>;
864 };
865 };
Sean Andersone2dc0e62022-05-05 13:11:42 -0400866
867 eth3_addr: mac-address@24 {
868 reg = <24 6>;
869 };
Simon Glass7df766e2014-12-10 08:55:55 -0700870 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200871
Simon Glass336b2952015-05-22 15:42:17 -0600872 rtc_0: rtc@43 {
Sean Anderson5768e8b2022-05-05 13:11:43 -0400873 #address-cells = <1>;
874 #size-cells = <1>;
Simon Glass336b2952015-05-22 15:42:17 -0600875 reg = <0x43>;
876 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700877 sandbox,emul = <&emul0>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400878
879 eth4_addr: mac-address@40 {
880 reg = <0x40 6>;
881 };
Simon Glass336b2952015-05-22 15:42:17 -0600882 };
883
884 rtc_1: rtc@61 {
885 reg = <0x61>;
886 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700887 sandbox,emul = <&emul1>;
888 };
889
890 i2c_emul: emul {
891 reg = <0xff>;
892 compatible = "sandbox,i2c-emul-parent";
893 emul_eeprom: emul-eeprom {
894 compatible = "sandbox,i2c-eeprom";
895 sandbox,filename = "i2c.bin";
896 sandbox,size = <256>;
897 };
898 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700899 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700900 };
901 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700902 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600903 };
904 };
905
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200906 sandbox_pmic: sandbox_pmic {
907 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700908 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200909 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200910
911 mc34708: pmic@41 {
912 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700913 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200914 };
Simon Glass7df766e2014-12-10 08:55:55 -0700915 };
916
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100917 bootcount@0 {
918 compatible = "u-boot,bootcount-rtc";
919 rtc = <&rtc_1>;
920 offset = <0x13>;
921 };
922
Michal Simek4f18f922020-05-28 11:48:55 +0200923 bootcount {
924 compatible = "u-boot,bootcount-i2c-eeprom";
925 i2c-eeprom = <&bootcount_i2c>;
926 };
927
Nandor Han88895812021-06-10 15:40:38 +0300928 bootcount_4@0 {
929 compatible = "u-boot,bootcount-syscon";
930 syscon = <&syscon0>;
931 reg = <0x0 0x04>, <0x0 0x04>;
932 reg-names = "syscon_reg", "offset";
933 };
934
935 bootcount_2@0 {
936 compatible = "u-boot,bootcount-syscon";
937 syscon = <&syscon0>;
938 reg = <0x0 0x04>, <0x0 0x02> ;
939 reg-names = "syscon_reg", "offset";
940 };
941
Marek Szyprowskiad398592021-02-18 11:33:18 +0100942 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100943 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100944 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100945 vdd-supply = <&buck2>;
946 vss-microvolts = <0>;
947 };
948
Mark Kettenis67748ee2021-10-23 16:58:02 +0200949 iommu: iommu@0 {
950 compatible = "sandbox,iommu";
951 #iommu-cells = <0>;
952 };
953
Simon Glass515dcff2020-02-06 09:55:00 -0700954 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700955 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700956 interrupt-controller;
957 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700958 };
959
Simon Glass90b6fef2016-01-18 19:52:26 -0700960 lcd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700961 bootph-all;
Simon Glass90b6fef2016-01-18 19:52:26 -0700962 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200963 pinctrl-names = "default";
964 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700965 xres = <1366>;
966 yres = <768>;
967 };
968
Simon Glassd783eb32015-07-06 12:54:34 -0600969 leds {
970 compatible = "gpio-leds";
971
972 iracibble {
973 gpios = <&gpio_a 1 0>;
974 label = "sandbox:red";
975 };
976
977 martinet {
978 gpios = <&gpio_a 2 0>;
979 label = "sandbox:green";
980 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200981
982 default_on {
983 gpios = <&gpio_a 5 0>;
984 label = "sandbox:default_on";
985 default-state = "on";
986 };
987
988 default_off {
989 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400990 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200991 default-state = "off";
992 };
Simon Glassd783eb32015-07-06 12:54:34 -0600993 };
994
Paul Doelle709f0372022-07-04 09:00:25 +0000995 wdt-gpio-toggle {
Simon Glasse0f8cd22023-08-10 09:53:13 -0600996 gpios = <&gpio_a 8 0>;
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200997 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +0200998 hw_margin_ms = <100>;
Paul Doelle709f0372022-07-04 09:00:25 +0000999 hw_algo = "toggle";
1000 always-running;
1001 };
1002
1003 wdt-gpio-level {
1004 gpios = <&gpio_a 7 0>;
1005 compatible = "linux,wdt-gpio";
1006 hw_margin_ms = <100>;
1007 hw_algo = "level";
Rasmus Villemoes2b673872021-08-19 11:57:05 +02001008 always-running;
1009 };
1010
Stephen Warren62f2c902016-05-16 17:41:37 -06001011 mbox: mbox {
1012 compatible = "sandbox,mbox";
1013 #mbox-cells = <1>;
1014 };
1015
1016 mbox-test {
1017 compatible = "sandbox,mbox-test";
1018 mboxes = <&mbox 100>, <&mbox 1>;
1019 mbox-names = "other", "test";
1020 };
1021
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001022 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001023 #address-cells = <1>;
1024 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -04001025 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001026 cpu1: cpu@1 {
1027 device_type = "cpu";
1028 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -04001029 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001030 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001031 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001032 };
Mario Sixdea5df72018-08-06 10:23:44 +02001033
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001034 cpu2: cpu@2 {
1035 device_type = "cpu";
1036 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001037 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001038 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001039 };
Mario Sixdea5df72018-08-06 10:23:44 +02001040
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001041 cpu3: cpu@3 {
1042 device_type = "cpu";
1043 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001044 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001045 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001046 };
Mario Sixdea5df72018-08-06 10:23:44 +02001047 };
1048
Dave Gerlach75dbdfc2020-07-15 23:39:58 -05001049 chipid: chipid {
1050 compatible = "sandbox,soc";
1051 };
1052
Simon Glassc953aaf2018-12-10 10:37:34 -07001053 i2s: i2s {
1054 compatible = "sandbox,i2s";
1055 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -07001056 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -07001057 };
1058
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +02001059 nop-test_0 {
1060 compatible = "sandbox,nop_sandbox1";
1061 nop-test_1 {
1062 compatible = "sandbox,nop_sandbox2";
1063 bind = "True";
1064 };
1065 nop-test_2 {
1066 compatible = "sandbox,nop_sandbox2";
1067 bind = "False";
1068 };
1069 };
1070
Roger Quadrosb0679a72022-10-20 16:30:46 +03001071 memory-controller {
1072 compatible = "sandbox,memory";
1073 };
1074
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001075 misc-test {
Sean Anderson13652b82022-05-05 13:11:44 -04001076 #address-cells = <1>;
1077 #size-cells = <1>;
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001078 compatible = "sandbox,misc_sandbox";
Sean Anderson13652b82022-05-05 13:11:44 -04001079
1080 eth5_addr: mac-address@10 {
1081 reg = <0x10 6>;
1082 };
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001083 };
1084
Simon Glasse4fef742017-04-23 20:02:07 -06001085 mmc2 {
1086 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -06001087 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -06001088 };
1089
Simon Glassb255efc2022-04-24 23:31:24 -06001090 /* This is used for the bootdev tests */
Simon Glasse4fef742017-04-23 20:02:07 -06001091 mmc1 {
1092 compatible = "sandbox,mmc";
Simon Glassb255efc2022-04-24 23:31:24 -06001093 filename = "mmc1.img";
Simon Glasse4fef742017-04-23 20:02:07 -06001094 };
1095
Simon Glassb255efc2022-04-24 23:31:24 -06001096 /* This is used for the fastboot tests */
Sughosh Ganu77079e72022-10-21 18:16:05 +05301097 mmc0: mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -06001098 compatible = "sandbox,mmc";
1099 };
1100
Simon Glassf1eba352022-10-20 18:23:20 -06001101 /* This is used for VBE VPL tests */
1102 mmc3 {
1103 status = "disabled";
1104 compatible = "sandbox,mmc";
1105 filename = "image.bin";
1106 non-removable;
1107 };
1108
Simon Glassd2bc33ed2023-01-06 08:52:41 -06001109 /* This is used for bootstd bootmenu tests */
1110 mmc4 {
1111 status = "disabled";
1112 compatible = "sandbox,mmc";
1113 filename = "mmc4.img";
1114 };
1115
Simon Glassfff928c2023-08-24 13:55:41 -06001116 /* This is used for ChromiumOS tests */
1117 mmc5 {
1118 status = "disabled";
1119 compatible = "sandbox,mmc";
1120 filename = "mmc5.img";
1121 };
1122
Alexander Gendin038cb022023-10-09 01:24:36 +00001123 /* This is used for mbr tests */
1124 mmc6 {
1125 status = "disabled";
1126 compatible = "sandbox,mmc";
1127 filename = "mmc6.img";
1128 };
1129
Simon Glass53a68b32019-02-16 20:24:50 -07001130 pch {
1131 compatible = "sandbox,pch";
1132 };
1133
Tom Rini4a3ca482020-02-11 12:41:23 -05001134 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -07001135 compatible = "sandbox,pci";
1136 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001137 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001138 #address-cells = <3>;
1139 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -06001140 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -07001141 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Mark Kettenis5dfd4ec2023-01-21 20:27:57 +01001142 iommu-map = <0x0010 &iommu 0 1>;
1143 iommu-map-mask = <0xfffffff8>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001144 pci@0,0 {
1145 compatible = "pci-generic";
1146 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001147 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001148 };
Alex Margineanf1274432019-06-07 11:24:24 +03001149 pci@1,0 {
1150 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001151 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
Simon Glass4289c262023-09-26 08:14:58 -06001152 reg = <0x02000814 0 0 0x80 0
1153 0x01000810 0 0 0xc0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001154 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +03001155 };
Simon Glass937bb472019-12-06 21:41:57 -07001156 p2sb-pci@2,0 {
1157 compatible = "sandbox,p2sb";
1158 reg = <0x02001010 0 0 0 0>;
1159 sandbox,emul = <&p2sb_emul>;
1160
1161 adder {
1162 intel,p2sb-port-id = <3>;
1163 compatible = "sandbox,adder";
1164 };
1165 };
Simon Glass8c501022019-12-06 21:41:54 -07001166 pci@1e,0 {
1167 compatible = "sandbox,pmc";
1168 reg = <0xf000 0 0 0 0>;
1169 sandbox,emul = <&pmc_emul1e>;
1170 acpi-base = <0x400>;
1171 gpe0-dwx-mask = <0xf>;
1172 gpe0-dwx-shift-base = <4>;
1173 gpe0-dw = <6 7 9>;
1174 gpe0-sts = <0x20>;
1175 gpe0-en = <0x30>;
1176 };
Simon Glass3a6eae62015-03-05 12:25:34 -07001177 pci@1f,0 {
1178 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001179 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
Simon Glass4289c262023-09-26 08:14:58 -06001180 reg = <0x0100f810 0 0 0x100 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001181 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001182 };
1183 };
1184
Simon Glassb98ba4c2019-09-25 08:56:10 -06001185 pci-emul0 {
1186 compatible = "sandbox,pci-emul-parent";
1187 swap_case_emul0_0: emul0@0,0 {
1188 compatible = "sandbox,swap-case";
1189 };
1190 swap_case_emul0_1: emul0@1,0 {
1191 compatible = "sandbox,swap-case";
1192 use-ea;
1193 };
1194 swap_case_emul0_1f: emul0@1f,0 {
1195 compatible = "sandbox,swap-case";
1196 };
Simon Glass937bb472019-12-06 21:41:57 -07001197 p2sb_emul: emul@2,0 {
1198 compatible = "sandbox,p2sb-emul";
1199 };
Simon Glass8c501022019-12-06 21:41:54 -07001200 pmc_emul1e: emul@1e,0 {
1201 compatible = "sandbox,pmc-emul";
1202 };
Simon Glassb98ba4c2019-09-25 08:56:10 -06001203 };
1204
Tom Rini4a3ca482020-02-11 12:41:23 -05001205 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -07001206 compatible = "sandbox,pci";
1207 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001208 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -07001209 #address-cells = <3>;
1210 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001211 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scullc7456a42022-04-21 16:11:09 +00001212 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001213 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -07001214 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +02001215 0x0c 0x00 0x1234 0x5678
1216 0x10 0x00 0x1234 0x5678>;
1217 pci@10,0 {
1218 reg = <0x8000 0 0 0 0>;
1219 };
Bin Meng408e5902018-08-03 01:14:41 -07001220 };
1221
Tom Rini4a3ca482020-02-11 12:41:23 -05001222 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -07001223 compatible = "sandbox,pci";
1224 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001225 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -07001226 #address-cells = <3>;
1227 #size-cells = <2>;
1228 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1229 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1230 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1231 pci@1f,0 {
1232 compatible = "pci-generic";
1233 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001234 sandbox,emul = <&swap_case_emul2_1f>;
1235 };
1236 };
1237
1238 pci-emul2 {
1239 compatible = "sandbox,pci-emul-parent";
1240 swap_case_emul2_1f: emul2@1f,0 {
1241 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001242 };
1243 };
1244
Ramon Friedc64f19b2019-04-27 11:15:23 +03001245 pci_ep: pci_ep {
1246 compatible = "sandbox,pci_ep";
1247 };
1248
Simon Glass9c433fe2017-04-23 20:10:44 -06001249 probing {
1250 compatible = "simple-bus";
1251 test1 {
1252 compatible = "denx,u-boot-probe-test";
1253 };
1254
1255 test2 {
1256 compatible = "denx,u-boot-probe-test";
1257 };
1258
1259 test3 {
1260 compatible = "denx,u-boot-probe-test";
1261 };
1262
1263 test4 {
1264 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001265 first-syscon = <&syscon0>;
1266 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001267 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001268 };
1269 };
1270
Stephen Warren92c67fa2016-07-13 13:45:31 -06001271 pwrdom: power-domain {
1272 compatible = "sandbox,power-domain";
1273 #power-domain-cells = <1>;
1274 };
1275
1276 power-domain-test {
1277 compatible = "sandbox,power-domain-test";
1278 power-domains = <&pwrdom 2>;
1279 };
1280
Simon Glass5620cf82018-10-01 12:22:40 -06001281 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001282 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001283 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001284 pinctrl-names = "default";
1285 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001286 };
1287
1288 pwm2 {
1289 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001290 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001291 };
1292
Simon Glass3d355e62015-07-06 12:54:31 -06001293 ram {
1294 compatible = "sandbox,ram";
1295 };
1296
Simon Glassd860f222015-07-06 12:54:29 -06001297 reset@0 {
1298 compatible = "sandbox,warm-reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001299 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001300 };
1301
1302 reset@1 {
1303 compatible = "sandbox,reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001304 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001305 };
1306
Stephen Warren6488e642016-06-17 09:43:59 -06001307 resetc: reset-ctl {
1308 compatible = "sandbox,reset-ctl";
1309 #reset-cells = <1>;
1310 };
1311
1312 reset-ctl-test {
1313 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001314 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1315 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001316 };
1317
Sughosh Ganu23e37512019-12-28 23:58:31 +05301318 rng {
1319 compatible = "sandbox,sandbox-rng";
1320 };
1321
Nishanth Menonedf85812015-09-17 15:42:41 -05001322 rproc_1: rproc@1 {
1323 compatible = "sandbox,test-processor";
1324 remoteproc-name = "remoteproc-test-dev1";
1325 };
1326
1327 rproc_2: rproc@2 {
1328 compatible = "sandbox,test-processor";
1329 internal-memory-mapped;
1330 remoteproc-name = "remoteproc-test-dev2";
1331 };
1332
Simon Glass5620cf82018-10-01 12:22:40 -06001333 panel {
1334 compatible = "simple-panel";
1335 backlight = <&backlight 0 100>;
1336 };
1337
Simon Glass509f32e2022-09-21 16:21:47 +02001338 scsi {
1339 compatible = "sandbox,scsi";
1340 sandbox,filepath = "scsi.img";
1341 };
1342
Ramon Fried26ed32e2018-07-02 02:57:59 +03001343 smem@0 {
1344 compatible = "sandbox,smem";
1345 };
1346
Simon Glass76072ac2018-12-10 10:37:36 -07001347 sound {
1348 compatible = "sandbox,sound";
1349 cpu {
1350 sound-dai = <&i2s 0>;
1351 };
1352
1353 codec {
1354 sound-dai = <&audio 0>;
1355 };
1356 };
1357
Simon Glass25348a42014-10-13 23:42:11 -06001358 spi@0 {
1359 #address-cells = <1>;
1360 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001361 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001362 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001363 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001364 pinctrl-names = "default";
1365 pinctrl-0 = <&pinmux_spi0_pins>;
1366
Simon Glass25348a42014-10-13 23:42:11 -06001367 spi.bin@0 {
1368 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001369 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001370 spi-max-frequency = <40000000>;
1371 sandbox,filename = "spi.bin";
1372 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001373 spi.bin@1 {
1374 reg = <1>;
1375 compatible = "spansion,m25p16", "jedec,spi-nor";
1376 spi-max-frequency = <50000000>;
1377 sandbox,filename = "spi.bin";
1378 spi-cpol;
1379 spi-cpha;
1380 };
Simon Glass25348a42014-10-13 23:42:11 -06001381 };
1382
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001383 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001384 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001385 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001386 };
1387
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001388 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001389 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001390 reg = <0x20 5
1391 0x28 6
1392 0x30 7
1393 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001394 };
1395
Patrick Delaunayee010432019-03-07 09:57:13 +01001396 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001397 compatible = "simple-mfd", "syscon";
1398 reg = <0x40 5
1399 0x48 6
1400 0x50 7
1401 0x58 8>;
1402 };
1403
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301404 syscon3: syscon@3 {
1405 compatible = "simple-mfd", "syscon";
1406 reg = <0x000100 0x10>;
1407
1408 muxcontroller0: a-mux-controller {
1409 compatible = "mmio-mux";
1410 #mux-control-cells = <1>;
1411
1412 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1413 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1414 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1415 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1416 u-boot,mux-autoprobe;
1417 };
1418 };
1419
1420 muxcontroller1: emul-mux-controller {
1421 compatible = "mux-emul";
1422 #mux-control-cells = <0>;
1423 u-boot,mux-autoprobe;
1424 idle-state = <0xabcd>;
1425 };
1426
Simon Glass791a17f2020-12-16 21:20:27 -07001427 testfdtm0 {
1428 compatible = "denx,u-boot-fdtm-test";
1429 };
1430
1431 testfdtm1: testfdtm1 {
1432 compatible = "denx,u-boot-fdtm-test";
1433 };
1434
1435 testfdtm2 {
1436 compatible = "denx,u-boot-fdtm-test";
1437 };
1438
Sean Anderson79d3bba2020-09-28 10:52:23 -04001439 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001440 compatible = "sandbox,timer";
1441 clock-frequency = <1000000>;
1442 };
1443
Sean Anderson79d3bba2020-09-28 10:52:23 -04001444 timer@1 {
1445 compatible = "sandbox,timer";
1446 sandbox,timebase-frequency-fallback;
1447 };
1448
Miquel Raynal80938c12018-05-15 11:57:27 +02001449 tpm2 {
1450 compatible = "sandbox,tpm2";
Eddie James1a55a7a2023-10-24 10:43:51 -05001451 memory-region = <&event_log>;
Miquel Raynal80938c12018-05-15 11:57:27 +02001452 };
1453
Simon Glasseef107e2023-02-21 06:24:51 -07001454 tpm {
1455 compatible = "google,sandbox-tpm";
1456 };
1457
Simon Glass5b968632015-05-22 15:42:15 -06001458 uart0: serial {
1459 compatible = "sandbox,serial";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001460 bootph-all;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001461 pinctrl-names = "default";
1462 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001463 };
1464
Simon Glass31680482015-03-25 12:23:05 -06001465 usb_0: usb@0 {
1466 compatible = "sandbox,usb";
1467 status = "disabled";
1468 hub {
1469 compatible = "sandbox,usb-hub";
1470 #address-cells = <1>;
1471 #size-cells = <0>;
1472 flash-stick {
1473 reg = <0>;
1474 compatible = "sandbox,usb-flash";
1475 };
1476 };
1477 };
1478
1479 usb_1: usb@1 {
1480 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001481 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001482 hub {
1483 compatible = "usb-hub";
1484 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001485 #address-cells = <1>;
1486 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001487 hub-emul {
1488 compatible = "sandbox,usb-hub";
1489 #address-cells = <1>;
1490 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001491 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001492 reg = <0>;
1493 compatible = "sandbox,usb-flash";
1494 sandbox,filepath = "testflash.bin";
1495 };
1496
Simon Glass4700fe52015-11-08 23:48:01 -07001497 flash-stick@1 {
1498 reg = <1>;
1499 compatible = "sandbox,usb-flash";
1500 sandbox,filepath = "testflash1.bin";
1501 };
1502
1503 flash-stick@2 {
1504 reg = <2>;
1505 compatible = "sandbox,usb-flash";
1506 sandbox,filepath = "testflash2.bin";
1507 };
1508
Simon Glassc0ccc722015-11-08 23:48:08 -07001509 keyb@3 {
1510 reg = <3>;
1511 compatible = "sandbox,usb-keyb";
1512 };
1513
Simon Glass31680482015-03-25 12:23:05 -06001514 };
Michael Walle7c961322020-06-02 01:47:07 +02001515
1516 usbstor@1 {
1517 reg = <1>;
1518 };
1519 usbstor@3 {
1520 reg = <3>;
1521 };
Simon Glass31680482015-03-25 12:23:05 -06001522 };
1523 };
1524
1525 usb_2: usb@2 {
1526 compatible = "sandbox,usb";
1527 status = "disabled";
1528 };
1529
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001530 spmi: spmi@0 {
1531 compatible = "sandbox,spmi";
1532 #address-cells = <0x1>;
1533 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001534 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001535 pm8916@0 {
1536 compatible = "qcom,spmi-pmic";
1537 reg = <0x0 0x1>;
1538 #address-cells = <0x1>;
1539 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001540 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001541
1542 spmi_gpios: gpios@c000 {
1543 compatible = "qcom,pm8916-gpio";
1544 reg = <0xc000 0x400>;
1545 gpio-controller;
1546 gpio-count = <4>;
1547 #gpio-cells = <2>;
1548 gpio-bank-name="spmi";
1549 };
1550 };
1551 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001552
1553 wdt0: wdt@0 {
1554 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001555 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001556 };
Rob Clarka471b672018-01-10 11:33:30 +01001557
Mario Six95922152018-08-09 14:51:19 +02001558 axi: axi@0 {
1559 compatible = "sandbox,axi";
1560 #address-cells = <0x1>;
1561 #size-cells = <0x1>;
1562 store@0 {
1563 compatible = "sandbox,sandbox_store";
1564 reg = <0x0 0x400>;
1565 };
1566 };
1567
Rob Clarka471b672018-01-10 11:33:30 +01001568 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001569 #address-cells = <1>;
1570 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001571 setting = "sunrise ohoka";
1572 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001573 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001574 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001575 chosen-test {
1576 compatible = "denx,u-boot-fdt-test";
1577 reg = <9 1>;
1578 };
1579 };
Mario Six35616ef2018-03-12 14:53:33 +01001580
1581 translation-test@8000 {
1582 compatible = "simple-bus";
1583 reg = <0x8000 0x4000>;
1584
1585 #address-cells = <0x2>;
1586 #size-cells = <0x1>;
1587
1588 ranges = <0 0x0 0x8000 0x1000
1589 1 0x100 0x9000 0x1000
1590 2 0x200 0xA000 0x1000
1591 3 0x300 0xB000 0x1000
1592 >;
1593
Fabien Dessenne22236e02019-05-31 15:11:30 +02001594 dma-ranges = <0 0x000 0x10000000 0x1000
1595 1 0x100 0x20000000 0x1000
1596 >;
1597
Mario Six35616ef2018-03-12 14:53:33 +01001598 dev@0,0 {
1599 compatible = "denx,u-boot-fdt-dummy";
1600 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +01001601 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001602 };
1603
1604 dev@1,100 {
1605 compatible = "denx,u-boot-fdt-dummy";
1606 reg = <1 0x100 0x1000>;
1607
1608 };
1609
1610 dev@2,200 {
1611 compatible = "denx,u-boot-fdt-dummy";
1612 reg = <2 0x200 0x1000>;
1613 };
1614
1615
1616 noxlatebus@3,300 {
1617 compatible = "simple-bus";
1618 reg = <3 0x300 0x1000>;
1619
1620 #address-cells = <0x1>;
1621 #size-cells = <0x0>;
1622
1623 dev@42 {
1624 compatible = "denx,u-boot-fdt-dummy";
1625 reg = <0x42>;
1626 };
1627 };
1628 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001629
Dzmitry Sankouski54f4c832023-01-22 18:21:23 +03001630 ofnode-foreach {
1631 compatible = "foreach";
1632
1633 first {
1634 prop1 = <1>;
1635 prop2 = <2>;
1636 };
1637
1638 second {
1639 prop1 = <1>;
1640 prop2 = <2>;
1641 };
1642 };
1643
Mario Six02ad6fb2018-09-27 09:19:31 +02001644 osd {
1645 compatible = "sandbox,sandbox_osd";
1646 };
Tom Rinib93eea72018-09-30 18:16:51 -04001647
Jens Wiklander86afaa62018-09-25 16:40:16 +02001648 sandbox_tee {
1649 compatible = "sandbox,tee";
1650 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001651
1652 sandbox_virtio1 {
1653 compatible = "sandbox,virtio1";
Simon Glass8de5a542023-01-17 10:47:51 -07001654 virtio-type = <4>; /* rng */
Bin Meng1bb290d2018-10-15 02:21:26 -07001655 };
1656
1657 sandbox_virtio2 {
1658 compatible = "sandbox,virtio2";
1659 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001660
Simon Glass8de5a542023-01-17 10:47:51 -07001661 sandbox-virtio-blk {
1662 compatible = "sandbox,virtio1";
1663 virtio-type = <2>; /* block */
1664 };
1665
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001666 sandbox_scmi {
1667 compatible = "sandbox,scmi-devices";
AKASHI Takahiro535a7bd2023-10-16 14:39:45 +09001668 power-domains = <&pwrdom_scmi 2>;
Etienne Carrierebf1f1322022-02-21 09:22:41 +01001669 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere09665cb2022-02-21 09:22:39 +01001670 resets = <&reset_scmi 3>;
1671 regul0-supply = <&regul0_scmi>;
1672 regul1-supply = <&regul1_scmi>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001673 };
1674
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001675 pinctrl {
1676 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001677
Sean Anderson3438e3b2020-09-14 11:01:57 -04001678 pinctrl-names = "default", "alternate";
1679 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1680 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001681
Sean Anderson3438e3b2020-09-14 11:01:57 -04001682 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001683 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001684 pins = "P5";
1685 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001686 bias-pull-up;
1687 input-disable;
1688 };
1689 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001690 pins = "P6";
1691 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001692 output-high;
1693 drive-open-drain;
1694 };
1695 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001696 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001697 bias-pull-down;
1698 input-enable;
1699 };
1700 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001701 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001702 bias-disable;
1703 };
1704 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001705
1706 pinctrl_i2c: i2c {
1707 groups {
1708 groups = "I2C_UART";
1709 function = "I2C";
1710 };
1711
1712 pins {
1713 pins = "P0", "P1";
1714 drive-open-drain;
1715 };
1716 };
1717
1718 pinctrl_i2s: i2s {
1719 groups = "SPI_I2S";
1720 function = "I2S";
1721 };
1722
1723 pinctrl_spi: spi {
1724 groups = "SPI_I2S";
1725 function = "SPI";
1726
1727 cs {
1728 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1729 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1730 };
1731 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001732 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001733
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001734 pinctrl-single-no-width {
1735 compatible = "pinctrl-single";
1736 reg = <0x0000 0x238>;
1737 #pinctrl-cells = <1>;
1738 pinctrl-single,function-mask = <0x7f>;
1739 };
1740
1741 pinctrl-single-pins {
1742 compatible = "pinctrl-single";
1743 reg = <0x0000 0x238>;
1744 #pinctrl-cells = <1>;
1745 pinctrl-single,register-width = <32>;
1746 pinctrl-single,function-mask = <0x7f>;
1747
1748 pinmux_pwm_pins: pinmux_pwm_pins {
1749 pinctrl-single,pins = < 0x48 0x06 >;
1750 };
1751
1752 pinmux_spi0_pins: pinmux_spi0_pins {
1753 pinctrl-single,pins = <
1754 0x190 0x0c
1755 0x194 0x0c
1756 0x198 0x23
1757 0x19c 0x0c
1758 >;
1759 };
1760
1761 pinmux_uart0_pins: pinmux_uart0_pins {
1762 pinctrl-single,pins = <
1763 0x70 0x30
1764 0x74 0x00
1765 >;
1766 };
1767 };
1768
1769 pinctrl-single-bits {
1770 compatible = "pinctrl-single";
1771 reg = <0x0000 0x50>;
1772 #pinctrl-cells = <2>;
1773 pinctrl-single,bit-per-mux;
1774 pinctrl-single,register-width = <32>;
1775 pinctrl-single,function-mask = <0xf>;
1776
1777 pinmux_i2c0_pins: pinmux_i2c0_pins {
1778 pinctrl-single,bits = <
1779 0x10 0x00002200 0x0000ff00
1780 >;
1781 };
1782
1783 pinmux_lcd_pins: pinmux_lcd_pins {
1784 pinctrl-single,bits = <
1785 0x40 0x22222200 0xffffff00
1786 0x44 0x22222222 0xffffffff
1787 0x48 0x00000022 0x000000ff
1788 0x48 0x02000000 0x0f000000
1789 0x4c 0x02000022 0x0f0000ff
1790 >;
1791 };
1792 };
1793
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001794 hwspinlock@0 {
1795 compatible = "sandbox,hwspinlock";
1796 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001797
1798 dma: dma {
1799 compatible = "sandbox,dma";
1800 #dma-cells = <1>;
1801
1802 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1803 dma-names = "m2m", "tx0", "rx0";
1804 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001805
Alex Marginean0649be52019-07-12 10:13:53 +03001806 /*
1807 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1808 * end of the test. If parent mdio is removed first, clean-up of the
1809 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1810 * active at the end of the test. That it turn doesn't allow the mdio
1811 * class to be destroyed, triggering an error.
1812 */
1813 mdio-mux-test {
1814 compatible = "sandbox,mdio-mux";
1815 #address-cells = <1>;
1816 #size-cells = <0>;
1817 mdio-parent-bus = <&mdio>;
1818
1819 mdio-ch-test@0 {
1820 reg = <0>;
1821 };
1822 mdio-ch-test@1 {
1823 reg = <1>;
1824 };
1825 };
1826
1827 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001828 compatible = "sandbox,mdio";
Marek Behúnf4f1ddc2022-04-07 00:32:57 +02001829 #address-cells = <1>;
1830 #size-cells = <0>;
1831
1832 ethphy1: ethernet-phy@1 {
1833 reg = <1>;
1834 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001835 };
Sean Andersonb7860542020-06-24 06:41:12 -04001836
1837 pm-bus-test {
1838 compatible = "simple-pm-bus";
1839 clocks = <&clk_sandbox 4>;
1840 power-domains = <&pwrdom 1>;
1841 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001842
1843 resetc2: syscon-reset {
1844 compatible = "syscon-reset";
1845 #reset-cells = <1>;
1846 regmap = <&syscon0>;
1847 offset = <1>;
1848 mask = <0x27FFFFFF>;
1849 assert-high = <0>;
1850 };
1851
1852 syscon-reset-test {
1853 compatible = "sandbox,misc_sandbox";
1854 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1855 reset-names = "valid", "no_mask", "out_of_range";
1856 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301857
Simon Glass458b66a2020-11-05 06:32:05 -07001858 sysinfo {
1859 compatible = "sandbox,sysinfo-sandbox";
1860 };
1861
Sean Anderson1c830672021-04-20 10:50:58 -04001862 sysinfo-gpio {
1863 compatible = "gpio-sysinfo";
1864 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1865 revisions = <19>, <5>;
1866 names = "rev_a", "foo";
1867 };
1868
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301869 some_regmapped-bus {
1870 #address-cells = <0x1>;
1871 #size-cells = <0x1>;
1872
1873 ranges = <0x0 0x0 0x10>;
1874 compatible = "simple-bus";
1875
1876 regmap-test_0 {
1877 reg = <0 0x10>;
1878 compatible = "sandbox,regmap_test";
1879 };
1880 };
Robert Marko9cf87122022-09-06 13:30:35 +02001881
1882 thermal {
1883 compatible = "sandbox,thermal";
1884 };
Sughosh Ganu77079e72022-10-21 18:16:05 +05301885
1886 fwu-mdata {
1887 compatible = "u-boot,fwu-mdata-gpt";
1888 fwu-mdata-store = <&mmc0>;
1889 };
Abdellatif El Khlifi6b005872023-04-17 10:11:55 +01001890
1891 nvmxip-qspi1@08000000 {
1892 compatible = "nvmxip,qspi";
1893 reg = <0x08000000 0x00200000>;
1894 lba_shift = <9>;
1895 lba = <4096>;
1896 };
1897
1898 nvmxip-qspi2@08200000 {
1899 compatible = "nvmxip,qspi";
1900 reg = <0x08200000 0x00100000>;
1901 lba_shift = <9>;
1902 lba = <2048>;
1903 };
Svyatoslav Ryhel669f5c82023-04-25 10:57:21 +03001904
1905 extcon {
1906 compatible = "sandbox,extcon";
1907 };
Abdellatif El Khlifi4970d5b2023-08-04 14:33:41 +01001908
1909 arm-ffa-emul {
1910 compatible = "sandbox,arm-ffa-emul";
1911
1912 sandbox-arm-ffa {
1913 compatible = "sandbox,arm-ffa";
1914 };
1915 };
Sean Anderson326422b2023-11-04 16:37:52 -04001916
1917 nand-controller {
1918 #address-cells = <1>;
1919 #size-cells = <0>;
1920 compatible = "sandbox,nand";
1921
1922 nand@0 {
1923 reg = <0>;
1924 nand-ecc-mode = "soft";
1925 sandbox,id = [00 e3];
1926 sandbox,erasesize = <(8 * 1024)>;
1927 sandbox,oobsize = <16>;
1928 sandbox,pagesize = <512>;
1929 sandbox,pages = <0x2000>;
1930 sandbox,err-count = <1>;
1931 sandbox,err-step-size = <512>;
1932 };
1933
1934 /* MT29F64G08AKABA */
1935 nand@1 {
1936 reg = <1>;
1937 nand-ecc-mode = "soft_bch";
1938 sandbox,id = [2C 48 00 26 89 00 00 00];
1939 sandbox,onfi = [
1940 4f 4e 46 49 0e 00 5a 00
1941 ff 01 00 00 00 00 03 00
1942 00 00 00 00 00 00 00 00
1943 00 00 00 00 00 00 00 00
1944 4d 49 43 52 4f 4e 20 20
1945 20 20 20 20 4d 54 32 39
1946 46 36 34 47 30 38 41 4b
1947 41 42 41 43 35 20 20 20
1948 2c 00 00 00 00 00 00 00
1949 00 00 00 00 00 00 00 00
1950 00 10 00 00 e0 00 00 02
1951 00 00 1c 00 80 00 00 00
1952 00 10 00 00 02 23 01 50
1953 00 01 05 01 00 00 04 00
1954 04 01 1e 00 00 00 00 00
1955 00 00 00 00 00 00 00 00
1956 0e 1f 00 1f 00 f4 01 ac
1957 0d 19 00 c8 00 00 00 00
1958 00 00 00 00 00 00 0a 07
1959 19 00 00 00 00 00 00 00
1960 00 00 00 00 01 00 01 00
1961 00 00 04 10 01 81 04 02
1962 02 01 1e 90 00 00 00 00
1963 00 00 00 00 00 00 00 00
1964 00 00 00 00 00 00 00 00
1965 00 00 00 00 00 00 00 00
1966 00 00 00 00 00 00 00 00
1967 00 00 00 00 00 00 00 00
1968 00 00 00 00 00 00 00 00
1969 00 00 00 00 00 00 00 00
1970 00 00 00 00 00 00 00 00
1971 00 00 00 00 00 03 20 7d
1972 ];
1973 sandbox,erasesize = <(512 * 1024)>;
1974 sandbox,oobsize = <224>;
1975 sandbox,pagesize = <4096>;
1976 sandbox,pages = <0x200000>;
1977 sandbox,err-count = <3>;
1978 sandbox,err-step-size = <512>;
1979 };
1980 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001981};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001982
1983#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001984#include "cros-ec-keyboard.dtsi"
Simon Glass5e135d32022-10-20 18:23:15 -06001985
1986#ifdef CONFIG_SANDBOX_VPL
1987#include "sandbox_vpl.dtsi"
1988#endif
Simon Glass61300722023-06-01 10:23:01 -06001989
1990#include "cedit.dtsi"