blob: 52e9ddbf50f9e41630e93d34f7e924ca7c793dd8 [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Eddie James1a55a7a2023-10-24 10:43:51 -050012#include <config.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010013#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010015#include <dt-bindings/input/input.h>
Heiko Schocher350d2522025-01-28 14:52:46 +010016#include <dt-bindings/leds/common.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040017#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053018#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010019
Simon Glassb2c1cac2014-02-26 15:59:21 -070020/ {
21 model = "sandbox";
22 compatible = "sandbox";
23 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060024 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070025
Simon Glassfef72b72014-07-23 06:55:03 -060026 aliases {
27 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010028 ethernet0 = "/eth@10002000";
29 ethernet2 = &swp_0;
30 ethernet3 = &eth_3;
31 ethernet4 = &dsa_eth0;
32 ethernet5 = &eth_5;
Sean Anderson67d93a42022-05-05 13:11:30 -040033 ethernet6 = "/eth@10004000";
34 ethernet7 = &swp_1;
35 ethernet8 = &phy_eth0;
Simon Glass5620cf82018-10-01 12:22:40 -060036 gpio1 = &gpio_a;
37 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010038 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070039 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060040 mmc0 = "/mmc0";
41 mmc1 = "/mmc1";
Simon Glassf1eba352022-10-20 18:23:20 -060042 mmc2 = "/mmc2";
43 mmc3 = "/mmc3";
Simon Glassfff928c2023-08-24 13:55:41 -060044 mmc4 = "/mmc4";
45 mmc5 = "/mmc5";
Alexander Gendin038cb022023-10-09 01:24:36 +000046 mmc6 = "/mmc6";
Mattijs Korpershoekd77f8152024-07-10 10:40:06 +020047 mmc7 = "/mmc7";
Guillaume La Roque368ad9e2024-11-26 09:06:13 +010048 mmc8 = "/mmc8";
Bin Meng408e5902018-08-03 01:14:41 -070049 pci0 = &pci0;
50 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070051 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020052 remoteproc0 = &rproc_1;
53 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060054 rtc0 = &rtc_0;
55 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060056 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020057 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070058 testbus3 = "/some-bus";
59 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070060 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070061 testfdt3 = "/b-test";
62 testfdt5 = "/some-bus/c-test@5";
63 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070064 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020065 fdt-dummy0 = "/translation-test@8000/dev@0,0";
66 fdt-dummy1 = "/translation-test@8000/dev@1,100";
67 fdt-dummy2 = "/translation-test@8000/dev@2,200";
68 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060069 usb0 = &usb_0;
70 usb1 = &usb_1;
71 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020072 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020073 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060074 };
75
Eddie James1a55a7a2023-10-24 10:43:51 -050076 reserved-memory {
77 #address-cells = <1>;
78 #size-cells = <1>;
79 ranges;
80
81 event_log: tcg_event_log {
82 no-map;
Sughosh Ganu3f768682024-08-26 17:29:32 +053083 reg = <(CFG_SYS_SDRAM_BASE + 0x100000) 0x2000>;
Eddie James1a55a7a2023-10-24 10:43:51 -050084 };
85 };
86
Simon Glass5e135d32022-10-20 18:23:15 -060087 binman: binman {
Philippe Reynes462d1632022-03-28 22:56:53 +020088 };
89
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020090 config {
Simon Glass0034d962021-08-07 07:24:01 -060091 testing-bool;
92 testing-int = <123>;
93 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020094 environment {
95 from_fdt = "yes";
96 fdt_env_path = "";
97 };
98 };
99
Michal Simek43c42bd2023-08-31 08:59:05 +0200100 options {
101 u-boot {
102 compatible = "u-boot,config";
103 bootscr-ram-offset = /bits/ 64 <0x12345678>;
Michal Simek6a7c1ce2023-08-31 09:04:27 +0200104 bootscr-flash-offset = /bits/ 64 <0>;
105 bootscr-flash-size = /bits/ 64 <0x2000>;
Christian Marangifd53ad42024-11-10 12:50:27 +0100106 boot-led = <&sandbox_led_green>;
107 activity-led = <&sandbox_led_red>;
Christian Marangicdc38152024-10-01 14:24:44 +0200108 testing-bool;
109 testing-int = <123>;
110 testing-str = "testing";
Christian Marangi81ce47e2024-11-10 12:50:25 +0100111 testing-phandle = <&phandle_node_1>;
Michal Simek43c42bd2023-08-31 08:59:05 +0200112 };
113 };
114
Simon Glassb255efc2022-04-24 23:31:24 -0600115 bootstd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700116 bootph-verify;
Simon Glassb255efc2022-04-24 23:31:24 -0600117 compatible = "u-boot,boot-std";
118
119 filename-prefixes = "/", "/boot/";
120 bootdev-order = "mmc2", "mmc1";
121
Simon Glassb71d7f72023-05-10 16:34:46 -0600122 extlinux {
123 compatible = "u-boot,extlinux";
Simon Glassb255efc2022-04-24 23:31:24 -0600124 };
125
126 efi {
127 compatible = "u-boot,distro-efi";
128 };
Simon Glassa9289612022-10-20 18:23:14 -0600129
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600130 theme {
131 font-size = <30>;
Simon Glass86f1ac52023-06-01 10:23:00 -0600132 menu-inset = <3>;
133 menuitem-gap-y = <1>;
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600134 };
135
Simon Glass82adc292023-08-14 16:40:30 -0600136 cedit-theme {
137 font-size = <30>;
138 menu-inset = <3>;
139 menuitem-gap-y = <1>;
140 };
141
Simon Glassf1eba352022-10-20 18:23:20 -0600142 /*
143 * This is used for the VBE OS-request tests. A FAT filesystem
144 * created in a partition with the VBE information appearing
Michal Simek33224372023-09-07 14:55:48 +0200145 * before the partition starts
Simon Glassf1eba352022-10-20 18:23:20 -0600146 */
Simon Glassa9289612022-10-20 18:23:14 -0600147 firmware0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700148 bootph-verify;
Simon Glassa9289612022-10-20 18:23:14 -0600149 compatible = "fwupd,vbe-simple";
150 storage = "mmc1";
151 skip-offset = <0x200>;
152 area-start = <0x400>;
153 area-size = <0x1000>;
154 state-offset = <0x400>;
155 state-size = <0x40>;
156 version-offset = <0x800>;
157 version-size = <0x100>;
158 };
Simon Glassf1eba352022-10-20 18:23:20 -0600159
160 /*
161 * This is used for the VBE VPL tests. The MMC device holds the
162 * binman image.bin file. The test progresses through each phase
163 * of U-Boot, loading each in turn from MMC.
164 *
165 * Note that the test enables this node (and mmc3) before
166 * running U-Boot
167 */
168 firmware1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700169 bootph-verify;
Simon Glassf1eba352022-10-20 18:23:20 -0600170 status = "disabled";
171 compatible = "fwupd,vbe-simple";
172 storage = "mmc3";
Simon Glass9bb73e32023-04-02 14:01:24 +1200173 skip-offset = <0x800000>;
Simon Glassf1eba352022-10-20 18:23:20 -0600174 area-start = <0>;
175 area-size = <0xe00000>;
176 state-offset = <0xdffc00>;
177 state-size = <0x40>;
178 version-offset = <0xdffe00>;
179 version-size = <0x100>;
180 };
Simon Glassb255efc2022-04-24 23:31:24 -0600181 };
182
Simon Glass61300722023-06-01 10:23:01 -0600183 cedit: cedit {
184 };
185
Andrew Scull451b8b12022-05-30 10:00:12 +0000186 fuzzing-engine {
187 compatible = "sandbox,fuzzing-engine";
188 };
189
Nandor Han6521e5d2021-06-10 16:56:44 +0300190 reboot-mode0 {
191 compatible = "reboot-mode-gpio";
192 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
193 u-boot,env-variable = "bootstatus";
194 mode-test = <0x01>;
195 mode-download = <0x03>;
196 };
197
Nandor Han7e4067a2021-06-10 16:56:45 +0300198 reboot_mode1: reboot-mode@14 {
199 compatible = "reboot-mode-rtc";
200 rtc = <&rtc_0>;
201 reg = <0x30 4>;
202 u-boot,env-variable = "bootstatus";
203 big-endian;
204 mode-test = <0x21969147>;
205 mode-download = <0x51939147>;
206 };
207
Simon Glassed96cde2018-12-10 10:37:33 -0700208 audio: audio-codec {
209 compatible = "sandbox,audio-codec";
210 #sound-dai-cells = <1>;
211 };
212
Philippe Reynes1ee26482020-07-24 18:19:51 +0200213 buttons {
214 compatible = "gpio-keys";
215
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200216 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200217 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200218 label = "button1";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300219 linux,code = <BTN_1>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200220 };
221
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200222 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200223 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200224 label = "button2";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300225 linux,code = <BTN_2>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200226 };
227 };
228
Marek Szyprowskiad398592021-02-18 11:33:18 +0100229 buttons2 {
230 compatible = "adc-keys";
231 io-channels = <&adc 3>;
232 keyup-threshold-microvolt = <3000000>;
233
234 button-up {
235 label = "button3";
236 linux,code = <KEY_F3>;
237 press-threshold-microvolt = <1500000>;
238 };
239
240 button-down {
241 label = "button4";
242 linux,code = <KEY_F4>;
243 press-threshold-microvolt = <1000000>;
244 };
245
246 button-enter {
247 label = "button5";
248 linux,code = <KEY_F5>;
249 press-threshold-microvolt = <500000>;
250 };
251 };
252
Simon Glassc953aaf2018-12-10 10:37:34 -0700253 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600254 reg = <0 0>;
255 compatible = "google,cros-ec-sandbox";
256
257 /*
258 * This describes the flash memory within the EC. Note
259 * that the STM32L flash erases to 0, not 0xff.
260 */
261 flash {
262 image-pos = <0x08000000>;
263 size = <0x20000>;
264 erase-value = <0>;
265
266 /* Information for sandbox */
267 ro {
268 image-pos = <0>;
269 size = <0xf000>;
270 };
271 wp-ro {
272 image-pos = <0xf000>;
273 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700274 used = <0x884>;
275 compress = "lz4";
276 uncomp-size = <0xcf8>;
277 hash {
278 algo = "sha256";
279 value = [00 01 02 03 04 05 06 07
280 08 09 0a 0b 0c 0d 0e 0f
281 10 11 12 13 14 15 16 17
282 18 19 1a 1b 1c 1d 1e 1f];
283 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600284 };
285 rw {
286 image-pos = <0x10000>;
287 size = <0x10000>;
288 };
289 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300290
291 cros_ec_pwm: cros-ec-pwm {
292 compatible = "google,cros-ec-pwm";
293 #pwm-cells = <1>;
294 };
295
Simon Glass699c9ca2018-10-01 12:22:08 -0600296 };
297
Yannick Fertré9712c822019-10-07 15:29:05 +0200298 dsi_host: dsi_host {
299 compatible = "sandbox,dsi-host";
300 };
301
Christian Marangia1a1e0e2024-11-10 12:50:23 +0100302 phandle_node_1: phandle-node-1 {
303 };
304
305 phandle_node_2: phandle-node-2 {
306 };
307
Simon Glassb2c1cac2014-02-26 15:59:21 -0700308 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600309 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700310 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600311 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700312 ping-add = <0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700313 bootph-all;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100314 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
315 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700316 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100317 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
318 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
319 <&gpio_b 7 GPIO_IN 3 2 1>,
320 <&gpio_b 8 GPIO_OUT 3 2 1>,
321 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100322 test3-gpios =
323 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
324 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
325 <&gpio_c 2 GPIO_OUT>,
326 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
327 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200328 <&gpio_c 5 GPIO_IN>,
329 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
330 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530331 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
332 test5-gpios = <&gpio_a 19>;
333
Simon Glass73025392021-10-23 17:26:04 -0600334 bool-value;
Stefan Herbrechtsmeier1b090e62022-06-14 15:21:30 +0200335 int8-value = /bits/ 8 <0x12>;
336 int16-value = /bits/ 16 <0x1234>;
Simon Glass6df01f92018-12-10 10:37:37 -0700337 int-value = <1234>;
338 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200339 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200340 int-array = <5678 9123 4567>;
Michal Simek08a194e2023-08-25 11:37:46 +0200341 int64-array = /bits/ 64 <0x1111222233334444 0x4444333322221111>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600342 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700343 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600344 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200345 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Christian Marangia1a1e0e2024-11-10 12:50:23 +0100346 phandle-nodes = <&phandle_node_1>, <&phandle_node_2>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530347
348 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
349 <&muxcontroller0 2>, <&muxcontroller0 3>,
350 <&muxcontroller1>;
351 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
352 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100353 display-timings {
354 timing0: 240x320 {
355 clock-frequency = <6500000>;
356 hactive = <240>;
357 vactive = <320>;
358 hfront-porch = <6>;
359 hback-porch = <7>;
360 hsync-len = <1>;
361 vback-porch = <5>;
362 vfront-porch = <8>;
363 vsync-len = <2>;
364 hsync-active = <1>;
365 vsync-active = <0>;
366 de-active = <1>;
367 pixelclk-active = <1>;
368 interlaced;
369 doublescan;
370 doubleclk;
371 };
372 timing1: 480x800 {
373 clock-frequency = <9000000>;
374 hactive = <480>;
375 vactive = <800>;
376 hfront-porch = <10>;
377 hback-porch = <59>;
378 hsync-len = <12>;
379 vback-porch = <15>;
380 vfront-porch = <17>;
381 vsync-len = <16>;
382 hsync-active = <0>;
383 vsync-active = <1>;
384 de-active = <0>;
385 pixelclk-active = <0>;
386 };
387 timing2: 800x480 {
388 clock-frequency = <33500000>;
389 hactive = <800>;
390 vactive = <480>;
391 hback-porch = <89>;
392 hfront-porch = <164>;
393 vback-porch = <23>;
394 vfront-porch = <10>;
395 hsync-len = <11>;
396 vsync-len = <13>;
397 };
398 };
Raphael Gallais-Poua853b922023-05-11 16:36:52 +0200399 panel-timing {
Nikhil M Jainbb9d1312023-01-31 15:35:15 +0530400 clock-frequency = <6500000>;
401 hactive = <240>;
402 vactive = <320>;
403 hfront-porch = <6>;
404 hback-porch = <7>;
405 hsync-len = <1>;
406 vback-porch = <5>;
407 vfront-porch = <8>;
408 vsync-len = <2>;
409 hsync-active = <1>;
410 vsync-active = <0>;
411 de-active = <1>;
412 pixelclk-active = <1>;
413 interlaced;
414 doublescan;
415 doubleclk;
416 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700417 };
418
419 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600420 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700421 compatible = "not,compatible";
422 };
423
424 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600425 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700426 };
427
Simon Glass5620cf82018-10-01 12:22:40 -0600428 backlight: backlight {
429 compatible = "pwm-backlight";
430 enable-gpios = <&gpio_a 1>;
431 power-supply = <&ldo_1>;
432 pwms = <&pwm 0 1000>;
433 default-brightness-level = <5>;
434 brightness-levels = <0 16 32 64 128 170 202 234 255>;
435 };
436
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200437 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200438 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200439 bind-test-child1 {
440 compatible = "sandbox,phy";
441 #phy-cells = <1>;
442 };
443
444 bind-test-child2 {
445 compatible = "simple-bus";
446 };
447 };
448
Simon Glassb2c1cac2014-02-26 15:59:21 -0700449 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600450 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700451 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600452 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700453 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530454
455 mux-controls = <&muxcontroller0 0>;
456 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700457 };
458
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200459 phy_provider0: gen_phy@0 {
460 compatible = "sandbox,phy";
461 #phy-cells = <1>;
462 };
463
464 phy_provider1: gen_phy@1 {
465 compatible = "sandbox,phy";
466 #phy-cells = <0>;
467 broken;
468 };
469
developer71092972020-05-02 11:35:12 +0200470 phy_provider2: gen_phy@2 {
471 compatible = "sandbox,phy";
472 #phy-cells = <0>;
473 };
474
Jonas Karlman9f89e682023-08-31 22:16:35 +0000475 phy_provider3: gen_phy@3 {
476 compatible = "sandbox,phy";
477 #phy-cells = <2>;
478 };
479
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200480 gen_phy_user: gen_phy_user {
481 compatible = "simple-bus";
482 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
483 phy-names = "phy1", "phy2", "phy3";
484 };
485
developer71092972020-05-02 11:35:12 +0200486 gen_phy_user1: gen_phy_user1 {
487 compatible = "simple-bus";
488 phys = <&phy_provider0 0>, <&phy_provider2>;
489 phy-names = "phy1", "phy2";
490 };
491
Jonas Karlman9f89e682023-08-31 22:16:35 +0000492 gen_phy_user2: gen_phy_user2 {
493 compatible = "simple-bus";
494 phys = <&phy_provider3 0 0>;
495 phy-names = "phy1";
496 };
497
Simon Glassb2c1cac2014-02-26 15:59:21 -0700498 some-bus {
499 #address-cells = <1>;
500 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600501 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600502 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600503 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700504 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600505 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700506 compatible = "denx,u-boot-fdt-test";
507 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600508 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700509 ping-add = <5>;
510 };
Simon Glass40717422014-07-23 06:55:18 -0600511 c-test@0 {
512 compatible = "denx,u-boot-fdt-test";
513 reg = <0>;
514 ping-expect = <6>;
515 ping-add = <6>;
516 };
517 c-test@1 {
518 compatible = "denx,u-boot-fdt-test";
519 reg = <1>;
520 ping-expect = <7>;
521 ping-add = <7>;
522 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700523 };
524
525 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600526 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600527 ping-expect = <6>;
528 ping-add = <6>;
529 compatible = "google,another-fdt-test";
530 };
531
532 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600533 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600534 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700535 ping-add = <6>;
536 compatible = "google,another-fdt-test";
537 };
538
Simon Glass0ccb0972015-01-25 08:27:05 -0700539 f-test {
Patrick Rudolph0fe88cc2024-10-23 15:20:05 +0200540 #interrupt-cells = <2>;
541 interrupt-parent = <&irq>;
542 interrupts = <4 0>;
Simon Glass0ccb0972015-01-25 08:27:05 -0700543 compatible = "denx,u-boot-fdt-test";
544 };
545
546 g-test {
547 compatible = "denx,u-boot-fdt-test";
548 };
549
Bin Mengd9d24782018-10-10 22:07:01 -0700550 h-test {
551 compatible = "denx,u-boot-fdt-test1";
552 };
553
developercf8bc132020-05-02 11:35:10 +0200554 i-test {
555 compatible = "mediatek,u-boot-fdt-test";
556 #address-cells = <1>;
557 #size-cells = <0>;
558
559 subnode@0 {
560 reg = <0>;
561 };
562
563 subnode@1 {
564 reg = <1>;
565 };
566
567 subnode@2 {
568 reg = <2>;
569 };
570 };
571
Simon Glass204675c2019-12-29 21:19:25 -0700572 devres-test {
573 compatible = "denx,u-boot-devres-test";
574 };
575
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530576 another-test {
577 reg = <0 2>;
578 compatible = "denx,u-boot-fdt-test";
579 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
580 test5-gpios = <&gpio_a 19>;
581 };
582
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100583 mmio-bus@0 {
584 #address-cells = <1>;
585 #size-cells = <1>;
586 compatible = "denx,u-boot-test-bus";
587 dma-ranges = <0x10000000 0x00000000 0x00040000>;
588
589 subnode@0 {
590 compatible = "denx,u-boot-fdt-test";
591 };
592 };
593
594 mmio-bus@1 {
595 #address-cells = <1>;
596 #size-cells = <1>;
597 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100598
599 subnode@0 {
600 compatible = "denx,u-boot-fdt-test";
601 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100602 };
603
Simon Glass3c601b12020-07-07 13:12:06 -0600604 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600605 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600606 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600607 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600608 child {
609 compatible = "denx,u-boot-acpi-test";
610 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600611 };
612
Simon Glass3c601b12020-07-07 13:12:06 -0600613 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600614 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600615 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600616 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600617 };
618
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200619 clocks {
620 clk_fixed: clk-fixed {
621 compatible = "fixed-clock";
622 #clock-cells = <0>;
623 clock-frequency = <1234>;
624 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000625
626 clk_fixed_factor: clk-fixed-factor {
627 compatible = "fixed-factor-clock";
628 #clock-cells = <0>;
629 clock-div = <3>;
630 clock-mult = <2>;
631 clocks = <&clk_fixed>;
632 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200633
634 osc {
635 compatible = "fixed-clock";
636 #clock-cells = <0>;
637 clock-frequency = <20000000>;
638 };
Stephen Warrena9622432016-06-17 09:44:00 -0600639 };
640
641 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600642 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600643 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200644 assigned-clocks = <&clk_sandbox 3>;
645 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600646 };
647
648 clk-test {
649 compatible = "sandbox,clk-test";
650 clocks = <&clk_fixed>,
651 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200652 <&clk_sandbox 0>,
Yang Xiwene89289c2023-12-16 02:28:52 +0800653 <&ccf 11>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200654 <&clk_sandbox 3>,
655 <&clk_sandbox 2>;
Yang Xiwene89289c2023-12-16 02:28:52 +0800656 clock-names = "fixed", "i2c", "spi", "i2c_root", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600657 };
658
Ashok Reddy Soma8f03cef2023-08-30 10:31:42 +0200659 clk-test2 {
660 compatible = "sandbox,clk-test";
661 assigned-clock-rates = <321>;
662 };
663
664 clk-test3 {
665 compatible = "sandbox,clk-test";
666 assigned-clocks = <&clk_sandbox 1>;
667 };
668
669 clk-test4 {
670 compatible = "sandbox,clk-test";
671 assigned-clock-rates = <654>, <321>;
672 assigned-clocks = <&clk_sandbox 1>;
673 };
674
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200675 ccf: clk-ccf {
676 compatible = "sandbox,clk-ccf";
Yang Xiwene89289c2023-12-16 02:28:52 +0800677 #clock-cells = <1>;
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200678 };
679
Simon Glass507ab962021-12-04 08:56:31 -0700680 efi-media {
681 compatible = "sandbox,efi-media";
682 };
683
Simon Glass5b968632015-05-22 15:42:15 -0600684 eth@10002000 {
685 compatible = "sandbox,eth";
686 reg = <0x10002000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600687 };
688
689 eth_5: eth@10003000 {
690 compatible = "sandbox,eth";
691 reg = <0x10003000 0x1000>;
Sean Anderson13652b82022-05-05 13:11:44 -0400692 nvmem-cells = <&eth5_addr>;
693 nvmem-cell-names = "mac-address";
Simon Glass5b968632015-05-22 15:42:15 -0600694 };
695
Bin Meng04a11cb2015-08-27 22:25:53 -0700696 eth_3: sbe5 {
697 compatible = "sandbox,eth";
698 reg = <0x10005000 0x1000>;
Sean Andersone2dc0e62022-05-05 13:11:42 -0400699 nvmem-cells = <&eth3_addr>;
700 nvmem-cell-names = "mac-address";
Bin Meng04a11cb2015-08-27 22:25:53 -0700701 };
702
Simon Glass5b968632015-05-22 15:42:15 -0600703 eth@10004000 {
704 compatible = "sandbox,eth";
705 reg = <0x10004000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600706 };
707
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200708 phy_eth0: phy-test-eth {
709 compatible = "sandbox,eth";
710 reg = <0x10007000 0x1000>;
Sean Anderson24b1b8d2022-05-05 13:11:35 -0400711 mac-address = [ 02 00 11 22 33 49 ];
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200712 phy-handle = <&ethphy1>;
Marek Behúnbc194772022-04-07 00:33:01 +0200713 phy-mode = "2500base-x";
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200714 };
715
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800716 dsa_eth0: dsa-test-eth {
717 compatible = "sandbox,eth";
718 reg = <0x10006000 0x1000>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400719 nvmem-cells = <&eth4_addr>;
720 nvmem-cell-names = "mac-address";
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800721 };
722
723 dsa-test {
724 compatible = "sandbox,dsa";
725
726 ports {
727 #address-cells = <1>;
728 #size-cells = <0>;
729 swp_0: port@0 {
730 reg = <0>;
731 label = "lan0";
732 phy-mode = "rgmii-rxid";
733
734 fixed-link {
735 speed = <100>;
736 full-duplex;
737 };
738 };
739
740 swp_1: port@1 {
741 reg = <1>;
742 label = "lan1";
743 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800744 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800745 };
746
747 port@2 {
748 reg = <2>;
749 ethernet = <&dsa_eth0>;
750
751 fixed-link {
752 speed = <1000>;
753 full-duplex;
754 };
755 };
756 };
757 };
758
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700759 firmware {
760 sandbox_firmware: sandbox-firmware {
761 compatible = "sandbox,firmware";
762 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200763
Etienne Carriere09665cb2022-02-21 09:22:39 +0100764 scmi {
Etienne Carriere02fd1262020-09-09 18:44:00 +0200765 compatible = "sandbox,scmi-agent";
766 #address-cells = <1>;
767 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200768
AKASHI Takahiro535a7bd2023-10-16 14:39:45 +0900769 pwrdom_scmi: protocol@11 {
770 reg = <0x11>;
771 #power-domain-cells = <1>;
772 };
773
Etienne Carriere09665cb2022-02-21 09:22:39 +0100774 clk_scmi: protocol@14 {
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200775 reg = <0x14>;
776 #clock-cells = <1>;
AKASHI Takahirocc4ecda2023-10-11 19:06:59 +0900777 linaro,sandbox-channel-id = <0x14>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200778 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200779
Etienne Carriere09665cb2022-02-21 09:22:39 +0100780 reset_scmi: protocol@16 {
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200781 reg = <0x16>;
782 #reset-cells = <1>;
783 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100784
785 protocol@17 {
786 reg = <0x17>;
787
788 regulators {
789 #address-cells = <1>;
790 #size-cells = <0>;
791
Etienne Carriere09665cb2022-02-21 09:22:39 +0100792 regul0_scmi: reg@0 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100793 reg = <0>;
794 regulator-name = "sandbox-voltd0";
795 regulator-min-microvolt = <1100000>;
796 regulator-max-microvolt = <3300000>;
797 };
Etienne Carriere09665cb2022-02-21 09:22:39 +0100798 regul1_scmi: reg@1 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100799 reg = <0x1>;
800 regulator-name = "sandbox-voltd1";
801 regulator-min-microvolt = <1800000>;
802 };
803 };
804 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200805 };
Alexey Romanov9dc617d2023-09-21 11:13:36 +0300806
807 sm: secure-monitor {
808 compatible = "sandbox,sm";
809 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700810 };
811
Alexander Dahl6ac319d2022-09-30 14:04:30 +0200812 fpga {
813 compatible = "sandbox,fpga";
814 };
815
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100816 pinctrl-gpio {
817 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700818
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100819 gpio_a: base-gpios {
820 compatible = "sandbox,gpio";
821 gpio-controller;
822 #gpio-cells = <1>;
823 gpio-bank-name = "a";
Heiko Schocher350d2522025-01-28 14:52:46 +0100824 sandbox,gpio-count = <25>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200825 hog_input_active_low {
826 gpio-hog;
827 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200828 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200829 };
830 hog_input_active_high {
831 gpio-hog;
832 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200833 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200834 };
835 hog_output_low {
836 gpio-hog;
837 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200838 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200839 };
840 hog_output_high {
841 gpio-hog;
842 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200843 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200844 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100845 };
846
847 gpio_b: extra-gpios {
848 compatible = "sandbox,gpio";
849 gpio-controller;
850 #gpio-cells = <5>;
851 gpio-bank-name = "b";
852 sandbox,gpio-count = <10>;
853 };
Simon Glass25348a42014-10-13 23:42:11 -0600854
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100855 gpio_c: pinmux-gpios {
856 compatible = "sandbox,gpio";
857 gpio-controller;
858 #gpio-cells = <2>;
859 gpio-bank-name = "c";
860 sandbox,gpio-count = <10>;
861 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100862 };
863
Simon Glass7df766e2014-12-10 08:55:55 -0700864 i2c@0 {
865 #address-cells = <1>;
866 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600867 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700868 compatible = "sandbox,i2c";
869 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200870 pinctrl-names = "default";
871 pinctrl-0 = <&pinmux_i2c0_pins>;
872
Simon Glass7df766e2014-12-10 08:55:55 -0700873 eeprom@2c {
Sean Andersone2dc0e62022-05-05 13:11:42 -0400874 #address-cells = <1>;
875 #size-cells = <1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700876 reg = <0x2c>;
877 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700878 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200879 partitions {
880 compatible = "fixed-partitions";
881 #address-cells = <1>;
882 #size-cells = <1>;
883 bootcount_i2c: bootcount@10 {
884 reg = <10 2>;
885 };
886 };
Sean Andersone2dc0e62022-05-05 13:11:42 -0400887
888 eth3_addr: mac-address@24 {
889 reg = <24 6>;
890 };
Simon Glass7df766e2014-12-10 08:55:55 -0700891 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200892
Simon Glass336b2952015-05-22 15:42:17 -0600893 rtc_0: rtc@43 {
Sean Anderson5768e8b2022-05-05 13:11:43 -0400894 #address-cells = <1>;
895 #size-cells = <1>;
Simon Glass336b2952015-05-22 15:42:17 -0600896 reg = <0x43>;
897 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700898 sandbox,emul = <&emul0>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400899
900 eth4_addr: mac-address@40 {
901 reg = <0x40 6>;
902 };
Simon Glass336b2952015-05-22 15:42:17 -0600903 };
904
905 rtc_1: rtc@61 {
906 reg = <0x61>;
907 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700908 sandbox,emul = <&emul1>;
909 };
910
911 i2c_emul: emul {
912 reg = <0xff>;
913 compatible = "sandbox,i2c-emul-parent";
914 emul_eeprom: emul-eeprom {
915 compatible = "sandbox,i2c-eeprom";
916 sandbox,filename = "i2c.bin";
917 sandbox,size = <256>;
918 };
919 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700920 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700921 };
922 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700923 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600924 };
925 };
926
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200927 sandbox_pmic: sandbox_pmic {
928 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700929 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200930 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200931
932 mc34708: pmic@41 {
933 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700934 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200935 };
Simon Glass7df766e2014-12-10 08:55:55 -0700936 };
937
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100938 bootcount@0 {
939 compatible = "u-boot,bootcount-rtc";
940 rtc = <&rtc_1>;
941 offset = <0x13>;
942 };
943
Michal Simek4f18f922020-05-28 11:48:55 +0200944 bootcount {
945 compatible = "u-boot,bootcount-i2c-eeprom";
946 i2c-eeprom = <&bootcount_i2c>;
947 };
948
Nandor Han88895812021-06-10 15:40:38 +0300949 bootcount_4@0 {
950 compatible = "u-boot,bootcount-syscon";
951 syscon = <&syscon0>;
952 reg = <0x0 0x04>, <0x0 0x04>;
953 reg-names = "syscon_reg", "offset";
954 };
955
956 bootcount_2@0 {
957 compatible = "u-boot,bootcount-syscon";
958 syscon = <&syscon0>;
959 reg = <0x0 0x04>, <0x0 0x02> ;
960 reg-names = "syscon_reg", "offset";
961 };
962
Marek Szyprowskiad398592021-02-18 11:33:18 +0100963 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100964 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100965 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100966 vdd-supply = <&buck2>;
967 vss-microvolts = <0>;
968 };
969
Mark Kettenis67748ee2021-10-23 16:58:02 +0200970 iommu: iommu@0 {
971 compatible = "sandbox,iommu";
972 #iommu-cells = <0>;
973 };
974
Simon Glass515dcff2020-02-06 09:55:00 -0700975 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700976 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700977 interrupt-controller;
978 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700979 };
980
Simon Glass90b6fef2016-01-18 19:52:26 -0700981 lcd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700982 bootph-all;
Simon Glass90b6fef2016-01-18 19:52:26 -0700983 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200984 pinctrl-names = "default";
985 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700986 xres = <1366>;
987 yres = <768>;
988 };
989
Simon Glassd783eb32015-07-06 12:54:34 -0600990 leds {
991 compatible = "gpio-leds";
992
Christian Marangifd53ad42024-11-10 12:50:27 +0100993 sandbox_led_red: iracibble {
Simon Glassd783eb32015-07-06 12:54:34 -0600994 gpios = <&gpio_a 1 0>;
995 label = "sandbox:red";
996 };
997
Christian Marangifd53ad42024-11-10 12:50:27 +0100998 sandbox_led_green: martinet {
Simon Glassd783eb32015-07-06 12:54:34 -0600999 gpios = <&gpio_a 2 0>;
1000 label = "sandbox:green";
1001 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +02001002
1003 default_on {
1004 gpios = <&gpio_a 5 0>;
1005 label = "sandbox:default_on";
1006 default-state = "on";
1007 };
1008
1009 default_off {
1010 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -04001011 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +02001012 default-state = "off";
1013 };
Heiko Schocher350d2522025-01-28 14:52:46 +01001014
1015 led-20 {
1016 gpios = <&gpio_a 20 0>;
1017 /* label intentionally omitted */
1018 function = LED_FUNCTION_STATUS;
1019 color = <LED_COLOR_ID_RED>;
1020 function-enumerator = <20>;
1021 };
1022
1023 led-21 {
1024 gpios = <&gpio_a 21 0>;
1025 /* label intentionally omitted */
1026 function = LED_FUNCTION_STATUS;
1027 color = <LED_COLOR_ID_GREEN>;
1028 };
1029
1030 led-22 {
1031 gpios = <&gpio_a 22 0>;
1032 /* label intentionally omitted */
1033 function = LED_FUNCTION_STATUS;
1034 };
1035
1036 led-23 {
1037 gpios = <&gpio_a 23 0>;
1038 /* label intentionally omitted */
1039 color = <LED_COLOR_ID_GREEN>;
1040 };
1041
1042 led-24 {
1043 gpios = <&gpio_a 24 0>;
1044 label = "sandbox:function";
1045 function = LED_FUNCTION_STATUS;
1046 color = <LED_COLOR_ID_GREEN>;
1047 };
Simon Glassd783eb32015-07-06 12:54:34 -06001048 };
1049
Svyatoslav Ryhel1d91d5d2025-02-16 19:09:31 +02001050 lvds-encoder {
1051 compatible = "lvds-encoder";
1052
1053 ports {
1054 #address-cells = <1>;
1055 #size-cells = <0>;
1056
1057 port@0 {
1058 reg = <0>;
1059
1060 bridge_input: endpoint {
1061 /* link to output */
1062 };
1063 };
1064
1065 port@1 {
1066 reg = <1>;
1067
1068 bridge_output: endpoint {
1069 remote-endpoint = <&panel_input>;
1070 };
1071 };
1072 };
1073 };
1074
Paul Doelle709f0372022-07-04 09:00:25 +00001075 wdt-gpio-toggle {
Simon Glasse0f8cd22023-08-10 09:53:13 -06001076 gpios = <&gpio_a 8 0>;
Rasmus Villemoes2b673872021-08-19 11:57:05 +02001077 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001078 hw_margin_ms = <100>;
Paul Doelle709f0372022-07-04 09:00:25 +00001079 hw_algo = "toggle";
1080 always-running;
1081 };
1082
1083 wdt-gpio-level {
1084 gpios = <&gpio_a 7 0>;
1085 compatible = "linux,wdt-gpio";
1086 hw_margin_ms = <100>;
1087 hw_algo = "level";
Rasmus Villemoes2b673872021-08-19 11:57:05 +02001088 always-running;
1089 };
1090
Stephen Warren62f2c902016-05-16 17:41:37 -06001091 mbox: mbox {
1092 compatible = "sandbox,mbox";
1093 #mbox-cells = <1>;
1094 };
1095
1096 mbox-test {
1097 compatible = "sandbox,mbox-test";
1098 mboxes = <&mbox 100>, <&mbox 1>;
1099 mbox-names = "other", "test";
1100 };
1101
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001102 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001103 #address-cells = <1>;
1104 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -04001105 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001106 cpu1: cpu@1 {
1107 device_type = "cpu";
1108 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -04001109 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001110 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001111 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001112 };
Mario Sixdea5df72018-08-06 10:23:44 +02001113
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001114 cpu2: cpu@2 {
1115 device_type = "cpu";
1116 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001117 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001118 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001119 };
Mario Sixdea5df72018-08-06 10:23:44 +02001120
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001121 cpu3: cpu@3 {
1122 device_type = "cpu";
1123 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001124 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001125 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001126 };
Mario Sixdea5df72018-08-06 10:23:44 +02001127 };
1128
Dave Gerlach75dbdfc2020-07-15 23:39:58 -05001129 chipid: chipid {
1130 compatible = "sandbox,soc";
1131 };
1132
Simon Glassc953aaf2018-12-10 10:37:34 -07001133 i2s: i2s {
1134 compatible = "sandbox,i2s";
1135 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -07001136 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -07001137 };
1138
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +02001139 nop-test_0 {
1140 compatible = "sandbox,nop_sandbox1";
1141 nop-test_1 {
1142 compatible = "sandbox,nop_sandbox2";
1143 bind = "True";
1144 };
1145 nop-test_2 {
1146 compatible = "sandbox,nop_sandbox2";
1147 bind = "False";
1148 };
1149 };
1150
Roger Quadrosb0679a72022-10-20 16:30:46 +03001151 memory-controller {
1152 compatible = "sandbox,memory";
1153 };
1154
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001155 misc-test {
Sean Anderson13652b82022-05-05 13:11:44 -04001156 #address-cells = <1>;
1157 #size-cells = <1>;
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001158 compatible = "sandbox,misc_sandbox";
Sean Anderson13652b82022-05-05 13:11:44 -04001159
1160 eth5_addr: mac-address@10 {
1161 reg = <0x10 6>;
1162 };
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001163 };
1164
Simon Glasse4fef742017-04-23 20:02:07 -06001165 mmc2 {
1166 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -06001167 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -06001168 };
1169
Simon Glassb255efc2022-04-24 23:31:24 -06001170 /* This is used for the bootdev tests */
Simon Glasse4fef742017-04-23 20:02:07 -06001171 mmc1 {
1172 compatible = "sandbox,mmc";
Simon Glassb255efc2022-04-24 23:31:24 -06001173 filename = "mmc1.img";
Simon Glasse4fef742017-04-23 20:02:07 -06001174 };
1175
Simon Glassb255efc2022-04-24 23:31:24 -06001176 /* This is used for the fastboot tests */
Sughosh Ganu77079e72022-10-21 18:16:05 +05301177 mmc0: mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -06001178 compatible = "sandbox,mmc";
1179 };
1180
Simon Glassf1eba352022-10-20 18:23:20 -06001181 /* This is used for VBE VPL tests */
1182 mmc3 {
1183 status = "disabled";
1184 compatible = "sandbox,mmc";
1185 filename = "image.bin";
1186 non-removable;
1187 };
1188
Simon Glassd2bc33ed2023-01-06 08:52:41 -06001189 /* This is used for bootstd bootmenu tests */
1190 mmc4 {
1191 status = "disabled";
1192 compatible = "sandbox,mmc";
1193 filename = "mmc4.img";
1194 };
1195
Simon Glassfff928c2023-08-24 13:55:41 -06001196 /* This is used for ChromiumOS tests */
1197 mmc5 {
1198 status = "disabled";
1199 compatible = "sandbox,mmc";
1200 filename = "mmc5.img";
1201 };
1202
Alexander Gendin038cb022023-10-09 01:24:36 +00001203 /* This is used for mbr tests */
1204 mmc6 {
1205 status = "disabled";
1206 compatible = "sandbox,mmc";
1207 filename = "mmc6.img";
1208 };
1209
Guillaume La Roque368ad9e2024-11-26 09:06:13 +01001210 /* This is used for Android boot image v4 tests */
Mattijs Korpershoekd77f8152024-07-10 10:40:06 +02001211 mmc7 {
1212 status = "disabled";
1213 compatible = "sandbox,mmc";
1214 filename = "mmc7.img";
1215 };
1216
Guillaume La Roque368ad9e2024-11-26 09:06:13 +01001217 /* This is used for Android boot image v2 tests. */
1218 mmc8 {
1219 status = "disabled";
1220 compatible = "sandbox,mmc";
1221 filename = "mmc8.img";
1222 };
1223
Simon Glass53a68b32019-02-16 20:24:50 -07001224 pch {
1225 compatible = "sandbox,pch";
1226 };
1227
Tom Rini4a3ca482020-02-11 12:41:23 -05001228 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -07001229 compatible = "sandbox,pci";
1230 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001231 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001232 #address-cells = <3>;
1233 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -06001234 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -07001235 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Mark Kettenis5dfd4ec2023-01-21 20:27:57 +01001236 iommu-map = <0x0010 &iommu 0 1>;
1237 iommu-map-mask = <0xfffffff8>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001238 pci@0,0 {
1239 compatible = "pci-generic";
1240 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001241 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001242 };
Alex Margineanf1274432019-06-07 11:24:24 +03001243 pci@1,0 {
1244 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001245 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
Simon Glass4289c262023-09-26 08:14:58 -06001246 reg = <0x02000814 0 0 0x80 0
1247 0x01000810 0 0 0xc0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001248 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +03001249 };
Simon Glass937bb472019-12-06 21:41:57 -07001250 p2sb-pci@2,0 {
1251 compatible = "sandbox,p2sb";
1252 reg = <0x02001010 0 0 0 0>;
1253 sandbox,emul = <&p2sb_emul>;
1254
1255 adder {
1256 intel,p2sb-port-id = <3>;
1257 compatible = "sandbox,adder";
1258 };
1259 };
Simon Glass8c501022019-12-06 21:41:54 -07001260 pci@1e,0 {
1261 compatible = "sandbox,pmc";
1262 reg = <0xf000 0 0 0 0>;
1263 sandbox,emul = <&pmc_emul1e>;
1264 acpi-base = <0x400>;
1265 gpe0-dwx-mask = <0xf>;
1266 gpe0-dwx-shift-base = <4>;
1267 gpe0-dw = <6 7 9>;
1268 gpe0-sts = <0x20>;
1269 gpe0-en = <0x30>;
1270 };
Simon Glass3a6eae62015-03-05 12:25:34 -07001271 pci@1f,0 {
1272 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001273 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
Simon Glass4289c262023-09-26 08:14:58 -06001274 reg = <0x0100f810 0 0 0x100 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001275 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001276 };
1277 };
1278
Simon Glassb98ba4c2019-09-25 08:56:10 -06001279 pci-emul0 {
1280 compatible = "sandbox,pci-emul-parent";
1281 swap_case_emul0_0: emul0@0,0 {
1282 compatible = "sandbox,swap-case";
1283 };
1284 swap_case_emul0_1: emul0@1,0 {
1285 compatible = "sandbox,swap-case";
1286 use-ea;
1287 };
1288 swap_case_emul0_1f: emul0@1f,0 {
1289 compatible = "sandbox,swap-case";
1290 };
Simon Glass937bb472019-12-06 21:41:57 -07001291 p2sb_emul: emul@2,0 {
1292 compatible = "sandbox,p2sb-emul";
1293 };
Simon Glass8c501022019-12-06 21:41:54 -07001294 pmc_emul1e: emul@1e,0 {
1295 compatible = "sandbox,pmc-emul";
1296 };
Simon Glassb98ba4c2019-09-25 08:56:10 -06001297 };
1298
Tom Rini4a3ca482020-02-11 12:41:23 -05001299 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -07001300 compatible = "sandbox,pci";
1301 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001302 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -07001303 #address-cells = <3>;
1304 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001305 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scullc7456a42022-04-21 16:11:09 +00001306 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001307 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -07001308 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +02001309 0x0c 0x00 0x1234 0x5678
1310 0x10 0x00 0x1234 0x5678>;
1311 pci@10,0 {
1312 reg = <0x8000 0 0 0 0>;
1313 };
Bin Meng408e5902018-08-03 01:14:41 -07001314 };
1315
Tom Rini4a3ca482020-02-11 12:41:23 -05001316 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -07001317 compatible = "sandbox,pci";
1318 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001319 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -07001320 #address-cells = <3>;
1321 #size-cells = <2>;
1322 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1323 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1324 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1325 pci@1f,0 {
1326 compatible = "pci-generic";
1327 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001328 sandbox,emul = <&swap_case_emul2_1f>;
1329 };
1330 };
1331
1332 pci-emul2 {
1333 compatible = "sandbox,pci-emul-parent";
1334 swap_case_emul2_1f: emul2@1f,0 {
1335 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001336 };
1337 };
1338
Ramon Friedc64f19b2019-04-27 11:15:23 +03001339 pci_ep: pci_ep {
1340 compatible = "sandbox,pci_ep";
1341 };
1342
Simon Glass9c433fe2017-04-23 20:10:44 -06001343 probing {
1344 compatible = "simple-bus";
1345 test1 {
1346 compatible = "denx,u-boot-probe-test";
1347 };
1348
1349 test2 {
1350 compatible = "denx,u-boot-probe-test";
1351 };
1352
1353 test3 {
1354 compatible = "denx,u-boot-probe-test";
1355 };
1356
1357 test4 {
1358 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001359 first-syscon = <&syscon0>;
1360 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001361 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001362 };
1363 };
1364
Stephen Warren92c67fa2016-07-13 13:45:31 -06001365 pwrdom: power-domain {
1366 compatible = "sandbox,power-domain";
1367 #power-domain-cells = <1>;
1368 };
1369
1370 power-domain-test {
1371 compatible = "sandbox,power-domain-test";
1372 power-domains = <&pwrdom 2>;
1373 };
1374
Simon Glass5620cf82018-10-01 12:22:40 -06001375 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001376 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001377 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001378 pinctrl-names = "default";
1379 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001380 };
1381
1382 pwm2 {
1383 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001384 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001385 };
1386
Simon Glass3d355e62015-07-06 12:54:31 -06001387 ram {
1388 compatible = "sandbox,ram";
1389 };
1390
Simon Glassd860f222015-07-06 12:54:29 -06001391 reset@0 {
1392 compatible = "sandbox,warm-reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001393 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001394 };
1395
1396 reset@1 {
1397 compatible = "sandbox,reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001398 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001399 };
1400
Stephen Warren6488e642016-06-17 09:43:59 -06001401 resetc: reset-ctl {
1402 compatible = "sandbox,reset-ctl";
1403 #reset-cells = <1>;
1404 };
1405
1406 reset-ctl-test {
1407 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001408 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1409 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001410 };
1411
Sughosh Ganu23e37512019-12-28 23:58:31 +05301412 rng {
1413 compatible = "sandbox,sandbox-rng";
1414 };
1415
Nishanth Menonedf85812015-09-17 15:42:41 -05001416 rproc_1: rproc@1 {
1417 compatible = "sandbox,test-processor";
1418 remoteproc-name = "remoteproc-test-dev1";
1419 };
1420
1421 rproc_2: rproc@2 {
1422 compatible = "sandbox,test-processor";
1423 internal-memory-mapped;
1424 remoteproc-name = "remoteproc-test-dev2";
1425 };
1426
Simon Glass5620cf82018-10-01 12:22:40 -06001427 panel {
1428 compatible = "simple-panel";
1429 backlight = <&backlight 0 100>;
Svyatoslav Ryhel1d91d5d2025-02-16 19:09:31 +02001430
1431 display-timings {
1432 timing@0 {
1433 /* 1280x800@60Hz */
1434 clock-frequency = <68000000>;
1435 hactive = <1280>;
1436 hfront-porch = <48>;
1437 hback-porch = <18>;
1438 hsync-len = <30>;
1439 vactive = <800>;
1440 vfront-porch = <3>;
1441 vback-porch = <12>;
1442 vsync-len = <5>;
1443 };
1444 };
1445
1446 port {
1447 panel_input: endpoint {
1448 remote-endpoint = <&bridge_output>;
1449 };
1450 };
Simon Glass5620cf82018-10-01 12:22:40 -06001451 };
1452
Simon Glass509f32e2022-09-21 16:21:47 +02001453 scsi {
1454 compatible = "sandbox,scsi";
1455 sandbox,filepath = "scsi.img";
1456 };
1457
Ramon Fried26ed32e2018-07-02 02:57:59 +03001458 smem@0 {
1459 compatible = "sandbox,smem";
1460 };
1461
Simon Glass76072ac2018-12-10 10:37:36 -07001462 sound {
1463 compatible = "sandbox,sound";
1464 cpu {
1465 sound-dai = <&i2s 0>;
1466 };
1467
1468 codec {
1469 sound-dai = <&audio 0>;
1470 };
1471 };
1472
Simon Glass25348a42014-10-13 23:42:11 -06001473 spi@0 {
1474 #address-cells = <1>;
1475 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001476 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001477 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001478 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001479 pinctrl-names = "default";
1480 pinctrl-0 = <&pinmux_spi0_pins>;
1481
Simon Glass25348a42014-10-13 23:42:11 -06001482 spi.bin@0 {
1483 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001484 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001485 spi-max-frequency = <40000000>;
1486 sandbox,filename = "spi.bin";
1487 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001488 spi.bin@1 {
1489 reg = <1>;
1490 compatible = "spansion,m25p16", "jedec,spi-nor";
1491 spi-max-frequency = <50000000>;
1492 sandbox,filename = "spi.bin";
1493 spi-cpol;
1494 spi-cpha;
1495 };
Simon Glass25348a42014-10-13 23:42:11 -06001496 };
1497
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001498 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001499 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001500 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001501 };
1502
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001503 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001504 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001505 reg = <0x20 5
1506 0x28 6
1507 0x30 7
1508 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001509 };
1510
Patrick Delaunayee010432019-03-07 09:57:13 +01001511 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001512 compatible = "simple-mfd", "syscon";
1513 reg = <0x40 5
1514 0x48 6
1515 0x50 7
1516 0x58 8>;
1517 };
1518
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301519 syscon3: syscon@3 {
1520 compatible = "simple-mfd", "syscon";
1521 reg = <0x000100 0x10>;
1522
1523 muxcontroller0: a-mux-controller {
1524 compatible = "mmio-mux";
1525 #mux-control-cells = <1>;
1526
1527 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1528 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1529 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1530 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1531 u-boot,mux-autoprobe;
1532 };
1533 };
1534
1535 muxcontroller1: emul-mux-controller {
1536 compatible = "mux-emul";
1537 #mux-control-cells = <0>;
1538 u-boot,mux-autoprobe;
1539 idle-state = <0xabcd>;
1540 };
1541
Simon Glass791a17f2020-12-16 21:20:27 -07001542 testfdtm0 {
1543 compatible = "denx,u-boot-fdtm-test";
1544 };
1545
1546 testfdtm1: testfdtm1 {
1547 compatible = "denx,u-boot-fdtm-test";
1548 };
1549
1550 testfdtm2 {
1551 compatible = "denx,u-boot-fdtm-test";
1552 };
1553
Sean Anderson79d3bba2020-09-28 10:52:23 -04001554 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001555 compatible = "sandbox,timer";
1556 clock-frequency = <1000000>;
1557 };
1558
Sean Anderson79d3bba2020-09-28 10:52:23 -04001559 timer@1 {
1560 compatible = "sandbox,timer";
1561 sandbox,timebase-frequency-fallback;
1562 };
1563
Miquel Raynal80938c12018-05-15 11:57:27 +02001564 tpm2 {
1565 compatible = "sandbox,tpm2";
Eddie James1a55a7a2023-10-24 10:43:51 -05001566 memory-region = <&event_log>;
Miquel Raynal80938c12018-05-15 11:57:27 +02001567 };
1568
Simon Glasseef107e2023-02-21 06:24:51 -07001569 tpm {
1570 compatible = "google,sandbox-tpm";
1571 };
1572
Simon Glass5b968632015-05-22 15:42:15 -06001573 uart0: serial {
1574 compatible = "sandbox,serial";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001575 bootph-all;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001576 pinctrl-names = "default";
1577 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001578 };
1579
Simon Glass31680482015-03-25 12:23:05 -06001580 usb_0: usb@0 {
1581 compatible = "sandbox,usb";
1582 status = "disabled";
1583 hub {
1584 compatible = "sandbox,usb-hub";
1585 #address-cells = <1>;
1586 #size-cells = <0>;
1587 flash-stick {
1588 reg = <0>;
1589 compatible = "sandbox,usb-flash";
1590 };
1591 };
1592 };
1593
1594 usb_1: usb@1 {
1595 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001596 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001597 hub {
1598 compatible = "usb-hub";
1599 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001600 #address-cells = <1>;
1601 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001602 hub-emul {
1603 compatible = "sandbox,usb-hub";
1604 #address-cells = <1>;
1605 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001606 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001607 reg = <0>;
1608 compatible = "sandbox,usb-flash";
1609 sandbox,filepath = "testflash.bin";
1610 };
1611
Simon Glass4700fe52015-11-08 23:48:01 -07001612 flash-stick@1 {
1613 reg = <1>;
1614 compatible = "sandbox,usb-flash";
Simon Glass64c63252024-11-07 14:31:49 -07001615 sandbox,filepath = "flash1.img";
Simon Glass4700fe52015-11-08 23:48:01 -07001616 };
1617
1618 flash-stick@2 {
1619 reg = <2>;
1620 compatible = "sandbox,usb-flash";
1621 sandbox,filepath = "testflash2.bin";
1622 };
1623
Simon Glassc0ccc722015-11-08 23:48:08 -07001624 keyb@3 {
1625 reg = <3>;
1626 compatible = "sandbox,usb-keyb";
1627 };
1628
Simon Glass31680482015-03-25 12:23:05 -06001629 };
Michael Walle7c961322020-06-02 01:47:07 +02001630
1631 usbstor@1 {
1632 reg = <1>;
1633 };
1634 usbstor@3 {
1635 reg = <3>;
1636 };
Simon Glass31680482015-03-25 12:23:05 -06001637 };
1638 };
1639
1640 usb_2: usb@2 {
1641 compatible = "sandbox,usb";
1642 status = "disabled";
1643 };
1644
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001645 spmi: spmi@0 {
1646 compatible = "sandbox,spmi";
1647 #address-cells = <0x1>;
1648 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001649 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001650 pm8916@0 {
1651 compatible = "qcom,spmi-pmic";
1652 reg = <0x0 0x1>;
1653 #address-cells = <0x1>;
1654 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001655 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001656
1657 spmi_gpios: gpios@c000 {
1658 compatible = "qcom,pm8916-gpio";
1659 reg = <0xc000 0x400>;
Caleb Connolly1edc45f2024-01-08 15:30:51 +00001660 gpio-ranges = <&spmi_gpios 0 0 4>;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001661 gpio-controller;
1662 gpio-count = <4>;
1663 #gpio-cells = <2>;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001664 };
1665 };
1666 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001667
1668 wdt0: wdt@0 {
1669 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001670 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001671 };
Rob Clarka471b672018-01-10 11:33:30 +01001672
Mario Six95922152018-08-09 14:51:19 +02001673 axi: axi@0 {
1674 compatible = "sandbox,axi";
1675 #address-cells = <0x1>;
1676 #size-cells = <0x1>;
1677 store@0 {
1678 compatible = "sandbox,sandbox_store";
1679 reg = <0x0 0x400>;
1680 };
1681 };
1682
Rob Clarka471b672018-01-10 11:33:30 +01001683 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001684 #address-cells = <1>;
1685 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001686 setting = "sunrise ohoka";
1687 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001688 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001689 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Algapally Santosh Sagardf178992023-09-21 16:50:43 +05301690 stdout-path = "serial0:115200n8";
Rob Clarka471b672018-01-10 11:33:30 +01001691 chosen-test {
1692 compatible = "denx,u-boot-fdt-test";
1693 reg = <9 1>;
1694 };
1695 };
Mario Six35616ef2018-03-12 14:53:33 +01001696
1697 translation-test@8000 {
1698 compatible = "simple-bus";
1699 reg = <0x8000 0x4000>;
1700
1701 #address-cells = <0x2>;
1702 #size-cells = <0x1>;
1703
1704 ranges = <0 0x0 0x8000 0x1000
1705 1 0x100 0x9000 0x1000
1706 2 0x200 0xA000 0x1000
1707 3 0x300 0xB000 0x1000
1708 >;
1709
Fabien Dessenne22236e02019-05-31 15:11:30 +02001710 dma-ranges = <0 0x000 0x10000000 0x1000
1711 1 0x100 0x20000000 0x1000
1712 >;
1713
Mario Six35616ef2018-03-12 14:53:33 +01001714 dev@0,0 {
1715 compatible = "denx,u-boot-fdt-dummy";
1716 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +01001717 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001718 };
1719
1720 dev@1,100 {
1721 compatible = "denx,u-boot-fdt-dummy";
1722 reg = <1 0x100 0x1000>;
1723
1724 };
1725
1726 dev@2,200 {
1727 compatible = "denx,u-boot-fdt-dummy";
1728 reg = <2 0x200 0x1000>;
1729 };
1730
1731
1732 noxlatebus@3,300 {
1733 compatible = "simple-bus";
1734 reg = <3 0x300 0x1000>;
1735
1736 #address-cells = <0x1>;
1737 #size-cells = <0x0>;
1738
1739 dev@42 {
1740 compatible = "denx,u-boot-fdt-dummy";
1741 reg = <0x42>;
1742 };
1743 };
1744 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001745
Dzmitry Sankouski54f4c832023-01-22 18:21:23 +03001746 ofnode-foreach {
1747 compatible = "foreach";
1748
1749 first {
1750 prop1 = <1>;
1751 prop2 = <2>;
1752 };
1753
1754 second {
1755 prop1 = <1>;
1756 prop2 = <2>;
1757 };
1758 };
1759
Mario Six02ad6fb2018-09-27 09:19:31 +02001760 osd {
1761 compatible = "sandbox,sandbox_osd";
1762 };
Tom Rinib93eea72018-09-30 18:16:51 -04001763
Jens Wiklander86afaa62018-09-25 16:40:16 +02001764 sandbox_tee {
1765 compatible = "sandbox,tee";
1766 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001767
1768 sandbox_virtio1 {
1769 compatible = "sandbox,virtio1";
Simon Glass8de5a542023-01-17 10:47:51 -07001770 virtio-type = <4>; /* rng */
Bin Meng1bb290d2018-10-15 02:21:26 -07001771 };
1772
1773 sandbox_virtio2 {
1774 compatible = "sandbox,virtio2";
1775 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001776
Simon Glass8de5a542023-01-17 10:47:51 -07001777 sandbox-virtio-blk {
1778 compatible = "sandbox,virtio1";
1779 virtio-type = <2>; /* block */
1780 };
1781
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001782 sandbox_scmi {
1783 compatible = "sandbox,scmi-devices";
AKASHI Takahiro535a7bd2023-10-16 14:39:45 +09001784 power-domains = <&pwrdom_scmi 2>;
Etienne Carrierebf1f1322022-02-21 09:22:41 +01001785 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere09665cb2022-02-21 09:22:39 +01001786 resets = <&reset_scmi 3>;
1787 regul0-supply = <&regul0_scmi>;
1788 regul1-supply = <&regul1_scmi>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001789 };
1790
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001791 pinctrl {
1792 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001793
Sean Anderson3438e3b2020-09-14 11:01:57 -04001794 pinctrl-names = "default", "alternate";
1795 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1796 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001797
Sean Anderson3438e3b2020-09-14 11:01:57 -04001798 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001799 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001800 pins = "P5";
1801 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001802 bias-pull-up;
1803 input-disable;
1804 };
1805 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001806 pins = "P6";
1807 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001808 output-high;
1809 drive-open-drain;
1810 };
1811 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001812 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001813 bias-pull-down;
1814 input-enable;
1815 };
1816 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001817 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001818 bias-disable;
1819 };
1820 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001821
1822 pinctrl_i2c: i2c {
1823 groups {
1824 groups = "I2C_UART";
1825 function = "I2C";
1826 };
1827
1828 pins {
1829 pins = "P0", "P1";
1830 drive-open-drain;
1831 };
1832 };
1833
1834 pinctrl_i2s: i2s {
1835 groups = "SPI_I2S";
1836 function = "I2S";
1837 };
1838
1839 pinctrl_spi: spi {
1840 groups = "SPI_I2S";
1841 function = "SPI";
1842
1843 cs {
1844 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1845 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1846 };
1847 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001848 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001849
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001850 pinctrl-single-no-width {
1851 compatible = "pinctrl-single";
1852 reg = <0x0000 0x238>;
1853 #pinctrl-cells = <1>;
1854 pinctrl-single,function-mask = <0x7f>;
1855 };
1856
1857 pinctrl-single-pins {
1858 compatible = "pinctrl-single";
1859 reg = <0x0000 0x238>;
1860 #pinctrl-cells = <1>;
1861 pinctrl-single,register-width = <32>;
1862 pinctrl-single,function-mask = <0x7f>;
1863
1864 pinmux_pwm_pins: pinmux_pwm_pins {
1865 pinctrl-single,pins = < 0x48 0x06 >;
1866 };
1867
1868 pinmux_spi0_pins: pinmux_spi0_pins {
1869 pinctrl-single,pins = <
1870 0x190 0x0c
1871 0x194 0x0c
1872 0x198 0x23
1873 0x19c 0x0c
1874 >;
1875 };
1876
1877 pinmux_uart0_pins: pinmux_uart0_pins {
1878 pinctrl-single,pins = <
1879 0x70 0x30
1880 0x74 0x00
1881 >;
1882 };
1883 };
1884
1885 pinctrl-single-bits {
1886 compatible = "pinctrl-single";
1887 reg = <0x0000 0x50>;
1888 #pinctrl-cells = <2>;
1889 pinctrl-single,bit-per-mux;
1890 pinctrl-single,register-width = <32>;
1891 pinctrl-single,function-mask = <0xf>;
1892
1893 pinmux_i2c0_pins: pinmux_i2c0_pins {
1894 pinctrl-single,bits = <
1895 0x10 0x00002200 0x0000ff00
1896 >;
1897 };
1898
1899 pinmux_lcd_pins: pinmux_lcd_pins {
1900 pinctrl-single,bits = <
1901 0x40 0x22222200 0xffffff00
1902 0x44 0x22222222 0xffffffff
1903 0x48 0x00000022 0x000000ff
1904 0x48 0x02000000 0x0f000000
1905 0x4c 0x02000022 0x0f0000ff
1906 >;
1907 };
1908 };
1909
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001910 hwspinlock@0 {
1911 compatible = "sandbox,hwspinlock";
1912 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001913
1914 dma: dma {
1915 compatible = "sandbox,dma";
1916 #dma-cells = <1>;
1917
1918 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1919 dma-names = "m2m", "tx0", "rx0";
1920 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001921
Alex Marginean0649be52019-07-12 10:13:53 +03001922 /*
1923 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1924 * end of the test. If parent mdio is removed first, clean-up of the
1925 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1926 * active at the end of the test. That it turn doesn't allow the mdio
1927 * class to be destroyed, triggering an error.
1928 */
1929 mdio-mux-test {
1930 compatible = "sandbox,mdio-mux";
1931 #address-cells = <1>;
1932 #size-cells = <0>;
1933 mdio-parent-bus = <&mdio>;
1934
1935 mdio-ch-test@0 {
1936 reg = <0>;
1937 };
1938 mdio-ch-test@1 {
1939 reg = <1>;
1940 };
1941 };
1942
1943 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001944 compatible = "sandbox,mdio";
Marek Behúnf4f1ddc2022-04-07 00:32:57 +02001945 #address-cells = <1>;
1946 #size-cells = <0>;
1947
1948 ethphy1: ethernet-phy@1 {
1949 reg = <1>;
1950 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001951 };
Sean Andersonb7860542020-06-24 06:41:12 -04001952
1953 pm-bus-test {
1954 compatible = "simple-pm-bus";
1955 clocks = <&clk_sandbox 4>;
1956 power-domains = <&pwrdom 1>;
1957 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001958
1959 resetc2: syscon-reset {
1960 compatible = "syscon-reset";
1961 #reset-cells = <1>;
1962 regmap = <&syscon0>;
1963 offset = <1>;
1964 mask = <0x27FFFFFF>;
1965 assert-high = <0>;
1966 };
1967
1968 syscon-reset-test {
1969 compatible = "sandbox,misc_sandbox";
1970 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1971 reset-names = "valid", "no_mask", "out_of_range";
1972 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301973
Simon Glass458b66a2020-11-05 06:32:05 -07001974 sysinfo {
1975 compatible = "sandbox,sysinfo-sandbox";
1976 };
1977
Sean Anderson1c830672021-04-20 10:50:58 -04001978 sysinfo-gpio {
1979 compatible = "gpio-sysinfo";
1980 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1981 revisions = <19>, <5>;
1982 names = "rev_a", "foo";
1983 };
1984
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301985 some_regmapped-bus {
1986 #address-cells = <0x1>;
1987 #size-cells = <0x1>;
1988
1989 ranges = <0x0 0x0 0x10>;
1990 compatible = "simple-bus";
1991
1992 regmap-test_0 {
1993 reg = <0 0x10>;
1994 compatible = "sandbox,regmap_test";
1995 };
1996 };
Robert Marko9cf87122022-09-06 13:30:35 +02001997
1998 thermal {
1999 compatible = "sandbox,thermal";
2000 };
Sughosh Ganu77079e72022-10-21 18:16:05 +05302001
2002 fwu-mdata {
2003 compatible = "u-boot,fwu-mdata-gpt";
2004 fwu-mdata-store = <&mmc0>;
2005 };
Abdellatif El Khlifi6b005872023-04-17 10:11:55 +01002006
2007 nvmxip-qspi1@08000000 {
2008 compatible = "nvmxip,qspi";
2009 reg = <0x08000000 0x00200000>;
2010 lba_shift = <9>;
2011 lba = <4096>;
2012 };
2013
2014 nvmxip-qspi2@08200000 {
2015 compatible = "nvmxip,qspi";
2016 reg = <0x08200000 0x00100000>;
2017 lba_shift = <9>;
2018 lba = <2048>;
2019 };
Svyatoslav Ryhel669f5c82023-04-25 10:57:21 +03002020
2021 extcon {
2022 compatible = "sandbox,extcon";
2023 };
Abdellatif El Khlifi4970d5b2023-08-04 14:33:41 +01002024
2025 arm-ffa-emul {
2026 compatible = "sandbox,arm-ffa-emul";
2027
2028 sandbox-arm-ffa {
2029 compatible = "sandbox,arm-ffa";
2030 };
2031 };
Sean Anderson326422b2023-11-04 16:37:52 -04002032
2033 nand-controller {
2034 #address-cells = <1>;
2035 #size-cells = <0>;
2036 compatible = "sandbox,nand";
2037
2038 nand@0 {
2039 reg = <0>;
2040 nand-ecc-mode = "soft";
2041 sandbox,id = [00 e3];
2042 sandbox,erasesize = <(8 * 1024)>;
2043 sandbox,oobsize = <16>;
2044 sandbox,pagesize = <512>;
2045 sandbox,pages = <0x2000>;
2046 sandbox,err-count = <1>;
2047 sandbox,err-step-size = <512>;
2048 };
2049
2050 /* MT29F64G08AKABA */
2051 nand@1 {
2052 reg = <1>;
2053 nand-ecc-mode = "soft_bch";
2054 sandbox,id = [2C 48 00 26 89 00 00 00];
2055 sandbox,onfi = [
2056 4f 4e 46 49 0e 00 5a 00
2057 ff 01 00 00 00 00 03 00
2058 00 00 00 00 00 00 00 00
2059 00 00 00 00 00 00 00 00
2060 4d 49 43 52 4f 4e 20 20
2061 20 20 20 20 4d 54 32 39
2062 46 36 34 47 30 38 41 4b
2063 41 42 41 43 35 20 20 20
2064 2c 00 00 00 00 00 00 00
2065 00 00 00 00 00 00 00 00
2066 00 10 00 00 e0 00 00 02
2067 00 00 1c 00 80 00 00 00
2068 00 10 00 00 02 23 01 50
2069 00 01 05 01 00 00 04 00
2070 04 01 1e 00 00 00 00 00
2071 00 00 00 00 00 00 00 00
2072 0e 1f 00 1f 00 f4 01 ac
2073 0d 19 00 c8 00 00 00 00
2074 00 00 00 00 00 00 0a 07
2075 19 00 00 00 00 00 00 00
2076 00 00 00 00 01 00 01 00
2077 00 00 04 10 01 81 04 02
2078 02 01 1e 90 00 00 00 00
2079 00 00 00 00 00 00 00 00
2080 00 00 00 00 00 00 00 00
2081 00 00 00 00 00 00 00 00
2082 00 00 00 00 00 00 00 00
2083 00 00 00 00 00 00 00 00
2084 00 00 00 00 00 00 00 00
2085 00 00 00 00 00 00 00 00
2086 00 00 00 00 00 00 00 00
2087 00 00 00 00 00 03 20 7d
2088 ];
2089 sandbox,erasesize = <(512 * 1024)>;
2090 sandbox,oobsize = <224>;
2091 sandbox,pagesize = <4096>;
2092 sandbox,pages = <0x200000>;
2093 sandbox,err-count = <3>;
2094 sandbox,err-step-size = <512>;
2095 };
2096 };
Svyatoslav Ryhel1f5298f2025-02-16 13:14:40 +02002097
2098 graph1 {
2099 ports {
2100 #address-cells = <1>;
2101 #size-cells = <0>;
2102
2103 port@0 {
2104 #address-cells = <1>;
2105 #size-cells = <0>;
2106
2107 reg = <0>;
2108
2109 endpoint@0 {
2110 reg = <0>;
2111 };
2112
2113 endpoint@1 {
2114 reg = <1>;
2115 };
2116 };
2117
2118 port@1 {
2119 reg = <1>;
2120
2121 endpoint {
2122 test-property-0;
2123 };
2124 };
2125
2126 port@2 {
2127 #address-cells = <1>;
2128 #size-cells = <0>;
2129
2130 reg = <2>;
2131
2132 graph2_link: endpoint@0 {
2133 reg = <0>;
2134 test-property-1;
2135 remote-endpoint = <&graph1_link>;
2136 };
2137
2138 endpoint@1 {
2139 reg = <1>;
2140 };
2141 };
2142 };
2143 };
2144
2145 graph2 {
2146 port {
2147 graph1_link: endpoint {
2148 remote-endpoint = <&graph2_link>;
2149 };
2150 };
2151 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07002152};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02002153
2154#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01002155#include "cros-ec-keyboard.dtsi"
Simon Glass5e135d32022-10-20 18:23:15 -06002156
2157#ifdef CONFIG_SANDBOX_VPL
2158#include "sandbox_vpl.dtsi"
2159#endif
Simon Glass61300722023-06-01 10:23:01 -06002160
Sughosh Ganu05137922024-03-27 16:19:00 +05302161#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
2162#include "sandbox_capsule.dtsi"
2163#endif
2164
Simon Glass61300722023-06-01 10:23:01 -06002165#include "cedit.dtsi"