blob: 36cfbf213e4cfe17d9ca98d6e40f7caf95631254 [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Eddie James1a55a7a2023-10-24 10:43:51 -050012#include <config.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010013#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010015#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040016#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053017#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010018
Simon Glassb2c1cac2014-02-26 15:59:21 -070019/ {
20 model = "sandbox";
21 compatible = "sandbox";
22 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060023 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070024
Simon Glassfef72b72014-07-23 06:55:03 -060025 aliases {
26 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010027 ethernet0 = "/eth@10002000";
28 ethernet2 = &swp_0;
29 ethernet3 = &eth_3;
30 ethernet4 = &dsa_eth0;
31 ethernet5 = &eth_5;
Sean Anderson67d93a42022-05-05 13:11:30 -040032 ethernet6 = "/eth@10004000";
33 ethernet7 = &swp_1;
34 ethernet8 = &phy_eth0;
Simon Glass5620cf82018-10-01 12:22:40 -060035 gpio1 = &gpio_a;
36 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010037 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070038 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060039 mmc0 = "/mmc0";
40 mmc1 = "/mmc1";
Simon Glassf1eba352022-10-20 18:23:20 -060041 mmc2 = "/mmc2";
42 mmc3 = "/mmc3";
Simon Glassfff928c2023-08-24 13:55:41 -060043 mmc4 = "/mmc4";
44 mmc5 = "/mmc5";
Alexander Gendin038cb022023-10-09 01:24:36 +000045 mmc6 = "/mmc6";
Mattijs Korpershoekd77f8152024-07-10 10:40:06 +020046 mmc7 = "/mmc7";
Guillaume La Roque368ad9e2024-11-26 09:06:13 +010047 mmc8 = "/mmc8";
Bin Meng408e5902018-08-03 01:14:41 -070048 pci0 = &pci0;
49 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070050 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020051 remoteproc0 = &rproc_1;
52 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060053 rtc0 = &rtc_0;
54 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060055 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020056 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070057 testbus3 = "/some-bus";
58 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070059 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070060 testfdt3 = "/b-test";
61 testfdt5 = "/some-bus/c-test@5";
62 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070063 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020064 fdt-dummy0 = "/translation-test@8000/dev@0,0";
65 fdt-dummy1 = "/translation-test@8000/dev@1,100";
66 fdt-dummy2 = "/translation-test@8000/dev@2,200";
67 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060068 usb0 = &usb_0;
69 usb1 = &usb_1;
70 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020071 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020072 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060073 };
74
Eddie James1a55a7a2023-10-24 10:43:51 -050075 reserved-memory {
76 #address-cells = <1>;
77 #size-cells = <1>;
78 ranges;
79
80 event_log: tcg_event_log {
81 no-map;
Sughosh Ganu3f768682024-08-26 17:29:32 +053082 reg = <(CFG_SYS_SDRAM_BASE + 0x100000) 0x2000>;
Eddie James1a55a7a2023-10-24 10:43:51 -050083 };
84 };
85
Simon Glass5e135d32022-10-20 18:23:15 -060086 binman: binman {
Philippe Reynes462d1632022-03-28 22:56:53 +020087 };
88
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020089 config {
Simon Glass0034d962021-08-07 07:24:01 -060090 testing-bool;
91 testing-int = <123>;
92 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020093 environment {
94 from_fdt = "yes";
95 fdt_env_path = "";
96 };
97 };
98
Michal Simek43c42bd2023-08-31 08:59:05 +020099 options {
100 u-boot {
101 compatible = "u-boot,config";
102 bootscr-ram-offset = /bits/ 64 <0x12345678>;
Michal Simek6a7c1ce2023-08-31 09:04:27 +0200103 bootscr-flash-offset = /bits/ 64 <0>;
104 bootscr-flash-size = /bits/ 64 <0x2000>;
Christian Marangi719108e2024-10-01 14:24:43 +0200105 boot-led = "sandbox:green";
106 activity-led = "sandbox:red";
Christian Marangicdc38152024-10-01 14:24:44 +0200107 testing-bool;
108 testing-int = <123>;
109 testing-str = "testing";
Michal Simek43c42bd2023-08-31 08:59:05 +0200110 };
111 };
112
Simon Glassb255efc2022-04-24 23:31:24 -0600113 bootstd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700114 bootph-verify;
Simon Glassb255efc2022-04-24 23:31:24 -0600115 compatible = "u-boot,boot-std";
116
117 filename-prefixes = "/", "/boot/";
118 bootdev-order = "mmc2", "mmc1";
119
Simon Glassb71d7f72023-05-10 16:34:46 -0600120 extlinux {
121 compatible = "u-boot,extlinux";
Simon Glassb255efc2022-04-24 23:31:24 -0600122 };
123
124 efi {
125 compatible = "u-boot,distro-efi";
126 };
Simon Glassa9289612022-10-20 18:23:14 -0600127
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600128 theme {
129 font-size = <30>;
Simon Glass86f1ac52023-06-01 10:23:00 -0600130 menu-inset = <3>;
131 menuitem-gap-y = <1>;
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600132 };
133
Simon Glass82adc292023-08-14 16:40:30 -0600134 cedit-theme {
135 font-size = <30>;
136 menu-inset = <3>;
137 menuitem-gap-y = <1>;
138 };
139
Simon Glassf1eba352022-10-20 18:23:20 -0600140 /*
141 * This is used for the VBE OS-request tests. A FAT filesystem
142 * created in a partition with the VBE information appearing
Michal Simek33224372023-09-07 14:55:48 +0200143 * before the partition starts
Simon Glassf1eba352022-10-20 18:23:20 -0600144 */
Simon Glassa9289612022-10-20 18:23:14 -0600145 firmware0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700146 bootph-verify;
Simon Glassa9289612022-10-20 18:23:14 -0600147 compatible = "fwupd,vbe-simple";
148 storage = "mmc1";
149 skip-offset = <0x200>;
150 area-start = <0x400>;
151 area-size = <0x1000>;
152 state-offset = <0x400>;
153 state-size = <0x40>;
154 version-offset = <0x800>;
155 version-size = <0x100>;
156 };
Simon Glassf1eba352022-10-20 18:23:20 -0600157
158 /*
159 * This is used for the VBE VPL tests. The MMC device holds the
160 * binman image.bin file. The test progresses through each phase
161 * of U-Boot, loading each in turn from MMC.
162 *
163 * Note that the test enables this node (and mmc3) before
164 * running U-Boot
165 */
166 firmware1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700167 bootph-verify;
Simon Glassf1eba352022-10-20 18:23:20 -0600168 status = "disabled";
169 compatible = "fwupd,vbe-simple";
170 storage = "mmc3";
Simon Glass9bb73e32023-04-02 14:01:24 +1200171 skip-offset = <0x800000>;
Simon Glassf1eba352022-10-20 18:23:20 -0600172 area-start = <0>;
173 area-size = <0xe00000>;
174 state-offset = <0xdffc00>;
175 state-size = <0x40>;
176 version-offset = <0xdffe00>;
177 version-size = <0x100>;
178 };
Simon Glassb255efc2022-04-24 23:31:24 -0600179 };
180
Simon Glass61300722023-06-01 10:23:01 -0600181 cedit: cedit {
182 };
183
Andrew Scull451b8b12022-05-30 10:00:12 +0000184 fuzzing-engine {
185 compatible = "sandbox,fuzzing-engine";
186 };
187
Nandor Han6521e5d2021-06-10 16:56:44 +0300188 reboot-mode0 {
189 compatible = "reboot-mode-gpio";
190 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
191 u-boot,env-variable = "bootstatus";
192 mode-test = <0x01>;
193 mode-download = <0x03>;
194 };
195
Nandor Han7e4067a2021-06-10 16:56:45 +0300196 reboot_mode1: reboot-mode@14 {
197 compatible = "reboot-mode-rtc";
198 rtc = <&rtc_0>;
199 reg = <0x30 4>;
200 u-boot,env-variable = "bootstatus";
201 big-endian;
202 mode-test = <0x21969147>;
203 mode-download = <0x51939147>;
204 };
205
Simon Glassed96cde2018-12-10 10:37:33 -0700206 audio: audio-codec {
207 compatible = "sandbox,audio-codec";
208 #sound-dai-cells = <1>;
209 };
210
Philippe Reynes1ee26482020-07-24 18:19:51 +0200211 buttons {
212 compatible = "gpio-keys";
213
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200214 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200215 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200216 label = "button1";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300217 linux,code = <BTN_1>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200218 };
219
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200220 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200221 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200222 label = "button2";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300223 linux,code = <BTN_2>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200224 };
225 };
226
Marek Szyprowskiad398592021-02-18 11:33:18 +0100227 buttons2 {
228 compatible = "adc-keys";
229 io-channels = <&adc 3>;
230 keyup-threshold-microvolt = <3000000>;
231
232 button-up {
233 label = "button3";
234 linux,code = <KEY_F3>;
235 press-threshold-microvolt = <1500000>;
236 };
237
238 button-down {
239 label = "button4";
240 linux,code = <KEY_F4>;
241 press-threshold-microvolt = <1000000>;
242 };
243
244 button-enter {
245 label = "button5";
246 linux,code = <KEY_F5>;
247 press-threshold-microvolt = <500000>;
248 };
249 };
250
Simon Glassc953aaf2018-12-10 10:37:34 -0700251 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600252 reg = <0 0>;
253 compatible = "google,cros-ec-sandbox";
254
255 /*
256 * This describes the flash memory within the EC. Note
257 * that the STM32L flash erases to 0, not 0xff.
258 */
259 flash {
260 image-pos = <0x08000000>;
261 size = <0x20000>;
262 erase-value = <0>;
263
264 /* Information for sandbox */
265 ro {
266 image-pos = <0>;
267 size = <0xf000>;
268 };
269 wp-ro {
270 image-pos = <0xf000>;
271 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700272 used = <0x884>;
273 compress = "lz4";
274 uncomp-size = <0xcf8>;
275 hash {
276 algo = "sha256";
277 value = [00 01 02 03 04 05 06 07
278 08 09 0a 0b 0c 0d 0e 0f
279 10 11 12 13 14 15 16 17
280 18 19 1a 1b 1c 1d 1e 1f];
281 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600282 };
283 rw {
284 image-pos = <0x10000>;
285 size = <0x10000>;
286 };
287 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300288
289 cros_ec_pwm: cros-ec-pwm {
290 compatible = "google,cros-ec-pwm";
291 #pwm-cells = <1>;
292 };
293
Simon Glass699c9ca2018-10-01 12:22:08 -0600294 };
295
Yannick Fertré9712c822019-10-07 15:29:05 +0200296 dsi_host: dsi_host {
297 compatible = "sandbox,dsi-host";
298 };
299
Simon Glassb2c1cac2014-02-26 15:59:21 -0700300 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600301 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700302 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600303 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700304 ping-add = <0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700305 bootph-all;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100306 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
307 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700308 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100309 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
310 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
311 <&gpio_b 7 GPIO_IN 3 2 1>,
312 <&gpio_b 8 GPIO_OUT 3 2 1>,
313 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100314 test3-gpios =
315 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
316 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
317 <&gpio_c 2 GPIO_OUT>,
318 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
319 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200320 <&gpio_c 5 GPIO_IN>,
321 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
322 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530323 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
324 test5-gpios = <&gpio_a 19>;
325
Simon Glass73025392021-10-23 17:26:04 -0600326 bool-value;
Stefan Herbrechtsmeier1b090e62022-06-14 15:21:30 +0200327 int8-value = /bits/ 8 <0x12>;
328 int16-value = /bits/ 16 <0x1234>;
Simon Glass6df01f92018-12-10 10:37:37 -0700329 int-value = <1234>;
330 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200331 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200332 int-array = <5678 9123 4567>;
Michal Simek08a194e2023-08-25 11:37:46 +0200333 int64-array = /bits/ 64 <0x1111222233334444 0x4444333322221111>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600334 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700335 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600336 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200337 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530338
339 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
340 <&muxcontroller0 2>, <&muxcontroller0 3>,
341 <&muxcontroller1>;
342 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
343 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100344 display-timings {
345 timing0: 240x320 {
346 clock-frequency = <6500000>;
347 hactive = <240>;
348 vactive = <320>;
349 hfront-porch = <6>;
350 hback-porch = <7>;
351 hsync-len = <1>;
352 vback-porch = <5>;
353 vfront-porch = <8>;
354 vsync-len = <2>;
355 hsync-active = <1>;
356 vsync-active = <0>;
357 de-active = <1>;
358 pixelclk-active = <1>;
359 interlaced;
360 doublescan;
361 doubleclk;
362 };
363 timing1: 480x800 {
364 clock-frequency = <9000000>;
365 hactive = <480>;
366 vactive = <800>;
367 hfront-porch = <10>;
368 hback-porch = <59>;
369 hsync-len = <12>;
370 vback-porch = <15>;
371 vfront-porch = <17>;
372 vsync-len = <16>;
373 hsync-active = <0>;
374 vsync-active = <1>;
375 de-active = <0>;
376 pixelclk-active = <0>;
377 };
378 timing2: 800x480 {
379 clock-frequency = <33500000>;
380 hactive = <800>;
381 vactive = <480>;
382 hback-porch = <89>;
383 hfront-porch = <164>;
384 vback-porch = <23>;
385 vfront-porch = <10>;
386 hsync-len = <11>;
387 vsync-len = <13>;
388 };
389 };
Raphael Gallais-Poua853b922023-05-11 16:36:52 +0200390 panel-timing {
Nikhil M Jainbb9d1312023-01-31 15:35:15 +0530391 clock-frequency = <6500000>;
392 hactive = <240>;
393 vactive = <320>;
394 hfront-porch = <6>;
395 hback-porch = <7>;
396 hsync-len = <1>;
397 vback-porch = <5>;
398 vfront-porch = <8>;
399 vsync-len = <2>;
400 hsync-active = <1>;
401 vsync-active = <0>;
402 de-active = <1>;
403 pixelclk-active = <1>;
404 interlaced;
405 doublescan;
406 doubleclk;
407 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700408 };
409
410 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600411 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700412 compatible = "not,compatible";
413 };
414
415 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600416 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700417 };
418
Simon Glass5620cf82018-10-01 12:22:40 -0600419 backlight: backlight {
420 compatible = "pwm-backlight";
421 enable-gpios = <&gpio_a 1>;
422 power-supply = <&ldo_1>;
423 pwms = <&pwm 0 1000>;
424 default-brightness-level = <5>;
425 brightness-levels = <0 16 32 64 128 170 202 234 255>;
426 };
427
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200428 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200429 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200430 bind-test-child1 {
431 compatible = "sandbox,phy";
432 #phy-cells = <1>;
433 };
434
435 bind-test-child2 {
436 compatible = "simple-bus";
437 };
438 };
439
Simon Glassb2c1cac2014-02-26 15:59:21 -0700440 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600441 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700442 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600443 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700444 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530445
446 mux-controls = <&muxcontroller0 0>;
447 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700448 };
449
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200450 phy_provider0: gen_phy@0 {
451 compatible = "sandbox,phy";
452 #phy-cells = <1>;
453 };
454
455 phy_provider1: gen_phy@1 {
456 compatible = "sandbox,phy";
457 #phy-cells = <0>;
458 broken;
459 };
460
developer71092972020-05-02 11:35:12 +0200461 phy_provider2: gen_phy@2 {
462 compatible = "sandbox,phy";
463 #phy-cells = <0>;
464 };
465
Jonas Karlman9f89e682023-08-31 22:16:35 +0000466 phy_provider3: gen_phy@3 {
467 compatible = "sandbox,phy";
468 #phy-cells = <2>;
469 };
470
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200471 gen_phy_user: gen_phy_user {
472 compatible = "simple-bus";
473 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
474 phy-names = "phy1", "phy2", "phy3";
475 };
476
developer71092972020-05-02 11:35:12 +0200477 gen_phy_user1: gen_phy_user1 {
478 compatible = "simple-bus";
479 phys = <&phy_provider0 0>, <&phy_provider2>;
480 phy-names = "phy1", "phy2";
481 };
482
Jonas Karlman9f89e682023-08-31 22:16:35 +0000483 gen_phy_user2: gen_phy_user2 {
484 compatible = "simple-bus";
485 phys = <&phy_provider3 0 0>;
486 phy-names = "phy1";
487 };
488
Simon Glassb2c1cac2014-02-26 15:59:21 -0700489 some-bus {
490 #address-cells = <1>;
491 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600492 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600493 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600494 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700495 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600496 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700497 compatible = "denx,u-boot-fdt-test";
498 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600499 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700500 ping-add = <5>;
501 };
Simon Glass40717422014-07-23 06:55:18 -0600502 c-test@0 {
503 compatible = "denx,u-boot-fdt-test";
504 reg = <0>;
505 ping-expect = <6>;
506 ping-add = <6>;
507 };
508 c-test@1 {
509 compatible = "denx,u-boot-fdt-test";
510 reg = <1>;
511 ping-expect = <7>;
512 ping-add = <7>;
513 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700514 };
515
516 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600517 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600518 ping-expect = <6>;
519 ping-add = <6>;
520 compatible = "google,another-fdt-test";
521 };
522
523 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600524 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600525 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700526 ping-add = <6>;
527 compatible = "google,another-fdt-test";
528 };
529
Simon Glass0ccb0972015-01-25 08:27:05 -0700530 f-test {
Patrick Rudolph0fe88cc2024-10-23 15:20:05 +0200531 #interrupt-cells = <2>;
532 interrupt-parent = <&irq>;
533 interrupts = <4 0>;
Simon Glass0ccb0972015-01-25 08:27:05 -0700534 compatible = "denx,u-boot-fdt-test";
535 };
536
537 g-test {
538 compatible = "denx,u-boot-fdt-test";
539 };
540
Bin Mengd9d24782018-10-10 22:07:01 -0700541 h-test {
542 compatible = "denx,u-boot-fdt-test1";
543 };
544
developercf8bc132020-05-02 11:35:10 +0200545 i-test {
546 compatible = "mediatek,u-boot-fdt-test";
547 #address-cells = <1>;
548 #size-cells = <0>;
549
550 subnode@0 {
551 reg = <0>;
552 };
553
554 subnode@1 {
555 reg = <1>;
556 };
557
558 subnode@2 {
559 reg = <2>;
560 };
561 };
562
Simon Glass204675c2019-12-29 21:19:25 -0700563 devres-test {
564 compatible = "denx,u-boot-devres-test";
565 };
566
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530567 another-test {
568 reg = <0 2>;
569 compatible = "denx,u-boot-fdt-test";
570 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
571 test5-gpios = <&gpio_a 19>;
572 };
573
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100574 mmio-bus@0 {
575 #address-cells = <1>;
576 #size-cells = <1>;
577 compatible = "denx,u-boot-test-bus";
578 dma-ranges = <0x10000000 0x00000000 0x00040000>;
579
580 subnode@0 {
581 compatible = "denx,u-boot-fdt-test";
582 };
583 };
584
585 mmio-bus@1 {
586 #address-cells = <1>;
587 #size-cells = <1>;
588 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100589
590 subnode@0 {
591 compatible = "denx,u-boot-fdt-test";
592 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100593 };
594
Simon Glass3c601b12020-07-07 13:12:06 -0600595 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600596 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600597 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600598 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600599 child {
600 compatible = "denx,u-boot-acpi-test";
601 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600602 };
603
Simon Glass3c601b12020-07-07 13:12:06 -0600604 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600605 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600606 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600607 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600608 };
609
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200610 clocks {
611 clk_fixed: clk-fixed {
612 compatible = "fixed-clock";
613 #clock-cells = <0>;
614 clock-frequency = <1234>;
615 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000616
617 clk_fixed_factor: clk-fixed-factor {
618 compatible = "fixed-factor-clock";
619 #clock-cells = <0>;
620 clock-div = <3>;
621 clock-mult = <2>;
622 clocks = <&clk_fixed>;
623 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200624
625 osc {
626 compatible = "fixed-clock";
627 #clock-cells = <0>;
628 clock-frequency = <20000000>;
629 };
Stephen Warrena9622432016-06-17 09:44:00 -0600630 };
631
632 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600633 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600634 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200635 assigned-clocks = <&clk_sandbox 3>;
636 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600637 };
638
639 clk-test {
640 compatible = "sandbox,clk-test";
641 clocks = <&clk_fixed>,
642 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200643 <&clk_sandbox 0>,
Yang Xiwene89289c2023-12-16 02:28:52 +0800644 <&ccf 11>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200645 <&clk_sandbox 3>,
646 <&clk_sandbox 2>;
Yang Xiwene89289c2023-12-16 02:28:52 +0800647 clock-names = "fixed", "i2c", "spi", "i2c_root", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600648 };
649
Ashok Reddy Soma8f03cef2023-08-30 10:31:42 +0200650 clk-test2 {
651 compatible = "sandbox,clk-test";
652 assigned-clock-rates = <321>;
653 };
654
655 clk-test3 {
656 compatible = "sandbox,clk-test";
657 assigned-clocks = <&clk_sandbox 1>;
658 };
659
660 clk-test4 {
661 compatible = "sandbox,clk-test";
662 assigned-clock-rates = <654>, <321>;
663 assigned-clocks = <&clk_sandbox 1>;
664 };
665
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200666 ccf: clk-ccf {
667 compatible = "sandbox,clk-ccf";
Yang Xiwene89289c2023-12-16 02:28:52 +0800668 #clock-cells = <1>;
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200669 };
670
Simon Glass507ab962021-12-04 08:56:31 -0700671 efi-media {
672 compatible = "sandbox,efi-media";
673 };
674
Simon Glass5b968632015-05-22 15:42:15 -0600675 eth@10002000 {
676 compatible = "sandbox,eth";
677 reg = <0x10002000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600678 };
679
680 eth_5: eth@10003000 {
681 compatible = "sandbox,eth";
682 reg = <0x10003000 0x1000>;
Sean Anderson13652b82022-05-05 13:11:44 -0400683 nvmem-cells = <&eth5_addr>;
684 nvmem-cell-names = "mac-address";
Simon Glass5b968632015-05-22 15:42:15 -0600685 };
686
Bin Meng04a11cb2015-08-27 22:25:53 -0700687 eth_3: sbe5 {
688 compatible = "sandbox,eth";
689 reg = <0x10005000 0x1000>;
Sean Andersone2dc0e62022-05-05 13:11:42 -0400690 nvmem-cells = <&eth3_addr>;
691 nvmem-cell-names = "mac-address";
Bin Meng04a11cb2015-08-27 22:25:53 -0700692 };
693
Simon Glass5b968632015-05-22 15:42:15 -0600694 eth@10004000 {
695 compatible = "sandbox,eth";
696 reg = <0x10004000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600697 };
698
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200699 phy_eth0: phy-test-eth {
700 compatible = "sandbox,eth";
701 reg = <0x10007000 0x1000>;
Sean Anderson24b1b8d2022-05-05 13:11:35 -0400702 mac-address = [ 02 00 11 22 33 49 ];
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200703 phy-handle = <&ethphy1>;
Marek Behúnbc194772022-04-07 00:33:01 +0200704 phy-mode = "2500base-x";
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200705 };
706
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800707 dsa_eth0: dsa-test-eth {
708 compatible = "sandbox,eth";
709 reg = <0x10006000 0x1000>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400710 nvmem-cells = <&eth4_addr>;
711 nvmem-cell-names = "mac-address";
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800712 };
713
714 dsa-test {
715 compatible = "sandbox,dsa";
716
717 ports {
718 #address-cells = <1>;
719 #size-cells = <0>;
720 swp_0: port@0 {
721 reg = <0>;
722 label = "lan0";
723 phy-mode = "rgmii-rxid";
724
725 fixed-link {
726 speed = <100>;
727 full-duplex;
728 };
729 };
730
731 swp_1: port@1 {
732 reg = <1>;
733 label = "lan1";
734 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800735 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800736 };
737
738 port@2 {
739 reg = <2>;
740 ethernet = <&dsa_eth0>;
741
742 fixed-link {
743 speed = <1000>;
744 full-duplex;
745 };
746 };
747 };
748 };
749
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700750 firmware {
751 sandbox_firmware: sandbox-firmware {
752 compatible = "sandbox,firmware";
753 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200754
Etienne Carriere09665cb2022-02-21 09:22:39 +0100755 scmi {
Etienne Carriere02fd1262020-09-09 18:44:00 +0200756 compatible = "sandbox,scmi-agent";
757 #address-cells = <1>;
758 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200759
AKASHI Takahiro535a7bd2023-10-16 14:39:45 +0900760 pwrdom_scmi: protocol@11 {
761 reg = <0x11>;
762 #power-domain-cells = <1>;
763 };
764
Etienne Carriere09665cb2022-02-21 09:22:39 +0100765 clk_scmi: protocol@14 {
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200766 reg = <0x14>;
767 #clock-cells = <1>;
AKASHI Takahirocc4ecda2023-10-11 19:06:59 +0900768 linaro,sandbox-channel-id = <0x14>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200769 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200770
Etienne Carriere09665cb2022-02-21 09:22:39 +0100771 reset_scmi: protocol@16 {
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200772 reg = <0x16>;
773 #reset-cells = <1>;
774 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100775
776 protocol@17 {
777 reg = <0x17>;
778
779 regulators {
780 #address-cells = <1>;
781 #size-cells = <0>;
782
Etienne Carriere09665cb2022-02-21 09:22:39 +0100783 regul0_scmi: reg@0 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100784 reg = <0>;
785 regulator-name = "sandbox-voltd0";
786 regulator-min-microvolt = <1100000>;
787 regulator-max-microvolt = <3300000>;
788 };
Etienne Carriere09665cb2022-02-21 09:22:39 +0100789 regul1_scmi: reg@1 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100790 reg = <0x1>;
791 regulator-name = "sandbox-voltd1";
792 regulator-min-microvolt = <1800000>;
793 };
794 };
795 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200796 };
Alexey Romanov9dc617d2023-09-21 11:13:36 +0300797
798 sm: secure-monitor {
799 compatible = "sandbox,sm";
800 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700801 };
802
Alexander Dahl6ac319d2022-09-30 14:04:30 +0200803 fpga {
804 compatible = "sandbox,fpga";
805 };
806
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100807 pinctrl-gpio {
808 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700809
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100810 gpio_a: base-gpios {
811 compatible = "sandbox,gpio";
812 gpio-controller;
813 #gpio-cells = <1>;
814 gpio-bank-name = "a";
815 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200816 hog_input_active_low {
817 gpio-hog;
818 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200819 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200820 };
821 hog_input_active_high {
822 gpio-hog;
823 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200824 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200825 };
826 hog_output_low {
827 gpio-hog;
828 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200829 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200830 };
831 hog_output_high {
832 gpio-hog;
833 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200834 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200835 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100836 };
837
838 gpio_b: extra-gpios {
839 compatible = "sandbox,gpio";
840 gpio-controller;
841 #gpio-cells = <5>;
842 gpio-bank-name = "b";
843 sandbox,gpio-count = <10>;
844 };
Simon Glass25348a42014-10-13 23:42:11 -0600845
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100846 gpio_c: pinmux-gpios {
847 compatible = "sandbox,gpio";
848 gpio-controller;
849 #gpio-cells = <2>;
850 gpio-bank-name = "c";
851 sandbox,gpio-count = <10>;
852 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100853 };
854
Simon Glass7df766e2014-12-10 08:55:55 -0700855 i2c@0 {
856 #address-cells = <1>;
857 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600858 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700859 compatible = "sandbox,i2c";
860 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200861 pinctrl-names = "default";
862 pinctrl-0 = <&pinmux_i2c0_pins>;
863
Simon Glass7df766e2014-12-10 08:55:55 -0700864 eeprom@2c {
Sean Andersone2dc0e62022-05-05 13:11:42 -0400865 #address-cells = <1>;
866 #size-cells = <1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700867 reg = <0x2c>;
868 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700869 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200870 partitions {
871 compatible = "fixed-partitions";
872 #address-cells = <1>;
873 #size-cells = <1>;
874 bootcount_i2c: bootcount@10 {
875 reg = <10 2>;
876 };
877 };
Sean Andersone2dc0e62022-05-05 13:11:42 -0400878
879 eth3_addr: mac-address@24 {
880 reg = <24 6>;
881 };
Simon Glass7df766e2014-12-10 08:55:55 -0700882 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200883
Simon Glass336b2952015-05-22 15:42:17 -0600884 rtc_0: rtc@43 {
Sean Anderson5768e8b2022-05-05 13:11:43 -0400885 #address-cells = <1>;
886 #size-cells = <1>;
Simon Glass336b2952015-05-22 15:42:17 -0600887 reg = <0x43>;
888 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700889 sandbox,emul = <&emul0>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400890
891 eth4_addr: mac-address@40 {
892 reg = <0x40 6>;
893 };
Simon Glass336b2952015-05-22 15:42:17 -0600894 };
895
896 rtc_1: rtc@61 {
897 reg = <0x61>;
898 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700899 sandbox,emul = <&emul1>;
900 };
901
902 i2c_emul: emul {
903 reg = <0xff>;
904 compatible = "sandbox,i2c-emul-parent";
905 emul_eeprom: emul-eeprom {
906 compatible = "sandbox,i2c-eeprom";
907 sandbox,filename = "i2c.bin";
908 sandbox,size = <256>;
909 };
910 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700911 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700912 };
913 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700914 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600915 };
916 };
917
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200918 sandbox_pmic: sandbox_pmic {
919 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700920 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200921 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200922
923 mc34708: pmic@41 {
924 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700925 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200926 };
Simon Glass7df766e2014-12-10 08:55:55 -0700927 };
928
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100929 bootcount@0 {
930 compatible = "u-boot,bootcount-rtc";
931 rtc = <&rtc_1>;
932 offset = <0x13>;
933 };
934
Michal Simek4f18f922020-05-28 11:48:55 +0200935 bootcount {
936 compatible = "u-boot,bootcount-i2c-eeprom";
937 i2c-eeprom = <&bootcount_i2c>;
938 };
939
Nandor Han88895812021-06-10 15:40:38 +0300940 bootcount_4@0 {
941 compatible = "u-boot,bootcount-syscon";
942 syscon = <&syscon0>;
943 reg = <0x0 0x04>, <0x0 0x04>;
944 reg-names = "syscon_reg", "offset";
945 };
946
947 bootcount_2@0 {
948 compatible = "u-boot,bootcount-syscon";
949 syscon = <&syscon0>;
950 reg = <0x0 0x04>, <0x0 0x02> ;
951 reg-names = "syscon_reg", "offset";
952 };
953
Marek Szyprowskiad398592021-02-18 11:33:18 +0100954 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100955 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100956 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100957 vdd-supply = <&buck2>;
958 vss-microvolts = <0>;
959 };
960
Mark Kettenis67748ee2021-10-23 16:58:02 +0200961 iommu: iommu@0 {
962 compatible = "sandbox,iommu";
963 #iommu-cells = <0>;
964 };
965
Simon Glass515dcff2020-02-06 09:55:00 -0700966 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700967 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700968 interrupt-controller;
969 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700970 };
971
Simon Glass90b6fef2016-01-18 19:52:26 -0700972 lcd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700973 bootph-all;
Simon Glass90b6fef2016-01-18 19:52:26 -0700974 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200975 pinctrl-names = "default";
976 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700977 xres = <1366>;
978 yres = <768>;
979 };
980
Simon Glassd783eb32015-07-06 12:54:34 -0600981 leds {
982 compatible = "gpio-leds";
983
984 iracibble {
985 gpios = <&gpio_a 1 0>;
986 label = "sandbox:red";
987 };
988
989 martinet {
990 gpios = <&gpio_a 2 0>;
991 label = "sandbox:green";
992 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200993
994 default_on {
995 gpios = <&gpio_a 5 0>;
996 label = "sandbox:default_on";
997 default-state = "on";
998 };
999
1000 default_off {
1001 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -04001002 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +02001003 default-state = "off";
1004 };
Simon Glassd783eb32015-07-06 12:54:34 -06001005 };
1006
Paul Doelle709f0372022-07-04 09:00:25 +00001007 wdt-gpio-toggle {
Simon Glasse0f8cd22023-08-10 09:53:13 -06001008 gpios = <&gpio_a 8 0>;
Rasmus Villemoes2b673872021-08-19 11:57:05 +02001009 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001010 hw_margin_ms = <100>;
Paul Doelle709f0372022-07-04 09:00:25 +00001011 hw_algo = "toggle";
1012 always-running;
1013 };
1014
1015 wdt-gpio-level {
1016 gpios = <&gpio_a 7 0>;
1017 compatible = "linux,wdt-gpio";
1018 hw_margin_ms = <100>;
1019 hw_algo = "level";
Rasmus Villemoes2b673872021-08-19 11:57:05 +02001020 always-running;
1021 };
1022
Stephen Warren62f2c902016-05-16 17:41:37 -06001023 mbox: mbox {
1024 compatible = "sandbox,mbox";
1025 #mbox-cells = <1>;
1026 };
1027
1028 mbox-test {
1029 compatible = "sandbox,mbox-test";
1030 mboxes = <&mbox 100>, <&mbox 1>;
1031 mbox-names = "other", "test";
1032 };
1033
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001034 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001035 #address-cells = <1>;
1036 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -04001037 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001038 cpu1: cpu@1 {
1039 device_type = "cpu";
1040 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -04001041 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001042 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001043 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001044 };
Mario Sixdea5df72018-08-06 10:23:44 +02001045
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001046 cpu2: cpu@2 {
1047 device_type = "cpu";
1048 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001049 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001050 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001051 };
Mario Sixdea5df72018-08-06 10:23:44 +02001052
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001053 cpu3: cpu@3 {
1054 device_type = "cpu";
1055 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001056 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001057 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001058 };
Mario Sixdea5df72018-08-06 10:23:44 +02001059 };
1060
Dave Gerlach75dbdfc2020-07-15 23:39:58 -05001061 chipid: chipid {
1062 compatible = "sandbox,soc";
1063 };
1064
Simon Glassc953aaf2018-12-10 10:37:34 -07001065 i2s: i2s {
1066 compatible = "sandbox,i2s";
1067 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -07001068 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -07001069 };
1070
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +02001071 nop-test_0 {
1072 compatible = "sandbox,nop_sandbox1";
1073 nop-test_1 {
1074 compatible = "sandbox,nop_sandbox2";
1075 bind = "True";
1076 };
1077 nop-test_2 {
1078 compatible = "sandbox,nop_sandbox2";
1079 bind = "False";
1080 };
1081 };
1082
Roger Quadrosb0679a72022-10-20 16:30:46 +03001083 memory-controller {
1084 compatible = "sandbox,memory";
1085 };
1086
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001087 misc-test {
Sean Anderson13652b82022-05-05 13:11:44 -04001088 #address-cells = <1>;
1089 #size-cells = <1>;
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001090 compatible = "sandbox,misc_sandbox";
Sean Anderson13652b82022-05-05 13:11:44 -04001091
1092 eth5_addr: mac-address@10 {
1093 reg = <0x10 6>;
1094 };
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001095 };
1096
Simon Glasse4fef742017-04-23 20:02:07 -06001097 mmc2 {
1098 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -06001099 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -06001100 };
1101
Simon Glassb255efc2022-04-24 23:31:24 -06001102 /* This is used for the bootdev tests */
Simon Glasse4fef742017-04-23 20:02:07 -06001103 mmc1 {
1104 compatible = "sandbox,mmc";
Simon Glassb255efc2022-04-24 23:31:24 -06001105 filename = "mmc1.img";
Simon Glasse4fef742017-04-23 20:02:07 -06001106 };
1107
Simon Glassb255efc2022-04-24 23:31:24 -06001108 /* This is used for the fastboot tests */
Sughosh Ganu77079e72022-10-21 18:16:05 +05301109 mmc0: mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -06001110 compatible = "sandbox,mmc";
1111 };
1112
Simon Glassf1eba352022-10-20 18:23:20 -06001113 /* This is used for VBE VPL tests */
1114 mmc3 {
1115 status = "disabled";
1116 compatible = "sandbox,mmc";
1117 filename = "image.bin";
1118 non-removable;
1119 };
1120
Simon Glassd2bc33ed2023-01-06 08:52:41 -06001121 /* This is used for bootstd bootmenu tests */
1122 mmc4 {
1123 status = "disabled";
1124 compatible = "sandbox,mmc";
1125 filename = "mmc4.img";
1126 };
1127
Simon Glassfff928c2023-08-24 13:55:41 -06001128 /* This is used for ChromiumOS tests */
1129 mmc5 {
1130 status = "disabled";
1131 compatible = "sandbox,mmc";
1132 filename = "mmc5.img";
1133 };
1134
Alexander Gendin038cb022023-10-09 01:24:36 +00001135 /* This is used for mbr tests */
1136 mmc6 {
1137 status = "disabled";
1138 compatible = "sandbox,mmc";
1139 filename = "mmc6.img";
1140 };
1141
Guillaume La Roque368ad9e2024-11-26 09:06:13 +01001142 /* This is used for Android boot image v4 tests */
Mattijs Korpershoekd77f8152024-07-10 10:40:06 +02001143 mmc7 {
1144 status = "disabled";
1145 compatible = "sandbox,mmc";
1146 filename = "mmc7.img";
1147 };
1148
Guillaume La Roque368ad9e2024-11-26 09:06:13 +01001149 /* This is used for Android boot image v2 tests. */
1150 mmc8 {
1151 status = "disabled";
1152 compatible = "sandbox,mmc";
1153 filename = "mmc8.img";
1154 };
1155
Simon Glass53a68b32019-02-16 20:24:50 -07001156 pch {
1157 compatible = "sandbox,pch";
1158 };
1159
Tom Rini4a3ca482020-02-11 12:41:23 -05001160 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -07001161 compatible = "sandbox,pci";
1162 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001163 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001164 #address-cells = <3>;
1165 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -06001166 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -07001167 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Mark Kettenis5dfd4ec2023-01-21 20:27:57 +01001168 iommu-map = <0x0010 &iommu 0 1>;
1169 iommu-map-mask = <0xfffffff8>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001170 pci@0,0 {
1171 compatible = "pci-generic";
1172 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001173 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001174 };
Alex Margineanf1274432019-06-07 11:24:24 +03001175 pci@1,0 {
1176 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001177 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
Simon Glass4289c262023-09-26 08:14:58 -06001178 reg = <0x02000814 0 0 0x80 0
1179 0x01000810 0 0 0xc0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001180 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +03001181 };
Simon Glass937bb472019-12-06 21:41:57 -07001182 p2sb-pci@2,0 {
1183 compatible = "sandbox,p2sb";
1184 reg = <0x02001010 0 0 0 0>;
1185 sandbox,emul = <&p2sb_emul>;
1186
1187 adder {
1188 intel,p2sb-port-id = <3>;
1189 compatible = "sandbox,adder";
1190 };
1191 };
Simon Glass8c501022019-12-06 21:41:54 -07001192 pci@1e,0 {
1193 compatible = "sandbox,pmc";
1194 reg = <0xf000 0 0 0 0>;
1195 sandbox,emul = <&pmc_emul1e>;
1196 acpi-base = <0x400>;
1197 gpe0-dwx-mask = <0xf>;
1198 gpe0-dwx-shift-base = <4>;
1199 gpe0-dw = <6 7 9>;
1200 gpe0-sts = <0x20>;
1201 gpe0-en = <0x30>;
1202 };
Simon Glass3a6eae62015-03-05 12:25:34 -07001203 pci@1f,0 {
1204 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001205 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
Simon Glass4289c262023-09-26 08:14:58 -06001206 reg = <0x0100f810 0 0 0x100 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001207 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001208 };
1209 };
1210
Simon Glassb98ba4c2019-09-25 08:56:10 -06001211 pci-emul0 {
1212 compatible = "sandbox,pci-emul-parent";
1213 swap_case_emul0_0: emul0@0,0 {
1214 compatible = "sandbox,swap-case";
1215 };
1216 swap_case_emul0_1: emul0@1,0 {
1217 compatible = "sandbox,swap-case";
1218 use-ea;
1219 };
1220 swap_case_emul0_1f: emul0@1f,0 {
1221 compatible = "sandbox,swap-case";
1222 };
Simon Glass937bb472019-12-06 21:41:57 -07001223 p2sb_emul: emul@2,0 {
1224 compatible = "sandbox,p2sb-emul";
1225 };
Simon Glass8c501022019-12-06 21:41:54 -07001226 pmc_emul1e: emul@1e,0 {
1227 compatible = "sandbox,pmc-emul";
1228 };
Simon Glassb98ba4c2019-09-25 08:56:10 -06001229 };
1230
Tom Rini4a3ca482020-02-11 12:41:23 -05001231 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -07001232 compatible = "sandbox,pci";
1233 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001234 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -07001235 #address-cells = <3>;
1236 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001237 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scullc7456a42022-04-21 16:11:09 +00001238 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001239 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -07001240 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +02001241 0x0c 0x00 0x1234 0x5678
1242 0x10 0x00 0x1234 0x5678>;
1243 pci@10,0 {
1244 reg = <0x8000 0 0 0 0>;
1245 };
Bin Meng408e5902018-08-03 01:14:41 -07001246 };
1247
Tom Rini4a3ca482020-02-11 12:41:23 -05001248 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -07001249 compatible = "sandbox,pci";
1250 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001251 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -07001252 #address-cells = <3>;
1253 #size-cells = <2>;
1254 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1255 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1256 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1257 pci@1f,0 {
1258 compatible = "pci-generic";
1259 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001260 sandbox,emul = <&swap_case_emul2_1f>;
1261 };
1262 };
1263
1264 pci-emul2 {
1265 compatible = "sandbox,pci-emul-parent";
1266 swap_case_emul2_1f: emul2@1f,0 {
1267 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001268 };
1269 };
1270
Ramon Friedc64f19b2019-04-27 11:15:23 +03001271 pci_ep: pci_ep {
1272 compatible = "sandbox,pci_ep";
1273 };
1274
Simon Glass9c433fe2017-04-23 20:10:44 -06001275 probing {
1276 compatible = "simple-bus";
1277 test1 {
1278 compatible = "denx,u-boot-probe-test";
1279 };
1280
1281 test2 {
1282 compatible = "denx,u-boot-probe-test";
1283 };
1284
1285 test3 {
1286 compatible = "denx,u-boot-probe-test";
1287 };
1288
1289 test4 {
1290 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001291 first-syscon = <&syscon0>;
1292 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001293 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001294 };
1295 };
1296
Stephen Warren92c67fa2016-07-13 13:45:31 -06001297 pwrdom: power-domain {
1298 compatible = "sandbox,power-domain";
1299 #power-domain-cells = <1>;
1300 };
1301
1302 power-domain-test {
1303 compatible = "sandbox,power-domain-test";
1304 power-domains = <&pwrdom 2>;
1305 };
1306
Simon Glass5620cf82018-10-01 12:22:40 -06001307 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001308 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001309 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001310 pinctrl-names = "default";
1311 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001312 };
1313
1314 pwm2 {
1315 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001316 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001317 };
1318
Simon Glass3d355e62015-07-06 12:54:31 -06001319 ram {
1320 compatible = "sandbox,ram";
1321 };
1322
Simon Glassd860f222015-07-06 12:54:29 -06001323 reset@0 {
1324 compatible = "sandbox,warm-reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001325 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001326 };
1327
1328 reset@1 {
1329 compatible = "sandbox,reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001330 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001331 };
1332
Stephen Warren6488e642016-06-17 09:43:59 -06001333 resetc: reset-ctl {
1334 compatible = "sandbox,reset-ctl";
1335 #reset-cells = <1>;
1336 };
1337
1338 reset-ctl-test {
1339 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001340 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1341 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001342 };
1343
Sughosh Ganu23e37512019-12-28 23:58:31 +05301344 rng {
1345 compatible = "sandbox,sandbox-rng";
1346 };
1347
Nishanth Menonedf85812015-09-17 15:42:41 -05001348 rproc_1: rproc@1 {
1349 compatible = "sandbox,test-processor";
1350 remoteproc-name = "remoteproc-test-dev1";
1351 };
1352
1353 rproc_2: rproc@2 {
1354 compatible = "sandbox,test-processor";
1355 internal-memory-mapped;
1356 remoteproc-name = "remoteproc-test-dev2";
1357 };
1358
Simon Glass5620cf82018-10-01 12:22:40 -06001359 panel {
1360 compatible = "simple-panel";
1361 backlight = <&backlight 0 100>;
1362 };
1363
Simon Glass509f32e2022-09-21 16:21:47 +02001364 scsi {
1365 compatible = "sandbox,scsi";
1366 sandbox,filepath = "scsi.img";
1367 };
1368
Ramon Fried26ed32e2018-07-02 02:57:59 +03001369 smem@0 {
1370 compatible = "sandbox,smem";
1371 };
1372
Simon Glass76072ac2018-12-10 10:37:36 -07001373 sound {
1374 compatible = "sandbox,sound";
1375 cpu {
1376 sound-dai = <&i2s 0>;
1377 };
1378
1379 codec {
1380 sound-dai = <&audio 0>;
1381 };
1382 };
1383
Simon Glass25348a42014-10-13 23:42:11 -06001384 spi@0 {
1385 #address-cells = <1>;
1386 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001387 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001388 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001389 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001390 pinctrl-names = "default";
1391 pinctrl-0 = <&pinmux_spi0_pins>;
1392
Simon Glass25348a42014-10-13 23:42:11 -06001393 spi.bin@0 {
1394 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001395 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001396 spi-max-frequency = <40000000>;
1397 sandbox,filename = "spi.bin";
1398 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001399 spi.bin@1 {
1400 reg = <1>;
1401 compatible = "spansion,m25p16", "jedec,spi-nor";
1402 spi-max-frequency = <50000000>;
1403 sandbox,filename = "spi.bin";
1404 spi-cpol;
1405 spi-cpha;
1406 };
Simon Glass25348a42014-10-13 23:42:11 -06001407 };
1408
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001409 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001410 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001411 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001412 };
1413
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001414 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001415 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001416 reg = <0x20 5
1417 0x28 6
1418 0x30 7
1419 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001420 };
1421
Patrick Delaunayee010432019-03-07 09:57:13 +01001422 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001423 compatible = "simple-mfd", "syscon";
1424 reg = <0x40 5
1425 0x48 6
1426 0x50 7
1427 0x58 8>;
1428 };
1429
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301430 syscon3: syscon@3 {
1431 compatible = "simple-mfd", "syscon";
1432 reg = <0x000100 0x10>;
1433
1434 muxcontroller0: a-mux-controller {
1435 compatible = "mmio-mux";
1436 #mux-control-cells = <1>;
1437
1438 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1439 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1440 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1441 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1442 u-boot,mux-autoprobe;
1443 };
1444 };
1445
1446 muxcontroller1: emul-mux-controller {
1447 compatible = "mux-emul";
1448 #mux-control-cells = <0>;
1449 u-boot,mux-autoprobe;
1450 idle-state = <0xabcd>;
1451 };
1452
Simon Glass791a17f2020-12-16 21:20:27 -07001453 testfdtm0 {
1454 compatible = "denx,u-boot-fdtm-test";
1455 };
1456
1457 testfdtm1: testfdtm1 {
1458 compatible = "denx,u-boot-fdtm-test";
1459 };
1460
1461 testfdtm2 {
1462 compatible = "denx,u-boot-fdtm-test";
1463 };
1464
Sean Anderson79d3bba2020-09-28 10:52:23 -04001465 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001466 compatible = "sandbox,timer";
1467 clock-frequency = <1000000>;
1468 };
1469
Sean Anderson79d3bba2020-09-28 10:52:23 -04001470 timer@1 {
1471 compatible = "sandbox,timer";
1472 sandbox,timebase-frequency-fallback;
1473 };
1474
Miquel Raynal80938c12018-05-15 11:57:27 +02001475 tpm2 {
1476 compatible = "sandbox,tpm2";
Eddie James1a55a7a2023-10-24 10:43:51 -05001477 memory-region = <&event_log>;
Miquel Raynal80938c12018-05-15 11:57:27 +02001478 };
1479
Simon Glasseef107e2023-02-21 06:24:51 -07001480 tpm {
1481 compatible = "google,sandbox-tpm";
1482 };
1483
Simon Glass5b968632015-05-22 15:42:15 -06001484 uart0: serial {
1485 compatible = "sandbox,serial";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001486 bootph-all;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001487 pinctrl-names = "default";
1488 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001489 };
1490
Simon Glass31680482015-03-25 12:23:05 -06001491 usb_0: usb@0 {
1492 compatible = "sandbox,usb";
1493 status = "disabled";
1494 hub {
1495 compatible = "sandbox,usb-hub";
1496 #address-cells = <1>;
1497 #size-cells = <0>;
1498 flash-stick {
1499 reg = <0>;
1500 compatible = "sandbox,usb-flash";
1501 };
1502 };
1503 };
1504
1505 usb_1: usb@1 {
1506 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001507 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001508 hub {
1509 compatible = "usb-hub";
1510 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001511 #address-cells = <1>;
1512 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001513 hub-emul {
1514 compatible = "sandbox,usb-hub";
1515 #address-cells = <1>;
1516 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001517 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001518 reg = <0>;
1519 compatible = "sandbox,usb-flash";
1520 sandbox,filepath = "testflash.bin";
1521 };
1522
Simon Glass4700fe52015-11-08 23:48:01 -07001523 flash-stick@1 {
1524 reg = <1>;
1525 compatible = "sandbox,usb-flash";
Simon Glass64c63252024-11-07 14:31:49 -07001526 sandbox,filepath = "flash1.img";
Simon Glass4700fe52015-11-08 23:48:01 -07001527 };
1528
1529 flash-stick@2 {
1530 reg = <2>;
1531 compatible = "sandbox,usb-flash";
1532 sandbox,filepath = "testflash2.bin";
1533 };
1534
Simon Glassc0ccc722015-11-08 23:48:08 -07001535 keyb@3 {
1536 reg = <3>;
1537 compatible = "sandbox,usb-keyb";
1538 };
1539
Simon Glass31680482015-03-25 12:23:05 -06001540 };
Michael Walle7c961322020-06-02 01:47:07 +02001541
1542 usbstor@1 {
1543 reg = <1>;
1544 };
1545 usbstor@3 {
1546 reg = <3>;
1547 };
Simon Glass31680482015-03-25 12:23:05 -06001548 };
1549 };
1550
1551 usb_2: usb@2 {
1552 compatible = "sandbox,usb";
1553 status = "disabled";
1554 };
1555
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001556 spmi: spmi@0 {
1557 compatible = "sandbox,spmi";
1558 #address-cells = <0x1>;
1559 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001560 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001561 pm8916@0 {
1562 compatible = "qcom,spmi-pmic";
1563 reg = <0x0 0x1>;
1564 #address-cells = <0x1>;
1565 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001566 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001567
1568 spmi_gpios: gpios@c000 {
1569 compatible = "qcom,pm8916-gpio";
1570 reg = <0xc000 0x400>;
Caleb Connolly1edc45f2024-01-08 15:30:51 +00001571 gpio-ranges = <&spmi_gpios 0 0 4>;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001572 gpio-controller;
1573 gpio-count = <4>;
1574 #gpio-cells = <2>;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001575 };
1576 };
1577 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001578
1579 wdt0: wdt@0 {
1580 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001581 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001582 };
Rob Clarka471b672018-01-10 11:33:30 +01001583
Mario Six95922152018-08-09 14:51:19 +02001584 axi: axi@0 {
1585 compatible = "sandbox,axi";
1586 #address-cells = <0x1>;
1587 #size-cells = <0x1>;
1588 store@0 {
1589 compatible = "sandbox,sandbox_store";
1590 reg = <0x0 0x400>;
1591 };
1592 };
1593
Rob Clarka471b672018-01-10 11:33:30 +01001594 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001595 #address-cells = <1>;
1596 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001597 setting = "sunrise ohoka";
1598 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001599 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001600 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Algapally Santosh Sagardf178992023-09-21 16:50:43 +05301601 stdout-path = "serial0:115200n8";
Rob Clarka471b672018-01-10 11:33:30 +01001602 chosen-test {
1603 compatible = "denx,u-boot-fdt-test";
1604 reg = <9 1>;
1605 };
1606 };
Mario Six35616ef2018-03-12 14:53:33 +01001607
1608 translation-test@8000 {
1609 compatible = "simple-bus";
1610 reg = <0x8000 0x4000>;
1611
1612 #address-cells = <0x2>;
1613 #size-cells = <0x1>;
1614
1615 ranges = <0 0x0 0x8000 0x1000
1616 1 0x100 0x9000 0x1000
1617 2 0x200 0xA000 0x1000
1618 3 0x300 0xB000 0x1000
1619 >;
1620
Fabien Dessenne22236e02019-05-31 15:11:30 +02001621 dma-ranges = <0 0x000 0x10000000 0x1000
1622 1 0x100 0x20000000 0x1000
1623 >;
1624
Mario Six35616ef2018-03-12 14:53:33 +01001625 dev@0,0 {
1626 compatible = "denx,u-boot-fdt-dummy";
1627 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +01001628 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001629 };
1630
1631 dev@1,100 {
1632 compatible = "denx,u-boot-fdt-dummy";
1633 reg = <1 0x100 0x1000>;
1634
1635 };
1636
1637 dev@2,200 {
1638 compatible = "denx,u-boot-fdt-dummy";
1639 reg = <2 0x200 0x1000>;
1640 };
1641
1642
1643 noxlatebus@3,300 {
1644 compatible = "simple-bus";
1645 reg = <3 0x300 0x1000>;
1646
1647 #address-cells = <0x1>;
1648 #size-cells = <0x0>;
1649
1650 dev@42 {
1651 compatible = "denx,u-boot-fdt-dummy";
1652 reg = <0x42>;
1653 };
1654 };
1655 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001656
Dzmitry Sankouski54f4c832023-01-22 18:21:23 +03001657 ofnode-foreach {
1658 compatible = "foreach";
1659
1660 first {
1661 prop1 = <1>;
1662 prop2 = <2>;
1663 };
1664
1665 second {
1666 prop1 = <1>;
1667 prop2 = <2>;
1668 };
1669 };
1670
Mario Six02ad6fb2018-09-27 09:19:31 +02001671 osd {
1672 compatible = "sandbox,sandbox_osd";
1673 };
Tom Rinib93eea72018-09-30 18:16:51 -04001674
Jens Wiklander86afaa62018-09-25 16:40:16 +02001675 sandbox_tee {
1676 compatible = "sandbox,tee";
1677 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001678
1679 sandbox_virtio1 {
1680 compatible = "sandbox,virtio1";
Simon Glass8de5a542023-01-17 10:47:51 -07001681 virtio-type = <4>; /* rng */
Bin Meng1bb290d2018-10-15 02:21:26 -07001682 };
1683
1684 sandbox_virtio2 {
1685 compatible = "sandbox,virtio2";
1686 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001687
Simon Glass8de5a542023-01-17 10:47:51 -07001688 sandbox-virtio-blk {
1689 compatible = "sandbox,virtio1";
1690 virtio-type = <2>; /* block */
1691 };
1692
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001693 sandbox_scmi {
1694 compatible = "sandbox,scmi-devices";
AKASHI Takahiro535a7bd2023-10-16 14:39:45 +09001695 power-domains = <&pwrdom_scmi 2>;
Etienne Carrierebf1f1322022-02-21 09:22:41 +01001696 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere09665cb2022-02-21 09:22:39 +01001697 resets = <&reset_scmi 3>;
1698 regul0-supply = <&regul0_scmi>;
1699 regul1-supply = <&regul1_scmi>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001700 };
1701
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001702 pinctrl {
1703 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001704
Sean Anderson3438e3b2020-09-14 11:01:57 -04001705 pinctrl-names = "default", "alternate";
1706 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1707 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001708
Sean Anderson3438e3b2020-09-14 11:01:57 -04001709 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001710 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001711 pins = "P5";
1712 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001713 bias-pull-up;
1714 input-disable;
1715 };
1716 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001717 pins = "P6";
1718 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001719 output-high;
1720 drive-open-drain;
1721 };
1722 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001723 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001724 bias-pull-down;
1725 input-enable;
1726 };
1727 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001728 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001729 bias-disable;
1730 };
1731 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001732
1733 pinctrl_i2c: i2c {
1734 groups {
1735 groups = "I2C_UART";
1736 function = "I2C";
1737 };
1738
1739 pins {
1740 pins = "P0", "P1";
1741 drive-open-drain;
1742 };
1743 };
1744
1745 pinctrl_i2s: i2s {
1746 groups = "SPI_I2S";
1747 function = "I2S";
1748 };
1749
1750 pinctrl_spi: spi {
1751 groups = "SPI_I2S";
1752 function = "SPI";
1753
1754 cs {
1755 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1756 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1757 };
1758 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001759 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001760
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001761 pinctrl-single-no-width {
1762 compatible = "pinctrl-single";
1763 reg = <0x0000 0x238>;
1764 #pinctrl-cells = <1>;
1765 pinctrl-single,function-mask = <0x7f>;
1766 };
1767
1768 pinctrl-single-pins {
1769 compatible = "pinctrl-single";
1770 reg = <0x0000 0x238>;
1771 #pinctrl-cells = <1>;
1772 pinctrl-single,register-width = <32>;
1773 pinctrl-single,function-mask = <0x7f>;
1774
1775 pinmux_pwm_pins: pinmux_pwm_pins {
1776 pinctrl-single,pins = < 0x48 0x06 >;
1777 };
1778
1779 pinmux_spi0_pins: pinmux_spi0_pins {
1780 pinctrl-single,pins = <
1781 0x190 0x0c
1782 0x194 0x0c
1783 0x198 0x23
1784 0x19c 0x0c
1785 >;
1786 };
1787
1788 pinmux_uart0_pins: pinmux_uart0_pins {
1789 pinctrl-single,pins = <
1790 0x70 0x30
1791 0x74 0x00
1792 >;
1793 };
1794 };
1795
1796 pinctrl-single-bits {
1797 compatible = "pinctrl-single";
1798 reg = <0x0000 0x50>;
1799 #pinctrl-cells = <2>;
1800 pinctrl-single,bit-per-mux;
1801 pinctrl-single,register-width = <32>;
1802 pinctrl-single,function-mask = <0xf>;
1803
1804 pinmux_i2c0_pins: pinmux_i2c0_pins {
1805 pinctrl-single,bits = <
1806 0x10 0x00002200 0x0000ff00
1807 >;
1808 };
1809
1810 pinmux_lcd_pins: pinmux_lcd_pins {
1811 pinctrl-single,bits = <
1812 0x40 0x22222200 0xffffff00
1813 0x44 0x22222222 0xffffffff
1814 0x48 0x00000022 0x000000ff
1815 0x48 0x02000000 0x0f000000
1816 0x4c 0x02000022 0x0f0000ff
1817 >;
1818 };
1819 };
1820
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001821 hwspinlock@0 {
1822 compatible = "sandbox,hwspinlock";
1823 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001824
1825 dma: dma {
1826 compatible = "sandbox,dma";
1827 #dma-cells = <1>;
1828
1829 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1830 dma-names = "m2m", "tx0", "rx0";
1831 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001832
Alex Marginean0649be52019-07-12 10:13:53 +03001833 /*
1834 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1835 * end of the test. If parent mdio is removed first, clean-up of the
1836 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1837 * active at the end of the test. That it turn doesn't allow the mdio
1838 * class to be destroyed, triggering an error.
1839 */
1840 mdio-mux-test {
1841 compatible = "sandbox,mdio-mux";
1842 #address-cells = <1>;
1843 #size-cells = <0>;
1844 mdio-parent-bus = <&mdio>;
1845
1846 mdio-ch-test@0 {
1847 reg = <0>;
1848 };
1849 mdio-ch-test@1 {
1850 reg = <1>;
1851 };
1852 };
1853
1854 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001855 compatible = "sandbox,mdio";
Marek Behúnf4f1ddc2022-04-07 00:32:57 +02001856 #address-cells = <1>;
1857 #size-cells = <0>;
1858
1859 ethphy1: ethernet-phy@1 {
1860 reg = <1>;
1861 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001862 };
Sean Andersonb7860542020-06-24 06:41:12 -04001863
1864 pm-bus-test {
1865 compatible = "simple-pm-bus";
1866 clocks = <&clk_sandbox 4>;
1867 power-domains = <&pwrdom 1>;
1868 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001869
1870 resetc2: syscon-reset {
1871 compatible = "syscon-reset";
1872 #reset-cells = <1>;
1873 regmap = <&syscon0>;
1874 offset = <1>;
1875 mask = <0x27FFFFFF>;
1876 assert-high = <0>;
1877 };
1878
1879 syscon-reset-test {
1880 compatible = "sandbox,misc_sandbox";
1881 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1882 reset-names = "valid", "no_mask", "out_of_range";
1883 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301884
Simon Glass458b66a2020-11-05 06:32:05 -07001885 sysinfo {
1886 compatible = "sandbox,sysinfo-sandbox";
1887 };
1888
Sean Anderson1c830672021-04-20 10:50:58 -04001889 sysinfo-gpio {
1890 compatible = "gpio-sysinfo";
1891 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1892 revisions = <19>, <5>;
1893 names = "rev_a", "foo";
1894 };
1895
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301896 some_regmapped-bus {
1897 #address-cells = <0x1>;
1898 #size-cells = <0x1>;
1899
1900 ranges = <0x0 0x0 0x10>;
1901 compatible = "simple-bus";
1902
1903 regmap-test_0 {
1904 reg = <0 0x10>;
1905 compatible = "sandbox,regmap_test";
1906 };
1907 };
Robert Marko9cf87122022-09-06 13:30:35 +02001908
1909 thermal {
1910 compatible = "sandbox,thermal";
1911 };
Sughosh Ganu77079e72022-10-21 18:16:05 +05301912
1913 fwu-mdata {
1914 compatible = "u-boot,fwu-mdata-gpt";
1915 fwu-mdata-store = <&mmc0>;
1916 };
Abdellatif El Khlifi6b005872023-04-17 10:11:55 +01001917
1918 nvmxip-qspi1@08000000 {
1919 compatible = "nvmxip,qspi";
1920 reg = <0x08000000 0x00200000>;
1921 lba_shift = <9>;
1922 lba = <4096>;
1923 };
1924
1925 nvmxip-qspi2@08200000 {
1926 compatible = "nvmxip,qspi";
1927 reg = <0x08200000 0x00100000>;
1928 lba_shift = <9>;
1929 lba = <2048>;
1930 };
Svyatoslav Ryhel669f5c82023-04-25 10:57:21 +03001931
1932 extcon {
1933 compatible = "sandbox,extcon";
1934 };
Abdellatif El Khlifi4970d5b2023-08-04 14:33:41 +01001935
1936 arm-ffa-emul {
1937 compatible = "sandbox,arm-ffa-emul";
1938
1939 sandbox-arm-ffa {
1940 compatible = "sandbox,arm-ffa";
1941 };
1942 };
Sean Anderson326422b2023-11-04 16:37:52 -04001943
1944 nand-controller {
1945 #address-cells = <1>;
1946 #size-cells = <0>;
1947 compatible = "sandbox,nand";
1948
1949 nand@0 {
1950 reg = <0>;
1951 nand-ecc-mode = "soft";
1952 sandbox,id = [00 e3];
1953 sandbox,erasesize = <(8 * 1024)>;
1954 sandbox,oobsize = <16>;
1955 sandbox,pagesize = <512>;
1956 sandbox,pages = <0x2000>;
1957 sandbox,err-count = <1>;
1958 sandbox,err-step-size = <512>;
1959 };
1960
1961 /* MT29F64G08AKABA */
1962 nand@1 {
1963 reg = <1>;
1964 nand-ecc-mode = "soft_bch";
1965 sandbox,id = [2C 48 00 26 89 00 00 00];
1966 sandbox,onfi = [
1967 4f 4e 46 49 0e 00 5a 00
1968 ff 01 00 00 00 00 03 00
1969 00 00 00 00 00 00 00 00
1970 00 00 00 00 00 00 00 00
1971 4d 49 43 52 4f 4e 20 20
1972 20 20 20 20 4d 54 32 39
1973 46 36 34 47 30 38 41 4b
1974 41 42 41 43 35 20 20 20
1975 2c 00 00 00 00 00 00 00
1976 00 00 00 00 00 00 00 00
1977 00 10 00 00 e0 00 00 02
1978 00 00 1c 00 80 00 00 00
1979 00 10 00 00 02 23 01 50
1980 00 01 05 01 00 00 04 00
1981 04 01 1e 00 00 00 00 00
1982 00 00 00 00 00 00 00 00
1983 0e 1f 00 1f 00 f4 01 ac
1984 0d 19 00 c8 00 00 00 00
1985 00 00 00 00 00 00 0a 07
1986 19 00 00 00 00 00 00 00
1987 00 00 00 00 01 00 01 00
1988 00 00 04 10 01 81 04 02
1989 02 01 1e 90 00 00 00 00
1990 00 00 00 00 00 00 00 00
1991 00 00 00 00 00 00 00 00
1992 00 00 00 00 00 00 00 00
1993 00 00 00 00 00 00 00 00
1994 00 00 00 00 00 00 00 00
1995 00 00 00 00 00 00 00 00
1996 00 00 00 00 00 00 00 00
1997 00 00 00 00 00 00 00 00
1998 00 00 00 00 00 03 20 7d
1999 ];
2000 sandbox,erasesize = <(512 * 1024)>;
2001 sandbox,oobsize = <224>;
2002 sandbox,pagesize = <4096>;
2003 sandbox,pages = <0x200000>;
2004 sandbox,err-count = <3>;
2005 sandbox,err-step-size = <512>;
2006 };
2007 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07002008};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02002009
2010#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01002011#include "cros-ec-keyboard.dtsi"
Simon Glass5e135d32022-10-20 18:23:15 -06002012
2013#ifdef CONFIG_SANDBOX_VPL
2014#include "sandbox_vpl.dtsi"
2015#endif
Simon Glass61300722023-06-01 10:23:01 -06002016
Sughosh Ganu05137922024-03-27 16:19:00 +05302017#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
2018#include "sandbox_capsule.dtsi"
2019#endif
2020
Simon Glass61300722023-06-01 10:23:01 -06002021#include "cedit.dtsi"