blob: f273778128786d7c4b8ee1f35a5f6d90ce195790 [file] [log] [blame]
Trevor Woerner513f6402020-05-06 08:02:41 -04001if ARCH_TEGRA
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +09002
Simon Glass035939e2021-07-10 21:14:30 -06003config SPL_GPIO
Simon Glass0bdfc3e2016-09-12 23:18:39 -06004 default y
5
Simon Glassf2a89462016-09-12 23:18:41 -06006config SPL_LIBCOMMON_SUPPORT
7 default y
8
Simon Glassb16c92c2016-09-12 23:18:43 -06009config SPL_LIBGENERIC_SUPPORT
10 default y
11
Simon Glassf4d60392021-08-08 12:20:12 -060012config SPL_SERIAL
Simon Glasse076d6f2016-09-12 23:18:56 -060013 default y
14
Thierry Reding45ad0b02019-04-15 11:32:18 +020015config TEGRA_CLKRST
16 bool
17
Svyatoslav Ryhel7d5a2f42023-02-14 19:35:35 +020018config TEGRA_CRYPTO
19 bool "Tegra AES128 crypto module"
20 select AES
Svyatoslav Ryhel7d5a2f42023-02-14 19:35:35 +020021
Thierry Redingc3598a42019-04-15 11:32:19 +020022config TEGRA_GP_PADCTRL
23 bool
24
Stephen Warrenadf3abd2016-07-18 12:17:11 -060025config TEGRA_IVC
26 bool "Tegra IVC protocol"
27 help
28 IVC (Inter-VM Communication) protocol is a Tegra-specific IPC
29 (Inter Processor Communication) framework. Within the context of
30 U-Boot, it is typically used for communication between the main CPU
31 and various auxiliary processors.
32
Thierry Reding17987bb2019-04-15 11:32:20 +020033config TEGRA_MC
34 bool
35
Thierry Reding7c0b1502019-04-15 11:32:21 +020036config TEGRA_PINCTRL
37 bool
38
Thierry Reding8ffbcfc2019-04-15 11:32:22 +020039config TEGRA_PMC
40 bool
41
Thierry Redingce7eb162019-04-15 11:32:25 +020042config TEGRA_PMC_SECURE
43 bool
44 depends on TEGRA_PMC
45
Stephen Warren8c29e652015-11-23 10:32:01 -070046config TEGRA_COMMON
47 bool "Tegra common options"
Michal Simek84f3dec2018-07-23 15:55:13 +020048 select BOARD_EARLY_INIT_F
Stephen Warren905752c2016-09-13 10:46:00 -060049 select CLK
Tom Warren7b5002e2015-07-17 08:12:51 -070050 select DM
Tom Warren7b5002e2015-07-17 08:12:51 -070051 select DM_GPIO
Stephen Warren8c29e652015-11-23 10:32:01 -070052 select DM_I2C
Simon Glass01e99402015-10-18 21:17:16 -060053 select DM_KEYBOARD
Tom Warrena66f7722016-09-13 10:45:48 -060054 select DM_MMC
Simon Glassd8af3c92016-01-30 16:38:01 -070055 select DM_PWM
Stephen Warren905752c2016-09-13 10:46:00 -060056 select DM_RESET
Stephen Warren8c29e652015-11-23 10:32:01 -070057 select DM_SERIAL
58 select DM_SPI
59 select DM_SPI_FLASH
Stephen Warren905752c2016-09-13 10:46:00 -060060 select MISC
Stephen Warren8c29e652015-11-23 10:32:01 -070061 select OF_CONTROL
Michal Simek84f3dec2018-07-23 15:55:13 +020062 select SPI
Svyatoslav Ryhel4936bad2023-10-24 10:49:04 +030063 select SYSRESET
64 select SPL_SYSRESET if SPL
65 select SYSRESET_TEGRA
Michal Simek2e7c8192018-07-23 15:55:14 +020066 imply CMD_DM
Daniel Thompsona9e2c672017-05-19 17:26:58 +010067 imply CRC32_VERIFY
Stephen Warren8c29e652015-11-23 10:32:01 -070068
Stephen Warren905752c2016-09-13 10:46:00 -060069config TEGRA_NO_BPMP
70 bool "Tegra common options for SoCs without BPMP"
71 select TEGRA_CAR
72 select TEGRA_CAR_CLOCK
73 select TEGRA_CAR_RESET
74
Stephen Warren8c29e652015-11-23 10:32:01 -070075config TEGRA_ARMV7_COMMON
76 bool "Tegra 32-bit common options"
Simon Glassa0c32762020-07-19 13:56:00 -060077 select BINMAN
Lokesh Vutla81b1a672018-04-26 18:21:26 +053078 select CPU_V7A
Stephen Warren8c29e652015-11-23 10:32:01 -070079 select SPL
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080080 select SPL_BOARD_INIT if SPL
Tom Rinie1e85442021-08-27 21:18:30 -040081 select SPL_SKIP_LOWLEVEL_INIT_ONLY if SPL
Stephen Warren8c29e652015-11-23 10:32:01 -070082 select SUPPORT_SPL
Svyatoslav Ryhel79a7e412023-02-01 10:53:03 +020083 select TIMER
Thierry Reding45ad0b02019-04-15 11:32:18 +020084 select TEGRA_CLKRST
Stephen Warren8c29e652015-11-23 10:32:01 -070085 select TEGRA_COMMON
Stephen Warrenaf974be2016-05-12 12:07:41 -060086 select TEGRA_GPIO
Thierry Redingc3598a42019-04-15 11:32:19 +020087 select TEGRA_GP_PADCTRL
Thierry Reding17987bb2019-04-15 11:32:20 +020088 select TEGRA_MC
Stephen Warren905752c2016-09-13 10:46:00 -060089 select TEGRA_NO_BPMP
Thierry Reding7c0b1502019-04-15 11:32:21 +020090 select TEGRA_PINCTRL
Thierry Reding8ffbcfc2019-04-15 11:32:22 +020091 select TEGRA_PMC
Svyatoslav Ryhel79a7e412023-02-01 10:53:03 +020092 select TEGRA_TIMER
Stephen Warren8c29e652015-11-23 10:32:01 -070093
94config TEGRA_ARMV8_COMMON
95 bool "Tegra 64-bit common options"
96 select ARM64
Masahiro Yamadabf4645c2019-06-26 13:51:46 +090097 select INIT_SP_RELATIVE
Stephen Warreneab36052018-01-03 14:31:52 -070098 select LINUX_KERNEL_IMAGE_HEADER
Thierry Reding29ce1d02019-04-15 11:32:32 +020099 select POSITION_INDEPENDENT
Stephen Warren8c29e652015-11-23 10:32:01 -0700100 select TEGRA_COMMON
Tom Warren7b5002e2015-07-17 08:12:51 -0700101
Stephen Warreneab36052018-01-03 14:31:52 -0700102if TEGRA_ARMV8_COMMON
103config LNX_KRNL_IMG_TEXT_OFFSET_BASE
104 default 0x80000000
105endif
106
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900107choice
108 prompt "Tegra SoC select"
Joe Hershbergerf0699602015-05-12 14:46:23 -0500109 optional
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900110
111config TEGRA20
112 bool "Tegra20 family"
Tom Rinibacb52c2017-03-07 07:13:42 -0500113 select ARM_ERRATA_716044
114 select ARM_ERRATA_742230
115 select ARM_ERRATA_751472
Tom Warren7b5002e2015-07-17 08:12:51 -0700116 select TEGRA_ARMV7_COMMON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900117
118config TEGRA30
119 bool "Tegra30 family"
Tom Rinibacb52c2017-03-07 07:13:42 -0500120 select ARM_ERRATA_743622
121 select ARM_ERRATA_751472
Tom Warren7b5002e2015-07-17 08:12:51 -0700122 select TEGRA_ARMV7_COMMON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900123
124config TEGRA114
125 bool "Tegra114 family"
Tom Warren7b5002e2015-07-17 08:12:51 -0700126 select TEGRA_ARMV7_COMMON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900127
128config TEGRA124
129 bool "Tegra124 family"
Tom Warren7b5002e2015-07-17 08:12:51 -0700130 select TEGRA_ARMV7_COMMON
Simon Glass0662cf22017-07-25 08:29:58 -0600131 imply REGMAP
132 imply SYSCON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900133
Tom Warrenab0cc6b2015-03-04 16:36:00 -0700134config TEGRA210
135 bool "Tegra210 family"
Tom Rini249f11f2021-08-19 14:19:39 -0400136 select GICV2
Svyatoslav Ryhel79a7e412023-02-01 10:53:03 +0200137 select TIMER
Stephen Warren8c29e652015-11-23 10:32:01 -0700138 select TEGRA_ARMV8_COMMON
Thierry Reding45ad0b02019-04-15 11:32:18 +0200139 select TEGRA_CLKRST
Michal Simek84f3dec2018-07-23 15:55:13 +0200140 select TEGRA_GPIO
Thierry Redingc3598a42019-04-15 11:32:19 +0200141 select TEGRA_GP_PADCTRL
Thierry Reding17987bb2019-04-15 11:32:20 +0200142 select TEGRA_MC
Stephen Warren905752c2016-09-13 10:46:00 -0600143 select TEGRA_NO_BPMP
Thierry Reding7c0b1502019-04-15 11:32:21 +0200144 select TEGRA_PINCTRL
Thierry Reding8ffbcfc2019-04-15 11:32:22 +0200145 select TEGRA_PMC
Thierry Redingce7eb162019-04-15 11:32:25 +0200146 select TEGRA_PMC_SECURE
Svyatoslav Ryhel79a7e412023-02-01 10:53:03 +0200147 select TEGRA_TIMER
Tom Warrenab0cc6b2015-03-04 16:36:00 -0700148
Stephen Warren03667eb2016-05-12 13:32:55 -0600149config TEGRA186
150 bool "Tegra186 family"
Stephen Warrene0e2b262016-06-17 09:43:57 -0600151 select DM_MAILBOX
Tom Rini249f11f2021-08-19 14:19:39 -0400152 select GICV2
Stephen Warrena2148922016-08-08 09:41:34 -0600153 select TEGRA186_BPMP
Stephen Warrene8e3f202016-08-08 11:28:24 -0600154 select TEGRA186_CLOCK
Stephen Warren03667eb2016-05-12 13:32:55 -0600155 select TEGRA186_GPIO
Stephen Warrenfccc9c52016-08-08 11:28:25 -0600156 select TEGRA186_RESET
Stephen Warren03667eb2016-05-12 13:32:55 -0600157 select TEGRA_ARMV8_COMMON
Stephen Warrene0e2b262016-06-17 09:43:57 -0600158 select TEGRA_HSP
Stephen Warrenadf3abd2016-07-18 12:17:11 -0600159 select TEGRA_IVC
Stephen Warren03667eb2016-05-12 13:32:55 -0600160
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900161endchoice
162
Stephen Warren5a44ab42016-01-26 10:59:42 -0700163config TEGRA_DISCONNECT_UDC_ON_BOOT
164 bool "Disconnect USB device mode controller on boot"
Thierry Reding4e9260c2019-04-15 11:32:26 +0200165 depends on CI_UDC
Stephen Warren5a44ab42016-01-26 10:59:42 -0700166 default y
167 help
168 When loading U-Boot into RAM over USB protocols using tools such as
169 tegrarcm or L4T's exec-uboot.sh/tegraflash.py, Tegra's USB device
170 mode controller is initialized and enumerated by the host PC running
171 the tool. Unfortunately, these tools do not shut down the USB
172 controller before executing the downloaded code, and so the host PC
173 does not "de-enumerate" the USB device. This option shuts down the
174 USB controller when U-Boot boots to avoid leaving a stale USB device
175 present.
176
Tom Rinid8d1fb62022-03-30 18:07:13 -0400177config CI_UDC_HAS_HOSTPC
178 def_bool y
179 depends on CI_UDC && !TEGRA20
180
Simon Glass838723b2015-02-11 16:32:59 -0700181config SYS_MALLOC_F_LEN
182 default 0x1800
183
Masahiro Yamadaed1632a2015-02-20 17:04:04 +0900184source "arch/arm/mach-tegra/tegra20/Kconfig"
185source "arch/arm/mach-tegra/tegra30/Kconfig"
186source "arch/arm/mach-tegra/tegra114/Kconfig"
187source "arch/arm/mach-tegra/tegra124/Kconfig"
Tom Warrenab0cc6b2015-03-04 16:36:00 -0700188source "arch/arm/mach-tegra/tegra210/Kconfig"
Stephen Warren03667eb2016-05-12 13:32:55 -0600189source "arch/arm/mach-tegra/tegra186/Kconfig"
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900190
Tom Rini4b3e7c02022-12-02 16:42:45 -0500191config TEGRA_SPI
192 def_bool y
193 depends on TEGRA20_SFLASH || TEGRA20_SLINK || TEGRA114_SPI
194
195choice
196 prompt "UART to use for console"
197 depends on TEGRA_PINCTRL
198 default TEGRA_ENABLE_UARTA
199
200config TEGRA_ENABLE_UARTA
201 bool "Use UARTA"
202
203config TEGRA_ENABLE_UARTB
204 bool "Use UARTB"
205
206config TEGRA_ENABLE_UARTC
207 bool "Use UARTC"
208
209config TEGRA_ENABLE_UARTD
210 bool "Use UARTD"
211
212endchoice
213
Tom Rini4dbaf6f2022-06-08 08:24:33 -0400214config TEGRA_GPU
215 bool "Enable setting up the GPU"
216 depends on TEGRA124 || TEGRA210
217
Simon Glassbd74b032017-05-17 03:25:11 -0600218config CMD_ENTERRCM
219 bool "Enable 'enterrcm' command"
220 default y
221 help
222 Tegra's boot ROM supports a mode whereby code may be downloaded and
223 flash-programmed over a USB connection. On dev boards, this is
224 typically entered by holding down a "force recovery" button and
225 resetting the CPU. However, not all boards have such a button (one
226 example is the Compulab Trimslice), so a method to enter RCM from
227 software is useful.
228
229 Even on boards other than Trimslice, controlling this over a UART
230 may be useful, e.g. to allow simple remote control without the need
231 for mechanical button actuators, or hooking up relays/... to the
232 button.
233
Ramin Khonsarif2f708d2023-02-14 19:35:37 +0200234config CMD_EBTUPDATE
235 bool "Enable 'ebtupdate' command"
Svyatoslav Ryhelf8700e42023-02-14 19:35:38 +0200236 depends on TEGRA20 || TEGRA30
Ramin Khonsarif2f708d2023-02-14 19:35:37 +0200237 select TEGRA_CRYPTO
238 help
239 Updating u-boot from within u-boot in rather complex or even
240 impossible on production devices. To make it easier procedure of
241 re-cryption was created. If your device was re-crypted choose Y.
242
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900243endif