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Trevor Woerner513f6402020-05-06 08:02:41 -04001if ARCH_TEGRA
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +09002
Simon Glass035939e2021-07-10 21:14:30 -06003config SPL_GPIO
Simon Glass0bdfc3e2016-09-12 23:18:39 -06004 default y
5
Simon Glassf2a89462016-09-12 23:18:41 -06006config SPL_LIBCOMMON_SUPPORT
7 default y
8
Simon Glassb16c92c2016-09-12 23:18:43 -06009config SPL_LIBGENERIC_SUPPORT
10 default y
11
Simon Glassf4d60392021-08-08 12:20:12 -060012config SPL_SERIAL
Simon Glasse076d6f2016-09-12 23:18:56 -060013 default y
14
Thierry Reding45ad0b02019-04-15 11:32:18 +020015config TEGRA_CLKRST
16 bool
17
Thierry Redingc3598a42019-04-15 11:32:19 +020018config TEGRA_GP_PADCTRL
19 bool
20
Stephen Warrenadf3abd2016-07-18 12:17:11 -060021config TEGRA_IVC
22 bool "Tegra IVC protocol"
23 help
24 IVC (Inter-VM Communication) protocol is a Tegra-specific IPC
25 (Inter Processor Communication) framework. Within the context of
26 U-Boot, it is typically used for communication between the main CPU
27 and various auxiliary processors.
28
Thierry Reding17987bb2019-04-15 11:32:20 +020029config TEGRA_MC
30 bool
31
Thierry Reding7c0b1502019-04-15 11:32:21 +020032config TEGRA_PINCTRL
33 bool
34
Thierry Reding8ffbcfc2019-04-15 11:32:22 +020035config TEGRA_PMC
36 bool
37
Thierry Redingce7eb162019-04-15 11:32:25 +020038config TEGRA_PMC_SECURE
39 bool
40 depends on TEGRA_PMC
41
Stephen Warren8c29e652015-11-23 10:32:01 -070042config TEGRA_COMMON
43 bool "Tegra common options"
Michal Simek84f3dec2018-07-23 15:55:13 +020044 select BOARD_EARLY_INIT_F
Stephen Warren905752c2016-09-13 10:46:00 -060045 select CLK
Tom Warren7b5002e2015-07-17 08:12:51 -070046 select DM
Simon Glassa403c9f2015-11-29 13:18:01 -070047 select DM_ETH
Tom Warren7b5002e2015-07-17 08:12:51 -070048 select DM_GPIO
Stephen Warren8c29e652015-11-23 10:32:01 -070049 select DM_I2C
Simon Glass01e99402015-10-18 21:17:16 -060050 select DM_KEYBOARD
Tom Warrena66f7722016-09-13 10:45:48 -060051 select DM_MMC
Simon Glassd8af3c92016-01-30 16:38:01 -070052 select DM_PWM
Stephen Warren905752c2016-09-13 10:46:00 -060053 select DM_RESET
Stephen Warren8c29e652015-11-23 10:32:01 -070054 select DM_SERIAL
55 select DM_SPI
56 select DM_SPI_FLASH
Stephen Warren905752c2016-09-13 10:46:00 -060057 select MISC
Stephen Warren8c29e652015-11-23 10:32:01 -070058 select OF_CONTROL
Michal Simek84f3dec2018-07-23 15:55:13 +020059 select SPI
Michal Simek2e7c8192018-07-23 15:55:14 +020060 imply CMD_DM
Daniel Thompsona9e2c672017-05-19 17:26:58 +010061 imply CRC32_VERIFY
Stephen Warren8c29e652015-11-23 10:32:01 -070062
Stephen Warren905752c2016-09-13 10:46:00 -060063config TEGRA_NO_BPMP
64 bool "Tegra common options for SoCs without BPMP"
65 select TEGRA_CAR
66 select TEGRA_CAR_CLOCK
67 select TEGRA_CAR_RESET
68
Stephen Warren8c29e652015-11-23 10:32:01 -070069config TEGRA_ARMV7_COMMON
70 bool "Tegra 32-bit common options"
Simon Glassa0c32762020-07-19 13:56:00 -060071 select BINMAN
Lokesh Vutla81b1a672018-04-26 18:21:26 +053072 select CPU_V7A
Stephen Warren8c29e652015-11-23 10:32:01 -070073 select SPL
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080074 select SPL_BOARD_INIT if SPL
Tom Rinie1e85442021-08-27 21:18:30 -040075 select SPL_SKIP_LOWLEVEL_INIT_ONLY if SPL
Stephen Warren8c29e652015-11-23 10:32:01 -070076 select SUPPORT_SPL
Thierry Reding45ad0b02019-04-15 11:32:18 +020077 select TEGRA_CLKRST
Stephen Warren8c29e652015-11-23 10:32:01 -070078 select TEGRA_COMMON
Stephen Warrenaf974be2016-05-12 12:07:41 -060079 select TEGRA_GPIO
Thierry Redingc3598a42019-04-15 11:32:19 +020080 select TEGRA_GP_PADCTRL
Thierry Reding17987bb2019-04-15 11:32:20 +020081 select TEGRA_MC
Stephen Warren905752c2016-09-13 10:46:00 -060082 select TEGRA_NO_BPMP
Thierry Reding7c0b1502019-04-15 11:32:21 +020083 select TEGRA_PINCTRL
Thierry Reding8ffbcfc2019-04-15 11:32:22 +020084 select TEGRA_PMC
Stephen Warren8c29e652015-11-23 10:32:01 -070085
86config TEGRA_ARMV8_COMMON
87 bool "Tegra 64-bit common options"
88 select ARM64
Masahiro Yamadabf4645c2019-06-26 13:51:46 +090089 select INIT_SP_RELATIVE
Stephen Warreneab36052018-01-03 14:31:52 -070090 select LINUX_KERNEL_IMAGE_HEADER
Thierry Reding29ce1d02019-04-15 11:32:32 +020091 select POSITION_INDEPENDENT
Stephen Warren8c29e652015-11-23 10:32:01 -070092 select TEGRA_COMMON
Tom Warren7b5002e2015-07-17 08:12:51 -070093
Stephen Warreneab36052018-01-03 14:31:52 -070094if TEGRA_ARMV8_COMMON
95config LNX_KRNL_IMG_TEXT_OFFSET_BASE
96 default 0x80000000
97endif
98
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +090099choice
100 prompt "Tegra SoC select"
Joe Hershbergerf0699602015-05-12 14:46:23 -0500101 optional
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900102
103config TEGRA20
104 bool "Tegra20 family"
Tom Rinibacb52c2017-03-07 07:13:42 -0500105 select ARM_ERRATA_716044
106 select ARM_ERRATA_742230
107 select ARM_ERRATA_751472
Tom Warren7b5002e2015-07-17 08:12:51 -0700108 select TEGRA_ARMV7_COMMON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900109
110config TEGRA30
111 bool "Tegra30 family"
Tom Rinibacb52c2017-03-07 07:13:42 -0500112 select ARM_ERRATA_743622
113 select ARM_ERRATA_751472
Tom Warren7b5002e2015-07-17 08:12:51 -0700114 select TEGRA_ARMV7_COMMON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900115
116config TEGRA114
117 bool "Tegra114 family"
Tom Warren7b5002e2015-07-17 08:12:51 -0700118 select TEGRA_ARMV7_COMMON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900119
120config TEGRA124
121 bool "Tegra124 family"
Tom Warren7b5002e2015-07-17 08:12:51 -0700122 select TEGRA_ARMV7_COMMON
Simon Glass0662cf22017-07-25 08:29:58 -0600123 imply REGMAP
124 imply SYSCON
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900125
Tom Warrenab0cc6b2015-03-04 16:36:00 -0700126config TEGRA210
127 bool "Tegra210 family"
Tom Rini249f11f2021-08-19 14:19:39 -0400128 select GICV2
Stephen Warren8c29e652015-11-23 10:32:01 -0700129 select TEGRA_ARMV8_COMMON
Thierry Reding45ad0b02019-04-15 11:32:18 +0200130 select TEGRA_CLKRST
Michal Simek84f3dec2018-07-23 15:55:13 +0200131 select TEGRA_GPIO
Thierry Redingc3598a42019-04-15 11:32:19 +0200132 select TEGRA_GP_PADCTRL
Thierry Reding17987bb2019-04-15 11:32:20 +0200133 select TEGRA_MC
Stephen Warren905752c2016-09-13 10:46:00 -0600134 select TEGRA_NO_BPMP
Thierry Reding7c0b1502019-04-15 11:32:21 +0200135 select TEGRA_PINCTRL
Thierry Reding8ffbcfc2019-04-15 11:32:22 +0200136 select TEGRA_PMC
Thierry Redingce7eb162019-04-15 11:32:25 +0200137 select TEGRA_PMC_SECURE
Tom Warrenab0cc6b2015-03-04 16:36:00 -0700138
Stephen Warren03667eb2016-05-12 13:32:55 -0600139config TEGRA186
140 bool "Tegra186 family"
Stephen Warrene0e2b262016-06-17 09:43:57 -0600141 select DM_MAILBOX
Tom Rini249f11f2021-08-19 14:19:39 -0400142 select GICV2
Stephen Warrena2148922016-08-08 09:41:34 -0600143 select TEGRA186_BPMP
Stephen Warrene8e3f202016-08-08 11:28:24 -0600144 select TEGRA186_CLOCK
Stephen Warren03667eb2016-05-12 13:32:55 -0600145 select TEGRA186_GPIO
Stephen Warrenfccc9c52016-08-08 11:28:25 -0600146 select TEGRA186_RESET
Stephen Warren03667eb2016-05-12 13:32:55 -0600147 select TEGRA_ARMV8_COMMON
Stephen Warrene0e2b262016-06-17 09:43:57 -0600148 select TEGRA_HSP
Stephen Warrenadf3abd2016-07-18 12:17:11 -0600149 select TEGRA_IVC
Stephen Warren03667eb2016-05-12 13:32:55 -0600150
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900151endchoice
152
Stephen Warren5a44ab42016-01-26 10:59:42 -0700153config TEGRA_DISCONNECT_UDC_ON_BOOT
154 bool "Disconnect USB device mode controller on boot"
Thierry Reding4e9260c2019-04-15 11:32:26 +0200155 depends on CI_UDC
Stephen Warren5a44ab42016-01-26 10:59:42 -0700156 default y
157 help
158 When loading U-Boot into RAM over USB protocols using tools such as
159 tegrarcm or L4T's exec-uboot.sh/tegraflash.py, Tegra's USB device
160 mode controller is initialized and enumerated by the host PC running
161 the tool. Unfortunately, these tools do not shut down the USB
162 controller before executing the downloaded code, and so the host PC
163 does not "de-enumerate" the USB device. This option shuts down the
164 USB controller when U-Boot boots to avoid leaving a stale USB device
165 present.
166
Tom Rinid8d1fb62022-03-30 18:07:13 -0400167config CI_UDC_HAS_HOSTPC
168 def_bool y
169 depends on CI_UDC && !TEGRA20
170
Simon Glass838723b2015-02-11 16:32:59 -0700171config SYS_MALLOC_F_LEN
172 default 0x1800
173
Masahiro Yamadaed1632a2015-02-20 17:04:04 +0900174source "arch/arm/mach-tegra/tegra20/Kconfig"
175source "arch/arm/mach-tegra/tegra30/Kconfig"
176source "arch/arm/mach-tegra/tegra114/Kconfig"
177source "arch/arm/mach-tegra/tegra124/Kconfig"
Tom Warrenab0cc6b2015-03-04 16:36:00 -0700178source "arch/arm/mach-tegra/tegra210/Kconfig"
Stephen Warren03667eb2016-05-12 13:32:55 -0600179source "arch/arm/mach-tegra/tegra186/Kconfig"
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900180
Tom Rini4dbaf6f2022-06-08 08:24:33 -0400181config TEGRA_GPU
182 bool "Enable setting up the GPU"
183 depends on TEGRA124 || TEGRA210
184
Simon Glassbd74b032017-05-17 03:25:11 -0600185config CMD_ENTERRCM
186 bool "Enable 'enterrcm' command"
187 default y
188 help
189 Tegra's boot ROM supports a mode whereby code may be downloaded and
190 flash-programmed over a USB connection. On dev boards, this is
191 typically entered by holding down a "force recovery" button and
192 resetting the CPU. However, not all boards have such a button (one
193 example is the Compulab Trimslice), so a method to enter RCM from
194 software is useful.
195
196 Even on boards other than Trimslice, controlling this over a UART
197 may be useful, e.g. to allow simple remote control without the need
198 for mechanical button actuators, or hooking up relays/... to the
199 button.
200
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900201endif