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Paul Beesleyfc9ee362019-03-07 15:47:15 +00001User Guide
2==========
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
Dan Handley610e7e12018-03-01 18:44:00 +00004This document describes how to build Trusted Firmware-A (TF-A) and run it with a
Douglas Raillardd7c21b72017-06-28 15:23:03 +01005tested set of other software components using defined configurations on the Juno
Dan Handley610e7e12018-03-01 18:44:00 +00006Arm development platform and Arm Fixed Virtual Platform (FVP) models. It is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01007possible to use other software components, configurations and platforms but that
8is outside the scope of this document.
9
10This document assumes that the reader has previous experience running a fully
11bootable Linux software stack on Juno or FVP using the prebuilt binaries and
zelalem-aweke81a21032019-09-20 11:15:20 -050012filesystems provided by Linaro. Further information may be found in the
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010013`Linaro instructions`_. It also assumes that the user understands the role of
14the different software components required to boot a Linux system:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010015
16- Specific firmware images required by the platform (e.g. SCP firmware on Juno)
17- Normal world bootloader (e.g. UEFI or U-Boot)
18- Device tree
19- Linux kernel image
20- Root filesystem
21
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010022This document also assumes that the user is familiar with the `FVP models`_ and
Douglas Raillardd7c21b72017-06-28 15:23:03 +010023the different command line options available to launch the model.
24
Paul Beesleyf8640672019-04-12 14:19:42 +010025This document should be used in conjunction with the :ref:`Firmware Design`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010026
27Host machine requirements
28-------------------------
29
30The minimum recommended machine specification for building the software and
31running the FVP models is a dual-core processor running at 2GHz with 12GB of
32RAM. For best performance, use a machine with a quad-core processor running at
332.6GHz with 16GB of RAM.
34
Joel Huttonfe027712018-03-19 11:59:57 +000035The software has been tested on Ubuntu 16.04 LTS (64-bit). Packages used for
Douglas Raillardd7c21b72017-06-28 15:23:03 +010036building the software were installed from that distribution unless otherwise
37specified.
38
39The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE,
David Cunadob2de0992017-06-29 12:01:33 +010040Cygwin, and Msys (MinGW) shells, using version 5.3.1 of the GNU toolchain.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010041
42Tools
43-----
44
Dan Handley610e7e12018-03-01 18:44:00 +000045Install the required packages to build TF-A with the following command:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010046
Paul Beesley493e3492019-03-13 15:11:04 +000047.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +010048
Sathees Balya2d0aeb02018-07-10 14:46:51 +010049 sudo apt-get install device-tree-compiler build-essential gcc make git libssl-dev
Douglas Raillardd7c21b72017-06-28 15:23:03 +010050
Louis Mayencourt7cf418c2019-07-15 10:23:58 +010051Download and install the AArch32 (arm-eabi) or AArch64 little-endian
Louis Mayencourt04e3d622019-09-26 11:29:21 +010052(aarch64-linux-gnu) GCC 8.3-2019.03 cross compiler from `Arm Developer page`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010053
Roberto Vargas0489bc02018-04-16 15:43:26 +010054Optionally, TF-A can be built using clang version 4.0 or newer or Arm
55Compiler 6. See instructions below on how to switch the default compiler.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010056
57In addition, the following optional packages and tools may be needed:
58
Sathees Balya017a67e2018-08-17 10:22:01 +010059- ``device-tree-compiler`` (dtc) package if you need to rebuild the Flattened Device
60 Tree (FDT) source files (``.dts`` files) provided with this software. The
61 version of dtc must be 1.4.6 or above.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010062
Dan Handley610e7e12018-03-01 18:44:00 +000063- For debugging, Arm `Development Studio 5 (DS-5)`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010064
Antonio Nino Diazb5d68092017-05-23 11:49:22 +010065- To create and modify the diagram files included in the documentation, `Dia`_.
66 This tool can be found in most Linux distributions. Inkscape is needed to
Antonio Nino Diaz80914a82018-08-08 16:28:43 +010067 generate the actual \*.png files.
Antonio Nino Diazb5d68092017-05-23 11:49:22 +010068
zelalem-aweke81a21032019-09-20 11:15:20 -050069TF-A has been tested with pre-built binaries and file systems from
70`Linaro Release 19.06`_. Alternatively, you can build the binaries from
71source using instructions provided at the `Arm Platforms User guide`_.
72
Dan Handley610e7e12018-03-01 18:44:00 +000073Getting the TF-A source code
74----------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +010075
Louis Mayencourt72ef3d42019-03-22 11:47:22 +000076Clone the repository from the Gerrit server. The project details may be found
77on the `arm-trusted-firmware-a project page`_. We recommend the "`Clone with
78commit-msg hook`" clone method, which will setup the git commit hook that
79automatically generates and inserts appropriate `Change-Id:` lines in your
80commit messages.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010081
Paul Beesley8b4bdeb2019-01-21 12:06:24 +000082Checking source code style
83~~~~~~~~~~~~~~~~~~~~~~~~~~
84
85Trusted Firmware follows the `Linux Coding Style`_ . When making changes to the
86source, for submission to the project, the source must be in compliance with
87this style guide.
88
Paul Beesleyf8640672019-04-12 14:19:42 +010089Additional, project-specific guidelines are defined in the
90:ref:`Coding Style & Guidelines` document.
Paul Beesley8b4bdeb2019-01-21 12:06:24 +000091
92To assist with coding style compliance, the project Makefile contains two
93targets which both utilise the `checkpatch.pl` script that ships with the Linux
94source tree. The project also defines certain *checkpatch* options in the
95``.checkpatch.conf`` file in the top-level directory.
96
Paul Beesleyba3ed402019-03-13 16:20:44 +000097.. note::
98 Checkpatch errors will gate upstream merging of pull requests.
99 Checkpatch warnings will not gate merging but should be reviewed and fixed if
100 possible.
Paul Beesley8b4bdeb2019-01-21 12:06:24 +0000101
102To check the entire source tree, you must first download copies of
103``checkpatch.pl``, ``spelling.txt`` and ``const_structs.checkpatch`` available
104in the `Linux master tree`_ *scripts* directory, then set the ``CHECKPATCH``
105environment variable to point to ``checkpatch.pl`` (with the other 2 files in
106the same directory) and build the `checkcodebase` target:
107
Paul Beesley493e3492019-03-13 15:11:04 +0000108.. code:: shell
Paul Beesley8b4bdeb2019-01-21 12:06:24 +0000109
110 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkcodebase
111
112To just check the style on the files that differ between your local branch and
113the remote master, use:
114
Paul Beesley493e3492019-03-13 15:11:04 +0000115.. code:: shell
Paul Beesley8b4bdeb2019-01-21 12:06:24 +0000116
117 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkpatch
118
119If you wish to check your patch against something other than the remote master,
120set the ``BASE_COMMIT`` variable to your desired branch. By default, ``BASE_COMMIT``
121is set to ``origin/master``.
122
Dan Handley610e7e12018-03-01 18:44:00 +0000123Building TF-A
124-------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100125
Dan Handley610e7e12018-03-01 18:44:00 +0000126- Before building TF-A, the environment variable ``CROSS_COMPILE`` must point
zelalem-aweke81a21032019-09-20 11:15:20 -0500127 to the cross compiler.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100128
129 For AArch64:
130
Paul Beesley493e3492019-03-13 15:11:04 +0000131 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100132
133 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
134
135 For AArch32:
136
Paul Beesley493e3492019-03-13 15:11:04 +0000137 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100138
Louis Mayencourt7cf418c2019-07-15 10:23:58 +0100139 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-eabi-
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100140
Roberto Vargas07b1e242018-04-23 08:38:12 +0100141 It is possible to build TF-A using Clang or Arm Compiler 6. To do so
142 ``CC`` needs to point to the clang or armclang binary, which will
143 also select the clang or armclang assembler. Be aware that the
144 GNU linker is used by default. In case of being needed the linker
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000145 can be overridden using the ``LD`` variable. Clang linker version 6 is
Roberto Vargas07b1e242018-04-23 08:38:12 +0100146 known to work with TF-A.
147
148 In both cases ``CROSS_COMPILE`` should be set as described above.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100149
Dan Handley610e7e12018-03-01 18:44:00 +0000150 Arm Compiler 6 will be selected when the base name of the path assigned
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100151 to ``CC`` matches the string 'armclang'.
152
Dan Handley610e7e12018-03-01 18:44:00 +0000153 For AArch64 using Arm Compiler 6:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100154
Paul Beesley493e3492019-03-13 15:11:04 +0000155 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100156
157 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
158 make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
159
160 Clang will be selected when the base name of the path assigned to ``CC``
161 contains the string 'clang'. This is to allow both clang and clang-X.Y
162 to work.
163
164 For AArch64 using clang:
165
Paul Beesley493e3492019-03-13 15:11:04 +0000166 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100167
168 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
169 make CC=<path-to-clang>/bin/clang PLAT=<platform> all
170
Dan Handley610e7e12018-03-01 18:44:00 +0000171- Change to the root directory of the TF-A source tree and build.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100172
173 For AArch64:
174
Paul Beesley493e3492019-03-13 15:11:04 +0000175 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100176
177 make PLAT=<platform> all
178
179 For AArch32:
180
Paul Beesley493e3492019-03-13 15:11:04 +0000181 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100182
183 make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all
184
185 Notes:
186
187 - If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the
188 `Summary of build options`_ for more information on available build
189 options.
190
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100191 - (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100192 corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp_min, is
Dan Handley610e7e12018-03-01 18:44:00 +0000193 provided by TF-A to demonstrate how PSCI Library can be integrated with
194 an AArch32 EL3 Runtime Software. Some AArch32 EL3 Runtime Software may
195 include other runtime services, for example Trusted OS services. A guide
196 to integrate PSCI library with AArch32 EL3 Runtime Software can be found
Paul Beesleyf8640672019-04-12 14:19:42 +0100197 at :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100198
199 - (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32
200 image, is not compiled in by default. Refer to the
201 `Building the Test Secure Payload`_ section below.
202
203 - By default this produces a release version of the build. To produce a
204 debug version instead, refer to the "Debugging options" section below.
205
206 - The build process creates products in a ``build`` directory tree, building
207 the objects and binaries for each boot loader stage in separate
208 sub-directories. The following boot loader binary files are created
209 from the corresponding ELF files:
210
211 - ``build/<platform>/<build-type>/bl1.bin``
212 - ``build/<platform>/<build-type>/bl2.bin``
213 - ``build/<platform>/<build-type>/bl31.bin`` (AArch64 only)
214 - ``build/<platform>/<build-type>/bl32.bin`` (mandatory for AArch32)
215
216 where ``<platform>`` is the name of the chosen platform and ``<build-type>``
217 is either ``debug`` or ``release``. The actual number of images might differ
218 depending on the platform.
219
220- Build products for a specific build variant can be removed using:
221
Paul Beesley493e3492019-03-13 15:11:04 +0000222 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100223
224 make DEBUG=<D> PLAT=<platform> clean
225
226 ... where ``<D>`` is ``0`` or ``1``, as specified when building.
227
228 The build tree can be removed completely using:
229
Paul Beesley493e3492019-03-13 15:11:04 +0000230 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100231
232 make realclean
233
234Summary of build options
235~~~~~~~~~~~~~~~~~~~~~~~~
236
Dan Handley610e7e12018-03-01 18:44:00 +0000237The TF-A build system supports the following build options. Unless mentioned
238otherwise, these options are expected to be specified at the build command
239line and are not to be modified in any component makefiles. Note that the
240build system doesn't track dependency for build options. Therefore, if any of
241the build options are changed from a previous build, a clean build must be
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100242performed.
243
244Common build options
245^^^^^^^^^^^^^^^^^^^^
246
Antonio Nino Diaz80914a82018-08-08 16:28:43 +0100247- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the
248 compiler should use. Valid values are T32 and A32. It defaults to T32 due to
249 code having a smaller resulting size.
250
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100251- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
252 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
253 directory containing the SP source, relative to the ``bl32/``; the directory
254 is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
255
Dan Handley610e7e12018-03-01 18:44:00 +0000256- ``ARCH`` : Choose the target build architecture for TF-A. It can take either
257 ``aarch64`` or ``aarch32`` as values. By default, it is defined to
258 ``aarch64``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100259
Dan Handley610e7e12018-03-01 18:44:00 +0000260- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when
261 compiling TF-A. Its value must be numeric, and defaults to 8 . See also,
262 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in
Paul Beesleyf8640672019-04-12 14:19:42 +0100263 :ref:`Firmware Design`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100264
Dan Handley610e7e12018-03-01 18:44:00 +0000265- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when
266 compiling TF-A. Its value must be a numeric, and defaults to 0. See also,
Paul Beesleyf8640672019-04-12 14:19:42 +0100267 *Armv8 Architecture Extensions* in :ref:`Firmware Design`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100268
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100269- ``BL2``: This is an optional build option which specifies the path to BL2
Dan Handley610e7e12018-03-01 18:44:00 +0000270 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be
271 built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100272
273- ``BL2U``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000274 BL2U image. In this case, the BL2U in TF-A will not be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100275
John Tsichritzisee10e792018-06-06 09:38:10 +0100276- ``BL2_AT_EL3``: This is an optional build option that enables the use of
Roberto Vargasb1584272017-11-20 13:36:10 +0000277 BL2 at EL3 execution level.
278
John Tsichritzisee10e792018-06-06 09:38:10 +0100279- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000280 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize
281 the RW sections in RAM, while leaving the RO sections in place. This option
282 enable this use-case. For now, this option is only supported when BL2_AT_EL3
283 is set to '1'.
284
Hadi Asyrafi461f8f42019-08-20 15:33:27 +0800285- ``BL2_INV_DCACHE``: This is an optional build option which control dcache
286 invalidation upon BL2 entry. Some platform cannot handle cache operations
287 during entry as the coherency unit is not yet initialized. This may cause
288 crashing. Leaving this option to '1' (default) will allow the operation.
289 This option is only relevant when BL2_AT_EL3 is set to '1'.
290
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100291- ``BL31``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000292 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not
293 be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100294
295- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
296 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
297 this file name will be used to save the key.
298
299- ``BL32``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000300 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not
301 be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100302
John Tsichritzisee10e792018-06-06 09:38:10 +0100303- ``BL32_EXTRA1``: This is an optional build option which specifies the path to
Summer Qin80726782017-04-20 16:28:39 +0100304 Trusted OS Extra1 image for the ``fip`` target.
305
John Tsichritzisee10e792018-06-06 09:38:10 +0100306- ``BL32_EXTRA2``: This is an optional build option which specifies the path to
Summer Qin80726782017-04-20 16:28:39 +0100307 Trusted OS Extra2 image for the ``fip`` target.
308
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100309- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
310 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
311 this file name will be used to save the key.
312
313- ``BL33``: Path to BL33 image in the host file system. This is mandatory for
Dan Handley610e7e12018-03-01 18:44:00 +0000314 ``fip`` target in case TF-A BL2 is used.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100315
316- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
317 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
318 this file name will be used to save the key.
319
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100320- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication
321 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves.
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100322 If enabled, it is needed to use a compiler (e.g GCC 9.1 and later versions) that
323 supports the option ``-mbranch-protection``.
324 Selects the branch protection features to use:
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100325- 0: Default value turns off all types of branch protection
326- 1: Enables all types of branch protection features
327- 2: Return address signing to its standard level
328- 3: Extend the signing to include leaf functions
329
330 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options
331 and resulting PAuth/BTI features.
332
333 +-------+--------------+-------+-----+
334 | Value | GCC option | PAuth | BTI |
335 +=======+==============+=======+=====+
336 | 0 | none | N | N |
337 +-------+--------------+-------+-----+
338 | 1 | standard | Y | Y |
339 +-------+--------------+-------+-----+
340 | 2 | pac-ret | Y | N |
341 +-------+--------------+-------+-----+
342 | 3 | pac-ret+leaf | Y | N |
343 +-------+--------------+-------+-----+
344
345 This option defaults to 0 and this is an experimental feature.
346 Note that Pointer Authentication is enabled for Non-secure world
347 irrespective of the value of this option if the CPU supports it.
348
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100349- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
350 compilation of each build. It must be set to a C string (including quotes
351 where applicable). Defaults to a string that contains the time and date of
352 the compilation.
353
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100354- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A
Dan Handley610e7e12018-03-01 18:44:00 +0000355 build to be uniquely identified. Defaults to the current git commit id.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100356
357- ``CFLAGS``: Extra user options appended on the compiler's command line in
358 addition to the options set by the build system.
359
360- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
361 release several CPUs out of reset. It can take either 0 (several CPUs may be
362 brought up) or 1 (only one CPU will ever be brought up during cold reset).
363 Default is 0. If the platform always brings up a single CPU, there is no
364 need to distinguish between primary and secondary CPUs and the boot path can
365 be optimised. The ``plat_is_my_cpu_primary()`` and
366 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
367 to be implemented in this case.
368
369- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
370 register state when an unexpected exception occurs during execution of
371 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
372 this is only enabled for a debug build of the firmware.
373
374- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
375 certificate generation tool to create new keys in case no valid keys are
376 present or specified. Allowed options are '0' or '1'. Default is '1'.
377
378- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
379 the AArch32 system registers to be included when saving and restoring the
380 CPU context. The option must be set to 0 for AArch64-only platforms (that
381 is on hardware that does not implement AArch32, or at least not at EL1 and
382 higher ELs). Default value is 1.
383
384- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
385 registers to be included when saving and restoring the CPU context. Default
386 is 0.
387
Justin Chadwell55c73512019-07-18 16:16:32 +0100388- ``CTX_INCLUDE_MTE_REGS``: Enables register saving/reloading support for
389 ARMv8.5 Memory Tagging Extension. A value of 0 will disable
390 saving/reloading and restrict the use of MTE to the normal world if the
391 CPU has support, while a value of 1 enables the saving/reloading, allowing
392 the use of MTE in both the secure and non-secure worlds. Default is 0
393 (disabled) and this feature is experimental.
394
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100395- ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables
396 Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth
397 registers to be included when saving and restoring the CPU context as
398 part of world switch. Default value is 0 and this is an experimental feature.
399 Note that Pointer Authentication is enabled for Non-secure world irrespective
400 of the value of this flag if the CPU supports it.
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000401
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100402- ``DEBUG``: Chooses between a debug and release build. It can take either 0
403 (release) or 1 (debug) as values. 0 is the default.
404
Christoph Müllner4f088e42019-04-24 09:45:30 +0200405- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation
406 of the binary image. If set to 1, then only the ELF image is built.
407 0 is the default.
408
John Tsichritzisee10e792018-06-06 09:38:10 +0100409- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted
410 Board Boot authentication at runtime. This option is meant to be enabled only
Roberto Vargas025946a2018-09-24 17:20:48 +0100411 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this
412 flag has to be enabled. 0 is the default.
Soby Mathew9fe88042018-03-26 12:43:37 +0100413
Ambroise Vincentba0442d2019-06-06 10:26:41 +0100414- ``E``: Boolean option to make warnings into errors. Default is 1.
415
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100416- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
417 the normal boot flow. It must specify the entry point address of the EL3
418 payload. Please refer to the "Booting an EL3 payload" section for more
419 details.
420
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100421- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions.
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100422 This is an optional architectural feature available on v8.4 onwards. Some
423 v8.2 implementations also implement an AMU and this option can be used to
424 enable this feature on those systems as well. Default is 0.
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100425
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100426- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
427 are compiled out. For debug builds, this option defaults to 1, and calls to
428 ``assert()`` are left in place. For release builds, this option defaults to 0
429 and calls to ``assert()`` function are compiled out. This option can be set
430 independently of ``DEBUG``. It can also be used to hide any auxiliary code
431 that is only required for the assertion and does not fit in the assertion
432 itself.
433
Douglas Raillard77414632018-08-21 12:54:45 +0100434- ``ENABLE_BACKTRACE``: This option controls whether to enables backtrace
435 dumps or not. It is supported in both AArch64 and AArch32. However, in
436 AArch32 the format of the frame records are not defined in the AAPCS and they
437 are defined by the implementation. This implementation of backtrace only
438 supports the format used by GCC when T32 interworking is disabled. For this
439 reason enabling this option in AArch32 will force the compiler to only
440 generate A32 code. This option is enabled by default only in AArch64 debug
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000441 builds, but this behaviour can be overridden in each platform's Makefile or
442 in the build command line.
Douglas Raillard77414632018-08-21 12:54:45 +0100443
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100444- ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM
445 feature. MPAM is an optional Armv8.4 extension that enables various memory
446 system components and resources to define partitions; software running at
447 various ELs can assign themselves to desired partition to control their
448 performance aspects.
449
450 When this option is set to ``1``, EL3 allows lower ELs to access their own
451 MPAM registers without trapping into EL3. This option doesn't make use of
452 partitioning in EL3, however. Platform initialisation code should configure
453 and use partitions in EL3 as required. This option defaults to ``0``.
454
Soby Mathew078f1a42018-08-28 11:13:55 +0100455- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE)
456 support within generic code in TF-A. This option is currently only supported
457 in BL31. Default is 0.
458
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100459- ``ENABLE_PMF``: Boolean option to enable support for optional Performance
460 Measurement Framework(PMF). Default is 0.
461
462- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
463 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
464 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
465 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
466 software.
467
468- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
Dan Handley610e7e12018-03-01 18:44:00 +0000469 instrumentation which injects timestamp collection points into TF-A to
470 allow runtime performance to be measured. Currently, only PSCI is
471 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option
472 as well. Default is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100473
Jeenu Viswambharand73dcf32017-07-19 13:52:12 +0100474- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100475 extensions. This is an optional architectural feature for AArch64.
476 The default is 1 but is automatically disabled when the target architecture
477 is AArch32.
Jeenu Viswambharand73dcf32017-07-19 13:52:12 +0100478
Sandrine Bailleux604f0a42018-09-20 12:44:39 +0200479- ``ENABLE_SPM`` : Boolean option to enable the Secure Partition Manager (SPM).
Paul Beesleyf8640672019-04-12 14:19:42 +0100480 Refer to :ref:`Secure Partition Manager` for more details about
Sandrine Bailleux604f0a42018-09-20 12:44:39 +0200481 this feature. Default is 0.
482
David Cunadoce88eee2017-10-20 11:30:57 +0100483- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
484 (SVE) for the Non-secure world only. SVE is an optional architectural feature
485 for AArch64. Note that when SVE is enabled for the Non-secure world, access
486 to SIMD and floating-point functionality from the Secure world is disabled.
487 This is to avoid corruption of the Non-secure world data in the Z-registers
488 which are aliased by the SIMD and FP registers. The build option is not
489 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
490 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to
491 1. The default is 1 but is automatically disabled when the target
492 architecture is AArch32.
493
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100494- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
Louis Mayencourt768bf0c2019-03-26 16:59:26 +0000495 checks in GCC. Allowed values are "all", "strong", "default" and "none". The
496 default value is set to "none". "strong" is the recommended stack protection
497 level if this feature is desired. "none" disables the stack protection. For
498 all values other than "none", the ``plat_get_stack_protector_canary()``
499 platform hook needs to be implemented. The value is passed as the last
500 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100501
502- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
503 deprecated platform APIs, helper functions or drivers within Trusted
504 Firmware as error. It can take the value 1 (flag the use of deprecated
505 APIs as error) or 0. The default is 0.
506
Jeenu Viswambharan10a67272017-09-22 08:32:10 +0100507- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
508 targeted at EL3. When set ``0`` (default), no exceptions are expected or
509 handled at EL3, and a panic will result. This is supported only for AArch64
510 builds.
511
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000512- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000513 injection from lower ELs, and this build option enables lower ELs to use
514 Error Records accessed via System Registers to inject faults. This is
515 applicable only to AArch64 builds.
516
517 This feature is intended for testing purposes only, and is advisable to keep
518 disabled for production images.
519
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100520- ``FIP_NAME``: This is an optional build option which specifies the FIP
521 filename for the ``fip`` target. Default is ``fip.bin``.
522
523- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
524 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
525
526- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
527 tool to create certificates as per the Chain of Trust described in
Paul Beesleyf8640672019-04-12 14:19:42 +0100528 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100529 include the certificates in the FIP and FWU_FIP. Default value is '0'.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100530
531 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
532 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
533 the corresponding certificates, and to include those certificates in the
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100534 FIP and FWU_FIP.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100535
536 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
537 images will not include support for Trusted Board Boot. The FIP will still
538 include the corresponding certificates. This FIP can be used to verify the
539 Chain of Trust on the host machine through other mechanisms.
540
541 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100542 images will include support for Trusted Board Boot, but the FIP and FWU_FIP
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100543 will not include the corresponding certificates, causing a boot failure.
544
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100545- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
546 inherent support for specific EL3 type interrupts. Setting this build option
547 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both
548 by `platform abstraction layer`__ and `Interrupt Management Framework`__.
549 This allows GICv2 platforms to enable features requiring EL3 interrupt type.
550 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and
551 the Secure Payload interrupts needs to be synchronously handed over to Secure
552 EL1 for handling. The default value of this option is ``0``, which means the
553 Group 0 interrupts are assumed to be handled by Secure EL1.
554
555 .. __: `platform-interrupt-controller-API.rst`
556 .. __: `interrupt-framework-design.rst`
557
Julius Wernerc51a2ec2018-08-28 14:45:43 -0700558- ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError
559 Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to
560 ``0`` (default), these exceptions will be trapped in the current exception
561 level (or in EL1 if the current exception level is EL0).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100562
Dan Handley610e7e12018-03-01 18:44:00 +0000563- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100564 software operations are required for CPUs to enter and exit coherency.
John Tsichritzisfe6df392019-03-19 17:20:52 +0000565 However, newer systems exist where CPUs' entry to and exit from coherency
566 is managed in hardware. Such systems require software to only initiate these
567 operations, and the rest is managed in hardware, minimizing active software
568 management. In such systems, this boolean option enables TF-A to carry out
569 build and run-time optimizations during boot and power management operations.
570 This option defaults to 0 and if it is enabled, then it implies
571 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
572
573 If this flag is disabled while the platform which TF-A is compiled for
574 includes cores that manage coherency in hardware, then a compilation error is
575 generated. This is based on the fact that a system cannot have, at the same
576 time, cores that manage coherency in hardware and cores that don't. In other
577 words, a platform cannot have, at the same time, cores that require
578 ``HW_ASSISTED_COHERENCY=1`` and cores that require
579 ``HW_ASSISTED_COHERENCY=0``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100580
Jeenu Viswambharane834ee12018-04-27 15:17:03 +0100581 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of
582 translation library (xlat tables v2) must be used; version 1 of translation
583 library is not supported.
584
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100585- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3
586 runtime software in AArch32 mode, which is required to run AArch32 on Juno.
587 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in
588 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
589 images.
590
Soby Mathew13b16052017-08-31 11:49:32 +0100591- ``KEY_ALG``: This build flag enables the user to select the algorithm to be
592 used for generating the PKCS keys and subsequent signing of the certificate.
Justin Chadwell3168a202019-09-09 15:24:31 +0100593 It accepts 2 values: ``rsa`` and ``ecdsa``. The default value of this flag
594 is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
Soby Mathew13b16052017-08-31 11:49:32 +0100595
Justin Chadwell82b06b32019-07-29 17:18:21 +0100596- ``KEY_SIZE``: This build flag enables the user to select the key size for
597 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE``
598 depend on the chosen algorithm.
599
600 +-----------+------------------------------------+
601 | KEY_ALG | Possible key sizes |
602 +===========+====================================+
603 | rsa | 1024, 2048 (default), 3072, 4096 |
604 +-----------+------------------------------------+
605 | ecdsa | unavailable |
606 +-----------+------------------------------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100607
Qixiang Xu1a1f2912017-11-09 13:56:29 +0800608- ``HASH_ALG``: This build flag enables the user to select the secure hash
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +0000609 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``.
Qixiang Xu1a1f2912017-11-09 13:56:29 +0800610 The default value of this flag is ``sha256``.
611
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100612- ``LDFLAGS``: Extra user options appended to the linkers' command line in
613 addition to the one set by the build system.
614
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100615- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
616 output compiled into the build. This should be one of the following:
617
618 ::
619
620 0 (LOG_LEVEL_NONE)
Daniel Boulby86c6b072018-06-14 10:07:40 +0100621 10 (LOG_LEVEL_ERROR)
622 20 (LOG_LEVEL_NOTICE)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100623 30 (LOG_LEVEL_WARNING)
624 40 (LOG_LEVEL_INFO)
625 50 (LOG_LEVEL_VERBOSE)
626
John Tsichritzis35006c42018-10-05 12:02:29 +0100627 All log output up to and including the selected log level is compiled into
628 the build. The default value is 40 in debug builds and 20 in release builds.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100629
630- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
631 specifies the file that contains the Non-Trusted World private key in PEM
632 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
633
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100634- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100635 optional. It is only needed if the platform makefile specifies that it
636 is required in order to build the ``fwu_fip`` target.
637
638- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
639 contents upon world switch. It can take either 0 (don't save and restore) or
640 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
641 wants the timer registers to be saved and restored.
642
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +0100643- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc
Varun Wadekar3f9002c2019-01-31 09:22:30 -0800644 for the BL image. It can be either 0 (include) or 1 (remove). The default
645 value is 0.
646
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100647- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
648 the underlying hardware is not a full PL011 UART but a minimally compliant
649 generic UART, which is a subset of the PL011. The driver will not access
650 any register that is not part of the SBSA generic UART specification.
651 Default value is 0 (a full PL011 compliant UART is present).
652
Dan Handley610e7e12018-03-01 18:44:00 +0000653- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name
654 must be subdirectory of any depth under ``plat/``, and must contain a
655 platform makefile named ``platform.mk``. For example, to build TF-A for the
656 Arm Juno board, select PLAT=juno.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100657
658- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
659 instead of the normal boot flow. When defined, it must specify the entry
660 point address for the preloaded BL33 image. This option is incompatible with
661 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
662 over ``PRELOADED_BL33_BASE``.
663
664- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
665 vector address can be programmed or is fixed on the platform. It can take
666 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
667 programmable reset address, it is expected that a CPU will start executing
668 code directly at the right address, both on a cold and warm reset. In this
669 case, there is no need to identify the entrypoint on boot and the boot path
670 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
671 does not need to be implemented in this case.
672
673- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +0000674 possible for the PSCI power-state parameter: original and extended State-ID
675 formats. This flag if set to 1, configures the generic PSCI layer to use the
676 extended format. The default value of this flag is 0, which means by default
677 the original power-state format is used by the PSCI implementation. This flag
678 should be specified by the platform makefile and it governs the return value
679 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is
680 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be
681 set to 1 as well.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100682
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100683- ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features
684 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2
685 or later CPUs.
686
687 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be
688 set to ``1``.
689
690 This option is disabled by default.
691
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100692- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
693 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
694 entrypoint) or 1 (CPU reset to BL31 entrypoint).
695 The default value is 0.
696
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100697- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided
698 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector
Dan Handley610e7e12018-03-01 18:44:00 +0000699 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100700 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100701
702- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
703 file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this
704 file name will be used to save the key.
705
Justin Chadwell83e04882019-08-20 11:01:52 +0100706- ``SANITIZE_UB``: This option enables the Undefined Behaviour sanitizer. It
707 can take 3 values: 'off' (default), 'on' and 'trap'. When using 'trap',
708 gcc and clang will insert calls to ``__builtin_trap`` on detected
709 undefined behaviour, which defaults to a ``brk`` instruction. When using
710 'on', undefined behaviour is translated to a call to special handlers which
711 prints the exact location of the problem and its cause and then panics.
712
713 .. note::
714 Because of the space penalty of the Undefined Behaviour sanitizer,
715 this option will increase the size of the binary. Depending on the
716 memory constraints of the target platform, it may not be possible to
717 enable the sanitizer for all images (BL1 and BL2 are especially
718 likely to be memory constrained). We recommend that the
719 sanitizer is enabled only in debug builds.
720
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100721- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
722 certificate generation tool to save the keys used to establish the Chain of
723 Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
724
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100725- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional.
726 If a SCP_BL2 image is present then this option must be passed for the ``fip``
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100727 target.
728
729- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100730 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100731 this file name will be used to save the key.
732
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100733- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100734 optional. It is only needed if the platform makefile specifies that it
735 is required in order to build the ``fwu_fip`` target.
736
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +0100737- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software
738 Delegated Exception Interface to BL31 image. This defaults to ``0``.
739
740 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be
741 set to ``1``.
742
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100743- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
744 isolated on separate memory pages. This is a trade-off between security and
745 memory usage. See "Isolating code and read-only data on separate memory
Paul Beesleyf8640672019-04-12 14:19:42 +0100746 pages" section in :ref:`Firmware Design`. This flag is disabled by default
747 and affects all BL images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100748
Dan Handley610e7e12018-03-01 18:44:00 +0000749- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
750 This build option is only valid if ``ARCH=aarch64``. The value should be
751 the path to the directory containing the SPD source, relative to
752 ``services/spd/``; the directory is expected to contain a makefile called
753 ``<spd-value>.mk``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100754
755- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
756 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
757 execution in BL1 just before handing over to BL31. At this point, all
758 firmware images have been loaded in memory, and the MMU and caches are
759 turned off. Refer to the "Debugging options" section for more details.
760
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100761- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
Etienne Carrieredc0fea72017-08-09 15:48:53 +0200762 secure interrupts (caught through the FIQ line). Platforms can enable
763 this directive if they need to handle such interruption. When enabled,
764 the FIQ are handled in monitor mode and non secure world is not allowed
765 to mask these events. Platforms that enable FIQ handling in SP_MIN shall
766 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
767
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100768- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
769 Boot feature. When set to '1', BL1 and BL2 images include support to load
770 and verify the certificates and images in a FIP, and BL1 includes support
771 for the Firmware Update. The default value is '0'. Generation and inclusion
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100772 of certificates in the FIP and FWU_FIP depends upon the value of the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100773 ``GENERATE_COT`` option.
774
Paul Beesleyba3ed402019-03-13 16:20:44 +0000775 .. warning::
776 This option depends on ``CREATE_KEYS`` to be enabled. If the keys
777 already exist in disk, they will be overwritten without further notice.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100778
779- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
780 specifies the file that contains the Trusted World private key in PEM
781 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
782
783- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
784 synchronous, (see "Initializing a BL32 Image" section in
Paul Beesleyf8640672019-04-12 14:19:42 +0100785 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100786 synchronous method) or 1 (BL32 is initialized using asynchronous method).
787 Default is 0.
788
789- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
790 routing model which routes non-secure interrupts asynchronously from TSP
791 to EL3 causing immediate preemption of TSP. The EL3 is responsible
792 for saving and restoring the TSP context in this routing model. The
793 default routing model (when the value is 0) is to route non-secure
794 interrupts to TSP allowing it to save its context and hand over
795 synchronously to EL3 via an SMC.
796
Paul Beesleyba3ed402019-03-13 16:20:44 +0000797 .. note::
798 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT``
799 must also be set to ``1``.
Jeenu Viswambharan2f40f322018-01-11 14:30:22 +0000800
Varun Wadekar4d034c52019-01-11 14:47:48 -0800801- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM
802 linker. When the ``LINKER`` build variable points to the armlink linker,
803 this flag is enabled automatically. To enable support for armlink, platforms
804 will have to provide a scatter file for the BL image. Currently, Tegra
805 platforms use the armlink support to compile BL3-1 images.
806
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100807- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
808 memory region in the BL memory map or not (see "Use of Coherent memory in
Paul Beesleyf8640672019-04-12 14:19:42 +0100809 TF-A" section in :ref:`Firmware Design`). It can take the value 1
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100810 (Coherent memory region is included) or 0 (Coherent memory region is
811 excluded). Default is 1.
812
John Tsichritzis2e42b622019-03-19 12:12:55 +0000813- ``USE_ROMLIB``: This flag determines whether library at ROM will be used.
814 This feature creates a library of functions to be placed in ROM and thus
Paul Beesleyf8640672019-04-12 14:19:42 +0100815 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details.
816 Default is 0.
John Tsichritzis2e42b622019-03-19 12:12:55 +0000817
Soby Mathewad042012019-09-25 14:03:41 +0100818- ``USE_SPINLOCK_CAS``: Setting this build flag to 1 selects the spinlock
819 implementation variant using the ARMv8.1-LSE compare-and-swap instruction.
820 Notice this option is experimental and only available to AArch64 builds.
821
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100822- ``V``: Verbose build. If assigned anything other than 0, the build commands
823 are printed. Default is 0.
824
Dan Handley610e7e12018-03-01 18:44:00 +0000825- ``VERSION_STRING``: String used in the log output for each TF-A image.
826 Defaults to a string formed by concatenating the version number, build type
827 and build string.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100828
Ambroise Vincentba0442d2019-06-06 10:26:41 +0100829- ``W``: Warning level. Some compiler warning options of interest have been
830 regrouped and put in the root Makefile. This flag can take the values 0 to 3,
831 each level enabling more warning options. Default is 0.
832
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100833- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
834 the CPU after warm boot. This is applicable for platforms which do not
835 require interconnect programming to enable cache coherency (eg: single
836 cluster platforms). If this option is enabled, then warm boot path
837 enables D-caches immediately after enabling MMU. This option defaults to 0.
838
Dan Handley610e7e12018-03-01 18:44:00 +0000839Arm development platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100840^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
841
842- ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured
843 DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load
844 BL31 in TZC secured DRAM. If TSP is present, then setting this option also
845 sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build
846 flag.
847
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100848- ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
849 frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
850 frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which should
851 match the frame used by the Non-Secure image (normally the Linux kernel).
852 Default is true (access to the frame is allowed).
853
854- ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
Dan Handley610e7e12018-03-01 18:44:00 +0000855 By default, Arm platforms use a watchdog to trigger a system reset in case
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100856 an error is encountered during the boot process (for example, when an image
857 could not be loaded or authenticated). The watchdog is enabled in the early
858 platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The
859 Trusted Watchdog may be disabled at build time for testing or development
860 purposes.
861
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100862- ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to
863 have specific values at boot. This boolean option allows the Trusted Firmware
864 to have a Linux kernel image as BL33 by preparing the registers to these
Manish Pandey37c4ec22018-11-02 13:28:25 +0000865 values before jumping to BL33. This option defaults to 0 (disabled). For
866 AArch64 ``RESET_TO_BL31`` and for AArch32 ``RESET_TO_SP_MIN`` must be 1 when
867 using it. If this option is set to 1, ``ARM_PRELOADED_DTB_BASE`` must be set
868 to the location of a device tree blob (DTB) already loaded in memory. The
869 Linux Image address must be specified using the ``PRELOADED_BL33_BASE``
870 option.
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100871
Sandrine Bailleux281f8f72019-01-31 13:12:41 +0100872- ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to
873 cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
874 is set, the functions which deal with MPIDR assume that the ``MT`` bit in
875 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
876 this flag is 0. Note that this option is not used on FVP platforms.
877
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100878- ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding
879 for the construction of composite state-ID in the power-state parameter.
880 The existing PSCI clients currently do not support this encoding of
881 State-ID yet. Hence this flag is used to configure whether to use the
882 recommended State-ID encoding or not. The default value of this flag is 0,
883 in which case the platform is configured to expect NULL in the State-ID
884 field of power-state parameter.
885
886- ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the
887 location of the ROTPK hash returned by the function ``plat_get_rotpk_info()``
Dan Handley610e7e12018-03-01 18:44:00 +0000888 for Arm platforms. Depending on the selected option, the proper private key
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100889 must be specified using the ``ROT_KEY`` option when building the Trusted
890 Firmware. This private key will be used by the certificate generation tool
891 to sign the BL2 and Trusted Key certificates. Available options for
892 ``ARM_ROTPK_LOCATION`` are:
893
894 - ``regs`` : return the ROTPK hash stored in the Trusted root-key storage
895 registers. The private key corresponding to this ROTPK hash is not
896 currently available.
897 - ``devel_rsa`` : return a development public key hash embedded in the BL1
898 and BL2 binaries. This hash has been obtained from the RSA public key
899 ``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use
900 this option, ``arm_rotprivk_rsa.pem`` must be specified as ``ROT_KEY`` when
901 creating the certificates.
Qixiang Xu1c2aef12017-08-24 15:12:20 +0800902 - ``devel_ecdsa`` : return a development public key hash embedded in the BL1
903 and BL2 binaries. This hash has been obtained from the ECDSA public key
904 ``arm_rotpk_ecdsa.der``, located in ``plat/arm/board/common/rotpk``. To use
905 this option, ``arm_rotprivk_ecdsa.pem`` must be specified as ``ROT_KEY``
906 when creating the certificates.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100907
908- ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options:
909
Qixiang Xuc7b12c52017-10-13 09:04:12 +0800910 - ``tsram`` : Trusted SRAM (default option when TBB is not enabled)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100911 - ``tdram`` : Trusted DRAM (if available)
John Tsichritzisee10e792018-06-06 09:38:10 +0100912 - ``dram`` : Secure region in DRAM (default option when TBB is enabled,
913 configured by the TrustZone controller)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100914
Dan Handley610e7e12018-03-01 18:44:00 +0000915- ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile TF-A with version 1
916 of the translation tables library instead of version 2. It is set to 0 by
917 default, which selects version 2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100918
Dan Handley610e7e12018-03-01 18:44:00 +0000919- ``ARM_CRYPTOCELL_INTEG`` : bool option to enable TF-A to invoke Arm®
920 TrustZone® CryptoCell functionality for Trusted Board Boot on capable Arm
921 platforms. If this option is specified, then the path to the CryptoCell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100922 SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
923
Dan Handley610e7e12018-03-01 18:44:00 +0000924For a better understanding of these options, the Arm development platform memory
Paul Beesleyf8640672019-04-12 14:19:42 +0100925map is explained in the :ref:`Firmware Design`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100926
Dan Handley610e7e12018-03-01 18:44:00 +0000927Arm CSS platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100928^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
929
930- ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version
931 incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards
932 compatible change to the MTL protocol, used for AP/SCP communication.
Dan Handley610e7e12018-03-01 18:44:00 +0000933 TF-A no longer supports earlier SCP versions. If this option is set to 1
934 then TF-A will detect if an earlier version is in use. Default is 1.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100935
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100936- ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP_BL2 and
937 SCP_BL2U to the FIP and FWU_FIP respectively, and enables them to be loaded
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100938 during boot. Default is 1.
939
Soby Mathew1ced6b82017-06-12 12:37:10 +0100940- ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers
941 instead of SCPI/BOM driver for communicating with the SCP during power
942 management operations and for SCP RAM Firmware transfer. If this option
943 is set to 1, then SCMI/SDS drivers will be used. Default is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100944
Dan Handley610e7e12018-03-01 18:44:00 +0000945Arm FVP platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100946^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
947
948- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
Dan Handley610e7e12018-03-01 18:44:00 +0000949 build the topology tree within TF-A. By default TF-A is configured for dual
950 cluster topology and this option can be used to override the default value.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100951
952- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
953 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
954 explained in the options below:
955
956 - ``FVP_CCI`` : The CCI driver is selected. This is the default
957 if 0 < ``FVP_CLUSTER_COUNT`` <= 2.
958 - ``FVP_CCN`` : The CCN driver is selected. This is the default
959 if ``FVP_CLUSTER_COUNT`` > 2.
960
Jeenu Viswambharan75421132018-01-31 14:52:08 +0000961- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in
962 a single cluster. This option defaults to 4.
963
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000964- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
965 in the system. This option defaults to 1. Note that the build option
966 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms.
967
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100968- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
969
970 - ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected
971 - ``FVP_GICV2`` : The GICv2 only driver is selected
972 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100973
974- ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer
975 for functions that wait for an arbitrary time length (udelay and mdelay).
976 The default value is 0.
977
Soby Mathewb1bf0442018-02-16 14:52:52 +0000978- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled
Paul Beesleyf8640672019-04-12 14:19:42 +0100979 to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for
Soby Mathewb1bf0442018-02-16 14:52:52 +0000980 details on HW_CONFIG. By default, this is initialized to a sensible DTS
981 file in ``fdts/`` folder depending on other build options. But some cases,
982 like shifted affinity format for MPIDR, cannot be detected at build time
983 and this option is needed to specify the appropriate DTS file.
984
985- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in
Paul Beesleyf8640672019-04-12 14:19:42 +0100986 FIP. See :ref:`Firmware Design` for details on HW_CONFIG. This option is
Soby Mathewb1bf0442018-02-16 14:52:52 +0000987 similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the
988 HW_CONFIG blob instead of the DTS file. This option is useful to override
989 the default HW_CONFIG selected by the build system.
990
Summer Qin13b95c22018-03-02 15:51:14 +0800991ARM JUNO platform specific build options
992^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
993
994- ``JUNO_TZMP1`` : Boolean option to configure Juno to be used for TrustZone
995 Media Protection (TZ-MP1). Default value of this flag is 0.
996
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100997Debugging options
998~~~~~~~~~~~~~~~~~
999
1000To compile a debug version and make the build more verbose use
1001
Paul Beesley493e3492019-03-13 15:11:04 +00001002.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001003
1004 make PLAT=<platform> DEBUG=1 V=1 all
1005
1006AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for
1007example DS-5) might not support this and may need an older version of DWARF
1008symbols to be emitted by GCC. This can be achieved by using the
1009``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the
1010version to 2 is recommended for DS-5 versions older than 5.16.
1011
1012When debugging logic problems it might also be useful to disable all compiler
1013optimizations by using ``-O0``.
1014
Paul Beesleyba3ed402019-03-13 16:20:44 +00001015.. warning::
1016 Using ``-O0`` could cause output images to be larger and base addresses
1017 might need to be recalculated (see the **Memory layout on Arm development
Paul Beesleyf8640672019-04-12 14:19:42 +01001018 platforms** section in the :ref:`Firmware Design`).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001019
1020Extra debug options can be passed to the build system by setting ``CFLAGS`` or
1021``LDFLAGS``:
1022
Paul Beesley493e3492019-03-13 15:11:04 +00001023.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001024
1025 CFLAGS='-O0 -gdwarf-2' \
1026 make PLAT=<platform> DEBUG=1 V=1 all
1027
1028Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
1029ignored as the linker is called directly.
1030
1031It is also possible to introduce an infinite loop to help in debugging the
Dan Handley610e7e12018-03-01 18:44:00 +00001032post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the
1033``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the `Summary of build options`_
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001034section. In this case, the developer may take control of the target using a
1035debugger when indicated by the console output. When using DS-5, the following
1036commands can be used:
1037
1038::
1039
1040 # Stop target execution
1041 interrupt
1042
1043 #
1044 # Prepare your debugging environment, e.g. set breakpoints
1045 #
1046
1047 # Jump over the debug loop
1048 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
1049
1050 # Resume execution
1051 continue
1052
1053Building the Test Secure Payload
1054~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1055
1056The TSP is coupled with a companion runtime service in the BL31 firmware,
1057called the TSPD. Therefore, if you intend to use the TSP, the BL31 image
1058must be recompiled as well. For more information on SPs and SPDs, see the
Paul Beesleyf8640672019-04-12 14:19:42 +01001059:ref:`Secure-EL1 Payloads and Dispatchers <firmware_design_sel1_spd>` section
1060in the :ref:`Firmware Design` document.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001061
Dan Handley610e7e12018-03-01 18:44:00 +00001062First clean the TF-A build directory to get rid of any previous BL31 binary.
1063Then to build the TSP image use:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001064
Paul Beesley493e3492019-03-13 15:11:04 +00001065.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001066
1067 make PLAT=<platform> SPD=tspd all
1068
1069An additional boot loader binary file is created in the ``build`` directory:
1070
1071::
1072
1073 build/<platform>/<build-type>/bl32.bin
1074
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001075
1076Building and using the FIP tool
1077~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1078
Dan Handley610e7e12018-03-01 18:44:00 +00001079Firmware Image Package (FIP) is a packaging format used by TF-A to package
1080firmware images in a single binary. The number and type of images that should
1081be packed in a FIP is platform specific and may include TF-A images and other
1082firmware images required by the platform. For example, most platforms require
1083a BL33 image which corresponds to the normal world bootloader (e.g. UEFI or
1084U-Boot).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001085
Dan Handley610e7e12018-03-01 18:44:00 +00001086The TF-A build system provides the make target ``fip`` to create a FIP file
1087for the specified platform using the FIP creation tool included in the TF-A
1088project. Examples below show how to build a FIP file for FVP, packaging TF-A
1089and BL33 images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001090
1091For AArch64:
1092
Paul Beesley493e3492019-03-13 15:11:04 +00001093.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001094
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001095 make PLAT=fvp BL33=<path-to>/bl33.bin fip
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001096
1097For AArch32:
1098
Paul Beesley493e3492019-03-13 15:11:04 +00001099.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001100
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001101 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path-to>/bl33.bin fip
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001102
1103The resulting FIP may be found in:
1104
1105::
1106
1107 build/fvp/<build-type>/fip.bin
1108
1109For advanced operations on FIP files, it is also possible to independently build
1110the tool and create or modify FIPs using this tool. To do this, follow these
1111steps:
1112
1113It is recommended to remove old artifacts before building the tool:
1114
Paul Beesley493e3492019-03-13 15:11:04 +00001115.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001116
1117 make -C tools/fiptool clean
1118
1119Build the tool:
1120
Paul Beesley493e3492019-03-13 15:11:04 +00001121.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001122
1123 make [DEBUG=1] [V=1] fiptool
1124
1125The tool binary can be located in:
1126
1127::
1128
1129 ./tools/fiptool/fiptool
1130
Alexei Fedorov2831d582019-03-13 11:05:07 +00001131Invoking the tool with ``help`` will print a help message with all available
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001132options.
1133
1134Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31:
1135
Paul Beesley493e3492019-03-13 15:11:04 +00001136.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001137
1138 ./tools/fiptool/fiptool create \
1139 --tb-fw build/<platform>/<build-type>/bl2.bin \
1140 --soc-fw build/<platform>/<build-type>/bl31.bin \
1141 fip.bin
1142
1143Example 2: view the contents of an existing Firmware package:
1144
Paul Beesley493e3492019-03-13 15:11:04 +00001145.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001146
1147 ./tools/fiptool/fiptool info <path-to>/fip.bin
1148
1149Example 3: update the entries of an existing Firmware package:
1150
Paul Beesley493e3492019-03-13 15:11:04 +00001151.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001152
1153 # Change the BL2 from Debug to Release version
1154 ./tools/fiptool/fiptool update \
1155 --tb-fw build/<platform>/release/bl2.bin \
1156 build/<platform>/debug/fip.bin
1157
1158Example 4: unpack all entries from an existing Firmware package:
1159
Paul Beesley493e3492019-03-13 15:11:04 +00001160.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001161
1162 # Images will be unpacked to the working directory
1163 ./tools/fiptool/fiptool unpack <path-to>/fip.bin
1164
1165Example 5: remove an entry from an existing Firmware package:
1166
Paul Beesley493e3492019-03-13 15:11:04 +00001167.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001168
1169 ./tools/fiptool/fiptool remove \
1170 --tb-fw build/<platform>/debug/fip.bin
1171
1172Note that if the destination FIP file exists, the create, update and
1173remove operations will automatically overwrite it.
1174
1175The unpack operation will fail if the images already exist at the
1176destination. In that case, use -f or --force to continue.
1177
Paul Beesleyf8640672019-04-12 14:19:42 +01001178More information about FIP can be found in the :ref:`Firmware Design` document.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001179
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001180Building FIP images with support for Trusted Board Boot
1181~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1182
1183Trusted Board Boot primarily consists of the following two features:
1184
Paul Beesleyf8640672019-04-12 14:19:42 +01001185- Image Authentication, described in :ref:`Trusted Board Boot`, and
1186- Firmware Update, described in :ref:`Firmware Update (FWU)`
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001187
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001188The following steps should be followed to build FIP and (optionally) FWU_FIP
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001189images with support for these features:
1190
1191#. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser
1192 modules by checking out a recent version of the `mbed TLS Repository`_. It
Dan Handley610e7e12018-03-01 18:44:00 +00001193 is important to use a version that is compatible with TF-A and fixes any
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001194 known security vulnerabilities. See `mbed TLS Security Center`_ for more
Dan Handley610e7e12018-03-01 18:44:00 +00001195 information. The latest version of TF-A is tested with tag
zelalem-aweke8f97ba92019-09-04 16:16:51 -05001196 ``mbedtls-2.16.2``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001197
1198 The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS
1199 source files the modules depend upon.
1200 ``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration
1201 options required to build the mbed TLS sources.
1202
1203 Note that the mbed TLS library is licensed under the Apache version 2.0
Dan Handley610e7e12018-03-01 18:44:00 +00001204 license. Using mbed TLS source code will affect the licensing of TF-A
1205 binaries that are built using this library.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001206
1207#. To build the FIP image, ensure the following command line variables are set
Dan Handley610e7e12018-03-01 18:44:00 +00001208 while invoking ``make`` to build TF-A:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001209
1210 - ``MBEDTLS_DIR=<path of the directory containing mbed TLS sources>``
1211 - ``TRUSTED_BOARD_BOOT=1``
1212 - ``GENERATE_COT=1``
1213
Dan Handley610e7e12018-03-01 18:44:00 +00001214 In the case of Arm platforms, the location of the ROTPK hash must also be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001215 specified at build time. Two locations are currently supported (see
1216 ``ARM_ROTPK_LOCATION`` build option):
1217
1218 - ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted
1219 root-key storage registers present in the platform. On Juno, this
1220 registers are read-only. On FVP Base and Cortex models, the registers
1221 are read-only, but the value can be specified using the command line
1222 option ``bp.trusted_key_storage.public_key`` when launching the model.
1223 On both Juno and FVP models, the default value corresponds to an
1224 ECDSA-SECP256R1 public key hash, whose private part is not currently
1225 available.
1226
1227 - ``ARM_ROTPK_LOCATION=devel_rsa``: use the ROTPK hash that is hardcoded
Dan Handley610e7e12018-03-01 18:44:00 +00001228 in the Arm platform port. The private/public RSA key pair may be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001229 found in ``plat/arm/board/common/rotpk``.
1230
Qixiang Xu1c2aef12017-08-24 15:12:20 +08001231 - ``ARM_ROTPK_LOCATION=devel_ecdsa``: use the ROTPK hash that is hardcoded
Dan Handley610e7e12018-03-01 18:44:00 +00001232 in the Arm platform port. The private/public ECDSA key pair may be
Qixiang Xu1c2aef12017-08-24 15:12:20 +08001233 found in ``plat/arm/board/common/rotpk``.
1234
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001235 Example of command line using RSA development keys:
1236
Paul Beesley493e3492019-03-13 15:11:04 +00001237 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001238
1239 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1240 make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1241 ARM_ROTPK_LOCATION=devel_rsa \
1242 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1243 BL33=<path-to>/<bl33_image> \
1244 all fip
1245
1246 The result of this build will be the bl1.bin and the fip.bin binaries. This
1247 FIP will include the certificates corresponding to the Chain of Trust
1248 described in the TBBR-client document. These certificates can also be found
1249 in the output build directory.
1250
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001251#. The optional FWU_FIP contains any additional images to be loaded from
Paul Beesleyf8640672019-04-12 14:19:42 +01001252 Non-Volatile storage during the :ref:`Firmware Update (FWU)` process. To
1253 build the FWU_FIP, any FWU images required by the platform must be specified
1254 on the command line. On Arm development platforms like Juno, these are:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001255
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001256 - NS_BL2U. The AP non-secure Firmware Updater image.
1257 - SCP_BL2U. The SCP Firmware Update Configuration image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001258
1259 Example of Juno command line for generating both ``fwu`` and ``fwu_fip``
1260 targets using RSA development:
1261
1262 ::
1263
1264 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1265 make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1266 ARM_ROTPK_LOCATION=devel_rsa \
1267 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1268 BL33=<path-to>/<bl33_image> \
1269 SCP_BL2=<path-to>/<scp_bl2_image> \
1270 SCP_BL2U=<path-to>/<scp_bl2u_image> \
1271 NS_BL2U=<path-to>/<ns_bl2u_image> \
1272 all fip fwu_fip
1273
Paul Beesleyba3ed402019-03-13 16:20:44 +00001274 .. note::
1275 The BL2U image will be built by default and added to the FWU_FIP.
1276 The user may override this by adding ``BL2U=<path-to>/<bl2u_image>``
1277 to the command line above.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001278
Paul Beesleyba3ed402019-03-13 16:20:44 +00001279 .. note::
1280 Building and installing the non-secure and SCP FWU images (NS_BL1U,
1281 NS_BL2U and SCP_BL2U) is outside the scope of this document.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001282
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001283 The result of this build will be bl1.bin, fip.bin and fwu_fip.bin binaries.
1284 Both the FIP and FWU_FIP will include the certificates corresponding to the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001285 Chain of Trust described in the TBBR-client document. These certificates
1286 can also be found in the output build directory.
1287
1288Building the Certificate Generation Tool
1289~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1290
Dan Handley610e7e12018-03-01 18:44:00 +00001291The ``cert_create`` tool is built as part of the TF-A build process when the
1292``fip`` make target is specified and TBB is enabled (as described in the
1293previous section), but it can also be built separately with the following
1294command:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001295
Paul Beesley493e3492019-03-13 15:11:04 +00001296.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001297
1298 make PLAT=<platform> [DEBUG=1] [V=1] certtool
1299
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +01001300For platforms that require their own IDs in certificate files, the generic
Paul Beesley62761cd2019-04-11 13:35:26 +01001301'cert_create' tool can be built with the following command. Note that the target
1302platform must define its IDs within a ``platform_oid.h`` header file for the
1303build to succeed.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001304
Paul Beesley493e3492019-03-13 15:11:04 +00001305.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001306
Paul Beesley62761cd2019-04-11 13:35:26 +01001307 make PLAT=<platform> USE_TBBR_DEFS=0 [DEBUG=1] [V=1] certtool
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001308
1309``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
1310verbose. The following command should be used to obtain help about the tool:
1311
Paul Beesley493e3492019-03-13 15:11:04 +00001312.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001313
1314 ./tools/cert_create/cert_create -h
1315
1316Building a FIP for Juno and FVP
1317-------------------------------
1318
1319This section provides Juno and FVP specific instructions to build Trusted
1320Firmware, obtain the additional required firmware, and pack it all together in
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001321a single FIP binary. It assumes that a `Linaro Release`_ has been installed.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001322
Paul Beesleyba3ed402019-03-13 16:20:44 +00001323.. note::
1324 Pre-built binaries for AArch32 are available from Linaro Release 16.12
1325 onwards. Before that release, pre-built binaries are only available for
1326 AArch64.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001327
Paul Beesleyba3ed402019-03-13 16:20:44 +00001328.. warning::
1329 Follow the full instructions for one platform before switching to a
1330 different one. Mixing instructions for different platforms may result in
1331 corrupted binaries.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001332
Paul Beesleyba3ed402019-03-13 16:20:44 +00001333.. warning::
1334 The uboot image downloaded by the Linaro workspace script does not always
1335 match the uboot image packaged as BL33 in the corresponding fip file. It is
1336 recommended to use the version that is packaged in the fip file using the
1337 instructions below.
Joel Huttonfe027712018-03-19 11:59:57 +00001338
Paul Beesleyba3ed402019-03-13 16:20:44 +00001339.. note::
1340 For the FVP, the kernel FDT is packaged in FIP during build and loaded
1341 by the firmware at runtime. See `Obtaining the Flattened Device Trees`_
1342 section for more info on selecting the right FDT to use.
Soby Mathewecd94ad2018-05-09 13:59:29 +01001343
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001344#. Clean the working directory
1345
Paul Beesley493e3492019-03-13 15:11:04 +00001346 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001347
1348 make realclean
1349
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001350#. Obtain SCP_BL2 (Juno) and BL33 (all platforms)
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001351
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001352 Use the fiptool to extract the SCP_BL2 and BL33 images from the FIP
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001353 package included in the Linaro release:
1354
Paul Beesley493e3492019-03-13 15:11:04 +00001355 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001356
1357 # Build the fiptool
1358 make [DEBUG=1] [V=1] fiptool
1359
1360 # Unpack firmware images from Linaro FIP
Artsem Artsemenka9c205502019-10-15 14:59:04 +01001361 ./tools/fiptool/fiptool unpack <path-to-linaro-release>/[SOFTWARE]/fip.bin
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001362
1363 The unpack operation will result in a set of binary images extracted to the
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001364 current working directory. The SCP_BL2 image corresponds to
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001365 ``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001366
Paul Beesleyba3ed402019-03-13 16:20:44 +00001367 .. note::
1368 The fiptool will complain if the images to be unpacked already
1369 exist in the current directory. If that is the case, either delete those
1370 files or use the ``--force`` option to overwrite.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001371
Paul Beesleyba3ed402019-03-13 16:20:44 +00001372 .. note::
1373 For AArch32, the instructions below assume that nt-fw.bin is a
1374 normal world boot loader that supports AArch32.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001375
Dan Handley610e7e12018-03-01 18:44:00 +00001376#. Build TF-A images and create a new FIP for FVP
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001377
Paul Beesley493e3492019-03-13 15:11:04 +00001378 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001379
1380 # AArch64
1381 make PLAT=fvp BL33=nt-fw.bin all fip
1382
1383 # AArch32
1384 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=nt-fw.bin all fip
1385
Dan Handley610e7e12018-03-01 18:44:00 +00001386#. Build TF-A images and create a new FIP for Juno
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001387
1388 For AArch64:
1389
1390 Building for AArch64 on Juno simply requires the addition of ``SCP_BL2``
1391 as a build parameter.
1392
Paul Beesley493e3492019-03-13 15:11:04 +00001393 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001394
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001395 make PLAT=juno BL33=nt-fw.bin SCP_BL2=scp-fw.bin all fip
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001396
1397 For AArch32:
1398
1399 Hardware restrictions on Juno prevent cold reset into AArch32 execution mode,
1400 therefore BL1 and BL2 must be compiled for AArch64, and BL32 is compiled
1401 separately for AArch32.
1402
1403 - Before building BL32, the environment variable ``CROSS_COMPILE`` must point
zelalem-aweke81a21032019-09-20 11:15:20 -05001404 to the AArch32 cross compiler.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001405
Paul Beesley493e3492019-03-13 15:11:04 +00001406 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001407
Artsem Artsemenka9c205502019-10-15 14:59:04 +01001408 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-eabi-
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001409
1410 - Build BL32 in AArch32.
1411
Paul Beesley493e3492019-03-13 15:11:04 +00001412 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001413
1414 make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \
1415 RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32
1416
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001417 - Save ``bl32.bin`` to a temporary location and clean the build products.
1418
1419 ::
1420
1421 cp <path-to-build>/bl32.bin <path-to-temporary>
1422 make realclean
1423
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001424 - Before building BL1 and BL2, the environment variable ``CROSS_COMPILE``
zelalem-aweke81a21032019-09-20 11:15:20 -05001425 must point to the AArch64 cross compiler.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001426
Paul Beesley493e3492019-03-13 15:11:04 +00001427 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001428
1429 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
1430
1431 - The following parameters should be used to build BL1 and BL2 in AArch64
1432 and point to the BL32 file.
1433
Paul Beesley493e3492019-03-13 15:11:04 +00001434 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001435
Soby Mathew97b1bff2018-09-27 16:46:41 +01001436 make ARCH=aarch64 PLAT=juno JUNO_AARCH32_EL3_RUNTIME=1 \
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001437 BL33=nt-fw.bin SCP_BL2=scp-fw.bin \
1438 BL32=<path-to-temporary>/bl32.bin all fip
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001439
1440The resulting BL1 and FIP images may be found in:
1441
1442::
1443
1444 # Juno
1445 ./build/juno/release/bl1.bin
1446 ./build/juno/release/fip.bin
1447
1448 # FVP
1449 ./build/fvp/release/bl1.bin
1450 ./build/fvp/release/fip.bin
1451
Roberto Vargas096f3a02017-10-17 10:19:00 +01001452
1453Booting Firmware Update images
1454-------------------------------------
1455
1456When Firmware Update (FWU) is enabled there are at least 2 new images
1457that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the
1458FWU FIP.
1459
1460Juno
1461~~~~
1462
1463The new images must be programmed in flash memory by adding
1464an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1465on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1466Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1467programming" for more information. User should ensure these do not
1468overlap with any other entries in the file.
1469
1470::
1471
1472 NOR10UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1473 NOR10ADDRESS: 0x00400000 ;Image Flash Address [ns_bl2u_base_address]
1474 NOR10FILE: \SOFTWARE\fwu_fip.bin ;Image File Name
1475 NOR10LOAD: 00000000 ;Image Load Address
1476 NOR10ENTRY: 00000000 ;Image Entry Point
1477
1478 NOR11UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1479 NOR11ADDRESS: 0x03EB8000 ;Image Flash Address [ns_bl1u_base_address]
1480 NOR11FILE: \SOFTWARE\ns_bl1u.bin ;Image File Name
1481 NOR11LOAD: 00000000 ;Image Load Address
1482
1483The address ns_bl1u_base_address is the value of NS_BL1U_BASE - 0x8000000.
1484In the same way, the address ns_bl2u_base_address is the value of
1485NS_BL2U_BASE - 0x8000000.
1486
1487FVP
1488~~~
1489
1490The additional fip images must be loaded with:
1491
1492::
1493
1494 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address]
1495 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address]
1496
1497The address ns_bl1u_base_address is the value of NS_BL1U_BASE.
1498In the same way, the address ns_bl2u_base_address is the value of
1499NS_BL2U_BASE.
1500
1501
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001502EL3 payloads alternative boot flow
1503----------------------------------
1504
1505On a pre-production system, the ability to execute arbitrary, bare-metal code at
1506the highest exception level is required. It allows full, direct access to the
1507hardware, for example to run silicon soak tests.
1508
1509Although it is possible to implement some baremetal secure firmware from
1510scratch, this is a complex task on some platforms, depending on the level of
1511configuration required to put the system in the expected state.
1512
1513Rather than booting a baremetal application, a possible compromise is to boot
Dan Handley610e7e12018-03-01 18:44:00 +00001514``EL3 payloads`` through TF-A instead. This is implemented as an alternative
1515boot flow, where a modified BL2 boots an EL3 payload, instead of loading the
1516other BL images and passing control to BL31. It reduces the complexity of
1517developing EL3 baremetal code by:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001518
1519- putting the system into a known architectural state;
1520- taking care of platform secure world initialization;
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001521- loading the SCP_BL2 image if required by the platform.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001522
Dan Handley610e7e12018-03-01 18:44:00 +00001523When booting an EL3 payload on Arm standard platforms, the configuration of the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001524TrustZone controller is simplified such that only region 0 is enabled and is
1525configured to permit secure access only. This gives full access to the whole
1526DRAM to the EL3 payload.
1527
1528The system is left in the same state as when entering BL31 in the default boot
1529flow. In particular:
1530
1531- Running in EL3;
1532- Current state is AArch64;
1533- Little-endian data access;
1534- All exceptions disabled;
1535- MMU disabled;
1536- Caches disabled.
1537
1538Booting an EL3 payload
1539~~~~~~~~~~~~~~~~~~~~~~
1540
1541The EL3 payload image is a standalone image and is not part of the FIP. It is
Dan Handley610e7e12018-03-01 18:44:00 +00001542not loaded by TF-A. Therefore, there are 2 possible scenarios:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001543
1544- The EL3 payload may reside in non-volatile memory (NVM) and execute in
1545 place. In this case, booting it is just a matter of specifying the right
Dan Handley610e7e12018-03-01 18:44:00 +00001546 address in NVM through ``EL3_PAYLOAD_BASE`` when building TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001547
1548- The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
1549 run-time.
1550
1551To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be
1552used. The infinite loop that it introduces in BL1 stops execution at the right
1553moment for a debugger to take control of the target and load the payload (for
1554example, over JTAG).
1555
1556It is expected that this loading method will work in most cases, as a debugger
1557connection is usually available in a pre-production system. The user is free to
1558use any other platform-specific mechanism to load the EL3 payload, though.
1559
1560Booting an EL3 payload on FVP
1561^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1562
1563The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
1564the secondary CPUs holding pen to work properly. Unfortunately, its reset value
1565is undefined on the FVP platform and the FVP platform code doesn't clear it.
1566Therefore, one must modify the way the model is normally invoked in order to
1567clear the mailbox at start-up.
1568
1569One way to do that is to create an 8-byte file containing all zero bytes using
1570the following command:
1571
Paul Beesley493e3492019-03-13 15:11:04 +00001572.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001573
1574 dd if=/dev/zero of=mailbox.dat bs=1 count=8
1575
1576and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
1577using the following model parameters:
1578
1579::
1580
1581 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
1582 --data=mailbox.dat@0x04000000 [Foundation FVP]
1583
1584To provide the model with the EL3 payload image, the following methods may be
1585used:
1586
1587#. If the EL3 payload is able to execute in place, it may be programmed into
1588 flash memory. On Base Cortex and AEM FVPs, the following model parameter
1589 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
1590 used for the FIP):
1591
1592 ::
1593
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001594 -C bp.flashloader1.fname="<path-to>/<el3-payload>"
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001595
1596 On Foundation FVP, there is no flash loader component and the EL3 payload
1597 may be programmed anywhere in flash using method 3 below.
1598
1599#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
1600 command may be used to load the EL3 payload ELF image over JTAG:
1601
1602 ::
1603
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001604 load <path-to>/el3-payload.elf
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001605
1606#. The EL3 payload may be pre-loaded in volatile memory using the following
1607 model parameters:
1608
1609 ::
1610
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001611 --data cluster0.cpu0="<path-to>/el3-payload>"@address [Base FVPs]
1612 --data="<path-to>/<el3-payload>"@address [Foundation FVP]
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001613
1614 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
Dan Handley610e7e12018-03-01 18:44:00 +00001615 used when building TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001616
1617Booting an EL3 payload on Juno
1618^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1619
1620If the EL3 payload is able to execute in place, it may be programmed in flash
1621memory by adding an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1622on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1623Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1624programming" for more information.
1625
1626Alternatively, the same DS-5 command mentioned in the FVP section above can
1627be used to load the EL3 payload's ELF file over JTAG on Juno.
1628
1629Preloaded BL33 alternative boot flow
1630------------------------------------
1631
1632Some platforms have the ability to preload BL33 into memory instead of relying
Dan Handley610e7e12018-03-01 18:44:00 +00001633on TF-A to load it. This may simplify packaging of the normal world code and
1634improve performance in a development environment. When secure world cold boot
1635is complete, TF-A simply jumps to a BL33 base address provided at build time.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001636
1637For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be
Dan Handley610e7e12018-03-01 18:44:00 +00001638used when compiling TF-A. For example, the following command will create a FIP
1639without a BL33 and prepare to jump to a BL33 image loaded at address
16400x80000000:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001641
Paul Beesley493e3492019-03-13 15:11:04 +00001642.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001643
1644 make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip
1645
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001646Boot of a preloaded kernel image on Base FVP
1647~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001648
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001649The following example uses a simplified boot flow by directly jumping from the
1650TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be
1651useful if both the kernel and the device tree blob (DTB) are already present in
1652memory (like in FVP).
1653
1654For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at
1655address ``0x82000000``, the firmware can be built like this:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001656
Paul Beesley493e3492019-03-13 15:11:04 +00001657.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001658
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001659 CROSS_COMPILE=aarch64-linux-gnu- \
1660 make PLAT=fvp DEBUG=1 \
1661 RESET_TO_BL31=1 \
1662 ARM_LINUX_KERNEL_AS_BL33=1 \
1663 PRELOADED_BL33_BASE=0x80080000 \
1664 ARM_PRELOADED_DTB_BASE=0x82000000 \
1665 all fip
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001666
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001667Now, it is needed to modify the DTB so that the kernel knows the address of the
1668ramdisk. The following script generates a patched DTB from the provided one,
1669assuming that the ramdisk is loaded at address ``0x84000000``. Note that this
1670script assumes that the user is using a ramdisk image prepared for U-Boot, like
1671the ones provided by Linaro. If using a ramdisk without this header,the ``0x40``
1672offset in ``INITRD_START`` has to be removed.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001673
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001674.. code:: bash
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001675
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001676 #!/bin/bash
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001677
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001678 # Path to the input DTB
1679 KERNEL_DTB=<path-to>/<fdt>
1680 # Path to the output DTB
1681 PATCHED_KERNEL_DTB=<path-to>/<patched-fdt>
1682 # Base address of the ramdisk
1683 INITRD_BASE=0x84000000
1684 # Path to the ramdisk
1685 INITRD=<path-to>/<ramdisk.img>
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001686
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001687 # Skip uboot header (64 bytes)
1688 INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) )
1689 INITRD_SIZE=$(stat -Lc %s ${INITRD})
1690 INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) )
1691
1692 CHOSEN_NODE=$(echo \
1693 "/ { \
1694 chosen { \
1695 linux,initrd-start = <${INITRD_START}>; \
1696 linux,initrd-end = <${INITRD_END}>; \
1697 }; \
1698 };")
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001699
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001700 echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \
1701 dtc -O dtb -o ${PATCHED_KERNEL_DTB} -
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001702
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001703And the FVP binary can be run with the following command:
1704
Paul Beesley493e3492019-03-13 15:11:04 +00001705.. code:: shell
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001706
1707 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1708 -C pctl.startup=0.0.0.0 \
1709 -C bp.secure_memory=1 \
1710 -C cluster0.NUM_CORES=4 \
1711 -C cluster1.NUM_CORES=4 \
1712 -C cache_state_modelled=1 \
1713 -C cluster0.cpu0.RVBAR=0x04020000 \
1714 -C cluster0.cpu1.RVBAR=0x04020000 \
1715 -C cluster0.cpu2.RVBAR=0x04020000 \
1716 -C cluster0.cpu3.RVBAR=0x04020000 \
1717 -C cluster1.cpu0.RVBAR=0x04020000 \
1718 -C cluster1.cpu1.RVBAR=0x04020000 \
1719 -C cluster1.cpu2.RVBAR=0x04020000 \
1720 -C cluster1.cpu3.RVBAR=0x04020000 \
1721 --data cluster0.cpu0="<path-to>/bl31.bin"@0x04020000 \
1722 --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \
1723 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1724 --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000
1725
1726Boot of a preloaded kernel image on Juno
1727~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001728
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001729The Trusted Firmware must be compiled in a similar way as for FVP explained
1730above. The process to load binaries to memory is the one explained in
1731`Booting an EL3 payload on Juno`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001732
Paul Beesleyf8640672019-04-12 14:19:42 +01001733.. _user_guide_run_fvp:
1734
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001735Running the software on FVP
1736---------------------------
1737
David Cunado7c032642018-03-12 18:47:05 +00001738The latest version of the AArch64 build of TF-A has been tested on the following
1739Arm FVPs without shifted affinities, and that do not support threaded CPU cores
1740(64-bit host machine only).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001741
Paul Beesleyba3ed402019-03-13 16:20:44 +00001742.. note::
1743 The FVP models used are Version 11.6 Build 45, unless otherwise stated.
David Cunado124415e2017-06-27 17:31:12 +01001744
David Cunado05845bf2017-12-19 16:33:25 +00001745- ``FVP_Base_AEMv8A-AEMv8A``
1746- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
David Cunado05845bf2017-12-19 16:33:25 +00001747- ``FVP_Base_RevC-2xAEMv8A``
1748- ``FVP_Base_Cortex-A32x4``
David Cunado124415e2017-06-27 17:31:12 +01001749- ``FVP_Base_Cortex-A35x4``
1750- ``FVP_Base_Cortex-A53x4``
David Cunado05845bf2017-12-19 16:33:25 +00001751- ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
1752- ``FVP_Base_Cortex-A55x4``
Ambroise Vincent6f4c0fc2019-03-28 12:51:48 +00001753- ``FVP_Base_Cortex-A57x1-A53x1``
1754- ``FVP_Base_Cortex-A57x2-A53x4``
David Cunado124415e2017-06-27 17:31:12 +01001755- ``FVP_Base_Cortex-A57x4-A53x4``
1756- ``FVP_Base_Cortex-A57x4``
1757- ``FVP_Base_Cortex-A72x4-A53x4``
1758- ``FVP_Base_Cortex-A72x4``
1759- ``FVP_Base_Cortex-A73x4-A53x4``
1760- ``FVP_Base_Cortex-A73x4``
David Cunado05845bf2017-12-19 16:33:25 +00001761- ``FVP_Base_Cortex-A75x4``
1762- ``FVP_Base_Cortex-A76x4``
John Tsichritzisd1894252019-05-20 13:09:34 +01001763- ``FVP_Base_Cortex-A76AEx4``
1764- ``FVP_Base_Cortex-A76AEx8``
Balint Dobszaycc942642019-07-03 13:02:56 +02001765- ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36)
John Tsichritzisd1894252019-05-20 13:09:34 +01001766- ``FVP_Base_Neoverse-N1x4``
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001767- ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
Ambroise Vincent6f4c0fc2019-03-28 12:51:48 +00001768- ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
1769- ``FVP_RD_E1Edge`` (Version 11.3 build 42)
John Tsichritzisd1894252019-05-20 13:09:34 +01001770- ``FVP_RD_N1Edge``
David Cunado05845bf2017-12-19 16:33:25 +00001771- ``Foundation_Platform``
David Cunado7c032642018-03-12 18:47:05 +00001772
1773The latest version of the AArch32 build of TF-A has been tested on the following
1774Arm FVPs without shifted affinities, and that do not support threaded CPU cores
1775(64-bit host machine only).
1776
1777- ``FVP_Base_AEMv8A-AEMv8A``
David Cunado124415e2017-06-27 17:31:12 +01001778- ``FVP_Base_Cortex-A32x4``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001779
Paul Beesleyba3ed402019-03-13 16:20:44 +00001780.. note::
1781 The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which
1782 is not compatible with legacy GIC configurations. Therefore this FVP does not
1783 support these legacy GIC configurations.
David Cunado7c032642018-03-12 18:47:05 +00001784
Paul Beesleyba3ed402019-03-13 16:20:44 +00001785.. note::
1786 The build numbers quoted above are those reported by launching the FVP
1787 with the ``--version`` parameter.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001788
Paul Beesleyba3ed402019-03-13 16:20:44 +00001789.. note::
1790 Linaro provides a ramdisk image in prebuilt FVP configurations and full
1791 file systems that can be downloaded separately. To run an FVP with a virtio
1792 file system image an additional FVP configuration option
1793 ``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
1794 used.
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001795
Paul Beesleyba3ed402019-03-13 16:20:44 +00001796.. note::
1797 The software will not work on Version 1.0 of the Foundation FVP.
1798 The commands below would report an ``unhandled argument`` error in this case.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001799
Paul Beesleyba3ed402019-03-13 16:20:44 +00001800.. note::
1801 FVPs can be launched with ``--cadi-server`` option such that a
1802 CADI-compliant debugger (for example, Arm DS-5) can connect to and control
1803 its execution.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001804
Paul Beesleyba3ed402019-03-13 16:20:44 +00001805.. warning::
1806 Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
1807 the internal synchronisation timings changed compared to older versions of
1808 the models. The models can be launched with ``-Q 100`` option if they are
1809 required to match the run time characteristics of the older versions.
David Cunado97309462017-07-31 12:24:51 +01001810
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001811The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be
Dan Handley610e7e12018-03-01 18:44:00 +00001812downloaded for free from `Arm's website`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001813
David Cunado124415e2017-06-27 17:31:12 +01001814The Cortex-A models listed above are also available to download from
Dan Handley610e7e12018-03-01 18:44:00 +00001815`Arm's website`_.
David Cunado124415e2017-06-27 17:31:12 +01001816
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001817Please refer to the FVP documentation for a detailed description of the model
Dan Handley610e7e12018-03-01 18:44:00 +00001818parameter options. A brief description of the important ones that affect TF-A
1819and normal world software behavior is provided below.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001820
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001821Obtaining the Flattened Device Trees
1822~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1823
1824Depending on the FVP configuration and Linux configuration used, different
Soby Mathewecd94ad2018-05-09 13:59:29 +01001825FDT files are required. FDT source files for the Foundation and Base FVPs can
1826be found in the TF-A source directory under ``fdts/``. The Foundation FVP has
1827a subset of the Base FVP components. For example, the Foundation FVP lacks
1828CLCD and MMC support, and has only one CPU cluster.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001829
Paul Beesleyba3ed402019-03-13 16:20:44 +00001830.. note::
1831 It is not recommended to use the FDTs built along the kernel because not
1832 all FDTs are available from there.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001833
Soby Mathewecd94ad2018-05-09 13:59:29 +01001834The dynamic configuration capability is enabled in the firmware for FVPs.
1835This means that the firmware can authenticate and load the FDT if present in
1836FIP. A default FDT is packaged into FIP during the build based on
1837the build configuration. This can be overridden by using the ``FVP_HW_CONFIG``
1838or ``FVP_HW_CONFIG_DTS`` build options (refer to the
1839`Arm FVP platform specific build options`_ section for detail on the options).
1840
1841- ``fvp-base-gicv2-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001842
David Cunado7c032642018-03-12 18:47:05 +00001843 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
1844 affinities and with Base memory map configuration.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001845
Soby Mathewecd94ad2018-05-09 13:59:29 +01001846- ``fvp-base-gicv2-psci-aarch32.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001847
David Cunado7c032642018-03-12 18:47:05 +00001848 For use with models such as the Cortex-A32 Base FVPs without shifted
1849 affinities and running Linux in AArch32 state with Base memory map
1850 configuration.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001851
Soby Mathewecd94ad2018-05-09 13:59:29 +01001852- ``fvp-base-gicv3-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001853
David Cunado7c032642018-03-12 18:47:05 +00001854 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
1855 affinities and with Base memory map configuration and Linux GICv3 support.
1856
Soby Mathewecd94ad2018-05-09 13:59:29 +01001857- ``fvp-base-gicv3-psci-1t.dts``
David Cunado7c032642018-03-12 18:47:05 +00001858
1859 For use with models such as the AEMv8-RevC Base FVP with shifted affinities,
1860 single threaded CPUs, Base memory map configuration and Linux GICv3 support.
1861
Soby Mathewecd94ad2018-05-09 13:59:29 +01001862- ``fvp-base-gicv3-psci-dynamiq.dts``
David Cunado7c032642018-03-12 18:47:05 +00001863
1864 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities,
1865 single cluster, single threaded CPUs, Base memory map configuration and Linux
1866 GICv3 support.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001867
Soby Mathewecd94ad2018-05-09 13:59:29 +01001868- ``fvp-base-gicv3-psci-aarch32.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001869
David Cunado7c032642018-03-12 18:47:05 +00001870 For use with models such as the Cortex-A32 Base FVPs without shifted
1871 affinities and running Linux in AArch32 state with Base memory map
1872 configuration and Linux GICv3 support.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001873
Soby Mathewecd94ad2018-05-09 13:59:29 +01001874- ``fvp-foundation-gicv2-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001875
1876 For use with Foundation FVP with Base memory map configuration.
1877
Soby Mathewecd94ad2018-05-09 13:59:29 +01001878- ``fvp-foundation-gicv3-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001879
1880 (Default) For use with Foundation FVP with Base memory map configuration
1881 and Linux GICv3 support.
1882
1883Running on the Foundation FVP with reset to BL1 entrypoint
1884~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1885
1886The following ``Foundation_Platform`` parameters should be used to boot Linux with
Dan Handley610e7e12018-03-01 18:44:00 +000018874 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001888
Paul Beesley493e3492019-03-13 15:11:04 +00001889.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001890
1891 <path-to>/Foundation_Platform \
1892 --cores=4 \
Antonio Nino Diazb44eda52018-02-23 11:01:31 +00001893 --arm-v8.0 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001894 --secure-memory \
1895 --visualization \
1896 --gicv3 \
1897 --data="<path-to>/<bl1-binary>"@0x0 \
1898 --data="<path-to>/<FIP-binary>"@0x08000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001899 --data="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001900 --data="<path-to>/<ramdisk-binary>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001901
1902Notes:
1903
1904- BL1 is loaded at the start of the Trusted ROM.
1905- The Firmware Image Package is loaded at the start of NOR FLASH0.
Soby Mathewecd94ad2018-05-09 13:59:29 +01001906- The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address
Paul Beesleyf8640672019-04-12 14:19:42 +01001907 is specified via the ``hw_config_addr`` property in ``TB_FW_CONFIG`` for FVP.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001908- The default use-case for the Foundation FVP is to use the ``--gicv3`` option
1909 and enable the GICv3 device in the model. Note that without this option,
1910 the Foundation FVP defaults to legacy (Versatile Express) memory map which
Dan Handley610e7e12018-03-01 18:44:00 +00001911 is not supported by TF-A.
1912- In order for TF-A to run correctly on the Foundation FVP, the architecture
1913 versions must match. The Foundation FVP defaults to the highest v8.x
1914 version it supports but the default build for TF-A is for v8.0. To avoid
1915 issues either start the Foundation FVP to use v8.0 architecture using the
1916 ``--arm-v8.0`` option, or build TF-A with an appropriate value for
1917 ``ARM_ARCH_MINOR``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001918
1919Running on the AEMv8 Base FVP with reset to BL1 entrypoint
1920~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1921
David Cunado7c032642018-03-12 18:47:05 +00001922The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001923with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001924
Paul Beesley493e3492019-03-13 15:11:04 +00001925.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001926
David Cunado7c032642018-03-12 18:47:05 +00001927 <path-to>/FVP_Base_RevC-2xAEMv8A \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001928 -C pctl.startup=0.0.0.0 \
1929 -C bp.secure_memory=1 \
1930 -C bp.tzc_400.diagnostics=1 \
1931 -C cluster0.NUM_CORES=4 \
1932 -C cluster1.NUM_CORES=4 \
1933 -C cache_state_modelled=1 \
1934 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1935 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001936 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001937 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001938
Paul Beesleyba3ed402019-03-13 16:20:44 +00001939.. note::
1940 The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires
1941 a specific DTS for all the CPUs to be loaded.
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001942
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001943Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
1944~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1945
1946The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001947with 8 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001948
Paul Beesley493e3492019-03-13 15:11:04 +00001949.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001950
1951 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1952 -C pctl.startup=0.0.0.0 \
1953 -C bp.secure_memory=1 \
1954 -C bp.tzc_400.diagnostics=1 \
1955 -C cluster0.NUM_CORES=4 \
1956 -C cluster1.NUM_CORES=4 \
1957 -C cache_state_modelled=1 \
1958 -C cluster0.cpu0.CONFIG64=0 \
1959 -C cluster0.cpu1.CONFIG64=0 \
1960 -C cluster0.cpu2.CONFIG64=0 \
1961 -C cluster0.cpu3.CONFIG64=0 \
1962 -C cluster1.cpu0.CONFIG64=0 \
1963 -C cluster1.cpu1.CONFIG64=0 \
1964 -C cluster1.cpu2.CONFIG64=0 \
1965 -C cluster1.cpu3.CONFIG64=0 \
1966 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1967 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001968 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001969 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001970
1971Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
1972~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1973
1974The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001975boot Linux with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001976
Paul Beesley493e3492019-03-13 15:11:04 +00001977.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001978
1979 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1980 -C pctl.startup=0.0.0.0 \
1981 -C bp.secure_memory=1 \
1982 -C bp.tzc_400.diagnostics=1 \
1983 -C cache_state_modelled=1 \
1984 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1985 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001986 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001987 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001988
1989Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
1990~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1991
1992The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001993boot Linux with 4 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001994
Paul Beesley493e3492019-03-13 15:11:04 +00001995.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001996
1997 <path-to>/FVP_Base_Cortex-A32x4 \
1998 -C pctl.startup=0.0.0.0 \
1999 -C bp.secure_memory=1 \
2000 -C bp.tzc_400.diagnostics=1 \
2001 -C cache_state_modelled=1 \
2002 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
2003 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002004 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002005 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002006
2007Running on the AEMv8 Base FVP with reset to BL31 entrypoint
2008~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2009
David Cunado7c032642018-03-12 18:47:05 +00002010The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00002011with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002012
Paul Beesley493e3492019-03-13 15:11:04 +00002013.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002014
David Cunado7c032642018-03-12 18:47:05 +00002015 <path-to>/FVP_Base_RevC-2xAEMv8A \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002016 -C pctl.startup=0.0.0.0 \
2017 -C bp.secure_memory=1 \
2018 -C bp.tzc_400.diagnostics=1 \
2019 -C cluster0.NUM_CORES=4 \
2020 -C cluster1.NUM_CORES=4 \
2021 -C cache_state_modelled=1 \
Soby Mathewba678c32018-12-12 14:54:23 +00002022 -C cluster0.cpu0.RVBAR=0x04010000 \
2023 -C cluster0.cpu1.RVBAR=0x04010000 \
2024 -C cluster0.cpu2.RVBAR=0x04010000 \
2025 -C cluster0.cpu3.RVBAR=0x04010000 \
2026 -C cluster1.cpu0.RVBAR=0x04010000 \
2027 -C cluster1.cpu1.RVBAR=0x04010000 \
2028 -C cluster1.cpu2.RVBAR=0x04010000 \
2029 -C cluster1.cpu3.RVBAR=0x04010000 \
2030 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
2031 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002032 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002033 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002034 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002035 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002036
2037Notes:
2038
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00002039- If Position Independent Executable (PIE) support is enabled for BL31
Soby Mathewba678c32018-12-12 14:54:23 +00002040 in this config, it can be loaded at any valid address for execution.
2041
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002042- Since a FIP is not loaded when using BL31 as reset entrypoint, the
2043 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
2044 parameter is needed to load the individual bootloader images in memory.
2045 BL32 image is only needed if BL31 has been built to expect a Secure-EL1
Soby Mathewecd94ad2018-05-09 13:59:29 +01002046 Payload. For the same reason, the FDT needs to be compiled from the DT source
2047 and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000``
2048 parameter.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002049
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00002050- The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a
2051 specific DTS for all the CPUs to be loaded.
2052
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002053- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
2054 X and Y are the cluster and CPU numbers respectively, is used to set the
2055 reset vector for each core.
2056
2057- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
2058 changing the value of
2059 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
2060 ``BL32_BASE``.
2061
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01002062Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint
2063~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002064
2065The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00002066with 8 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002067
Paul Beesley493e3492019-03-13 15:11:04 +00002068.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002069
2070 <path-to>/FVP_Base_AEMv8A-AEMv8A \
2071 -C pctl.startup=0.0.0.0 \
2072 -C bp.secure_memory=1 \
2073 -C bp.tzc_400.diagnostics=1 \
2074 -C cluster0.NUM_CORES=4 \
2075 -C cluster1.NUM_CORES=4 \
2076 -C cache_state_modelled=1 \
2077 -C cluster0.cpu0.CONFIG64=0 \
2078 -C cluster0.cpu1.CONFIG64=0 \
2079 -C cluster0.cpu2.CONFIG64=0 \
2080 -C cluster0.cpu3.CONFIG64=0 \
2081 -C cluster1.cpu0.CONFIG64=0 \
2082 -C cluster1.cpu1.CONFIG64=0 \
2083 -C cluster1.cpu2.CONFIG64=0 \
2084 -C cluster1.cpu3.CONFIG64=0 \
Soby Mathewba678c32018-12-12 14:54:23 +00002085 -C cluster0.cpu0.RVBAR=0x04002000 \
2086 -C cluster0.cpu1.RVBAR=0x04002000 \
2087 -C cluster0.cpu2.RVBAR=0x04002000 \
2088 -C cluster0.cpu3.RVBAR=0x04002000 \
2089 -C cluster1.cpu0.RVBAR=0x04002000 \
2090 -C cluster1.cpu1.RVBAR=0x04002000 \
2091 -C cluster1.cpu2.RVBAR=0x04002000 \
2092 -C cluster1.cpu3.RVBAR=0x04002000 \
Soby Mathewaf14b462018-06-01 16:53:38 +01002093 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002094 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002095 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002096 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002097 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002098
Paul Beesleyba3ed402019-03-13 16:20:44 +00002099.. note::
2100 The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
2101 It should match the address programmed into the RVBAR register as well.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002102
2103Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
2104~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2105
2106The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00002107boot Linux with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002108
Paul Beesley493e3492019-03-13 15:11:04 +00002109.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002110
2111 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
2112 -C pctl.startup=0.0.0.0 \
2113 -C bp.secure_memory=1 \
2114 -C bp.tzc_400.diagnostics=1 \
2115 -C cache_state_modelled=1 \
Soby Mathewba678c32018-12-12 14:54:23 +00002116 -C cluster0.cpu0.RVBARADDR=0x04010000 \
2117 -C cluster0.cpu1.RVBARADDR=0x04010000 \
2118 -C cluster0.cpu2.RVBARADDR=0x04010000 \
2119 -C cluster0.cpu3.RVBARADDR=0x04010000 \
2120 -C cluster1.cpu0.RVBARADDR=0x04010000 \
2121 -C cluster1.cpu1.RVBARADDR=0x04010000 \
2122 -C cluster1.cpu2.RVBARADDR=0x04010000 \
2123 -C cluster1.cpu3.RVBARADDR=0x04010000 \
2124 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
2125 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002126 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002127 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002128 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002129 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002130
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01002131Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint
2132~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002133
2134The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00002135boot Linux with 4 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002136
Paul Beesley493e3492019-03-13 15:11:04 +00002137.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002138
2139 <path-to>/FVP_Base_Cortex-A32x4 \
2140 -C pctl.startup=0.0.0.0 \
2141 -C bp.secure_memory=1 \
2142 -C bp.tzc_400.diagnostics=1 \
2143 -C cache_state_modelled=1 \
Soby Mathewba678c32018-12-12 14:54:23 +00002144 -C cluster0.cpu0.RVBARADDR=0x04002000 \
2145 -C cluster0.cpu1.RVBARADDR=0x04002000 \
2146 -C cluster0.cpu2.RVBARADDR=0x04002000 \
2147 -C cluster0.cpu3.RVBARADDR=0x04002000 \
Soby Mathewaf14b462018-06-01 16:53:38 +01002148 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002149 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002150 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002151 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002152 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002153
2154Running the software on Juno
2155----------------------------
2156
Dan Handley610e7e12018-03-01 18:44:00 +00002157This version of TF-A has been tested on variants r0, r1 and r2 of Juno.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002158
zelalem-aweke81a21032019-09-20 11:15:20 -05002159To execute the software stack on Juno, installing the latest Arm Platforms
2160software deliverables is recommended. Please install the deliverables by
2161following the `Instructions for using Linaro's deliverables on Juno`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002162
Dan Handley610e7e12018-03-01 18:44:00 +00002163Preparing TF-A images
2164~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002165
Dan Handley610e7e12018-03-01 18:44:00 +00002166After building TF-A, the files ``bl1.bin`` and ``fip.bin`` need copying to the
2167``SOFTWARE/`` directory of the Juno SD card.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002168
2169Other Juno software information
2170~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2171
Dan Handley610e7e12018-03-01 18:44:00 +00002172Please visit the `Arm Platforms Portal`_ to get support and obtain any other Juno
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002173software information. Please also refer to the `Juno Getting Started Guide`_ to
Dan Handley610e7e12018-03-01 18:44:00 +00002174get more detailed information about the Juno Arm development platform and how to
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002175configure it.
2176
2177Testing SYSTEM SUSPEND on Juno
2178~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2179
2180The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend
2181to RAM. For more details refer to section 5.16 of `PSCI`_. To test system suspend
2182on Juno, at the linux shell prompt, issue the following command:
2183
Paul Beesley493e3492019-03-13 15:11:04 +00002184.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002185
2186 echo +10 > /sys/class/rtc/rtc0/wakealarm
2187 echo -n mem > /sys/power/state
2188
2189The Juno board should suspend to RAM and then wakeup after 10 seconds due to
2190wakeup interrupt from RTC.
2191
2192--------------
2193
Antonio Nino Diaz0e402d32019-01-30 16:01:49 +00002194*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002195
zelalem-aweke81a21032019-09-20 11:15:20 -05002196.. _Arm Developer page: https://developer.arm.com/open-source/gnu-toolchain/gnu-a/downloads
2197.. _Linaro Release: http://releases.linaro.org/members/arm/platforms
2198.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06
2199.. _Linaro instructions: https://git.linaro.org/landing-teams/working/arm/arm-reference-platforms.git/about
2200.. _Arm Platforms User guide: https://git.linaro.org/landing-teams/working/arm/arm-reference-platforms.git/about/docs/user-guide.rst
David Cunado82509be2017-12-19 16:33:25 +00002201.. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno
Dan Handley610e7e12018-03-01 18:44:00 +00002202.. _Arm Platforms Portal: https://community.arm.com/dev-platforms/
Paul Beesley2437ddc2019-02-08 16:43:05 +00002203.. _Development Studio 5 (DS-5): https://developer.arm.com/products/software-development-tools/ds-5-development-studio
Louis Mayencourt72ef3d42019-03-22 11:47:22 +00002204.. _arm-trusted-firmware-a project page: https://review.trustedfirmware.org/admin/projects/TF-A/trusted-firmware-a
Paul Beesley8b4bdeb2019-01-21 12:06:24 +00002205.. _`Linux Coding Style`: https://www.kernel.org/doc/html/latest/process/coding-style.html
Sandrine Bailleux771535b2018-09-20 10:27:13 +02002206.. _Linux master tree: https://github.com/torvalds/linux/tree/master/
Antonio Nino Diazb5d68092017-05-23 11:49:22 +01002207.. _Dia: https://wiki.gnome.org/Apps/Dia/Download
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002208.. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git
2209.. _mbed TLS Security Center: https://tls.mbed.org/security
Dan Handley610e7e12018-03-01 18:44:00 +00002210.. _Arm's website: `FVP models`_
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002211.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002212.. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf
David Cunadob2de0992017-06-29 12:01:33 +01002213.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf