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Dan Handley610e7e12018-03-01 18:44:00 +00001Trusted Firmware-A User Guide
2=============================
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
4
5.. section-numbering::
6 :suffix: .
7
8.. contents::
9
Dan Handley610e7e12018-03-01 18:44:00 +000010This document describes how to build Trusted Firmware-A (TF-A) and run it with a
Douglas Raillardd7c21b72017-06-28 15:23:03 +010011tested set of other software components using defined configurations on the Juno
Dan Handley610e7e12018-03-01 18:44:00 +000012Arm development platform and Arm Fixed Virtual Platform (FVP) models. It is
Douglas Raillardd7c21b72017-06-28 15:23:03 +010013possible to use other software components, configurations and platforms but that
14is outside the scope of this document.
15
16This document assumes that the reader has previous experience running a fully
17bootable Linux software stack on Juno or FVP using the prebuilt binaries and
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010018filesystems provided by `Linaro`_. Further information may be found in the
19`Linaro instructions`_. It also assumes that the user understands the role of
20the different software components required to boot a Linux system:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010021
22- Specific firmware images required by the platform (e.g. SCP firmware on Juno)
23- Normal world bootloader (e.g. UEFI or U-Boot)
24- Device tree
25- Linux kernel image
26- Root filesystem
27
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010028This document also assumes that the user is familiar with the `FVP models`_ and
Douglas Raillardd7c21b72017-06-28 15:23:03 +010029the different command line options available to launch the model.
30
31This document should be used in conjunction with the `Firmware Design`_.
32
33Host machine requirements
34-------------------------
35
36The minimum recommended machine specification for building the software and
37running the FVP models is a dual-core processor running at 2GHz with 12GB of
38RAM. For best performance, use a machine with a quad-core processor running at
392.6GHz with 16GB of RAM.
40
Joel Huttonfe027712018-03-19 11:59:57 +000041The software has been tested on Ubuntu 16.04 LTS (64-bit). Packages used for
Douglas Raillardd7c21b72017-06-28 15:23:03 +010042building the software were installed from that distribution unless otherwise
43specified.
44
45The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE,
David Cunadob2de0992017-06-29 12:01:33 +010046Cygwin, and Msys (MinGW) shells, using version 5.3.1 of the GNU toolchain.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010047
48Tools
49-----
50
Dan Handley610e7e12018-03-01 18:44:00 +000051Install the required packages to build TF-A with the following command:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010052
53::
54
55 sudo apt-get install build-essential gcc make git libssl-dev
56
Dan Handley610e7e12018-03-01 18:44:00 +000057TF-A has been tested with `Linaro Release 17.10`_.
David Cunadob2de0992017-06-29 12:01:33 +010058
Douglas Raillardd7c21b72017-06-28 15:23:03 +010059Download and install the AArch32 or AArch64 little-endian GCC cross compiler.
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010060The `Linaro Release Notes`_ documents which version of the compiler to use for a
61given Linaro Release. Also, these `Linaro instructions`_ provide further
62guidance and a script, which can be used to download Linaro deliverables
63automatically.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010064
Roberto Vargas0489bc02018-04-16 15:43:26 +010065Optionally, TF-A can be built using clang version 4.0 or newer or Arm
66Compiler 6. See instructions below on how to switch the default compiler.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010067
68In addition, the following optional packages and tools may be needed:
69
70- ``device-tree-compiler`` package if you need to rebuild the Flattened Device
71 Tree (FDT) source files (``.dts`` files) provided with this software.
72
Dan Handley610e7e12018-03-01 18:44:00 +000073- For debugging, Arm `Development Studio 5 (DS-5)`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010074
Antonio Nino Diazb5d68092017-05-23 11:49:22 +010075- To create and modify the diagram files included in the documentation, `Dia`_.
76 This tool can be found in most Linux distributions. Inkscape is needed to
77 generate the actual *.png files.
78
Dan Handley610e7e12018-03-01 18:44:00 +000079Getting the TF-A source code
80----------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +010081
Dan Handley610e7e12018-03-01 18:44:00 +000082Download the TF-A source code from Github:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010083
84::
85
86 git clone https://github.com/ARM-software/arm-trusted-firmware.git
87
Dan Handley610e7e12018-03-01 18:44:00 +000088Building TF-A
89-------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +010090
Dan Handley610e7e12018-03-01 18:44:00 +000091- Before building TF-A, the environment variable ``CROSS_COMPILE`` must point
92 to the Linaro cross compiler.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010093
94 For AArch64:
95
96 ::
97
98 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
99
100 For AArch32:
101
102 ::
103
104 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
105
Dan Handley610e7e12018-03-01 18:44:00 +0000106 It is possible to build TF-A using clang or Arm Compiler 6. To do so
107 ``CC`` needs to point to the clang or armclang binary. Only the compiler
108 is switched; the assembler and linker need to be provided by the GNU
109 toolchain, thus ``CROSS_COMPILE`` should be set as described above.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100110
Dan Handley610e7e12018-03-01 18:44:00 +0000111 Arm Compiler 6 will be selected when the base name of the path assigned
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100112 to ``CC`` matches the string 'armclang'.
113
Dan Handley610e7e12018-03-01 18:44:00 +0000114 For AArch64 using Arm Compiler 6:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100115
116 ::
117
118 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
119 make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
120
121 Clang will be selected when the base name of the path assigned to ``CC``
122 contains the string 'clang'. This is to allow both clang and clang-X.Y
123 to work.
124
125 For AArch64 using clang:
126
127 ::
128
129 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
130 make CC=<path-to-clang>/bin/clang PLAT=<platform> all
131
Dan Handley610e7e12018-03-01 18:44:00 +0000132- Change to the root directory of the TF-A source tree and build.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100133
134 For AArch64:
135
136 ::
137
138 make PLAT=<platform> all
139
140 For AArch32:
141
142 ::
143
144 make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all
145
146 Notes:
147
148 - If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the
149 `Summary of build options`_ for more information on available build
150 options.
151
152 - (AArch32 only) Currently only ``PLAT=fvp`` is supported.
153
154 - (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
155 corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp\_min, is
Dan Handley610e7e12018-03-01 18:44:00 +0000156 provided by TF-A to demonstrate how PSCI Library can be integrated with
157 an AArch32 EL3 Runtime Software. Some AArch32 EL3 Runtime Software may
158 include other runtime services, for example Trusted OS services. A guide
159 to integrate PSCI library with AArch32 EL3 Runtime Software can be found
160 `here`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100161
162 - (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32
163 image, is not compiled in by default. Refer to the
164 `Building the Test Secure Payload`_ section below.
165
166 - By default this produces a release version of the build. To produce a
167 debug version instead, refer to the "Debugging options" section below.
168
169 - The build process creates products in a ``build`` directory tree, building
170 the objects and binaries for each boot loader stage in separate
171 sub-directories. The following boot loader binary files are created
172 from the corresponding ELF files:
173
174 - ``build/<platform>/<build-type>/bl1.bin``
175 - ``build/<platform>/<build-type>/bl2.bin``
176 - ``build/<platform>/<build-type>/bl31.bin`` (AArch64 only)
177 - ``build/<platform>/<build-type>/bl32.bin`` (mandatory for AArch32)
178
179 where ``<platform>`` is the name of the chosen platform and ``<build-type>``
180 is either ``debug`` or ``release``. The actual number of images might differ
181 depending on the platform.
182
183- Build products for a specific build variant can be removed using:
184
185 ::
186
187 make DEBUG=<D> PLAT=<platform> clean
188
189 ... where ``<D>`` is ``0`` or ``1``, as specified when building.
190
191 The build tree can be removed completely using:
192
193 ::
194
195 make realclean
196
197Summary of build options
198~~~~~~~~~~~~~~~~~~~~~~~~
199
Dan Handley610e7e12018-03-01 18:44:00 +0000200The TF-A build system supports the following build options. Unless mentioned
201otherwise, these options are expected to be specified at the build command
202line and are not to be modified in any component makefiles. Note that the
203build system doesn't track dependency for build options. Therefore, if any of
204the build options are changed from a previous build, a clean build must be
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100205performed.
206
207Common build options
208^^^^^^^^^^^^^^^^^^^^
209
210- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
211 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
212 directory containing the SP source, relative to the ``bl32/``; the directory
213 is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
214
Dan Handley610e7e12018-03-01 18:44:00 +0000215- ``ARCH`` : Choose the target build architecture for TF-A. It can take either
216 ``aarch64`` or ``aarch32`` as values. By default, it is defined to
217 ``aarch64``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100218
Dan Handley610e7e12018-03-01 18:44:00 +0000219- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when
220 compiling TF-A. Its value must be numeric, and defaults to 8 . See also,
221 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in
222 `Firmware Design`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100223
Dan Handley610e7e12018-03-01 18:44:00 +0000224- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when
225 compiling TF-A. Its value must be a numeric, and defaults to 0. See also,
226 *Armv8 Architecture Extensions* in `Firmware Design`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100227
Dan Handley610e7e12018-03-01 18:44:00 +0000228- ``ARM_GIC_ARCH``: Choice of Arm GIC architecture version used by the Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100229 Legacy GIC driver for implementing the platform GIC API. This API is used
230 by the interrupt management framework. Default is 2 (that is, version 2.0).
231 This build option is deprecated.
232
Dan Handley610e7e12018-03-01 18:44:00 +0000233- ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000234 cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
235 is set, the functions which deal with MPIDR assume that the ``MT`` bit in
236 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
237 this flag is 0. Note that this option is not used on FVP platforms.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100238
239- ``BL2``: This is an optional build option which specifies the path to BL2
Dan Handley610e7e12018-03-01 18:44:00 +0000240 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be
241 built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100242
243- ``BL2U``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000244 BL2U image. In this case, the BL2U in TF-A will not be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100245
John Tsichritzisee10e792018-06-06 09:38:10 +0100246- ``BL2_AT_EL3``: This is an optional build option that enables the use of
Roberto Vargasb1584272017-11-20 13:36:10 +0000247 BL2 at EL3 execution level.
248
John Tsichritzisee10e792018-06-06 09:38:10 +0100249- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000250 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize
251 the RW sections in RAM, while leaving the RO sections in place. This option
252 enable this use-case. For now, this option is only supported when BL2_AT_EL3
253 is set to '1'.
254
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100255- ``BL31``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000256 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not
257 be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100258
259- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
260 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
261 this file name will be used to save the key.
262
263- ``BL32``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000264 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not
265 be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100266
John Tsichritzisee10e792018-06-06 09:38:10 +0100267- ``BL32_EXTRA1``: This is an optional build option which specifies the path to
Summer Qin80726782017-04-20 16:28:39 +0100268 Trusted OS Extra1 image for the ``fip`` target.
269
John Tsichritzisee10e792018-06-06 09:38:10 +0100270- ``BL32_EXTRA2``: This is an optional build option which specifies the path to
Summer Qin80726782017-04-20 16:28:39 +0100271 Trusted OS Extra2 image for the ``fip`` target.
272
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100273- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
274 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
275 this file name will be used to save the key.
276
277- ``BL33``: Path to BL33 image in the host file system. This is mandatory for
Dan Handley610e7e12018-03-01 18:44:00 +0000278 ``fip`` target in case TF-A BL2 is used.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100279
280- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
281 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
282 this file name will be used to save the key.
283
284- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
285 compilation of each build. It must be set to a C string (including quotes
286 where applicable). Defaults to a string that contains the time and date of
287 the compilation.
288
Dan Handley610e7e12018-03-01 18:44:00 +0000289- ``BUILD_STRING``: Input string for VERSION\_STRING, which allows the TF-A
290 build to be uniquely identified. Defaults to the current git commit id.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100291
292- ``CFLAGS``: Extra user options appended on the compiler's command line in
293 addition to the options set by the build system.
294
295- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
296 release several CPUs out of reset. It can take either 0 (several CPUs may be
297 brought up) or 1 (only one CPU will ever be brought up during cold reset).
298 Default is 0. If the platform always brings up a single CPU, there is no
299 need to distinguish between primary and secondary CPUs and the boot path can
300 be optimised. The ``plat_is_my_cpu_primary()`` and
301 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
302 to be implemented in this case.
303
304- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
305 register state when an unexpected exception occurs during execution of
306 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
307 this is only enabled for a debug build of the firmware.
308
309- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
310 certificate generation tool to create new keys in case no valid keys are
311 present or specified. Allowed options are '0' or '1'. Default is '1'.
312
313- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
314 the AArch32 system registers to be included when saving and restoring the
315 CPU context. The option must be set to 0 for AArch64-only platforms (that
316 is on hardware that does not implement AArch32, or at least not at EL1 and
317 higher ELs). Default value is 1.
318
319- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
320 registers to be included when saving and restoring the CPU context. Default
321 is 0.
322
323- ``DEBUG``: Chooses between a debug and release build. It can take either 0
324 (release) or 1 (debug) as values. 0 is the default.
325
John Tsichritzisee10e792018-06-06 09:38:10 +0100326- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted
327 Board Boot authentication at runtime. This option is meant to be enabled only
328 for development platforms. Both TRUSTED_BOARD_BOOT and LOAD_IMAGE_V2 flags
329 must be set if this flag has to be enabled. 0 is the default.
Soby Mathew9fe88042018-03-26 12:43:37 +0100330
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100331- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
332 the normal boot flow. It must specify the entry point address of the EL3
333 payload. Please refer to the "Booting an EL3 payload" section for more
334 details.
335
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100336- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions.
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100337 This is an optional architectural feature available on v8.4 onwards. Some
338 v8.2 implementations also implement an AMU and this option can be used to
339 enable this feature on those systems as well. Default is 0.
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100340
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100341- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
342 are compiled out. For debug builds, this option defaults to 1, and calls to
343 ``assert()`` are left in place. For release builds, this option defaults to 0
344 and calls to ``assert()`` function are compiled out. This option can be set
345 independently of ``DEBUG``. It can also be used to hide any auxiliary code
346 that is only required for the assertion and does not fit in the assertion
347 itself.
348
349- ``ENABLE_PMF``: Boolean option to enable support for optional Performance
350 Measurement Framework(PMF). Default is 0.
351
352- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
353 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
354 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
355 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
356 software.
357
358- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
Dan Handley610e7e12018-03-01 18:44:00 +0000359 instrumentation which injects timestamp collection points into TF-A to
360 allow runtime performance to be measured. Currently, only PSCI is
361 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option
362 as well. Default is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100363
Jeenu Viswambharand73dcf32017-07-19 13:52:12 +0100364- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100365 extensions. This is an optional architectural feature for AArch64.
366 The default is 1 but is automatically disabled when the target architecture
367 is AArch32.
Jeenu Viswambharand73dcf32017-07-19 13:52:12 +0100368
David Cunadoce88eee2017-10-20 11:30:57 +0100369- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
370 (SVE) for the Non-secure world only. SVE is an optional architectural feature
371 for AArch64. Note that when SVE is enabled for the Non-secure world, access
372 to SIMD and floating-point functionality from the Secure world is disabled.
373 This is to avoid corruption of the Non-secure world data in the Z-registers
374 which are aliased by the SIMD and FP registers. The build option is not
375 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
376 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to
377 1. The default is 1 but is automatically disabled when the target
378 architecture is AArch32.
379
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100380- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
381 checks in GCC. Allowed values are "all", "strong" and "0" (default).
382 "strong" is the recommended stack protection level if this feature is
383 desired. 0 disables the stack protection. For all values other than 0, the
384 ``plat_get_stack_protector_canary()`` platform hook needs to be implemented.
385 The value is passed as the last component of the option
386 ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
387
388- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
389 deprecated platform APIs, helper functions or drivers within Trusted
390 Firmware as error. It can take the value 1 (flag the use of deprecated
391 APIs as error) or 0. The default is 0.
392
Jeenu Viswambharan10a67272017-09-22 08:32:10 +0100393- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
394 targeted at EL3. When set ``0`` (default), no exceptions are expected or
395 handled at EL3, and a panic will result. This is supported only for AArch64
396 builds.
397
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000398- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 externsions introduced support for fault
399 injection from lower ELs, and this build option enables lower ELs to use
400 Error Records accessed via System Registers to inject faults. This is
401 applicable only to AArch64 builds.
402
403 This feature is intended for testing purposes only, and is advisable to keep
404 disabled for production images.
405
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100406- ``FIP_NAME``: This is an optional build option which specifies the FIP
407 filename for the ``fip`` target. Default is ``fip.bin``.
408
409- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
410 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
411
412- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
413 tool to create certificates as per the Chain of Trust described in
414 `Trusted Board Boot`_. The build system then calls ``fiptool`` to
415 include the certificates in the FIP and FWU\_FIP. Default value is '0'.
416
417 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
418 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
419 the corresponding certificates, and to include those certificates in the
420 FIP and FWU\_FIP.
421
422 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
423 images will not include support for Trusted Board Boot. The FIP will still
424 include the corresponding certificates. This FIP can be used to verify the
425 Chain of Trust on the host machine through other mechanisms.
426
427 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
428 images will include support for Trusted Board Boot, but the FIP and FWU\_FIP
429 will not include the corresponding certificates, causing a boot failure.
430
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100431- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
432 inherent support for specific EL3 type interrupts. Setting this build option
433 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both
434 by `platform abstraction layer`__ and `Interrupt Management Framework`__.
435 This allows GICv2 platforms to enable features requiring EL3 interrupt type.
436 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and
437 the Secure Payload interrupts needs to be synchronously handed over to Secure
438 EL1 for handling. The default value of this option is ``0``, which means the
439 Group 0 interrupts are assumed to be handled by Secure EL1.
440
441 .. __: `platform-interrupt-controller-API.rst`
442 .. __: `interrupt-framework-design.rst`
443
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100444- ``HANDLE_EA_EL3_FIRST``: When defined External Aborts and SError Interrupts
445 will be always trapped in EL3 i.e. in BL31 at runtime.
446
Dan Handley610e7e12018-03-01 18:44:00 +0000447- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100448 software operations are required for CPUs to enter and exit coherency.
449 However, there exists newer systems where CPUs' entry to and exit from
450 coherency is managed in hardware. Such systems require software to only
451 initiate the operations, and the rest is managed in hardware, minimizing
Dan Handley610e7e12018-03-01 18:44:00 +0000452 active software management. In such systems, this boolean option enables
453 TF-A to carry out build and run-time optimizations during boot and power
454 management operations. This option defaults to 0 and if it is enabled,
455 then it implies ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100456
Jeenu Viswambharane834ee12018-04-27 15:17:03 +0100457 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of
458 translation library (xlat tables v2) must be used; version 1 of translation
459 library is not supported.
460
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100461- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3
462 runtime software in AArch32 mode, which is required to run AArch32 on Juno.
463 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in
464 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
465 images.
466
Soby Mathew13b16052017-08-31 11:49:32 +0100467- ``KEY_ALG``: This build flag enables the user to select the algorithm to be
468 used for generating the PKCS keys and subsequent signing of the certificate.
Qixiang Xu1a1f2912017-11-09 13:56:29 +0800469 It accepts 3 values viz. ``rsa``, ``rsa_1_5``, ``ecdsa``. The ``rsa_1_5`` is
Soby Mathew2fd70f62017-08-31 11:50:29 +0100470 the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR compliant and is
471 retained only for compatibility. The default value of this flag is ``rsa``
472 which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
Soby Mathew13b16052017-08-31 11:49:32 +0100473
Qixiang Xu1a1f2912017-11-09 13:56:29 +0800474- ``HASH_ALG``: This build flag enables the user to select the secure hash
475 algorithm. It accepts 3 values viz. ``sha256``, ``sha384``, ``sha512``.
476 The default value of this flag is ``sha256``.
477
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100478- ``LDFLAGS``: Extra user options appended to the linkers' command line in
479 addition to the one set by the build system.
480
481- ``LOAD_IMAGE_V2``: Boolean option to enable support for new version (v2) of
482 image loading, which provides more flexibility and scalability around what
483 images are loaded and executed during boot. Default is 0.
484 Note: ``TRUSTED_BOARD_BOOT`` is currently only supported for AArch64 when
485 ``LOAD_IMAGE_V2`` is enabled.
486
487- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
488 output compiled into the build. This should be one of the following:
489
490 ::
491
492 0 (LOG_LEVEL_NONE)
Daniel Boulby86c6b072018-06-14 10:07:40 +0100493 10 (LOG_LEVEL_ERROR)
494 20 (LOG_LEVEL_NOTICE)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100495 30 (LOG_LEVEL_WARNING)
496 40 (LOG_LEVEL_INFO)
497 50 (LOG_LEVEL_VERBOSE)
498
499 All log output up to and including the log level is compiled into the build.
500 The default value is 40 in debug builds and 20 in release builds.
501
502- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
503 specifies the file that contains the Non-Trusted World private key in PEM
504 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
505
506- ``NS_BL2U``: Path to NS\_BL2U image in the host file system. This image is
507 optional. It is only needed if the platform makefile specifies that it
508 is required in order to build the ``fwu_fip`` target.
509
510- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
511 contents upon world switch. It can take either 0 (don't save and restore) or
512 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
513 wants the timer registers to be saved and restored.
514
515- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
516 the underlying hardware is not a full PL011 UART but a minimally compliant
517 generic UART, which is a subset of the PL011. The driver will not access
518 any register that is not part of the SBSA generic UART specification.
519 Default value is 0 (a full PL011 compliant UART is present).
520
Dan Handley610e7e12018-03-01 18:44:00 +0000521- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name
522 must be subdirectory of any depth under ``plat/``, and must contain a
523 platform makefile named ``platform.mk``. For example, to build TF-A for the
524 Arm Juno board, select PLAT=juno.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100525
526- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
527 instead of the normal boot flow. When defined, it must specify the entry
528 point address for the preloaded BL33 image. This option is incompatible with
529 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
530 over ``PRELOADED_BL33_BASE``.
531
532- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
533 vector address can be programmed or is fixed on the platform. It can take
534 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
535 programmable reset address, it is expected that a CPU will start executing
536 code directly at the right address, both on a cold and warm reset. In this
537 case, there is no need to identify the entrypoint on boot and the boot path
538 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
539 does not need to be implemented in this case.
540
541- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
542 possible for the PSCI power-state parameter viz original and extended
543 State-ID formats. This flag if set to 1, configures the generic PSCI layer
544 to use the extended format. The default value of this flag is 0, which
545 means by default the original power-state format is used by the PSCI
546 implementation. This flag should be specified by the platform makefile
547 and it governs the return value of PSCI\_FEATURES API for CPU\_SUSPEND
Dan Handley610e7e12018-03-01 18:44:00 +0000548 smc function id. When this option is enabled on Arm platforms, the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100549 option ``ARM_RECOM_STATE_ID_ENC`` needs to be set to 1 as well.
550
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100551- ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features
552 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2
553 or later CPUs.
554
555 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be
556 set to ``1``.
557
558 This option is disabled by default.
559
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100560- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
561 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
562 entrypoint) or 1 (CPU reset to BL31 entrypoint).
563 The default value is 0.
564
Dan Handley610e7e12018-03-01 18:44:00 +0000565- ``RESET_TO_SP_MIN``: SP\_MIN is the minimal AArch32 Secure Payload provided
566 in TF-A. This flag configures SP\_MIN entrypoint as the CPU reset vector
567 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
568 entrypoint) or 1 (CPU reset to SP\_MIN entrypoint). The default value is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100569
570- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
571 file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this
572 file name will be used to save the key.
573
574- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
575 certificate generation tool to save the keys used to establish the Chain of
576 Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
577
578- ``SCP_BL2``: Path to SCP\_BL2 image in the host file system. This image is optional.
579 If a SCP\_BL2 image is present then this option must be passed for the ``fip``
580 target.
581
582- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
583 file that contains the SCP\_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
584 this file name will be used to save the key.
585
586- ``SCP_BL2U``: Path to SCP\_BL2U image in the host file system. This image is
587 optional. It is only needed if the platform makefile specifies that it
588 is required in order to build the ``fwu_fip`` target.
589
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +0100590- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software
591 Delegated Exception Interface to BL31 image. This defaults to ``0``.
592
593 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be
594 set to ``1``.
595
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100596- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
597 isolated on separate memory pages. This is a trade-off between security and
598 memory usage. See "Isolating code and read-only data on separate memory
599 pages" section in `Firmware Design`_. This flag is disabled by default and
600 affects all BL images.
601
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100602- ``SMCCC_MAJOR_VERSION``: Numeric value that indicates the major version of
603 the SMC Calling Convention that the Trusted Firmware supports. The only two
604 allowed values are 1 and 2, and it defaults to 1. The minor version is
605 determined using this value.
606
Dan Handley610e7e12018-03-01 18:44:00 +0000607- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
608 This build option is only valid if ``ARCH=aarch64``. The value should be
609 the path to the directory containing the SPD source, relative to
610 ``services/spd/``; the directory is expected to contain a makefile called
611 ``<spd-value>.mk``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100612
613- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
614 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
615 execution in BL1 just before handing over to BL31. At this point, all
616 firmware images have been loaded in memory, and the MMU and caches are
617 turned off. Refer to the "Debugging options" section for more details.
618
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100619- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
Etienne Carrieredc0fea72017-08-09 15:48:53 +0200620 secure interrupts (caught through the FIQ line). Platforms can enable
621 this directive if they need to handle such interruption. When enabled,
622 the FIQ are handled in monitor mode and non secure world is not allowed
623 to mask these events. Platforms that enable FIQ handling in SP_MIN shall
624 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
625
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100626- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
627 Boot feature. When set to '1', BL1 and BL2 images include support to load
628 and verify the certificates and images in a FIP, and BL1 includes support
629 for the Firmware Update. The default value is '0'. Generation and inclusion
630 of certificates in the FIP and FWU\_FIP depends upon the value of the
631 ``GENERATE_COT`` option.
632
633 Note: This option depends on ``CREATE_KEYS`` to be enabled. If the keys
634 already exist in disk, they will be overwritten without further notice.
635
636- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
637 specifies the file that contains the Trusted World private key in PEM
638 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
639
640- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
641 synchronous, (see "Initializing a BL32 Image" section in
642 `Firmware Design`_). It can take the value 0 (BL32 is initialized using
643 synchronous method) or 1 (BL32 is initialized using asynchronous method).
644 Default is 0.
645
646- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
647 routing model which routes non-secure interrupts asynchronously from TSP
648 to EL3 causing immediate preemption of TSP. The EL3 is responsible
649 for saving and restoring the TSP context in this routing model. The
650 default routing model (when the value is 0) is to route non-secure
651 interrupts to TSP allowing it to save its context and hand over
652 synchronously to EL3 via an SMC.
653
Jeenu Viswambharan2f40f322018-01-11 14:30:22 +0000654 Note: when ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT``
655 must also be set to ``1``.
656
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100657- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
658 memory region in the BL memory map or not (see "Use of Coherent memory in
Dan Handley610e7e12018-03-01 18:44:00 +0000659 TF-A" section in `Firmware Design`_). It can take the value 1
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100660 (Coherent memory region is included) or 0 (Coherent memory region is
661 excluded). Default is 1.
662
663- ``V``: Verbose build. If assigned anything other than 0, the build commands
664 are printed. Default is 0.
665
Dan Handley610e7e12018-03-01 18:44:00 +0000666- ``VERSION_STRING``: String used in the log output for each TF-A image.
667 Defaults to a string formed by concatenating the version number, build type
668 and build string.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100669
670- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
671 the CPU after warm boot. This is applicable for platforms which do not
672 require interconnect programming to enable cache coherency (eg: single
673 cluster platforms). If this option is enabled, then warm boot path
674 enables D-caches immediately after enabling MMU. This option defaults to 0.
675
Dan Handley610e7e12018-03-01 18:44:00 +0000676Arm development platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100677^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
678
679- ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured
680 DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load
681 BL31 in TZC secured DRAM. If TSP is present, then setting this option also
682 sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build
683 flag.
684
685- ``ARM_BOARD_OPTIMISE_MEM``: Boolean option to enable or disable optimisation
686 of the memory reserved for each image. This affects the maximum size of each
687 BL image as well as the number of allocated memory regions and translation
688 tables. By default this flag is 0, which means it uses the default
Dan Handley610e7e12018-03-01 18:44:00 +0000689 unoptimised values for these macros. Arm development platforms that wish to
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100690 optimise memory usage need to set this flag to 1 and must override the
691 related macros.
692
693- ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
694 frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
695 frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which should
696 match the frame used by the Non-Secure image (normally the Linux kernel).
697 Default is true (access to the frame is allowed).
698
699- ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
Dan Handley610e7e12018-03-01 18:44:00 +0000700 By default, Arm platforms use a watchdog to trigger a system reset in case
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100701 an error is encountered during the boot process (for example, when an image
702 could not be loaded or authenticated). The watchdog is enabled in the early
703 platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The
704 Trusted Watchdog may be disabled at build time for testing or development
705 purposes.
706
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100707- ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to
708 have specific values at boot. This boolean option allows the Trusted Firmware
709 to have a Linux kernel image as BL33 by preparing the registers to these
710 values before jumping to BL33. This option defaults to 0 (disabled). For now,
711 it only supports AArch64 kernels. ``RESET_TO_BL31`` must be 1 when using it.
712 If this option is set to 1, ``ARM_PRELOADED_DTB_BASE`` must be set to the
713 location of a device tree blob (DTB) already loaded in memory. The Linux
714 Image address must be specified using the ``PRELOADED_BL33_BASE`` option.
715
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100716- ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding
717 for the construction of composite state-ID in the power-state parameter.
718 The existing PSCI clients currently do not support this encoding of
719 State-ID yet. Hence this flag is used to configure whether to use the
720 recommended State-ID encoding or not. The default value of this flag is 0,
721 in which case the platform is configured to expect NULL in the State-ID
722 field of power-state parameter.
723
724- ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the
725 location of the ROTPK hash returned by the function ``plat_get_rotpk_info()``
Dan Handley610e7e12018-03-01 18:44:00 +0000726 for Arm platforms. Depending on the selected option, the proper private key
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100727 must be specified using the ``ROT_KEY`` option when building the Trusted
728 Firmware. This private key will be used by the certificate generation tool
729 to sign the BL2 and Trusted Key certificates. Available options for
730 ``ARM_ROTPK_LOCATION`` are:
731
732 - ``regs`` : return the ROTPK hash stored in the Trusted root-key storage
733 registers. The private key corresponding to this ROTPK hash is not
734 currently available.
735 - ``devel_rsa`` : return a development public key hash embedded in the BL1
736 and BL2 binaries. This hash has been obtained from the RSA public key
737 ``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use
738 this option, ``arm_rotprivk_rsa.pem`` must be specified as ``ROT_KEY`` when
739 creating the certificates.
Qixiang Xu1c2aef12017-08-24 15:12:20 +0800740 - ``devel_ecdsa`` : return a development public key hash embedded in the BL1
741 and BL2 binaries. This hash has been obtained from the ECDSA public key
742 ``arm_rotpk_ecdsa.der``, located in ``plat/arm/board/common/rotpk``. To use
743 this option, ``arm_rotprivk_ecdsa.pem`` must be specified as ``ROT_KEY``
744 when creating the certificates.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100745
746- ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options:
747
Qixiang Xuc7b12c52017-10-13 09:04:12 +0800748 - ``tsram`` : Trusted SRAM (default option when TBB is not enabled)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100749 - ``tdram`` : Trusted DRAM (if available)
John Tsichritzisee10e792018-06-06 09:38:10 +0100750 - ``dram`` : Secure region in DRAM (default option when TBB is enabled,
751 configured by the TrustZone controller)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100752
Dan Handley610e7e12018-03-01 18:44:00 +0000753- ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile TF-A with version 1
754 of the translation tables library instead of version 2. It is set to 0 by
755 default, which selects version 2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100756
Dan Handley610e7e12018-03-01 18:44:00 +0000757- ``ARM_CRYPTOCELL_INTEG`` : bool option to enable TF-A to invoke Arm®
758 TrustZone® CryptoCell functionality for Trusted Board Boot on capable Arm
759 platforms. If this option is specified, then the path to the CryptoCell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100760 SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
761
Dan Handley610e7e12018-03-01 18:44:00 +0000762For a better understanding of these options, the Arm development platform memory
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100763map is explained in the `Firmware Design`_.
764
Dan Handley610e7e12018-03-01 18:44:00 +0000765Arm CSS platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100766^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
767
768- ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version
769 incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards
770 compatible change to the MTL protocol, used for AP/SCP communication.
Dan Handley610e7e12018-03-01 18:44:00 +0000771 TF-A no longer supports earlier SCP versions. If this option is set to 1
772 then TF-A will detect if an earlier version is in use. Default is 1.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100773
774- ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP\_BL2 and
775 SCP\_BL2U to the FIP and FWU\_FIP respectively, and enables them to be loaded
776 during boot. Default is 1.
777
Soby Mathew1ced6b82017-06-12 12:37:10 +0100778- ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers
779 instead of SCPI/BOM driver for communicating with the SCP during power
780 management operations and for SCP RAM Firmware transfer. If this option
781 is set to 1, then SCMI/SDS drivers will be used. Default is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100782
Dan Handley610e7e12018-03-01 18:44:00 +0000783Arm FVP platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100784^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
785
786- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
Dan Handley610e7e12018-03-01 18:44:00 +0000787 build the topology tree within TF-A. By default TF-A is configured for dual
788 cluster topology and this option can be used to override the default value.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100789
790- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
791 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
792 explained in the options below:
793
794 - ``FVP_CCI`` : The CCI driver is selected. This is the default
795 if 0 < ``FVP_CLUSTER_COUNT`` <= 2.
796 - ``FVP_CCN`` : The CCN driver is selected. This is the default
797 if ``FVP_CLUSTER_COUNT`` > 2.
798
Jeenu Viswambharan75421132018-01-31 14:52:08 +0000799- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in
800 a single cluster. This option defaults to 4.
801
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000802- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
803 in the system. This option defaults to 1. Note that the build option
804 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms.
805
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100806- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
807
808 - ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected
809 - ``FVP_GICV2`` : The GICv2 only driver is selected
810 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
811 - ``FVP_GICV3_LEGACY``: The Legacy GICv3 driver is selected (deprecated)
Dan Handley610e7e12018-03-01 18:44:00 +0000812 Note: If TF-A is compiled with this option on FVPs with GICv3 hardware,
813 then it configures the hardware to run in GICv2 emulation mode
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100814
815- ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer
816 for functions that wait for an arbitrary time length (udelay and mdelay).
817 The default value is 0.
818
Soby Mathewb1bf0442018-02-16 14:52:52 +0000819- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled
820 to DTB and packaged in FIP as the HW_CONFIG. See `Firmware Design`_ for
821 details on HW_CONFIG. By default, this is initialized to a sensible DTS
822 file in ``fdts/`` folder depending on other build options. But some cases,
823 like shifted affinity format for MPIDR, cannot be detected at build time
824 and this option is needed to specify the appropriate DTS file.
825
826- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in
827 FIP. See `Firmware Design`_ for details on HW_CONFIG. This option is
828 similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the
829 HW_CONFIG blob instead of the DTS file. This option is useful to override
830 the default HW_CONFIG selected by the build system.
831
Summer Qin13b95c22018-03-02 15:51:14 +0800832ARM JUNO platform specific build options
833^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
834
835- ``JUNO_TZMP1`` : Boolean option to configure Juno to be used for TrustZone
836 Media Protection (TZ-MP1). Default value of this flag is 0.
837
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100838Debugging options
839~~~~~~~~~~~~~~~~~
840
841To compile a debug version and make the build more verbose use
842
843::
844
845 make PLAT=<platform> DEBUG=1 V=1 all
846
847AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for
848example DS-5) might not support this and may need an older version of DWARF
849symbols to be emitted by GCC. This can be achieved by using the
850``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the
851version to 2 is recommended for DS-5 versions older than 5.16.
852
853When debugging logic problems it might also be useful to disable all compiler
854optimizations by using ``-O0``.
855
856NOTE: Using ``-O0`` could cause output images to be larger and base addresses
Dan Handley610e7e12018-03-01 18:44:00 +0000857might need to be recalculated (see the **Memory layout on Arm development
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100858platforms** section in the `Firmware Design`_).
859
860Extra debug options can be passed to the build system by setting ``CFLAGS`` or
861``LDFLAGS``:
862
863.. code:: makefile
864
865 CFLAGS='-O0 -gdwarf-2' \
866 make PLAT=<platform> DEBUG=1 V=1 all
867
868Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
869ignored as the linker is called directly.
870
871It is also possible to introduce an infinite loop to help in debugging the
Dan Handley610e7e12018-03-01 18:44:00 +0000872post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the
873``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the `Summary of build options`_
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100874section. In this case, the developer may take control of the target using a
875debugger when indicated by the console output. When using DS-5, the following
876commands can be used:
877
878::
879
880 # Stop target execution
881 interrupt
882
883 #
884 # Prepare your debugging environment, e.g. set breakpoints
885 #
886
887 # Jump over the debug loop
888 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
889
890 # Resume execution
891 continue
892
893Building the Test Secure Payload
894~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
895
896The TSP is coupled with a companion runtime service in the BL31 firmware,
897called the TSPD. Therefore, if you intend to use the TSP, the BL31 image
898must be recompiled as well. For more information on SPs and SPDs, see the
899`Secure-EL1 Payloads and Dispatchers`_ section in the `Firmware Design`_.
900
Dan Handley610e7e12018-03-01 18:44:00 +0000901First clean the TF-A build directory to get rid of any previous BL31 binary.
902Then to build the TSP image use:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100903
904::
905
906 make PLAT=<platform> SPD=tspd all
907
908An additional boot loader binary file is created in the ``build`` directory:
909
910::
911
912 build/<platform>/<build-type>/bl32.bin
913
914Checking source code style
915~~~~~~~~~~~~~~~~~~~~~~~~~~
916
917When making changes to the source for submission to the project, the source
918must be in compliance with the Linux style guide, and to assist with this check
919the project Makefile contains two targets, which both utilise the
920``checkpatch.pl`` script that ships with the Linux source tree.
921
Joel Huttonfe027712018-03-19 11:59:57 +0000922To check the entire source tree, you must first download copies of
923``checkpatch.pl``, ``spelling.txt`` and ``const_structs.checkpatch`` available
924in the `Linux master tree`_ scripts directory, then set the ``CHECKPATCH``
925environment variable to point to ``checkpatch.pl`` (with the other 2 files in
John Tsichritzisee10e792018-06-06 09:38:10 +0100926the same directory) and build the target checkcodebase:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100927
928::
929
930 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkcodebase
931
932To just check the style on the files that differ between your local branch and
933the remote master, use:
934
935::
936
937 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkpatch
938
939If you wish to check your patch against something other than the remote master,
940set the ``BASE_COMMIT`` variable to your desired branch. By default, ``BASE_COMMIT``
941is set to ``origin/master``.
942
943Building and using the FIP tool
944~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
945
Dan Handley610e7e12018-03-01 18:44:00 +0000946Firmware Image Package (FIP) is a packaging format used by TF-A to package
947firmware images in a single binary. The number and type of images that should
948be packed in a FIP is platform specific and may include TF-A images and other
949firmware images required by the platform. For example, most platforms require
950a BL33 image which corresponds to the normal world bootloader (e.g. UEFI or
951U-Boot).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100952
Dan Handley610e7e12018-03-01 18:44:00 +0000953The TF-A build system provides the make target ``fip`` to create a FIP file
954for the specified platform using the FIP creation tool included in the TF-A
955project. Examples below show how to build a FIP file for FVP, packaging TF-A
956and BL33 images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100957
958For AArch64:
959
960::
961
962 make PLAT=fvp BL33=<path/to/bl33.bin> fip
963
964For AArch32:
965
966::
967
968 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path/to/bl33.bin> fip
969
970Note that AArch32 support for Normal world boot loader (BL33), like U-boot or
971UEFI, on FVP is not available upstream. Hence custom solutions are required to
972allow Linux boot on FVP. These instructions assume such a custom boot loader
973(BL33) is available.
974
975The resulting FIP may be found in:
976
977::
978
979 build/fvp/<build-type>/fip.bin
980
981For advanced operations on FIP files, it is also possible to independently build
982the tool and create or modify FIPs using this tool. To do this, follow these
983steps:
984
985It is recommended to remove old artifacts before building the tool:
986
987::
988
989 make -C tools/fiptool clean
990
991Build the tool:
992
993::
994
995 make [DEBUG=1] [V=1] fiptool
996
997The tool binary can be located in:
998
999::
1000
1001 ./tools/fiptool/fiptool
1002
1003Invoking the tool with ``--help`` will print a help message with all available
1004options.
1005
1006Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31:
1007
1008::
1009
1010 ./tools/fiptool/fiptool create \
1011 --tb-fw build/<platform>/<build-type>/bl2.bin \
1012 --soc-fw build/<platform>/<build-type>/bl31.bin \
1013 fip.bin
1014
1015Example 2: view the contents of an existing Firmware package:
1016
1017::
1018
1019 ./tools/fiptool/fiptool info <path-to>/fip.bin
1020
1021Example 3: update the entries of an existing Firmware package:
1022
1023::
1024
1025 # Change the BL2 from Debug to Release version
1026 ./tools/fiptool/fiptool update \
1027 --tb-fw build/<platform>/release/bl2.bin \
1028 build/<platform>/debug/fip.bin
1029
1030Example 4: unpack all entries from an existing Firmware package:
1031
1032::
1033
1034 # Images will be unpacked to the working directory
1035 ./tools/fiptool/fiptool unpack <path-to>/fip.bin
1036
1037Example 5: remove an entry from an existing Firmware package:
1038
1039::
1040
1041 ./tools/fiptool/fiptool remove \
1042 --tb-fw build/<platform>/debug/fip.bin
1043
1044Note that if the destination FIP file exists, the create, update and
1045remove operations will automatically overwrite it.
1046
1047The unpack operation will fail if the images already exist at the
1048destination. In that case, use -f or --force to continue.
1049
1050More information about FIP can be found in the `Firmware Design`_ document.
1051
1052Migrating from fip\_create to fiptool
1053^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1054
1055The previous version of fiptool was called fip\_create. A compatibility script
1056that emulates the basic functionality of the previous fip\_create is provided.
1057However, users are strongly encouraged to migrate to fiptool.
1058
1059- To create a new FIP file, replace "fip\_create" with "fiptool create".
1060- To update a FIP file, replace "fip\_create" with "fiptool update".
1061- To dump the contents of a FIP file, replace "fip\_create --dump"
1062 with "fiptool info".
1063
1064Building FIP images with support for Trusted Board Boot
1065~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1066
1067Trusted Board Boot primarily consists of the following two features:
1068
1069- Image Authentication, described in `Trusted Board Boot`_, and
1070- Firmware Update, described in `Firmware Update`_
1071
1072The following steps should be followed to build FIP and (optionally) FWU\_FIP
1073images with support for these features:
1074
1075#. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser
1076 modules by checking out a recent version of the `mbed TLS Repository`_. It
Dan Handley610e7e12018-03-01 18:44:00 +00001077 is important to use a version that is compatible with TF-A and fixes any
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001078 known security vulnerabilities. See `mbed TLS Security Center`_ for more
Dan Handley610e7e12018-03-01 18:44:00 +00001079 information. The latest version of TF-A is tested with tag
Jeenu Viswambharanec06c3b2018-06-07 15:14:42 +01001080 ``mbedtls-2.10.0``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001081
1082 The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS
1083 source files the modules depend upon.
1084 ``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration
1085 options required to build the mbed TLS sources.
1086
1087 Note that the mbed TLS library is licensed under the Apache version 2.0
Dan Handley610e7e12018-03-01 18:44:00 +00001088 license. Using mbed TLS source code will affect the licensing of TF-A
1089 binaries that are built using this library.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001090
1091#. To build the FIP image, ensure the following command line variables are set
Dan Handley610e7e12018-03-01 18:44:00 +00001092 while invoking ``make`` to build TF-A:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001093
1094 - ``MBEDTLS_DIR=<path of the directory containing mbed TLS sources>``
1095 - ``TRUSTED_BOARD_BOOT=1``
1096 - ``GENERATE_COT=1``
1097
Dan Handley610e7e12018-03-01 18:44:00 +00001098 In the case of Arm platforms, the location of the ROTPK hash must also be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001099 specified at build time. Two locations are currently supported (see
1100 ``ARM_ROTPK_LOCATION`` build option):
1101
1102 - ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted
1103 root-key storage registers present in the platform. On Juno, this
1104 registers are read-only. On FVP Base and Cortex models, the registers
1105 are read-only, but the value can be specified using the command line
1106 option ``bp.trusted_key_storage.public_key`` when launching the model.
1107 On both Juno and FVP models, the default value corresponds to an
1108 ECDSA-SECP256R1 public key hash, whose private part is not currently
1109 available.
1110
1111 - ``ARM_ROTPK_LOCATION=devel_rsa``: use the ROTPK hash that is hardcoded
Dan Handley610e7e12018-03-01 18:44:00 +00001112 in the Arm platform port. The private/public RSA key pair may be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001113 found in ``plat/arm/board/common/rotpk``.
1114
Qixiang Xu1c2aef12017-08-24 15:12:20 +08001115 - ``ARM_ROTPK_LOCATION=devel_ecdsa``: use the ROTPK hash that is hardcoded
Dan Handley610e7e12018-03-01 18:44:00 +00001116 in the Arm platform port. The private/public ECDSA key pair may be
Qixiang Xu1c2aef12017-08-24 15:12:20 +08001117 found in ``plat/arm/board/common/rotpk``.
1118
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001119 Example of command line using RSA development keys:
1120
1121 ::
1122
1123 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1124 make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1125 ARM_ROTPK_LOCATION=devel_rsa \
1126 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1127 BL33=<path-to>/<bl33_image> \
1128 all fip
1129
1130 The result of this build will be the bl1.bin and the fip.bin binaries. This
1131 FIP will include the certificates corresponding to the Chain of Trust
1132 described in the TBBR-client document. These certificates can also be found
1133 in the output build directory.
1134
1135#. The optional FWU\_FIP contains any additional images to be loaded from
1136 Non-Volatile storage during the `Firmware Update`_ process. To build the
1137 FWU\_FIP, any FWU images required by the platform must be specified on the
Dan Handley610e7e12018-03-01 18:44:00 +00001138 command line. On Arm development platforms like Juno, these are:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001139
1140 - NS\_BL2U. The AP non-secure Firmware Updater image.
1141 - SCP\_BL2U. The SCP Firmware Update Configuration image.
1142
1143 Example of Juno command line for generating both ``fwu`` and ``fwu_fip``
1144 targets using RSA development:
1145
1146 ::
1147
1148 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1149 make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1150 ARM_ROTPK_LOCATION=devel_rsa \
1151 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1152 BL33=<path-to>/<bl33_image> \
1153 SCP_BL2=<path-to>/<scp_bl2_image> \
1154 SCP_BL2U=<path-to>/<scp_bl2u_image> \
1155 NS_BL2U=<path-to>/<ns_bl2u_image> \
1156 all fip fwu_fip
1157
1158 Note: The BL2U image will be built by default and added to the FWU\_FIP.
1159 The user may override this by adding ``BL2U=<path-to>/<bl2u_image>``
1160 to the command line above.
1161
1162 Note: Building and installing the non-secure and SCP FWU images (NS\_BL1U,
1163 NS\_BL2U and SCP\_BL2U) is outside the scope of this document.
1164
1165 The result of this build will be bl1.bin, fip.bin and fwu\_fip.bin binaries.
1166 Both the FIP and FWU\_FIP will include the certificates corresponding to the
1167 Chain of Trust described in the TBBR-client document. These certificates
1168 can also be found in the output build directory.
1169
1170Building the Certificate Generation Tool
1171~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1172
Dan Handley610e7e12018-03-01 18:44:00 +00001173The ``cert_create`` tool is built as part of the TF-A build process when the
1174``fip`` make target is specified and TBB is enabled (as described in the
1175previous section), but it can also be built separately with the following
1176command:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001177
1178::
1179
1180 make PLAT=<platform> [DEBUG=1] [V=1] certtool
1181
1182For platforms that do not require their own IDs in certificate files,
1183the generic 'cert\_create' tool can be built with the following command:
1184
1185::
1186
1187 make USE_TBBR_DEFS=1 [DEBUG=1] [V=1] certtool
1188
1189``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
1190verbose. The following command should be used to obtain help about the tool:
1191
1192::
1193
1194 ./tools/cert_create/cert_create -h
1195
1196Building a FIP for Juno and FVP
1197-------------------------------
1198
1199This section provides Juno and FVP specific instructions to build Trusted
1200Firmware, obtain the additional required firmware, and pack it all together in
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001201a single FIP binary. It assumes that a `Linaro Release`_ has been installed.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001202
David Cunadob2de0992017-06-29 12:01:33 +01001203Note: Pre-built binaries for AArch32 are available from Linaro Release 16.12
1204onwards. Before that release, pre-built binaries are only available for AArch64.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001205
Joel Huttonfe027712018-03-19 11:59:57 +00001206Note: Follow the full instructions for one platform before switching to a
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001207different one. Mixing instructions for different platforms may result in
1208corrupted binaries.
1209
Joel Huttonfe027712018-03-19 11:59:57 +00001210Note: The uboot image downloaded by the Linaro workspace script does not always
1211match the uboot image packaged as BL33 in the corresponding fip file. It is
1212recommended to use the version that is packaged in the fip file using the
1213instructions below.
1214
Soby Mathewecd94ad2018-05-09 13:59:29 +01001215Note: For the FVP, the kernel FDT is packaged in FIP during build and loaded
1216by the firmware at runtime. See `Obtaining the Flattened Device Trees`_
1217section for more info on selecting the right FDT to use.
1218
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001219#. Clean the working directory
1220
1221 ::
1222
1223 make realclean
1224
1225#. Obtain SCP\_BL2 (Juno) and BL33 (all platforms)
1226
1227 Use the fiptool to extract the SCP\_BL2 and BL33 images from the FIP
1228 package included in the Linaro release:
1229
1230 ::
1231
1232 # Build the fiptool
1233 make [DEBUG=1] [V=1] fiptool
1234
1235 # Unpack firmware images from Linaro FIP
1236 ./tools/fiptool/fiptool unpack \
1237 <path/to/linaro/release>/fip.bin
1238
1239 The unpack operation will result in a set of binary images extracted to the
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001240 current working directory. The SCP\_BL2 image corresponds to
1241 ``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001242
Joel Huttonfe027712018-03-19 11:59:57 +00001243 Note: The fiptool will complain if the images to be unpacked already
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001244 exist in the current directory. If that is the case, either delete those
1245 files or use the ``--force`` option to overwrite.
1246
Joel Huttonfe027712018-03-19 11:59:57 +00001247 Note: For AArch32, the instructions below assume that nt-fw.bin is a custom
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001248 Normal world boot loader that supports AArch32.
1249
Dan Handley610e7e12018-03-01 18:44:00 +00001250#. Build TF-A images and create a new FIP for FVP
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001251
1252 ::
1253
1254 # AArch64
1255 make PLAT=fvp BL33=nt-fw.bin all fip
1256
1257 # AArch32
1258 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=nt-fw.bin all fip
1259
Dan Handley610e7e12018-03-01 18:44:00 +00001260#. Build TF-A images and create a new FIP for Juno
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001261
1262 For AArch64:
1263
1264 Building for AArch64 on Juno simply requires the addition of ``SCP_BL2``
1265 as a build parameter.
1266
1267 ::
1268
1269 make PLAT=juno all fip \
1270 BL33=<path-to-juno-oe-uboot>/SOFTWARE/bl33-uboot.bin \
1271 SCP_BL2=<path-to-juno-busybox-uboot>/SOFTWARE/scp_bl2.bin
1272
1273 For AArch32:
1274
1275 Hardware restrictions on Juno prevent cold reset into AArch32 execution mode,
1276 therefore BL1 and BL2 must be compiled for AArch64, and BL32 is compiled
1277 separately for AArch32.
1278
1279 - Before building BL32, the environment variable ``CROSS_COMPILE`` must point
1280 to the AArch32 Linaro cross compiler.
1281
1282 ::
1283
1284 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
1285
1286 - Build BL32 in AArch32.
1287
1288 ::
1289
1290 make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \
1291 RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32
1292
1293 - Before building BL1 and BL2, the environment variable ``CROSS_COMPILE``
1294 must point to the AArch64 Linaro cross compiler.
1295
1296 ::
1297
1298 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
1299
1300 - The following parameters should be used to build BL1 and BL2 in AArch64
1301 and point to the BL32 file.
1302
1303 ::
1304
1305 make ARCH=aarch64 PLAT=juno LOAD_IMAGE_V2=1 JUNO_AARCH32_EL3_RUNTIME=1 \
1306 BL33=<path-to-juno32-oe-uboot>/SOFTWARE/bl33-uboot.bin \
Soby Mathewbf169232017-11-14 14:10:10 +00001307 SCP_BL2=<path-to-juno32-oe-uboot>/SOFTWARE/scp_bl2.bin \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001308 BL32=<path-to-bl32>/bl32.bin all fip
1309
1310The resulting BL1 and FIP images may be found in:
1311
1312::
1313
1314 # Juno
1315 ./build/juno/release/bl1.bin
1316 ./build/juno/release/fip.bin
1317
1318 # FVP
1319 ./build/fvp/release/bl1.bin
1320 ./build/fvp/release/fip.bin
1321
Roberto Vargas096f3a02017-10-17 10:19:00 +01001322
1323Booting Firmware Update images
1324-------------------------------------
1325
1326When Firmware Update (FWU) is enabled there are at least 2 new images
1327that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the
1328FWU FIP.
1329
1330Juno
1331~~~~
1332
1333The new images must be programmed in flash memory by adding
1334an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1335on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1336Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1337programming" for more information. User should ensure these do not
1338overlap with any other entries in the file.
1339
1340::
1341
1342 NOR10UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1343 NOR10ADDRESS: 0x00400000 ;Image Flash Address [ns_bl2u_base_address]
1344 NOR10FILE: \SOFTWARE\fwu_fip.bin ;Image File Name
1345 NOR10LOAD: 00000000 ;Image Load Address
1346 NOR10ENTRY: 00000000 ;Image Entry Point
1347
1348 NOR11UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1349 NOR11ADDRESS: 0x03EB8000 ;Image Flash Address [ns_bl1u_base_address]
1350 NOR11FILE: \SOFTWARE\ns_bl1u.bin ;Image File Name
1351 NOR11LOAD: 00000000 ;Image Load Address
1352
1353The address ns_bl1u_base_address is the value of NS_BL1U_BASE - 0x8000000.
1354In the same way, the address ns_bl2u_base_address is the value of
1355NS_BL2U_BASE - 0x8000000.
1356
1357FVP
1358~~~
1359
1360The additional fip images must be loaded with:
1361
1362::
1363
1364 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address]
1365 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address]
1366
1367The address ns_bl1u_base_address is the value of NS_BL1U_BASE.
1368In the same way, the address ns_bl2u_base_address is the value of
1369NS_BL2U_BASE.
1370
1371
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001372EL3 payloads alternative boot flow
1373----------------------------------
1374
1375On a pre-production system, the ability to execute arbitrary, bare-metal code at
1376the highest exception level is required. It allows full, direct access to the
1377hardware, for example to run silicon soak tests.
1378
1379Although it is possible to implement some baremetal secure firmware from
1380scratch, this is a complex task on some platforms, depending on the level of
1381configuration required to put the system in the expected state.
1382
1383Rather than booting a baremetal application, a possible compromise is to boot
Dan Handley610e7e12018-03-01 18:44:00 +00001384``EL3 payloads`` through TF-A instead. This is implemented as an alternative
1385boot flow, where a modified BL2 boots an EL3 payload, instead of loading the
1386other BL images and passing control to BL31. It reduces the complexity of
1387developing EL3 baremetal code by:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001388
1389- putting the system into a known architectural state;
1390- taking care of platform secure world initialization;
1391- loading the SCP\_BL2 image if required by the platform.
1392
Dan Handley610e7e12018-03-01 18:44:00 +00001393When booting an EL3 payload on Arm standard platforms, the configuration of the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001394TrustZone controller is simplified such that only region 0 is enabled and is
1395configured to permit secure access only. This gives full access to the whole
1396DRAM to the EL3 payload.
1397
1398The system is left in the same state as when entering BL31 in the default boot
1399flow. In particular:
1400
1401- Running in EL3;
1402- Current state is AArch64;
1403- Little-endian data access;
1404- All exceptions disabled;
1405- MMU disabled;
1406- Caches disabled.
1407
1408Booting an EL3 payload
1409~~~~~~~~~~~~~~~~~~~~~~
1410
1411The EL3 payload image is a standalone image and is not part of the FIP. It is
Dan Handley610e7e12018-03-01 18:44:00 +00001412not loaded by TF-A. Therefore, there are 2 possible scenarios:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001413
1414- The EL3 payload may reside in non-volatile memory (NVM) and execute in
1415 place. In this case, booting it is just a matter of specifying the right
Dan Handley610e7e12018-03-01 18:44:00 +00001416 address in NVM through ``EL3_PAYLOAD_BASE`` when building TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001417
1418- The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
1419 run-time.
1420
1421To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be
1422used. The infinite loop that it introduces in BL1 stops execution at the right
1423moment for a debugger to take control of the target and load the payload (for
1424example, over JTAG).
1425
1426It is expected that this loading method will work in most cases, as a debugger
1427connection is usually available in a pre-production system. The user is free to
1428use any other platform-specific mechanism to load the EL3 payload, though.
1429
1430Booting an EL3 payload on FVP
1431^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1432
1433The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
1434the secondary CPUs holding pen to work properly. Unfortunately, its reset value
1435is undefined on the FVP platform and the FVP platform code doesn't clear it.
1436Therefore, one must modify the way the model is normally invoked in order to
1437clear the mailbox at start-up.
1438
1439One way to do that is to create an 8-byte file containing all zero bytes using
1440the following command:
1441
1442::
1443
1444 dd if=/dev/zero of=mailbox.dat bs=1 count=8
1445
1446and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
1447using the following model parameters:
1448
1449::
1450
1451 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
1452 --data=mailbox.dat@0x04000000 [Foundation FVP]
1453
1454To provide the model with the EL3 payload image, the following methods may be
1455used:
1456
1457#. If the EL3 payload is able to execute in place, it may be programmed into
1458 flash memory. On Base Cortex and AEM FVPs, the following model parameter
1459 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
1460 used for the FIP):
1461
1462 ::
1463
1464 -C bp.flashloader1.fname="/path/to/el3-payload"
1465
1466 On Foundation FVP, there is no flash loader component and the EL3 payload
1467 may be programmed anywhere in flash using method 3 below.
1468
1469#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
1470 command may be used to load the EL3 payload ELF image over JTAG:
1471
1472 ::
1473
1474 load /path/to/el3-payload.elf
1475
1476#. The EL3 payload may be pre-loaded in volatile memory using the following
1477 model parameters:
1478
1479 ::
1480
1481 --data cluster0.cpu0="/path/to/el3-payload"@address [Base FVPs]
1482 --data="/path/to/el3-payload"@address [Foundation FVP]
1483
1484 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
Dan Handley610e7e12018-03-01 18:44:00 +00001485 used when building TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001486
1487Booting an EL3 payload on Juno
1488^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1489
1490If the EL3 payload is able to execute in place, it may be programmed in flash
1491memory by adding an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1492on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1493Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1494programming" for more information.
1495
1496Alternatively, the same DS-5 command mentioned in the FVP section above can
1497be used to load the EL3 payload's ELF file over JTAG on Juno.
1498
1499Preloaded BL33 alternative boot flow
1500------------------------------------
1501
1502Some platforms have the ability to preload BL33 into memory instead of relying
Dan Handley610e7e12018-03-01 18:44:00 +00001503on TF-A to load it. This may simplify packaging of the normal world code and
1504improve performance in a development environment. When secure world cold boot
1505is complete, TF-A simply jumps to a BL33 base address provided at build time.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001506
1507For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be
Dan Handley610e7e12018-03-01 18:44:00 +00001508used when compiling TF-A. For example, the following command will create a FIP
1509without a BL33 and prepare to jump to a BL33 image loaded at address
15100x80000000:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001511
1512::
1513
1514 make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip
1515
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001516Boot of a preloaded kernel image on Base FVP
1517~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001518
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001519The following example uses a simplified boot flow by directly jumping from the
1520TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be
1521useful if both the kernel and the device tree blob (DTB) are already present in
1522memory (like in FVP).
1523
1524For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at
1525address ``0x82000000``, the firmware can be built like this:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001526
1527::
1528
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001529 CROSS_COMPILE=aarch64-linux-gnu- \
1530 make PLAT=fvp DEBUG=1 \
1531 RESET_TO_BL31=1 \
1532 ARM_LINUX_KERNEL_AS_BL33=1 \
1533 PRELOADED_BL33_BASE=0x80080000 \
1534 ARM_PRELOADED_DTB_BASE=0x82000000 \
1535 all fip
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001536
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001537Now, it is needed to modify the DTB so that the kernel knows the address of the
1538ramdisk. The following script generates a patched DTB from the provided one,
1539assuming that the ramdisk is loaded at address ``0x84000000``. Note that this
1540script assumes that the user is using a ramdisk image prepared for U-Boot, like
1541the ones provided by Linaro. If using a ramdisk without this header,the ``0x40``
1542offset in ``INITRD_START`` has to be removed.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001543
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001544.. code:: bash
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001545
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001546 #!/bin/bash
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001547
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001548 # Path to the input DTB
1549 KERNEL_DTB=<path-to>/<fdt>
1550 # Path to the output DTB
1551 PATCHED_KERNEL_DTB=<path-to>/<patched-fdt>
1552 # Base address of the ramdisk
1553 INITRD_BASE=0x84000000
1554 # Path to the ramdisk
1555 INITRD=<path-to>/<ramdisk.img>
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001556
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001557 # Skip uboot header (64 bytes)
1558 INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) )
1559 INITRD_SIZE=$(stat -Lc %s ${INITRD})
1560 INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) )
1561
1562 CHOSEN_NODE=$(echo \
1563 "/ { \
1564 chosen { \
1565 linux,initrd-start = <${INITRD_START}>; \
1566 linux,initrd-end = <${INITRD_END}>; \
1567 }; \
1568 };")
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001569
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001570 echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \
1571 dtc -O dtb -o ${PATCHED_KERNEL_DTB} -
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001572
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001573And the FVP binary can be run with the following command:
1574
1575::
1576
1577 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1578 -C pctl.startup=0.0.0.0 \
1579 -C bp.secure_memory=1 \
1580 -C cluster0.NUM_CORES=4 \
1581 -C cluster1.NUM_CORES=4 \
1582 -C cache_state_modelled=1 \
1583 -C cluster0.cpu0.RVBAR=0x04020000 \
1584 -C cluster0.cpu1.RVBAR=0x04020000 \
1585 -C cluster0.cpu2.RVBAR=0x04020000 \
1586 -C cluster0.cpu3.RVBAR=0x04020000 \
1587 -C cluster1.cpu0.RVBAR=0x04020000 \
1588 -C cluster1.cpu1.RVBAR=0x04020000 \
1589 -C cluster1.cpu2.RVBAR=0x04020000 \
1590 -C cluster1.cpu3.RVBAR=0x04020000 \
1591 --data cluster0.cpu0="<path-to>/bl31.bin"@0x04020000 \
1592 --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \
1593 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1594 --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000
1595
1596Boot of a preloaded kernel image on Juno
1597~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001598
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001599The Trusted Firmware must be compiled in a similar way as for FVP explained
1600above. The process to load binaries to memory is the one explained in
1601`Booting an EL3 payload on Juno`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001602
1603Running the software on FVP
1604---------------------------
1605
David Cunado7c032642018-03-12 18:47:05 +00001606The latest version of the AArch64 build of TF-A has been tested on the following
1607Arm FVPs without shifted affinities, and that do not support threaded CPU cores
1608(64-bit host machine only).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001609
David Cunado82509be2017-12-19 16:33:25 +00001610NOTE: Unless otherwise stated, the model version is Version 11.2 Build 11.2.33.
David Cunado124415e2017-06-27 17:31:12 +01001611
1612- ``Foundation_Platform``
David Cunado7c032642018-03-12 18:47:05 +00001613- ``FVP_Base_AEMv8A-AEMv8A`` (and also Version 9.0, Build 0.8.9005)
David Cunado124415e2017-06-27 17:31:12 +01001614- ``FVP_Base_Cortex-A35x4``
1615- ``FVP_Base_Cortex-A53x4``
1616- ``FVP_Base_Cortex-A57x4-A53x4``
1617- ``FVP_Base_Cortex-A57x4``
1618- ``FVP_Base_Cortex-A72x4-A53x4``
1619- ``FVP_Base_Cortex-A72x4``
1620- ``FVP_Base_Cortex-A73x4-A53x4``
1621- ``FVP_Base_Cortex-A73x4``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001622
David Cunado7c032642018-03-12 18:47:05 +00001623Additionally, the AArch64 build was tested on the following Arm FVPs with
1624shifted affinities, supporting threaded CPU cores (64-bit host machine only).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001625
David Cunado7c032642018-03-12 18:47:05 +00001626- ``FVP_Base_Cortex-A55x4-A75x4`` (Version 0.0, build 0.0.4395)
1627- ``FVP_Base_Cortex-A55x4`` (Version 0.0, build 0.0.4395)
1628- ``FVP_Base_Cortex-A75x4`` (Version 0.0, build 0.0.4395)
1629- ``FVP_Base_RevC-2xAEMv8A``
1630
1631The latest version of the AArch32 build of TF-A has been tested on the following
1632Arm FVPs without shifted affinities, and that do not support threaded CPU cores
1633(64-bit host machine only).
1634
1635- ``FVP_Base_AEMv8A-AEMv8A``
David Cunado124415e2017-06-27 17:31:12 +01001636- ``FVP_Base_Cortex-A32x4``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001637
David Cunado7c032642018-03-12 18:47:05 +00001638NOTE: The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which
1639is not compatible with legacy GIC configurations. Therefore this FVP does not
1640support these legacy GIC configurations.
1641
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001642NOTE: The build numbers quoted above are those reported by launching the FVP
1643with the ``--version`` parameter.
1644
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001645NOTE: Linaro provides a ramdisk image in prebuilt FVP configurations and full
1646file systems that can be downloaded separately. To run an FVP with a virtio
1647file system image an additional FVP configuration option
1648``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
1649used.
1650
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001651NOTE: The software will not work on Version 1.0 of the Foundation FVP.
1652The commands below would report an ``unhandled argument`` error in this case.
1653
1654NOTE: FVPs can be launched with ``--cadi-server`` option such that a
Dan Handley610e7e12018-03-01 18:44:00 +00001655CADI-compliant debugger (for example, Arm DS-5) can connect to and control its
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001656execution.
1657
Eleanor Bonnicie124dc42017-10-04 15:03:33 +01001658NOTE: Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
David Cunado97309462017-07-31 12:24:51 +01001659the internal synchronisation timings changed compared to older versions of the
1660models. The models can be launched with ``-Q 100`` option if they are required
1661to match the run time characteristics of the older versions.
1662
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001663The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be
Dan Handley610e7e12018-03-01 18:44:00 +00001664downloaded for free from `Arm's website`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001665
David Cunado124415e2017-06-27 17:31:12 +01001666The Cortex-A models listed above are also available to download from
Dan Handley610e7e12018-03-01 18:44:00 +00001667`Arm's website`_.
David Cunado124415e2017-06-27 17:31:12 +01001668
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001669Please refer to the FVP documentation for a detailed description of the model
Dan Handley610e7e12018-03-01 18:44:00 +00001670parameter options. A brief description of the important ones that affect TF-A
1671and normal world software behavior is provided below.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001672
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001673Obtaining the Flattened Device Trees
1674~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1675
1676Depending on the FVP configuration and Linux configuration used, different
Soby Mathewecd94ad2018-05-09 13:59:29 +01001677FDT files are required. FDT source files for the Foundation and Base FVPs can
1678be found in the TF-A source directory under ``fdts/``. The Foundation FVP has
1679a subset of the Base FVP components. For example, the Foundation FVP lacks
1680CLCD and MMC support, and has only one CPU cluster.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001681
1682Note: It is not recommended to use the FDTs built along the kernel because not
1683all FDTs are available from there.
1684
Soby Mathewecd94ad2018-05-09 13:59:29 +01001685The dynamic configuration capability is enabled in the firmware for FVPs.
1686This means that the firmware can authenticate and load the FDT if present in
1687FIP. A default FDT is packaged into FIP during the build based on
1688the build configuration. This can be overridden by using the ``FVP_HW_CONFIG``
1689or ``FVP_HW_CONFIG_DTS`` build options (refer to the
1690`Arm FVP platform specific build options`_ section for detail on the options).
1691
1692- ``fvp-base-gicv2-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001693
David Cunado7c032642018-03-12 18:47:05 +00001694 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
1695 affinities and with Base memory map configuration.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001696
Soby Mathewecd94ad2018-05-09 13:59:29 +01001697- ``fvp-base-gicv2-psci-aarch32.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001698
David Cunado7c032642018-03-12 18:47:05 +00001699 For use with models such as the Cortex-A32 Base FVPs without shifted
1700 affinities and running Linux in AArch32 state with Base memory map
1701 configuration.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001702
Soby Mathewecd94ad2018-05-09 13:59:29 +01001703- ``fvp-base-gicv3-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001704
David Cunado7c032642018-03-12 18:47:05 +00001705 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
1706 affinities and with Base memory map configuration and Linux GICv3 support.
1707
Soby Mathewecd94ad2018-05-09 13:59:29 +01001708- ``fvp-base-gicv3-psci-1t.dts``
David Cunado7c032642018-03-12 18:47:05 +00001709
1710 For use with models such as the AEMv8-RevC Base FVP with shifted affinities,
1711 single threaded CPUs, Base memory map configuration and Linux GICv3 support.
1712
Soby Mathewecd94ad2018-05-09 13:59:29 +01001713- ``fvp-base-gicv3-psci-dynamiq.dts``
David Cunado7c032642018-03-12 18:47:05 +00001714
1715 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities,
1716 single cluster, single threaded CPUs, Base memory map configuration and Linux
1717 GICv3 support.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001718
Soby Mathewecd94ad2018-05-09 13:59:29 +01001719- ``fvp-base-gicv3-psci-aarch32.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001720
David Cunado7c032642018-03-12 18:47:05 +00001721 For use with models such as the Cortex-A32 Base FVPs without shifted
1722 affinities and running Linux in AArch32 state with Base memory map
1723 configuration and Linux GICv3 support.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001724
Soby Mathewecd94ad2018-05-09 13:59:29 +01001725- ``fvp-foundation-gicv2-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001726
1727 For use with Foundation FVP with Base memory map configuration.
1728
Soby Mathewecd94ad2018-05-09 13:59:29 +01001729- ``fvp-foundation-gicv3-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001730
1731 (Default) For use with Foundation FVP with Base memory map configuration
1732 and Linux GICv3 support.
1733
1734Running on the Foundation FVP with reset to BL1 entrypoint
1735~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1736
1737The following ``Foundation_Platform`` parameters should be used to boot Linux with
Dan Handley610e7e12018-03-01 18:44:00 +000017384 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001739
1740::
1741
1742 <path-to>/Foundation_Platform \
1743 --cores=4 \
Antonio Nino Diazb44eda52018-02-23 11:01:31 +00001744 --arm-v8.0 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001745 --secure-memory \
1746 --visualization \
1747 --gicv3 \
1748 --data="<path-to>/<bl1-binary>"@0x0 \
1749 --data="<path-to>/<FIP-binary>"@0x08000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001750 --data="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001751 --data="<path-to>/<ramdisk-binary>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001752
1753Notes:
1754
1755- BL1 is loaded at the start of the Trusted ROM.
1756- The Firmware Image Package is loaded at the start of NOR FLASH0.
Soby Mathewecd94ad2018-05-09 13:59:29 +01001757- The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address
1758 is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001759- The default use-case for the Foundation FVP is to use the ``--gicv3`` option
1760 and enable the GICv3 device in the model. Note that without this option,
1761 the Foundation FVP defaults to legacy (Versatile Express) memory map which
Dan Handley610e7e12018-03-01 18:44:00 +00001762 is not supported by TF-A.
1763- In order for TF-A to run correctly on the Foundation FVP, the architecture
1764 versions must match. The Foundation FVP defaults to the highest v8.x
1765 version it supports but the default build for TF-A is for v8.0. To avoid
1766 issues either start the Foundation FVP to use v8.0 architecture using the
1767 ``--arm-v8.0`` option, or build TF-A with an appropriate value for
1768 ``ARM_ARCH_MINOR``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001769
1770Running on the AEMv8 Base FVP with reset to BL1 entrypoint
1771~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1772
David Cunado7c032642018-03-12 18:47:05 +00001773The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001774with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001775
1776::
1777
David Cunado7c032642018-03-12 18:47:05 +00001778 <path-to>/FVP_Base_RevC-2xAEMv8A \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001779 -C pctl.startup=0.0.0.0 \
1780 -C bp.secure_memory=1 \
1781 -C bp.tzc_400.diagnostics=1 \
1782 -C cluster0.NUM_CORES=4 \
1783 -C cluster1.NUM_CORES=4 \
1784 -C cache_state_modelled=1 \
1785 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1786 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001787 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001788 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001789
1790Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
1791~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1792
1793The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001794with 8 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001795
1796::
1797
1798 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1799 -C pctl.startup=0.0.0.0 \
1800 -C bp.secure_memory=1 \
1801 -C bp.tzc_400.diagnostics=1 \
1802 -C cluster0.NUM_CORES=4 \
1803 -C cluster1.NUM_CORES=4 \
1804 -C cache_state_modelled=1 \
1805 -C cluster0.cpu0.CONFIG64=0 \
1806 -C cluster0.cpu1.CONFIG64=0 \
1807 -C cluster0.cpu2.CONFIG64=0 \
1808 -C cluster0.cpu3.CONFIG64=0 \
1809 -C cluster1.cpu0.CONFIG64=0 \
1810 -C cluster1.cpu1.CONFIG64=0 \
1811 -C cluster1.cpu2.CONFIG64=0 \
1812 -C cluster1.cpu3.CONFIG64=0 \
1813 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1814 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001815 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001816 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001817
1818Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
1819~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1820
1821The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001822boot Linux with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001823
1824::
1825
1826 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1827 -C pctl.startup=0.0.0.0 \
1828 -C bp.secure_memory=1 \
1829 -C bp.tzc_400.diagnostics=1 \
1830 -C cache_state_modelled=1 \
1831 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1832 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001833 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001834 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001835
1836Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
1837~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1838
1839The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001840boot Linux with 4 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001841
1842::
1843
1844 <path-to>/FVP_Base_Cortex-A32x4 \
1845 -C pctl.startup=0.0.0.0 \
1846 -C bp.secure_memory=1 \
1847 -C bp.tzc_400.diagnostics=1 \
1848 -C cache_state_modelled=1 \
1849 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1850 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001851 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001852 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001853
1854Running on the AEMv8 Base FVP with reset to BL31 entrypoint
1855~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1856
David Cunado7c032642018-03-12 18:47:05 +00001857The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001858with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001859
1860::
1861
David Cunado7c032642018-03-12 18:47:05 +00001862 <path-to>/FVP_Base_RevC-2xAEMv8A \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001863 -C pctl.startup=0.0.0.0 \
1864 -C bp.secure_memory=1 \
1865 -C bp.tzc_400.diagnostics=1 \
1866 -C cluster0.NUM_CORES=4 \
1867 -C cluster1.NUM_CORES=4 \
1868 -C cache_state_modelled=1 \
Qixiang Xua5f72812017-08-31 11:45:32 +08001869 -C cluster0.cpu0.RVBAR=0x04020000 \
1870 -C cluster0.cpu1.RVBAR=0x04020000 \
1871 -C cluster0.cpu2.RVBAR=0x04020000 \
1872 -C cluster0.cpu3.RVBAR=0x04020000 \
1873 -C cluster1.cpu0.RVBAR=0x04020000 \
1874 -C cluster1.cpu1.RVBAR=0x04020000 \
1875 -C cluster1.cpu2.RVBAR=0x04020000 \
1876 -C cluster1.cpu3.RVBAR=0x04020000 \
1877 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001878 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
1879 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001880 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001881 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001882 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001883
1884Notes:
1885
1886- Since a FIP is not loaded when using BL31 as reset entrypoint, the
1887 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
1888 parameter is needed to load the individual bootloader images in memory.
1889 BL32 image is only needed if BL31 has been built to expect a Secure-EL1
Soby Mathewecd94ad2018-05-09 13:59:29 +01001890 Payload. For the same reason, the FDT needs to be compiled from the DT source
1891 and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000``
1892 parameter.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001893
1894- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
1895 X and Y are the cluster and CPU numbers respectively, is used to set the
1896 reset vector for each core.
1897
1898- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
1899 changing the value of
1900 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
1901 ``BL32_BASE``.
1902
1903Running on the AEMv8 Base FVP (AArch32) with reset to SP\_MIN entrypoint
1904~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1905
1906The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001907with 8 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001908
1909::
1910
1911 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1912 -C pctl.startup=0.0.0.0 \
1913 -C bp.secure_memory=1 \
1914 -C bp.tzc_400.diagnostics=1 \
1915 -C cluster0.NUM_CORES=4 \
1916 -C cluster1.NUM_CORES=4 \
1917 -C cache_state_modelled=1 \
1918 -C cluster0.cpu0.CONFIG64=0 \
1919 -C cluster0.cpu1.CONFIG64=0 \
1920 -C cluster0.cpu2.CONFIG64=0 \
1921 -C cluster0.cpu3.CONFIG64=0 \
1922 -C cluster1.cpu0.CONFIG64=0 \
1923 -C cluster1.cpu1.CONFIG64=0 \
1924 -C cluster1.cpu2.CONFIG64=0 \
1925 -C cluster1.cpu3.CONFIG64=0 \
1926 -C cluster0.cpu0.RVBAR=0x04001000 \
1927 -C cluster0.cpu1.RVBAR=0x04001000 \
1928 -C cluster0.cpu2.RVBAR=0x04001000 \
1929 -C cluster0.cpu3.RVBAR=0x04001000 \
1930 -C cluster1.cpu0.RVBAR=0x04001000 \
1931 -C cluster1.cpu1.RVBAR=0x04001000 \
1932 -C cluster1.cpu2.RVBAR=0x04001000 \
1933 -C cluster1.cpu3.RVBAR=0x04001000 \
Soby Mathewaf14b462018-06-01 16:53:38 +01001934 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001935 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001936 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001937 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001938 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001939
1940Note: The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
1941It should match the address programmed into the RVBAR register as well.
1942
1943Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
1944~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1945
1946The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001947boot Linux with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001948
1949::
1950
1951 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1952 -C pctl.startup=0.0.0.0 \
1953 -C bp.secure_memory=1 \
1954 -C bp.tzc_400.diagnostics=1 \
1955 -C cache_state_modelled=1 \
Qixiang Xua5f72812017-08-31 11:45:32 +08001956 -C cluster0.cpu0.RVBARADDR=0x04020000 \
1957 -C cluster0.cpu1.RVBARADDR=0x04020000 \
1958 -C cluster0.cpu2.RVBARADDR=0x04020000 \
1959 -C cluster0.cpu3.RVBARADDR=0x04020000 \
1960 -C cluster1.cpu0.RVBARADDR=0x04020000 \
1961 -C cluster1.cpu1.RVBARADDR=0x04020000 \
1962 -C cluster1.cpu2.RVBARADDR=0x04020000 \
1963 -C cluster1.cpu3.RVBARADDR=0x04020000 \
1964 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000 \
Soby Mathewaf14b462018-06-01 16:53:38 +01001965 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001966 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001967 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001968 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001969 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001970
1971Running on the Cortex-A32 Base FVP (AArch32) with reset to SP\_MIN entrypoint
1972~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1973
1974The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001975boot Linux with 4 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001976
1977::
1978
1979 <path-to>/FVP_Base_Cortex-A32x4 \
1980 -C pctl.startup=0.0.0.0 \
1981 -C bp.secure_memory=1 \
1982 -C bp.tzc_400.diagnostics=1 \
1983 -C cache_state_modelled=1 \
1984 -C cluster0.cpu0.RVBARADDR=0x04001000 \
1985 -C cluster0.cpu1.RVBARADDR=0x04001000 \
1986 -C cluster0.cpu2.RVBARADDR=0x04001000 \
1987 -C cluster0.cpu3.RVBARADDR=0x04001000 \
Soby Mathewaf14b462018-06-01 16:53:38 +01001988 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001989 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001990 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001991 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001992 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001993
1994Running the software on Juno
1995----------------------------
1996
Dan Handley610e7e12018-03-01 18:44:00 +00001997This version of TF-A has been tested on variants r0, r1 and r2 of Juno.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001998
1999To execute the software stack on Juno, the version of the Juno board recovery
2000image indicated in the `Linaro Release Notes`_ must be installed. If you have an
2001earlier version installed or are unsure which version is installed, please
2002re-install the recovery image by following the
2003`Instructions for using Linaro's deliverables on Juno`_.
2004
Dan Handley610e7e12018-03-01 18:44:00 +00002005Preparing TF-A images
2006~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002007
Dan Handley610e7e12018-03-01 18:44:00 +00002008After building TF-A, the files ``bl1.bin`` and ``fip.bin`` need copying to the
2009``SOFTWARE/`` directory of the Juno SD card.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002010
2011Other Juno software information
2012~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2013
Dan Handley610e7e12018-03-01 18:44:00 +00002014Please visit the `Arm Platforms Portal`_ to get support and obtain any other Juno
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002015software information. Please also refer to the `Juno Getting Started Guide`_ to
Dan Handley610e7e12018-03-01 18:44:00 +00002016get more detailed information about the Juno Arm development platform and how to
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002017configure it.
2018
2019Testing SYSTEM SUSPEND on Juno
2020~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2021
2022The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend
2023to RAM. For more details refer to section 5.16 of `PSCI`_. To test system suspend
2024on Juno, at the linux shell prompt, issue the following command:
2025
2026::
2027
2028 echo +10 > /sys/class/rtc/rtc0/wakealarm
2029 echo -n mem > /sys/power/state
2030
2031The Juno board should suspend to RAM and then wakeup after 10 seconds due to
2032wakeup interrupt from RTC.
2033
2034--------------
2035
Dan Handley610e7e12018-03-01 18:44:00 +00002036*Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002037
David Cunadob2de0992017-06-29 12:01:33 +01002038.. _Linaro: `Linaro Release Notes`_
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002039.. _Linaro Release: `Linaro Release Notes`_
David Cunado82509be2017-12-19 16:33:25 +00002040.. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-linaro-release-notes
2041.. _Linaro Release 17.10: https://community.arm.com/dev-platforms/w/docs/226/old-linaro-release-notes#1710
2042.. _Linaro instructions: https://community.arm.com/dev-platforms/w/docs/304/linaro-software-deliverables
2043.. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno
Dan Handley610e7e12018-03-01 18:44:00 +00002044.. _Arm Platforms Portal: https://community.arm.com/dev-platforms/
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002045.. _Development Studio 5 (DS-5): http://www.arm.com/products/tools/software-tools/ds-5/index.php
Joel Huttonfe027712018-03-19 11:59:57 +00002046.. _Linux master tree: <https://github.com/torvalds/linux/tree/master/>
Antonio Nino Diazb5d68092017-05-23 11:49:22 +01002047.. _Dia: https://wiki.gnome.org/Apps/Dia/Download
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002048.. _here: psci-lib-integration-guide.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002049.. _Trusted Board Boot: trusted-board-boot.rst
Soby Mathewecd94ad2018-05-09 13:59:29 +01002050.. _TB_FW_CONFIG for FVP: ../plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002051.. _Secure-EL1 Payloads and Dispatchers: firmware-design.rst#user-content-secure-el1-payloads-and-dispatchers
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002052.. _Firmware Update: firmware-update.rst
2053.. _Firmware Design: firmware-design.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002054.. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git
2055.. _mbed TLS Security Center: https://tls.mbed.org/security
Dan Handley610e7e12018-03-01 18:44:00 +00002056.. _Arm's website: `FVP models`_
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002057.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002058.. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf
David Cunadob2de0992017-06-29 12:01:33 +01002059.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf