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Yann Gautier4b0c72a2018-07-16 10:54:09 +02001/*
Yann Gautierb76c61a2020-12-16 10:17:35 +01002 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
Yann Gautier4b0c72a2018-07-16 10:54:09 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Yann Gautier4b0c72a2018-07-16 10:54:09 +02007#include <assert.h>
Yann Gautier658775c2021-07-06 10:00:44 +02008#include <errno.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009#include <string.h>
10
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <arch_helpers.h>
12#include <common/bl_common.h>
13#include <common/debug.h>
14#include <common/desc_image_load.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <drivers/generic_delay_timer.h>
Yann Gautiera3bd8d12021-06-18 11:33:26 +020016#include <drivers/mmc.h>
Yann Gautier3edc7c32019-05-20 19:17:08 +020017#include <drivers/st/bsec.h>
Pascal Pailletfc7b8052021-01-29 14:48:49 +010018#include <drivers/st/regulator_fixed.h>
Yann Gautier091eab52019-06-04 18:06:34 +020019#include <drivers/st/stm32_iwdg.h>
Nicolas Le Bayon5c66fab2020-12-02 16:23:49 +010020#include <drivers/st/stm32_rng.h>
Yann Gautier3d8497c2021-10-18 16:06:22 +020021#include <drivers/st/stm32_uart.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000022#include <drivers/st/stm32mp1_clk.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000023#include <drivers/st/stm32mp1_pwr.h>
24#include <drivers/st/stm32mp1_ram.h>
Yann Gautier0c810882021-12-17 09:53:04 +010025#include <drivers/st/stm32mp_pmic.h>
Yann Gautier658775c2021-07-06 10:00:44 +020026#include <lib/fconf/fconf.h>
27#include <lib/fconf/fconf_dyn_cfg_getter.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000028#include <lib/mmio.h>
Yann Gautierb3386f72019-04-19 09:41:01 +020029#include <lib/optee_utils.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000030#include <lib/xlat_tables/xlat_tables_v2.h>
31#include <plat/common/platform.h>
32
Yann Gautier0c810882021-12-17 09:53:04 +010033#include <platform_def.h>
Sughosh Ganu03e2f802021-12-01 15:56:27 +053034#include <stm32mp_common.h>
Yann Gautier091eab52019-06-04 18:06:34 +020035#include <stm32mp1_dbgmcu.h>
Yann Gautier4b0c72a2018-07-16 10:54:09 +020036
Lionel Debieve7192a002020-01-28 09:02:41 +010037#if DEBUG
38static const char debug_msg[] = {
39 "***************************************************\n"
40 "** DEBUG ACCESS PORT IS OPEN! **\n"
41 "** This boot image is only for debugging purpose **\n"
42 "** and is unsafe for production use. **\n"
43 "** **\n"
44 "** If you see this message and you are not **\n"
45 "** debugging report this immediately to your **\n"
46 "** vendor! **\n"
47 "***************************************************\n"
48};
49#endif
50
Yann Gautierf9d40d52019-01-17 14:41:46 +010051static void print_reset_reason(void)
52{
Yann Gautier3d78a2e2019-02-14 11:01:20 +010053 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR);
Yann Gautierf9d40d52019-01-17 14:41:46 +010054
55 if (rstsr == 0U) {
56 WARN("Reset reason unknown\n");
57 return;
58 }
59
60 INFO("Reset reason (0x%x):\n", rstsr);
61
62 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) {
63 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) {
64 INFO("System exits from STANDBY\n");
65 return;
66 }
67
68 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) {
69 INFO("MPU exits from CSTANDBY\n");
70 return;
71 }
72 }
73
74 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) {
75 INFO(" Power-on Reset (rst_por)\n");
76 return;
77 }
78
79 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) {
80 INFO(" Brownout Reset (rst_bor)\n");
81 return;
82 }
83
Yann Gautiercc5f89a2020-02-12 09:36:23 +010084#if STM32MP15
Yann Gautierf9d40d52019-01-17 14:41:46 +010085 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) {
86 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
87 INFO(" System reset generated by MCU (MCSYSRST)\n");
88 } else {
89 INFO(" Local reset generated by MCU (MCSYSRST)\n");
90 }
91 return;
92 }
Yann Gautiercc5f89a2020-02-12 09:36:23 +010093#endif
Yann Gautierf9d40d52019-01-17 14:41:46 +010094
95 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) {
96 INFO(" System reset generated by MPU (MPSYSRST)\n");
97 return;
98 }
99
100 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) {
101 INFO(" Reset due to a clock failure on HSE\n");
102 return;
103 }
104
105 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) {
106 INFO(" IWDG1 Reset (rst_iwdg1)\n");
107 return;
108 }
109
110 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) {
111 INFO(" IWDG2 Reset (rst_iwdg2)\n");
112 return;
113 }
114
115 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) {
116 INFO(" MPU Processor 0 Reset\n");
117 return;
118 }
119
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100120#if STM32MP15
Yann Gautierf9d40d52019-01-17 14:41:46 +0100121 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) {
122 INFO(" MPU Processor 1 Reset\n");
123 return;
124 }
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100125#endif
Yann Gautierf9d40d52019-01-17 14:41:46 +0100126
127 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
128 INFO(" Pad Reset from NRST\n");
129 return;
130 }
131
132 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) {
133 INFO(" Reset due to a failure of VDD_CORE\n");
134 return;
135 }
136
137 ERROR(" Unidentified reset reason\n");
138}
139
140void bl2_el3_early_platform_setup(u_register_t arg0,
141 u_register_t arg1 __unused,
142 u_register_t arg2 __unused,
143 u_register_t arg3 __unused)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200144{
Yann Gautierd1435742021-10-18 10:55:23 +0200145 stm32mp_setup_early_console();
146
Yann Gautiera2e2a302019-02-14 11:13:39 +0100147 stm32mp_save_boot_ctx_address(arg0);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200148}
149
150void bl2_platform_setup(void)
151{
Yann Gautiercaf575b2018-07-24 17:18:19 +0200152 int ret;
153
Yann Gautiercaf575b2018-07-24 17:18:19 +0200154 ret = stm32mp1_ddr_probe();
155 if (ret < 0) {
156 ERROR("Invalid DDR init: error %d\n", ret);
157 panic();
158 }
159
Yann Gautierf3bd87e2020-09-04 15:55:53 +0200160 /* Map DDR for binary load, now with cacheable attribute */
Yann Gautiera55169b2020-01-10 18:18:59 +0100161 ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
Yann Gautierf3bd87e2020-09-04 15:55:53 +0200162 STM32MP_DDR_MAX_SIZE, MT_MEMORY | MT_RW | MT_SECURE);
163 if (ret < 0) {
164 ERROR("DDR mapping: error %d\n", ret);
165 panic();
166 }
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200167}
168
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100169#if STM32MP15
Yann Gautier5c1dab32019-04-17 15:12:58 +0200170static void update_monotonic_counter(void)
171{
172 uint32_t version;
173 uint32_t otp;
174
175 CASSERT(STM32_TF_VERSION <= MAX_MONOTONIC_VALUE,
176 assert_stm32mp1_monotonic_counter_reach_max);
177
178 /* Check if monotonic counter needs to be incremented */
179 if (stm32_get_otp_index(MONOTONIC_OTP, &otp, NULL) != 0) {
180 panic();
181 }
182
183 if (stm32_get_otp_value_from_idx(otp, &version) != 0) {
184 panic();
185 }
186
187 if ((version + 1U) < BIT(STM32_TF_VERSION)) {
188 uint32_t result;
189
190 /* Need to increment the monotonic counter. */
191 version = BIT(STM32_TF_VERSION) - 1U;
192
193 result = bsec_program_otp(version, otp);
194 if (result != BSEC_OK) {
195 ERROR("BSEC: MONOTONIC_OTP program Error %u\n",
196 result);
197 panic();
198 }
199 INFO("Monotonic counter has been incremented (value 0x%x)\n",
200 version);
201 }
202}
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100203#endif
Yann Gautier5c1dab32019-04-17 15:12:58 +0200204
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200205void bl2_el3_plat_arch_setup(void)
206{
Yann Gautier69035a82018-07-05 16:48:16 +0200207 const char *board_model;
Yann Gautier41934662018-07-20 11:36:05 +0200208 boot_api_context_t *boot_context =
Yann Gautiera2e2a302019-02-14 11:13:39 +0100209 (boot_api_context_t *)stm32mp_get_boot_ctx_address();
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100210 uintptr_t pwr_base;
211 uintptr_t rcc_base;
Yann Gautier41934662018-07-20 11:36:05 +0200212
Nicolas Le Bayon97287cd2019-05-20 18:35:02 +0200213 if (bsec_probe() != 0U) {
214 panic();
215 }
216
Yann Gautierf9d40d52019-01-17 14:41:46 +0100217 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
218 BL_CODE_END - BL_CODE_BASE,
219 MT_CODE | MT_SECURE);
220
Yann Gautierf9d40d52019-01-17 14:41:46 +0100221 /* Prevent corruption of preloaded Device Tree */
222 mmap_add_region(DTB_BASE, DTB_BASE,
223 DTB_LIMIT - DTB_BASE,
Yann Gautier3d33df62019-12-17 17:11:10 +0100224 MT_RO_DATA | MT_SECURE);
Yann Gautierf9d40d52019-01-17 14:41:46 +0100225
226 configure_mmu();
227
Yann Gautier05773eb2020-08-24 11:51:50 +0200228 if (dt_open_and_check(STM32MP_DTB_BASE) < 0) {
Yann Gautierf9d40d52019-01-17 14:41:46 +0100229 panic();
230 }
231
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100232 pwr_base = stm32mp_pwr_base();
233 rcc_base = stm32mp_rcc_base();
234
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200235 /*
236 * Disable the backup domain write protection.
237 * The protection is enable at each reset by hardware
238 * and must be disabled by software.
239 */
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100240 mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200241
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100242 while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) {
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200243 ;
244 }
245
246 /* Reset backup domain on cold boot cases */
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100247 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) {
248 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200249
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100250 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) ==
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200251 0U) {
252 ;
253 }
254
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100255 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200256 }
257
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100258#if STM32MP15
Yann Gautiered342322019-02-15 17:33:27 +0100259 /* Disable MCKPROT */
260 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT);
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100261#endif
Yann Gautiered342322019-02-15 17:33:27 +0100262
Yann Gautierc0882f42021-04-27 18:19:13 +0200263 /*
264 * Set minimum reset pulse duration to 31ms for discrete power
265 * supplied boards.
266 */
267 if (dt_pmic_status() <= 0) {
268 mmio_clrsetbits_32(rcc_base + RCC_RDLSICR,
269 RCC_RDLSICR_MRD_MASK,
270 31U << RCC_RDLSICR_MRD_SHIFT);
271 }
272
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200273 generic_delay_timer_init();
274
Yann Gautier3d8497c2021-10-18 16:06:22 +0200275#if STM32MP_UART_PROGRAMMER
276 /* Disable programmer UART before changing clock tree */
277 if (boot_context->boot_interface_selected ==
278 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) {
279 uintptr_t uart_prog_addr =
280 get_uart_address(boot_context->boot_interface_instance);
281
282 stm32_uart_stop(uart_prog_addr);
283 }
284#endif
Yann Gautier9aea69e2018-07-24 17:13:36 +0200285 if (stm32mp1_clk_probe() < 0) {
286 panic();
287 }
288
289 if (stm32mp1_clk_init() < 0) {
290 panic();
291 }
292
Yann Gautier6eef5252021-12-10 17:04:40 +0100293 stm32_save_boot_interface(boot_context->boot_interface_selected,
294 boot_context->boot_interface_instance);
Igor Opaniukf07e8f32022-06-23 21:19:26 +0300295 stm32_save_boot_auth(boot_context->auth_status,
296 boot_context->boot_partition_used_toboot);
Yann Gautier6eef5252021-12-10 17:04:40 +0100297
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100298#if STM32MP_USB_PROGRAMMER && STM32MP15
Yann Gautiercd16df32021-06-04 14:04:05 +0200299 /* Deconfigure all UART RX pins configured by ROM code */
300 stm32mp1_deconfigure_uart_pins();
301#endif
302
Yann Gautier66baa962021-10-18 14:01:00 +0200303 if (stm32mp_uart_console_setup() != 0) {
Yann Gautier69035a82018-07-05 16:48:16 +0200304 goto skip_console_init;
305 }
306
Yann Gautierc7374052019-06-04 18:02:37 +0200307 stm32mp_print_cpuinfo();
308
Yann Gautier69035a82018-07-05 16:48:16 +0200309 board_model = dt_get_board_model();
310 if (board_model != NULL) {
Yann Gautierf9d40d52019-01-17 14:41:46 +0100311 NOTICE("Model: %s\n", board_model);
Yann Gautier69035a82018-07-05 16:48:16 +0200312 }
313
Yann Gautier35dc0772019-05-13 18:34:48 +0200314 stm32mp_print_boardinfo();
315
Lionel Debieve7bd96f42019-09-03 12:22:23 +0200316 if (boot_context->auth_status != BOOT_API_CTX_AUTH_NO) {
317 NOTICE("Bootrom authentication %s\n",
318 (boot_context->auth_status == BOOT_API_CTX_AUTH_FAILED) ?
319 "failed" : "succeeded");
320 }
321
Yann Gautier69035a82018-07-05 16:48:16 +0200322skip_console_init:
Lionel Debieve474ad812022-10-05 16:52:09 +0200323#if !TRUSTED_BOARD_BOOT
324 if (stm32mp_is_closed_device()) {
325 /* Closed chip mandates authentication */
326 ERROR("Secure chip: TRUSTED_BOARD_BOOT must be enabled\n");
327 panic();
328 }
329#endif
330
Pascal Pailletfc7b8052021-01-29 14:48:49 +0100331 if (fixed_regulator_register() != 0) {
332 panic();
333 }
334
Yann Gautier45c1e582020-09-17 11:54:52 +0200335 if (dt_pmic_status() > 0) {
336 initialize_pmic();
Yann Gautierb2ba78e2022-01-18 10:39:52 +0100337 if (pmic_voltages_init() != 0) {
338 ERROR("PMIC voltages init failed\n");
339 panic();
340 }
Nicolas Le Bayon0b10b652019-11-18 13:13:36 +0100341 print_pmic_info_and_debug();
Yann Gautier45c1e582020-09-17 11:54:52 +0200342 }
343
344 stm32mp1_syscfg_init();
345
Yann Gautier091eab52019-06-04 18:06:34 +0200346 if (stm32_iwdg_init() < 0) {
347 panic();
348 }
349
350 stm32_iwdg_refresh();
351
Lionel Debieve7192a002020-01-28 09:02:41 +0100352 if (bsec_read_debug_conf() != 0U) {
353 if (stm32mp_is_closed_device()) {
354#if DEBUG
355 WARN("\n%s", debug_msg);
356#else
357 ERROR("***Debug opened on closed chip***\n");
358#endif
359 }
360 }
361
Nicolas Le Bayon5c66fab2020-12-02 16:23:49 +0100362#if STM32MP13
363 if (stm32_rng_init() != 0) {
364 panic();
365 }
366#endif
367
Yann Gautiercaf575b2018-07-24 17:18:19 +0200368 stm32mp1_arch_security_setup();
369
Yann Gautierf9d40d52019-01-17 14:41:46 +0100370 print_reset_reason();
371
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100372#if STM32MP15
Yann Gautier5c1dab32019-04-17 15:12:58 +0200373 update_monotonic_counter();
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100374#endif
Yann Gautier5c1dab32019-04-17 15:12:58 +0200375
Yann Gautierb76c61a2020-12-16 10:17:35 +0100376 stm32mp1_syscfg_enable_io_compensation_finish();
377
Yann Gautier29f1f942021-07-13 18:07:41 +0200378 fconf_populate("TB_FW", STM32MP_DTB_BASE);
Yann Gautier29f1f942021-07-13 18:07:41 +0200379
Yann Gautiera2e2a302019-02-14 11:13:39 +0100380 stm32mp_io_setup();
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200381}
Yann Gautierb3386f72019-04-19 09:41:01 +0200382
Yann Gautierb3386f72019-04-19 09:41:01 +0200383/*******************************************************************************
384 * This function can be used by the platforms to update/use image
385 * information for given `image_id`.
386 ******************************************************************************/
387int bl2_plat_handle_post_image_load(unsigned int image_id)
388{
389 int err = 0;
390 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
391 bl_mem_params_node_t *bl32_mem_params;
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200392 bl_mem_params_node_t *pager_mem_params __unused;
393 bl_mem_params_node_t *paged_mem_params __unused;
Yann Gautier658775c2021-07-06 10:00:44 +0200394 const struct dyn_cfg_dtb_info_t *config_info;
395 bl_mem_params_node_t *tos_fw_mem_params;
396 unsigned int i;
Yann Gautierfd648352021-12-13 15:24:41 +0100397 unsigned int idx;
Yann Gautier658775c2021-07-06 10:00:44 +0200398 unsigned long long ddr_top __unused;
399 const unsigned int image_ids[] = {
400 BL32_IMAGE_ID,
401 BL33_IMAGE_ID,
402 HW_CONFIG_ID,
403 TOS_FW_CONFIG_ID,
404 };
Yann Gautierb3386f72019-04-19 09:41:01 +0200405
406 assert(bl_mem_params != NULL);
407
408 switch (image_id) {
Yann Gautier658775c2021-07-06 10:00:44 +0200409 case FW_CONFIG_ID:
410 /* Set global DTB info for fixed fw_config information */
Manish V Badarkhefab76282022-03-16 13:51:26 +0000411 set_config_info(STM32MP_FW_CONFIG_BASE, ~0UL, STM32MP_FW_CONFIG_MAX_SIZE,
412 FW_CONFIG_ID);
Yann Gautier658775c2021-07-06 10:00:44 +0200413 fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE);
414
Yann Gautierfd648352021-12-13 15:24:41 +0100415 idx = dyn_cfg_dtb_info_get_index(TOS_FW_CONFIG_ID);
416
Yann Gautier658775c2021-07-06 10:00:44 +0200417 /* Iterate through all the fw config IDs */
418 for (i = 0U; i < ARRAY_SIZE(image_ids); i++) {
Yann Gautierfd648352021-12-13 15:24:41 +0100419 if ((image_ids[i] == TOS_FW_CONFIG_ID) && (idx == FCONF_INVALID_IDX)) {
420 continue;
421 }
422
Yann Gautier658775c2021-07-06 10:00:44 +0200423 bl_mem_params = get_bl_mem_params_node(image_ids[i]);
424 assert(bl_mem_params != NULL);
425
426 config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]);
427 if (config_info == NULL) {
428 continue;
429 }
430
431 bl_mem_params->image_info.image_base = config_info->config_addr;
432 bl_mem_params->image_info.image_max_size = config_info->config_max_size;
433
434 bl_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING;
435
436 switch (image_ids[i]) {
437 case BL32_IMAGE_ID:
438 bl_mem_params->ep_info.pc = config_info->config_addr;
439
440 /* In case of OPTEE, initialize address space with tos_fw addr */
441 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
Yann Gautierc6f77b02022-05-06 09:50:43 +0200442 assert(pager_mem_params != NULL);
Yann Gautier658775c2021-07-06 10:00:44 +0200443 pager_mem_params->image_info.image_base = config_info->config_addr;
444 pager_mem_params->image_info.image_max_size =
445 config_info->config_max_size;
446
447 /* Init base and size for pager if exist */
448 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
Yann Gautiere622a3d2022-06-20 11:43:17 +0200449 if (paged_mem_params != NULL) {
450 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE +
451 (dt_get_ddr_size() - STM32MP_DDR_S_SIZE -
452 STM32MP_DDR_SHMEM_SIZE);
453 paged_mem_params->image_info.image_max_size =
454 STM32MP_DDR_S_SIZE;
455 }
Yann Gautier658775c2021-07-06 10:00:44 +0200456 break;
457
458 case BL33_IMAGE_ID:
459 bl_mem_params->ep_info.pc = config_info->config_addr;
460 break;
461
462 case HW_CONFIG_ID:
463 case TOS_FW_CONFIG_ID:
464 break;
465
466 default:
467 return -EINVAL;
468 }
469 }
470 break;
Yann Gautier658775c2021-07-06 10:00:44 +0200471
Yann Gautierb3386f72019-04-19 09:41:01 +0200472 case BL32_IMAGE_ID:
Yann Gautier90f84d72021-07-13 14:44:09 +0200473 if (optee_header_is_valid(bl_mem_params->image_info.image_base)) {
Yann Gautiere622a3d2022-06-20 11:43:17 +0200474 image_info_t *paged_image_info = NULL;
475
Yann Gautier90f84d72021-07-13 14:44:09 +0200476 /* BL32 is OP-TEE header */
477 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base;
478 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
Yann Gautiere622a3d2022-06-20 11:43:17 +0200479 assert(pager_mem_params != NULL);
480
Yann Gautier90f84d72021-07-13 14:44:09 +0200481 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
Yann Gautiere622a3d2022-06-20 11:43:17 +0200482 if (paged_mem_params != NULL) {
483 paged_image_info = &paged_mem_params->image_info;
484 }
Yann Gautierb3386f72019-04-19 09:41:01 +0200485
Yann Gautier90f84d72021-07-13 14:44:09 +0200486 err = parse_optee_header(&bl_mem_params->ep_info,
487 &pager_mem_params->image_info,
Yann Gautiere622a3d2022-06-20 11:43:17 +0200488 paged_image_info);
489 if (err != 0) {
Yann Gautier90f84d72021-07-13 14:44:09 +0200490 ERROR("OPTEE header parse error.\n");
491 panic();
492 }
Yann Gautierb3386f72019-04-19 09:41:01 +0200493
Yann Gautier90f84d72021-07-13 14:44:09 +0200494 /* Set optee boot info from parsed header data */
Yann Gautiere622a3d2022-06-20 11:43:17 +0200495 if (paged_mem_params != NULL) {
496 bl_mem_params->ep_info.args.arg0 =
497 paged_mem_params->image_info.image_base;
498 } else {
499 bl_mem_params->ep_info.args.arg0 = 0U;
500 }
501
502 bl_mem_params->ep_info.args.arg1 = 0U; /* Unused */
503 bl_mem_params->ep_info.args.arg2 = 0U; /* No DT supported */
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200504 } else {
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200505 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base;
Yann Gautier658775c2021-07-06 10:00:44 +0200506 tos_fw_mem_params = get_bl_mem_params_node(TOS_FW_CONFIG_ID);
Yann Gautierc6f77b02022-05-06 09:50:43 +0200507 assert(tos_fw_mem_params != NULL);
Yann Gautier658775c2021-07-06 10:00:44 +0200508 bl_mem_params->image_info.image_max_size +=
509 tos_fw_mem_params->image_info.image_max_size;
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200510 bl_mem_params->ep_info.args.arg0 = 0;
Yann Gautier90f84d72021-07-13 14:44:09 +0200511 }
Yann Gautierb3386f72019-04-19 09:41:01 +0200512 break;
513
514 case BL33_IMAGE_ID:
515 bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
516 assert(bl32_mem_params != NULL);
517 bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
Yann Gautier5d2eb552022-11-14 14:14:48 +0100518#if PSA_FWU_SUPPORT
Sughosh Ganu03e2f802021-12-01 15:56:27 +0530519 stm32mp1_fwu_set_boot_idx();
Yann Gautier5d2eb552022-11-14 14:14:48 +0100520#endif /* PSA_FWU_SUPPORT */
Yann Gautierb3386f72019-04-19 09:41:01 +0200521 break;
522
523 default:
524 /* Do nothing in default case */
525 break;
526 }
527
Yann Gautiera3bd8d12021-06-18 11:33:26 +0200528#if STM32MP_SDMMC || STM32MP_EMMC
529 /*
530 * Invalidate remaining data read from MMC but not flushed by load_image_flush().
531 * We take the worst case which is 2 MMC blocks.
532 */
533 if ((image_id != FW_CONFIG_ID) &&
534 ((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) {
535 inv_dcache_range(bl_mem_params->image_info.image_base +
536 bl_mem_params->image_info.image_size,
537 2U * MMC_BLOCK_SIZE);
538 }
539#endif /* STM32MP_SDMMC || STM32MP_EMMC */
540
Yann Gautierb3386f72019-04-19 09:41:01 +0200541 return err;
542}
Yann Gautierd2d9b962021-08-16 11:58:01 +0200543
544void bl2_el3_plat_prepare_exit(void)
545{
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200546 uint16_t boot_itf = stm32mp_get_boot_itf_selected();
547
548 switch (boot_itf) {
Patrick Delaunaye50571b2021-10-28 13:48:52 +0200549#if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
550 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART:
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200551 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB:
552 /* Invalidate the downloaded buffer used with io_memmap */
553 inv_dcache_range(DWL_BUFFER_BASE, DWL_BUFFER_SIZE);
554 break;
Patrick Delaunaye50571b2021-10-28 13:48:52 +0200555#endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200556 default:
557 /* Do nothing in default case */
558 break;
559 }
560
Yann Gautierd2d9b962021-08-16 11:58:01 +0200561 stm32mp1_security_setup();
562}