Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 1 | /* |
Yann Gautier | dca6154 | 2021-02-10 18:19:23 +0100 | [diff] [blame] | 2 | * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 7 | #include <assert.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | #include <string.h> |
| 9 | |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 10 | #include <platform_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 11 | |
| 12 | #include <arch_helpers.h> |
| 13 | #include <common/bl_common.h> |
| 14 | #include <common/debug.h> |
| 15 | #include <common/desc_image_load.h> |
| 16 | #include <drivers/delay_timer.h> |
| 17 | #include <drivers/generic_delay_timer.h> |
Yann Gautier | a3bd8d1 | 2021-06-18 11:33:26 +0200 | [diff] [blame^] | 18 | #include <drivers/mmc.h> |
Yann Gautier | 3edc7c3 | 2019-05-20 19:17:08 +0200 | [diff] [blame] | 19 | #include <drivers/st/bsec.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 20 | #include <drivers/st/stm32_console.h> |
Yann Gautier | 091eab5 | 2019-06-04 18:06:34 +0200 | [diff] [blame] | 21 | #include <drivers/st/stm32_iwdg.h> |
Yann Gautier | a45433b | 2019-01-16 18:31:00 +0100 | [diff] [blame] | 22 | #include <drivers/st/stm32mp_pmic.h> |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 23 | #include <drivers/st/stm32mp_reset.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 24 | #include <drivers/st/stm32mp1_clk.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 25 | #include <drivers/st/stm32mp1_pwr.h> |
| 26 | #include <drivers/st/stm32mp1_ram.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 27 | #include <lib/mmio.h> |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 28 | #include <lib/optee_utils.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 29 | #include <lib/xlat_tables/xlat_tables_v2.h> |
| 30 | #include <plat/common/platform.h> |
| 31 | |
Yann Gautier | 8593e44 | 2018-11-14 18:46:15 +0100 | [diff] [blame] | 32 | #include <stm32mp1_context.h> |
Yann Gautier | 091eab5 | 2019-06-04 18:06:34 +0200 | [diff] [blame] | 33 | #include <stm32mp1_dbgmcu.h> |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 34 | |
Etienne Carriere | f02647a | 2019-12-08 08:14:40 +0100 | [diff] [blame] | 35 | #define RESET_TIMEOUT_US_1MS 1000U |
| 36 | |
Andre Przywara | 678c6fa | 2020-01-25 00:58:35 +0000 | [diff] [blame] | 37 | static console_t console; |
Lionel Debieve | 7bd96f4 | 2019-09-03 12:22:23 +0200 | [diff] [blame] | 38 | static struct stm32mp_auth_ops stm32mp1_auth_ops; |
Yann Gautier | 8593e44 | 2018-11-14 18:46:15 +0100 | [diff] [blame] | 39 | |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 40 | static void print_reset_reason(void) |
| 41 | { |
Yann Gautier | 3d78a2e | 2019-02-14 11:01:20 +0100 | [diff] [blame] | 42 | uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR); |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 43 | |
| 44 | if (rstsr == 0U) { |
| 45 | WARN("Reset reason unknown\n"); |
| 46 | return; |
| 47 | } |
| 48 | |
| 49 | INFO("Reset reason (0x%x):\n", rstsr); |
| 50 | |
| 51 | if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) { |
| 52 | if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) { |
| 53 | INFO("System exits from STANDBY\n"); |
| 54 | return; |
| 55 | } |
| 56 | |
| 57 | if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) { |
| 58 | INFO("MPU exits from CSTANDBY\n"); |
| 59 | return; |
| 60 | } |
| 61 | } |
| 62 | |
| 63 | if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) { |
| 64 | INFO(" Power-on Reset (rst_por)\n"); |
| 65 | return; |
| 66 | } |
| 67 | |
| 68 | if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) { |
| 69 | INFO(" Brownout Reset (rst_bor)\n"); |
| 70 | return; |
| 71 | } |
| 72 | |
| 73 | if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) { |
| 74 | if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { |
| 75 | INFO(" System reset generated by MCU (MCSYSRST)\n"); |
| 76 | } else { |
| 77 | INFO(" Local reset generated by MCU (MCSYSRST)\n"); |
| 78 | } |
| 79 | return; |
| 80 | } |
| 81 | |
| 82 | if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) { |
| 83 | INFO(" System reset generated by MPU (MPSYSRST)\n"); |
| 84 | return; |
| 85 | } |
| 86 | |
| 87 | if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) { |
| 88 | INFO(" Reset due to a clock failure on HSE\n"); |
| 89 | return; |
| 90 | } |
| 91 | |
| 92 | if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) { |
| 93 | INFO(" IWDG1 Reset (rst_iwdg1)\n"); |
| 94 | return; |
| 95 | } |
| 96 | |
| 97 | if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) { |
| 98 | INFO(" IWDG2 Reset (rst_iwdg2)\n"); |
| 99 | return; |
| 100 | } |
| 101 | |
| 102 | if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) { |
| 103 | INFO(" MPU Processor 0 Reset\n"); |
| 104 | return; |
| 105 | } |
| 106 | |
| 107 | if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) { |
| 108 | INFO(" MPU Processor 1 Reset\n"); |
| 109 | return; |
| 110 | } |
| 111 | |
| 112 | if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { |
| 113 | INFO(" Pad Reset from NRST\n"); |
| 114 | return; |
| 115 | } |
| 116 | |
| 117 | if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) { |
| 118 | INFO(" Reset due to a failure of VDD_CORE\n"); |
| 119 | return; |
| 120 | } |
| 121 | |
| 122 | ERROR(" Unidentified reset reason\n"); |
| 123 | } |
| 124 | |
| 125 | void bl2_el3_early_platform_setup(u_register_t arg0, |
| 126 | u_register_t arg1 __unused, |
| 127 | u_register_t arg2 __unused, |
| 128 | u_register_t arg3 __unused) |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 129 | { |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 130 | stm32mp_save_boot_ctx_address(arg0); |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 131 | } |
| 132 | |
| 133 | void bl2_platform_setup(void) |
| 134 | { |
Yann Gautier | caf575b | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 135 | int ret; |
| 136 | |
Yann Gautier | f3928f6 | 2019-02-14 11:15:03 +0100 | [diff] [blame] | 137 | if (dt_pmic_status() > 0) { |
Yann Gautier | bb836ee | 2018-07-16 17:55:07 +0200 | [diff] [blame] | 138 | initialize_pmic(); |
| 139 | } |
| 140 | |
Yann Gautier | caf575b | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 141 | ret = stm32mp1_ddr_probe(); |
| 142 | if (ret < 0) { |
| 143 | ERROR("Invalid DDR init: error %d\n", ret); |
| 144 | panic(); |
| 145 | } |
| 146 | |
Yann Gautier | f3bd87e | 2020-09-04 15:55:53 +0200 | [diff] [blame] | 147 | /* Map DDR for binary load, now with cacheable attribute */ |
Yann Gautier | a55169b | 2020-01-10 18:18:59 +0100 | [diff] [blame] | 148 | ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, |
Yann Gautier | f3bd87e | 2020-09-04 15:55:53 +0200 | [diff] [blame] | 149 | STM32MP_DDR_MAX_SIZE, MT_MEMORY | MT_RW | MT_SECURE); |
| 150 | if (ret < 0) { |
| 151 | ERROR("DDR mapping: error %d\n", ret); |
| 152 | panic(); |
| 153 | } |
Yann Gautier | a55169b | 2020-01-10 18:18:59 +0100 | [diff] [blame] | 154 | |
Yann Gautier | 0ed7b2a | 2021-05-19 18:48:16 +0200 | [diff] [blame] | 155 | #if STM32MP_USE_STM32IMAGE |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 156 | #ifdef AARCH32_SP_OPTEE |
| 157 | INFO("BL2 runs OP-TEE setup\n"); |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 158 | #else |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 159 | INFO("BL2 runs SP_MIN setup\n"); |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 160 | #endif |
Yann Gautier | 0ed7b2a | 2021-05-19 18:48:16 +0200 | [diff] [blame] | 161 | #endif /* STM32MP_USE_STM32IMAGE */ |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 162 | } |
| 163 | |
| 164 | void bl2_el3_plat_arch_setup(void) |
| 165 | { |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 166 | int32_t result; |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 167 | struct dt_node_info dt_uart_info; |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 168 | const char *board_model; |
Yann Gautier | 4193466 | 2018-07-20 11:36:05 +0200 | [diff] [blame] | 169 | boot_api_context_t *boot_context = |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 170 | (boot_api_context_t *)stm32mp_get_boot_ctx_address(); |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 171 | uint32_t clk_rate; |
Yann Gautier | 3d78a2e | 2019-02-14 11:01:20 +0100 | [diff] [blame] | 172 | uintptr_t pwr_base; |
| 173 | uintptr_t rcc_base; |
Yann Gautier | 4193466 | 2018-07-20 11:36:05 +0200 | [diff] [blame] | 174 | |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 175 | mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, |
| 176 | BL_CODE_END - BL_CODE_BASE, |
| 177 | MT_CODE | MT_SECURE); |
| 178 | |
Yann Gautier | 0ed7b2a | 2021-05-19 18:48:16 +0200 | [diff] [blame] | 179 | #if STM32MP_USE_STM32IMAGE |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 180 | #ifdef AARCH32_SP_OPTEE |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 181 | mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE, |
| 182 | STM32MP_OPTEE_SIZE, |
| 183 | MT_MEMORY | MT_RW | MT_SECURE); |
Yann Gautier | 90f84d7 | 2021-07-13 14:44:09 +0200 | [diff] [blame] | 184 | #else |
| 185 | /* Prevent corruption of preloaded BL32 */ |
| 186 | mmap_add_region(BL32_BASE, BL32_BASE, |
| 187 | BL32_LIMIT - BL32_BASE, |
| 188 | MT_RO_DATA | MT_SECURE); |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 189 | #endif |
Yann Gautier | 0ed7b2a | 2021-05-19 18:48:16 +0200 | [diff] [blame] | 190 | #endif /* STM32MP_USE_STM32IMAGE */ |
| 191 | |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 192 | /* Prevent corruption of preloaded Device Tree */ |
| 193 | mmap_add_region(DTB_BASE, DTB_BASE, |
| 194 | DTB_LIMIT - DTB_BASE, |
Yann Gautier | 3d33df6 | 2019-12-17 17:11:10 +0100 | [diff] [blame] | 195 | MT_RO_DATA | MT_SECURE); |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 196 | |
| 197 | configure_mmu(); |
| 198 | |
Yann Gautier | 05773eb | 2020-08-24 11:51:50 +0200 | [diff] [blame] | 199 | if (dt_open_and_check(STM32MP_DTB_BASE) < 0) { |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 200 | panic(); |
| 201 | } |
| 202 | |
Yann Gautier | 3d78a2e | 2019-02-14 11:01:20 +0100 | [diff] [blame] | 203 | pwr_base = stm32mp_pwr_base(); |
| 204 | rcc_base = stm32mp_rcc_base(); |
| 205 | |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 206 | /* |
| 207 | * Disable the backup domain write protection. |
| 208 | * The protection is enable at each reset by hardware |
| 209 | * and must be disabled by software. |
| 210 | */ |
Yann Gautier | 3d78a2e | 2019-02-14 11:01:20 +0100 | [diff] [blame] | 211 | mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP); |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 212 | |
Yann Gautier | 3d78a2e | 2019-02-14 11:01:20 +0100 | [diff] [blame] | 213 | while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) { |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 214 | ; |
| 215 | } |
| 216 | |
Yann Gautier | 3edc7c3 | 2019-05-20 19:17:08 +0200 | [diff] [blame] | 217 | if (bsec_probe() != 0) { |
| 218 | panic(); |
| 219 | } |
| 220 | |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 221 | /* Reset backup domain on cold boot cases */ |
Yann Gautier | 3d78a2e | 2019-02-14 11:01:20 +0100 | [diff] [blame] | 222 | if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { |
| 223 | mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 224 | |
Yann Gautier | 3d78a2e | 2019-02-14 11:01:20 +0100 | [diff] [blame] | 225 | while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 226 | 0U) { |
| 227 | ; |
| 228 | } |
| 229 | |
Yann Gautier | 3d78a2e | 2019-02-14 11:01:20 +0100 | [diff] [blame] | 230 | mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 231 | } |
| 232 | |
Yann Gautier | ed34232 | 2019-02-15 17:33:27 +0100 | [diff] [blame] | 233 | /* Disable MCKPROT */ |
| 234 | mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); |
| 235 | |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 236 | generic_delay_timer_init(); |
| 237 | |
Yann Gautier | 9aea69e | 2018-07-24 17:13:36 +0200 | [diff] [blame] | 238 | if (stm32mp1_clk_probe() < 0) { |
| 239 | panic(); |
| 240 | } |
| 241 | |
| 242 | if (stm32mp1_clk_init() < 0) { |
| 243 | panic(); |
| 244 | } |
| 245 | |
Yann Gautier | 3edc7c3 | 2019-05-20 19:17:08 +0200 | [diff] [blame] | 246 | stm32mp1_syscfg_init(); |
| 247 | |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 248 | result = dt_get_stdout_uart_info(&dt_uart_info); |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 249 | |
| 250 | if ((result <= 0) || |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 251 | (dt_uart_info.status == 0U) || |
| 252 | (dt_uart_info.clock < 0) || |
| 253 | (dt_uart_info.reset < 0)) { |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 254 | goto skip_console_init; |
| 255 | } |
| 256 | |
| 257 | if (dt_set_stdout_pinctrl() != 0) { |
| 258 | goto skip_console_init; |
| 259 | } |
| 260 | |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 261 | stm32mp_clk_enable((unsigned long)dt_uart_info.clock); |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 262 | |
Etienne Carriere | f02647a | 2019-12-08 08:14:40 +0100 | [diff] [blame] | 263 | if (stm32mp_reset_assert((uint32_t)dt_uart_info.reset, |
| 264 | RESET_TIMEOUT_US_1MS) != 0) { |
| 265 | panic(); |
| 266 | } |
| 267 | |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 268 | udelay(2); |
Etienne Carriere | f02647a | 2019-12-08 08:14:40 +0100 | [diff] [blame] | 269 | |
| 270 | if (stm32mp_reset_deassert((uint32_t)dt_uart_info.reset, |
| 271 | RESET_TIMEOUT_US_1MS) != 0) { |
| 272 | panic(); |
| 273 | } |
| 274 | |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 275 | mdelay(1); |
| 276 | |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 277 | clk_rate = stm32mp_clk_get_rate((unsigned long)dt_uart_info.clock); |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 278 | |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 279 | if (console_stm32_register(dt_uart_info.base, clk_rate, |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 280 | STM32MP_UART_BAUDRATE, &console) == 0) { |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 281 | panic(); |
| 282 | } |
| 283 | |
Andre Przywara | 678c6fa | 2020-01-25 00:58:35 +0000 | [diff] [blame] | 284 | console_set_scope(&console, CONSOLE_FLAG_BOOT | |
Yann Gautier | a30e5f7 | 2019-09-04 11:55:10 +0200 | [diff] [blame] | 285 | CONSOLE_FLAG_CRASH | CONSOLE_FLAG_TRANSLATE_CRLF); |
| 286 | |
Yann Gautier | c737405 | 2019-06-04 18:02:37 +0200 | [diff] [blame] | 287 | stm32mp_print_cpuinfo(); |
| 288 | |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 289 | board_model = dt_get_board_model(); |
| 290 | if (board_model != NULL) { |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 291 | NOTICE("Model: %s\n", board_model); |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 292 | } |
| 293 | |
Yann Gautier | 35dc077 | 2019-05-13 18:34:48 +0200 | [diff] [blame] | 294 | stm32mp_print_boardinfo(); |
| 295 | |
Lionel Debieve | 7bd96f4 | 2019-09-03 12:22:23 +0200 | [diff] [blame] | 296 | if (boot_context->auth_status != BOOT_API_CTX_AUTH_NO) { |
| 297 | NOTICE("Bootrom authentication %s\n", |
| 298 | (boot_context->auth_status == BOOT_API_CTX_AUTH_FAILED) ? |
| 299 | "failed" : "succeeded"); |
| 300 | } |
| 301 | |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 302 | skip_console_init: |
Yann Gautier | 091eab5 | 2019-06-04 18:06:34 +0200 | [diff] [blame] | 303 | if (stm32_iwdg_init() < 0) { |
| 304 | panic(); |
| 305 | } |
| 306 | |
| 307 | stm32_iwdg_refresh(); |
| 308 | |
| 309 | result = stm32mp1_dbgmcu_freeze_iwdg2(); |
| 310 | if (result != 0) { |
| 311 | INFO("IWDG2 freeze error : %i\n", result); |
| 312 | } |
Yann Gautier | 69035a8 | 2018-07-05 16:48:16 +0200 | [diff] [blame] | 313 | |
Yann Gautier | 4193466 | 2018-07-20 11:36:05 +0200 | [diff] [blame] | 314 | if (stm32_save_boot_interface(boot_context->boot_interface_selected, |
| 315 | boot_context->boot_interface_instance) != |
| 316 | 0) { |
| 317 | ERROR("Cannot save boot interface\n"); |
| 318 | } |
| 319 | |
Lionel Debieve | 7bd96f4 | 2019-09-03 12:22:23 +0200 | [diff] [blame] | 320 | stm32mp1_auth_ops.check_key = boot_context->bootrom_ecdsa_check_key; |
| 321 | stm32mp1_auth_ops.verify_signature = |
| 322 | boot_context->bootrom_ecdsa_verify_signature; |
| 323 | |
| 324 | stm32mp_init_auth(&stm32mp1_auth_ops); |
| 325 | |
Yann Gautier | caf575b | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 326 | stm32mp1_arch_security_setup(); |
| 327 | |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 328 | print_reset_reason(); |
| 329 | |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 330 | stm32mp_io_setup(); |
Yann Gautier | 4b0c72a | 2018-07-16 10:54:09 +0200 | [diff] [blame] | 331 | } |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 332 | |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 333 | /******************************************************************************* |
| 334 | * This function can be used by the platforms to update/use image |
| 335 | * information for given `image_id`. |
| 336 | ******************************************************************************/ |
| 337 | int bl2_plat_handle_post_image_load(unsigned int image_id) |
| 338 | { |
| 339 | int err = 0; |
| 340 | bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); |
| 341 | bl_mem_params_node_t *bl32_mem_params; |
Yann Gautier | 0ed7b2a | 2021-05-19 18:48:16 +0200 | [diff] [blame] | 342 | bl_mem_params_node_t *pager_mem_params __unused; |
| 343 | bl_mem_params_node_t *paged_mem_params __unused; |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 344 | |
| 345 | assert(bl_mem_params != NULL); |
| 346 | |
| 347 | switch (image_id) { |
| 348 | case BL32_IMAGE_ID: |
Yann Gautier | 90f84d7 | 2021-07-13 14:44:09 +0200 | [diff] [blame] | 349 | if (optee_header_is_valid(bl_mem_params->image_info.image_base)) { |
| 350 | /* BL32 is OP-TEE header */ |
| 351 | bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; |
| 352 | pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); |
| 353 | paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); |
| 354 | assert((pager_mem_params != NULL) && (paged_mem_params != NULL)); |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 355 | |
Yann Gautier | 0ed7b2a | 2021-05-19 18:48:16 +0200 | [diff] [blame] | 356 | #if STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) |
Yann Gautier | 90f84d7 | 2021-07-13 14:44:09 +0200 | [diff] [blame] | 357 | /* Set OP-TEE extra image load areas at run-time */ |
| 358 | pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE; |
| 359 | pager_mem_params->image_info.image_max_size = STM32MP_OPTEE_SIZE; |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 360 | |
Yann Gautier | 90f84d7 | 2021-07-13 14:44:09 +0200 | [diff] [blame] | 361 | paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + |
| 362 | dt_get_ddr_size() - |
| 363 | STM32MP_DDR_S_SIZE - |
| 364 | STM32MP_DDR_SHMEM_SIZE; |
| 365 | paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; |
Yann Gautier | 0ed7b2a | 2021-05-19 18:48:16 +0200 | [diff] [blame] | 366 | #endif /* STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) */ |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 367 | |
Yann Gautier | 90f84d7 | 2021-07-13 14:44:09 +0200 | [diff] [blame] | 368 | err = parse_optee_header(&bl_mem_params->ep_info, |
| 369 | &pager_mem_params->image_info, |
| 370 | &paged_mem_params->image_info); |
| 371 | if (err) { |
| 372 | ERROR("OPTEE header parse error.\n"); |
| 373 | panic(); |
| 374 | } |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 375 | |
Yann Gautier | 90f84d7 | 2021-07-13 14:44:09 +0200 | [diff] [blame] | 376 | /* Set optee boot info from parsed header data */ |
| 377 | bl_mem_params->ep_info.args.arg0 = paged_mem_params->image_info.image_base; |
| 378 | bl_mem_params->ep_info.args.arg1 = 0; /* Unused */ |
| 379 | bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */ |
Yann Gautier | 0ed7b2a | 2021-05-19 18:48:16 +0200 | [diff] [blame] | 380 | } else { |
| 381 | #if !STM32MP_USE_STM32IMAGE |
| 382 | bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; |
| 383 | #endif /* !STM32MP_USE_STM32IMAGE */ |
| 384 | bl_mem_params->ep_info.args.arg0 = 0; |
Yann Gautier | 90f84d7 | 2021-07-13 14:44:09 +0200 | [diff] [blame] | 385 | } |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 386 | break; |
| 387 | |
| 388 | case BL33_IMAGE_ID: |
| 389 | bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); |
| 390 | assert(bl32_mem_params != NULL); |
| 391 | bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; |
| 392 | break; |
| 393 | |
| 394 | default: |
| 395 | /* Do nothing in default case */ |
| 396 | break; |
| 397 | } |
| 398 | |
Yann Gautier | a3bd8d1 | 2021-06-18 11:33:26 +0200 | [diff] [blame^] | 399 | #if STM32MP_SDMMC || STM32MP_EMMC |
| 400 | /* |
| 401 | * Invalidate remaining data read from MMC but not flushed by load_image_flush(). |
| 402 | * We take the worst case which is 2 MMC blocks. |
| 403 | */ |
| 404 | if ((image_id != FW_CONFIG_ID) && |
| 405 | ((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) { |
| 406 | inv_dcache_range(bl_mem_params->image_info.image_base + |
| 407 | bl_mem_params->image_info.image_size, |
| 408 | 2U * MMC_BLOCK_SIZE); |
| 409 | } |
| 410 | #endif /* STM32MP_SDMMC || STM32MP_EMMC */ |
| 411 | |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 412 | return err; |
| 413 | } |
Yann Gautier | d2d9b96 | 2021-08-16 11:58:01 +0200 | [diff] [blame] | 414 | |
| 415 | void bl2_el3_plat_prepare_exit(void) |
| 416 | { |
| 417 | stm32mp1_security_setup(); |
| 418 | } |