blob: 2477954b0fb7e324fd788a0c5be90f96240cb916 [file] [log] [blame]
Yann Gautier4b0c72a2018-07-16 10:54:09 +02001/*
Yann Gautiera45433b2019-01-16 18:31:00 +01002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Yann Gautier4b0c72a2018-07-16 10:54:09 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Yann Gautier4b0c72a2018-07-16 10:54:09 +02007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <string.h>
9
Yann Gautier4b0c72a2018-07-16 10:54:09 +020010#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011
12#include <arch_helpers.h>
13#include <common/bl_common.h>
14#include <common/debug.h>
15#include <common/desc_image_load.h>
16#include <drivers/delay_timer.h>
17#include <drivers/generic_delay_timer.h>
18#include <drivers/st/stm32_console.h>
Yann Gautiera45433b2019-01-16 18:31:00 +010019#include <drivers/st/stm32mp_pmic.h>
Yann Gautiera2e2a302019-02-14 11:13:39 +010020#include <drivers/st/stm32mp_reset.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000021#include <drivers/st/stm32mp1_clk.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000022#include <drivers/st/stm32mp1_pwr.h>
23#include <drivers/st/stm32mp1_ram.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000024#include <lib/mmio.h>
25#include <lib/xlat_tables/xlat_tables_v2.h>
26#include <plat/common/platform.h>
27
Yann Gautier8593e442018-11-14 18:46:15 +010028#include <stm32mp1_context.h>
Yann Gautier4b0c72a2018-07-16 10:54:09 +020029
Yann Gautier8593e442018-11-14 18:46:15 +010030static struct console_stm32 console;
31
Yann Gautierf9d40d52019-01-17 14:41:46 +010032static void print_reset_reason(void)
33{
Yann Gautier3d78a2e2019-02-14 11:01:20 +010034 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR);
Yann Gautierf9d40d52019-01-17 14:41:46 +010035
36 if (rstsr == 0U) {
37 WARN("Reset reason unknown\n");
38 return;
39 }
40
41 INFO("Reset reason (0x%x):\n", rstsr);
42
43 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) {
44 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) {
45 INFO("System exits from STANDBY\n");
46 return;
47 }
48
49 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) {
50 INFO("MPU exits from CSTANDBY\n");
51 return;
52 }
53 }
54
55 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) {
56 INFO(" Power-on Reset (rst_por)\n");
57 return;
58 }
59
60 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) {
61 INFO(" Brownout Reset (rst_bor)\n");
62 return;
63 }
64
65 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) {
66 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
67 INFO(" System reset generated by MCU (MCSYSRST)\n");
68 } else {
69 INFO(" Local reset generated by MCU (MCSYSRST)\n");
70 }
71 return;
72 }
73
74 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) {
75 INFO(" System reset generated by MPU (MPSYSRST)\n");
76 return;
77 }
78
79 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) {
80 INFO(" Reset due to a clock failure on HSE\n");
81 return;
82 }
83
84 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) {
85 INFO(" IWDG1 Reset (rst_iwdg1)\n");
86 return;
87 }
88
89 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) {
90 INFO(" IWDG2 Reset (rst_iwdg2)\n");
91 return;
92 }
93
94 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) {
95 INFO(" MPU Processor 0 Reset\n");
96 return;
97 }
98
99 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) {
100 INFO(" MPU Processor 1 Reset\n");
101 return;
102 }
103
104 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
105 INFO(" Pad Reset from NRST\n");
106 return;
107 }
108
109 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) {
110 INFO(" Reset due to a failure of VDD_CORE\n");
111 return;
112 }
113
114 ERROR(" Unidentified reset reason\n");
115}
116
117void bl2_el3_early_platform_setup(u_register_t arg0,
118 u_register_t arg1 __unused,
119 u_register_t arg2 __unused,
120 u_register_t arg3 __unused)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200121{
Yann Gautiera2e2a302019-02-14 11:13:39 +0100122 stm32mp_save_boot_ctx_address(arg0);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200123}
124
125void bl2_platform_setup(void)
126{
Yann Gautiercaf575b2018-07-24 17:18:19 +0200127 int ret;
128
Yann Gautierf3928f62019-02-14 11:15:03 +0100129 if (dt_pmic_status() > 0) {
Yann Gautierbb836ee2018-07-16 17:55:07 +0200130 initialize_pmic();
131 }
132
Yann Gautiercaf575b2018-07-24 17:18:19 +0200133 ret = stm32mp1_ddr_probe();
134 if (ret < 0) {
135 ERROR("Invalid DDR init: error %d\n", ret);
136 panic();
137 }
138
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200139 INFO("BL2 runs SP_MIN setup\n");
140}
141
142void bl2_el3_plat_arch_setup(void)
143{
Yann Gautier69035a82018-07-05 16:48:16 +0200144 int32_t result;
Yann Gautierf9d40d52019-01-17 14:41:46 +0100145 struct dt_node_info dt_uart_info;
Yann Gautier69035a82018-07-05 16:48:16 +0200146 const char *board_model;
Yann Gautier41934662018-07-20 11:36:05 +0200147 boot_api_context_t *boot_context =
Yann Gautiera2e2a302019-02-14 11:13:39 +0100148 (boot_api_context_t *)stm32mp_get_boot_ctx_address();
Yann Gautier69035a82018-07-05 16:48:16 +0200149 uint32_t clk_rate;
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100150 uintptr_t pwr_base;
151 uintptr_t rcc_base;
Yann Gautier41934662018-07-20 11:36:05 +0200152
Yann Gautierf9d40d52019-01-17 14:41:46 +0100153 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
154 BL_CODE_END - BL_CODE_BASE,
155 MT_CODE | MT_SECURE);
156
157 /* Prevent corruption of preloaded BL32 */
158 mmap_add_region(BL32_BASE, BL32_BASE,
159 BL32_LIMIT - BL32_BASE,
160 MT_MEMORY | MT_RO | MT_SECURE);
161
162 /* Map non secure DDR for BL33 load and DDR training area restore */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100163 mmap_add_region(STM32MP_DDR_BASE,
164 STM32MP_DDR_BASE,
165 STM32MP_DDR_MAX_SIZE,
Yann Gautierf9d40d52019-01-17 14:41:46 +0100166 MT_MEMORY | MT_RW | MT_NS);
167
168 /* Prevent corruption of preloaded Device Tree */
169 mmap_add_region(DTB_BASE, DTB_BASE,
170 DTB_LIMIT - DTB_BASE,
171 MT_MEMORY | MT_RO | MT_SECURE);
172
173 configure_mmu();
174
175 if (dt_open_and_check() < 0) {
176 panic();
177 }
178
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100179 pwr_base = stm32mp_pwr_base();
180 rcc_base = stm32mp_rcc_base();
181
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200182 /*
183 * Disable the backup domain write protection.
184 * The protection is enable at each reset by hardware
185 * and must be disabled by software.
186 */
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100187 mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200188
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100189 while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) {
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200190 ;
191 }
192
193 /* Reset backup domain on cold boot cases */
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100194 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) {
195 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200196
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100197 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) ==
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200198 0U) {
199 ;
200 }
201
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100202 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200203 }
204
Yann Gautiered342322019-02-15 17:33:27 +0100205 /* Disable MCKPROT */
206 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT);
207
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200208 generic_delay_timer_init();
209
Yann Gautier9aea69e2018-07-24 17:13:36 +0200210 if (stm32mp1_clk_probe() < 0) {
211 panic();
212 }
213
214 if (stm32mp1_clk_init() < 0) {
215 panic();
216 }
217
Yann Gautierf9d40d52019-01-17 14:41:46 +0100218 result = dt_get_stdout_uart_info(&dt_uart_info);
Yann Gautier69035a82018-07-05 16:48:16 +0200219
220 if ((result <= 0) ||
Yann Gautierf9d40d52019-01-17 14:41:46 +0100221 (dt_uart_info.status == 0U) ||
222 (dt_uart_info.clock < 0) ||
223 (dt_uart_info.reset < 0)) {
Yann Gautier69035a82018-07-05 16:48:16 +0200224 goto skip_console_init;
225 }
226
227 if (dt_set_stdout_pinctrl() != 0) {
228 goto skip_console_init;
229 }
230
Yann Gautiere4a3c352019-02-14 10:53:33 +0100231 stm32mp_clk_enable((unsigned long)dt_uart_info.clock);
Yann Gautier69035a82018-07-05 16:48:16 +0200232
Yann Gautiera2e2a302019-02-14 11:13:39 +0100233 stm32mp_reset_assert((uint32_t)dt_uart_info.reset);
Yann Gautier69035a82018-07-05 16:48:16 +0200234 udelay(2);
Yann Gautiera2e2a302019-02-14 11:13:39 +0100235 stm32mp_reset_deassert((uint32_t)dt_uart_info.reset);
Yann Gautier69035a82018-07-05 16:48:16 +0200236 mdelay(1);
237
Yann Gautiera2e2a302019-02-14 11:13:39 +0100238 clk_rate = stm32mp_clk_get_rate((unsigned long)dt_uart_info.clock);
Yann Gautier69035a82018-07-05 16:48:16 +0200239
Yann Gautierf9d40d52019-01-17 14:41:46 +0100240 if (console_stm32_register(dt_uart_info.base, clk_rate,
Yann Gautiera2e2a302019-02-14 11:13:39 +0100241 STM32MP_UART_BAUDRATE, &console) == 0) {
Yann Gautier69035a82018-07-05 16:48:16 +0200242 panic();
243 }
244
245 board_model = dt_get_board_model();
246 if (board_model != NULL) {
Yann Gautierf9d40d52019-01-17 14:41:46 +0100247 NOTICE("Model: %s\n", board_model);
Yann Gautier69035a82018-07-05 16:48:16 +0200248 }
249
250skip_console_init:
251
Yann Gautier41934662018-07-20 11:36:05 +0200252 if (stm32_save_boot_interface(boot_context->boot_interface_selected,
253 boot_context->boot_interface_instance) !=
254 0) {
255 ERROR("Cannot save boot interface\n");
256 }
257
Yann Gautiercaf575b2018-07-24 17:18:19 +0200258 stm32mp1_arch_security_setup();
259
Yann Gautierf9d40d52019-01-17 14:41:46 +0100260 print_reset_reason();
261
Yann Gautiera2e2a302019-02-14 11:13:39 +0100262 stm32mp_io_setup();
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200263}