feat(stm32mp1): remove unsupported features on STM32MP13
* GPIO: On STM32MP13, there are no banks GPIOJ, GPIOK and GPIOZ.
* STM32MP13 is a single Cortex-A7 CPU: remove reset from MPU1
and reset from MCU traces
* There is no MCU on STM32MP13. Put MCU security management
under STM32MP15 flag.
* The authentication feature is not supported yet on STM32MP13,
put the code under SPM32MP15 flag.
* On STM32MP13, the monotonic counter is managed in ROM code, keep
the monotonic counter update just for STM32MP15.
* SYSCFG: put registers not present on STM32MP13 under STM32MP15
flag, as the code that manages them.
* PMIC: use ldo3 during DDR configuration only for STM32MP15
* Reset UART pins on USB boot is no more required.
Change-Id: Iceba59484a9bb02828fe7e99f3ecafe69c837bc7
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c
index 33ad56f..20356e4 100644
--- a/plat/st/stm32mp1/bl2_plat_setup.c
+++ b/plat/st/stm32mp1/bl2_plat_setup.c
@@ -47,7 +47,9 @@
};
#endif
+#if STM32MP15
static struct stm32mp_auth_ops stm32mp1_auth_ops;
+#endif
static void print_reset_reason(void)
{
@@ -82,6 +84,7 @@
return;
}
+#if STM32MP15
if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) {
if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
INFO(" System reset generated by MCU (MCSYSRST)\n");
@@ -90,6 +93,7 @@
}
return;
}
+#endif
if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) {
INFO(" System reset generated by MPU (MPSYSRST)\n");
@@ -116,10 +120,12 @@
return;
}
+#if STM32MP15
if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) {
INFO(" MPU Processor 1 Reset\n");
return;
}
+#endif
if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
INFO(" Pad Reset from NRST\n");
@@ -171,6 +177,7 @@
#endif /* STM32MP_USE_STM32IMAGE */
}
+#if STM32MP15
static void update_monotonic_counter(void)
{
uint32_t version;
@@ -204,6 +211,7 @@
version);
}
}
+#endif
void bl2_el3_plat_arch_setup(void)
{
@@ -271,8 +279,10 @@
mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
}
+#if STM32MP15
/* Disable MCKPROT */
mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT);
+#endif
/*
* Set minimum reset pulse duration to 31ms for discrete power
@@ -307,7 +317,7 @@
stm32_save_boot_interface(boot_context->boot_interface_selected,
boot_context->boot_interface_instance);
-#if STM32MP_USB_PROGRAMMER
+#if STM32MP_USB_PROGRAMMER && STM32MP15
/* Deconfigure all UART RX pins configured by ROM code */
stm32mp1_deconfigure_uart_pins();
#endif
@@ -359,6 +369,7 @@
}
}
+#if STM32MP15
if (stm32mp_is_auth_supported()) {
stm32mp1_auth_ops.check_key =
boot_context->bootrom_ecdsa_check_key;
@@ -367,12 +378,15 @@
stm32mp_init_auth(&stm32mp1_auth_ops);
}
+#endif
stm32mp1_arch_security_setup();
print_reset_reason();
+#if STM32MP15
update_monotonic_counter();
+#endif
stm32mp1_syscfg_enable_io_compensation_finish();