blob: b5fc3ff75d65ef90db31e7e1608fe17f671698d0 [file] [log] [blame]
Yann Gautier4b0c72a2018-07-16 10:54:09 +02001/*
Yann Gautierb76c61a2020-12-16 10:17:35 +01002 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
Yann Gautier4b0c72a2018-07-16 10:54:09 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Yann Gautier4b0c72a2018-07-16 10:54:09 +02007#include <assert.h>
Yann Gautier658775c2021-07-06 10:00:44 +02008#include <errno.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009#include <string.h>
10
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <arch_helpers.h>
12#include <common/bl_common.h>
13#include <common/debug.h>
14#include <common/desc_image_load.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <drivers/generic_delay_timer.h>
Yann Gautiera3bd8d12021-06-18 11:33:26 +020016#include <drivers/mmc.h>
Yann Gautier3edc7c32019-05-20 19:17:08 +020017#include <drivers/st/bsec.h>
Pascal Pailletfc7b8052021-01-29 14:48:49 +010018#include <drivers/st/regulator_fixed.h>
Yann Gautier091eab52019-06-04 18:06:34 +020019#include <drivers/st/stm32_iwdg.h>
Yann Gautier3d8497c2021-10-18 16:06:22 +020020#include <drivers/st/stm32_uart.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000021#include <drivers/st/stm32mp1_clk.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000022#include <drivers/st/stm32mp1_pwr.h>
23#include <drivers/st/stm32mp1_ram.h>
Yann Gautier0c810882021-12-17 09:53:04 +010024#include <drivers/st/stm32mp_pmic.h>
Yann Gautier658775c2021-07-06 10:00:44 +020025#include <lib/fconf/fconf.h>
26#include <lib/fconf/fconf_dyn_cfg_getter.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000027#include <lib/mmio.h>
Yann Gautierb3386f72019-04-19 09:41:01 +020028#include <lib/optee_utils.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000029#include <lib/xlat_tables/xlat_tables_v2.h>
30#include <plat/common/platform.h>
31
Yann Gautier0c810882021-12-17 09:53:04 +010032#include <platform_def.h>
Sughosh Ganu03e2f802021-12-01 15:56:27 +053033#include <stm32mp_common.h>
Yann Gautier091eab52019-06-04 18:06:34 +020034#include <stm32mp1_dbgmcu.h>
Yann Gautier4b0c72a2018-07-16 10:54:09 +020035
Lionel Debieve7bd96f42019-09-03 12:22:23 +020036static struct stm32mp_auth_ops stm32mp1_auth_ops;
Yann Gautier8593e442018-11-14 18:46:15 +010037
Yann Gautierf9d40d52019-01-17 14:41:46 +010038static void print_reset_reason(void)
39{
Yann Gautier3d78a2e2019-02-14 11:01:20 +010040 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR);
Yann Gautierf9d40d52019-01-17 14:41:46 +010041
42 if (rstsr == 0U) {
43 WARN("Reset reason unknown\n");
44 return;
45 }
46
47 INFO("Reset reason (0x%x):\n", rstsr);
48
49 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) {
50 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) {
51 INFO("System exits from STANDBY\n");
52 return;
53 }
54
55 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) {
56 INFO("MPU exits from CSTANDBY\n");
57 return;
58 }
59 }
60
61 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) {
62 INFO(" Power-on Reset (rst_por)\n");
63 return;
64 }
65
66 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) {
67 INFO(" Brownout Reset (rst_bor)\n");
68 return;
69 }
70
71 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) {
72 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
73 INFO(" System reset generated by MCU (MCSYSRST)\n");
74 } else {
75 INFO(" Local reset generated by MCU (MCSYSRST)\n");
76 }
77 return;
78 }
79
80 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) {
81 INFO(" System reset generated by MPU (MPSYSRST)\n");
82 return;
83 }
84
85 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) {
86 INFO(" Reset due to a clock failure on HSE\n");
87 return;
88 }
89
90 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) {
91 INFO(" IWDG1 Reset (rst_iwdg1)\n");
92 return;
93 }
94
95 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) {
96 INFO(" IWDG2 Reset (rst_iwdg2)\n");
97 return;
98 }
99
100 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) {
101 INFO(" MPU Processor 0 Reset\n");
102 return;
103 }
104
105 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) {
106 INFO(" MPU Processor 1 Reset\n");
107 return;
108 }
109
110 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
111 INFO(" Pad Reset from NRST\n");
112 return;
113 }
114
115 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) {
116 INFO(" Reset due to a failure of VDD_CORE\n");
117 return;
118 }
119
120 ERROR(" Unidentified reset reason\n");
121}
122
123void bl2_el3_early_platform_setup(u_register_t arg0,
124 u_register_t arg1 __unused,
125 u_register_t arg2 __unused,
126 u_register_t arg3 __unused)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200127{
Yann Gautiera2e2a302019-02-14 11:13:39 +0100128 stm32mp_save_boot_ctx_address(arg0);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200129}
130
131void bl2_platform_setup(void)
132{
Yann Gautiercaf575b2018-07-24 17:18:19 +0200133 int ret;
134
Yann Gautiercaf575b2018-07-24 17:18:19 +0200135 ret = stm32mp1_ddr_probe();
136 if (ret < 0) {
137 ERROR("Invalid DDR init: error %d\n", ret);
138 panic();
139 }
140
Yann Gautierf3bd87e2020-09-04 15:55:53 +0200141 /* Map DDR for binary load, now with cacheable attribute */
Yann Gautiera55169b2020-01-10 18:18:59 +0100142 ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
Yann Gautierf3bd87e2020-09-04 15:55:53 +0200143 STM32MP_DDR_MAX_SIZE, MT_MEMORY | MT_RW | MT_SECURE);
144 if (ret < 0) {
145 ERROR("DDR mapping: error %d\n", ret);
146 panic();
147 }
Yann Gautiera55169b2020-01-10 18:18:59 +0100148
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200149#if STM32MP_USE_STM32IMAGE
Yann Gautierb3386f72019-04-19 09:41:01 +0200150#ifdef AARCH32_SP_OPTEE
151 INFO("BL2 runs OP-TEE setup\n");
Yann Gautierb3386f72019-04-19 09:41:01 +0200152#else
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200153 INFO("BL2 runs SP_MIN setup\n");
Yann Gautierb3386f72019-04-19 09:41:01 +0200154#endif
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200155#endif /* STM32MP_USE_STM32IMAGE */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200156}
157
158void bl2_el3_plat_arch_setup(void)
159{
Yann Gautier69035a82018-07-05 16:48:16 +0200160 const char *board_model;
Yann Gautier41934662018-07-20 11:36:05 +0200161 boot_api_context_t *boot_context =
Yann Gautiera2e2a302019-02-14 11:13:39 +0100162 (boot_api_context_t *)stm32mp_get_boot_ctx_address();
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100163 uintptr_t pwr_base;
164 uintptr_t rcc_base;
Yann Gautier41934662018-07-20 11:36:05 +0200165
Yann Gautierf9d40d52019-01-17 14:41:46 +0100166 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
167 BL_CODE_END - BL_CODE_BASE,
168 MT_CODE | MT_SECURE);
169
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200170#if STM32MP_USE_STM32IMAGE
Yann Gautierb3386f72019-04-19 09:41:01 +0200171#ifdef AARCH32_SP_OPTEE
Yann Gautierb3386f72019-04-19 09:41:01 +0200172 mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE,
173 STM32MP_OPTEE_SIZE,
174 MT_MEMORY | MT_RW | MT_SECURE);
Yann Gautier90f84d72021-07-13 14:44:09 +0200175#else
176 /* Prevent corruption of preloaded BL32 */
177 mmap_add_region(BL32_BASE, BL32_BASE,
178 BL32_LIMIT - BL32_BASE,
179 MT_RO_DATA | MT_SECURE);
Yann Gautierb3386f72019-04-19 09:41:01 +0200180#endif
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200181#endif /* STM32MP_USE_STM32IMAGE */
182
Yann Gautierf9d40d52019-01-17 14:41:46 +0100183 /* Prevent corruption of preloaded Device Tree */
184 mmap_add_region(DTB_BASE, DTB_BASE,
185 DTB_LIMIT - DTB_BASE,
Yann Gautier3d33df62019-12-17 17:11:10 +0100186 MT_RO_DATA | MT_SECURE);
Yann Gautierf9d40d52019-01-17 14:41:46 +0100187
188 configure_mmu();
189
Yann Gautier05773eb2020-08-24 11:51:50 +0200190 if (dt_open_and_check(STM32MP_DTB_BASE) < 0) {
Yann Gautierf9d40d52019-01-17 14:41:46 +0100191 panic();
192 }
193
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100194 pwr_base = stm32mp_pwr_base();
195 rcc_base = stm32mp_rcc_base();
196
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200197 /*
198 * Disable the backup domain write protection.
199 * The protection is enable at each reset by hardware
200 * and must be disabled by software.
201 */
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100202 mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200203
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100204 while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) {
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200205 ;
206 }
207
Yann Gautier3edc7c32019-05-20 19:17:08 +0200208 if (bsec_probe() != 0) {
209 panic();
210 }
211
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200212 /* Reset backup domain on cold boot cases */
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100213 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) {
214 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200215
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100216 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) ==
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200217 0U) {
218 ;
219 }
220
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100221 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200222 }
223
Yann Gautiered342322019-02-15 17:33:27 +0100224 /* Disable MCKPROT */
225 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT);
226
Yann Gautierc0882f42021-04-27 18:19:13 +0200227 /*
228 * Set minimum reset pulse duration to 31ms for discrete power
229 * supplied boards.
230 */
231 if (dt_pmic_status() <= 0) {
232 mmio_clrsetbits_32(rcc_base + RCC_RDLSICR,
233 RCC_RDLSICR_MRD_MASK,
234 31U << RCC_RDLSICR_MRD_SHIFT);
235 }
236
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200237 generic_delay_timer_init();
238
Yann Gautier3d8497c2021-10-18 16:06:22 +0200239#if STM32MP_UART_PROGRAMMER
240 /* Disable programmer UART before changing clock tree */
241 if (boot_context->boot_interface_selected ==
242 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) {
243 uintptr_t uart_prog_addr =
244 get_uart_address(boot_context->boot_interface_instance);
245
246 stm32_uart_stop(uart_prog_addr);
247 }
248#endif
Yann Gautier9aea69e2018-07-24 17:13:36 +0200249 if (stm32mp1_clk_probe() < 0) {
250 panic();
251 }
252
253 if (stm32mp1_clk_init() < 0) {
254 panic();
255 }
256
Yann Gautier6eef5252021-12-10 17:04:40 +0100257 stm32_save_boot_interface(boot_context->boot_interface_selected,
258 boot_context->boot_interface_instance);
259
Yann Gautiercd16df32021-06-04 14:04:05 +0200260#if STM32MP_USB_PROGRAMMER
261 /* Deconfigure all UART RX pins configured by ROM code */
262 stm32mp1_deconfigure_uart_pins();
263#endif
264
Yann Gautier66baa962021-10-18 14:01:00 +0200265 if (stm32mp_uart_console_setup() != 0) {
Yann Gautier69035a82018-07-05 16:48:16 +0200266 goto skip_console_init;
267 }
268
Yann Gautierc7374052019-06-04 18:02:37 +0200269 stm32mp_print_cpuinfo();
270
Yann Gautier69035a82018-07-05 16:48:16 +0200271 board_model = dt_get_board_model();
272 if (board_model != NULL) {
Yann Gautierf9d40d52019-01-17 14:41:46 +0100273 NOTICE("Model: %s\n", board_model);
Yann Gautier69035a82018-07-05 16:48:16 +0200274 }
275
Yann Gautier35dc0772019-05-13 18:34:48 +0200276 stm32mp_print_boardinfo();
277
Lionel Debieve7bd96f42019-09-03 12:22:23 +0200278 if (boot_context->auth_status != BOOT_API_CTX_AUTH_NO) {
279 NOTICE("Bootrom authentication %s\n",
280 (boot_context->auth_status == BOOT_API_CTX_AUTH_FAILED) ?
281 "failed" : "succeeded");
282 }
283
Yann Gautier69035a82018-07-05 16:48:16 +0200284skip_console_init:
Pascal Pailletfc7b8052021-01-29 14:48:49 +0100285 if (fixed_regulator_register() != 0) {
286 panic();
287 }
288
Yann Gautier45c1e582020-09-17 11:54:52 +0200289 if (dt_pmic_status() > 0) {
290 initialize_pmic();
Nicolas Le Bayon0b10b652019-11-18 13:13:36 +0100291 print_pmic_info_and_debug();
Yann Gautier45c1e582020-09-17 11:54:52 +0200292 }
293
294 stm32mp1_syscfg_init();
295
Yann Gautier091eab52019-06-04 18:06:34 +0200296 if (stm32_iwdg_init() < 0) {
297 panic();
298 }
299
300 stm32_iwdg_refresh();
301
Lionel Debieve7bd96f42019-09-03 12:22:23 +0200302 stm32mp1_auth_ops.check_key = boot_context->bootrom_ecdsa_check_key;
303 stm32mp1_auth_ops.verify_signature =
304 boot_context->bootrom_ecdsa_verify_signature;
305
306 stm32mp_init_auth(&stm32mp1_auth_ops);
307
Yann Gautiercaf575b2018-07-24 17:18:19 +0200308 stm32mp1_arch_security_setup();
309
Yann Gautierf9d40d52019-01-17 14:41:46 +0100310 print_reset_reason();
311
Yann Gautierb76c61a2020-12-16 10:17:35 +0100312 stm32mp1_syscfg_enable_io_compensation_finish();
313
Yann Gautier29f1f942021-07-13 18:07:41 +0200314#if !STM32MP_USE_STM32IMAGE
315 fconf_populate("TB_FW", STM32MP_DTB_BASE);
316#endif /* !STM32MP_USE_STM32IMAGE */
317
Yann Gautiera2e2a302019-02-14 11:13:39 +0100318 stm32mp_io_setup();
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200319}
Yann Gautierb3386f72019-04-19 09:41:01 +0200320
Yann Gautierb3386f72019-04-19 09:41:01 +0200321/*******************************************************************************
322 * This function can be used by the platforms to update/use image
323 * information for given `image_id`.
324 ******************************************************************************/
325int bl2_plat_handle_post_image_load(unsigned int image_id)
326{
327 int err = 0;
328 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
329 bl_mem_params_node_t *bl32_mem_params;
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200330 bl_mem_params_node_t *pager_mem_params __unused;
331 bl_mem_params_node_t *paged_mem_params __unused;
Yann Gautier658775c2021-07-06 10:00:44 +0200332#if !STM32MP_USE_STM32IMAGE
333 const struct dyn_cfg_dtb_info_t *config_info;
334 bl_mem_params_node_t *tos_fw_mem_params;
335 unsigned int i;
Yann Gautierfd648352021-12-13 15:24:41 +0100336 unsigned int idx;
Yann Gautier658775c2021-07-06 10:00:44 +0200337 unsigned long long ddr_top __unused;
338 const unsigned int image_ids[] = {
339 BL32_IMAGE_ID,
340 BL33_IMAGE_ID,
341 HW_CONFIG_ID,
342 TOS_FW_CONFIG_ID,
343 };
344#endif /* !STM32MP_USE_STM32IMAGE */
Yann Gautierb3386f72019-04-19 09:41:01 +0200345
346 assert(bl_mem_params != NULL);
347
348 switch (image_id) {
Yann Gautier658775c2021-07-06 10:00:44 +0200349#if !STM32MP_USE_STM32IMAGE
350 case FW_CONFIG_ID:
351 /* Set global DTB info for fixed fw_config information */
352 set_config_info(STM32MP_FW_CONFIG_BASE, STM32MP_FW_CONFIG_MAX_SIZE, FW_CONFIG_ID);
353 fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE);
354
Yann Gautierfd648352021-12-13 15:24:41 +0100355 idx = dyn_cfg_dtb_info_get_index(TOS_FW_CONFIG_ID);
356
Yann Gautier658775c2021-07-06 10:00:44 +0200357 /* Iterate through all the fw config IDs */
358 for (i = 0U; i < ARRAY_SIZE(image_ids); i++) {
Yann Gautierfd648352021-12-13 15:24:41 +0100359 if ((image_ids[i] == TOS_FW_CONFIG_ID) && (idx == FCONF_INVALID_IDX)) {
360 continue;
361 }
362
Yann Gautier658775c2021-07-06 10:00:44 +0200363 bl_mem_params = get_bl_mem_params_node(image_ids[i]);
364 assert(bl_mem_params != NULL);
365
366 config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]);
367 if (config_info == NULL) {
368 continue;
369 }
370
371 bl_mem_params->image_info.image_base = config_info->config_addr;
372 bl_mem_params->image_info.image_max_size = config_info->config_max_size;
373
374 bl_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING;
375
376 switch (image_ids[i]) {
377 case BL32_IMAGE_ID:
378 bl_mem_params->ep_info.pc = config_info->config_addr;
379
380 /* In case of OPTEE, initialize address space with tos_fw addr */
381 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
382 pager_mem_params->image_info.image_base = config_info->config_addr;
383 pager_mem_params->image_info.image_max_size =
384 config_info->config_max_size;
385
386 /* Init base and size for pager if exist */
387 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
388 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE +
389 (dt_get_ddr_size() - STM32MP_DDR_S_SIZE -
390 STM32MP_DDR_SHMEM_SIZE);
391 paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE;
392 break;
393
394 case BL33_IMAGE_ID:
395 bl_mem_params->ep_info.pc = config_info->config_addr;
396 break;
397
398 case HW_CONFIG_ID:
399 case TOS_FW_CONFIG_ID:
400 break;
401
402 default:
403 return -EINVAL;
404 }
405 }
406 break;
407#endif /* !STM32MP_USE_STM32IMAGE */
408
Yann Gautierb3386f72019-04-19 09:41:01 +0200409 case BL32_IMAGE_ID:
Yann Gautier90f84d72021-07-13 14:44:09 +0200410 if (optee_header_is_valid(bl_mem_params->image_info.image_base)) {
411 /* BL32 is OP-TEE header */
412 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base;
413 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
414 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
415 assert((pager_mem_params != NULL) && (paged_mem_params != NULL));
Yann Gautierb3386f72019-04-19 09:41:01 +0200416
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200417#if STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE)
Yann Gautier90f84d72021-07-13 14:44:09 +0200418 /* Set OP-TEE extra image load areas at run-time */
419 pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE;
420 pager_mem_params->image_info.image_max_size = STM32MP_OPTEE_SIZE;
Yann Gautierb3386f72019-04-19 09:41:01 +0200421
Yann Gautier90f84d72021-07-13 14:44:09 +0200422 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE +
423 dt_get_ddr_size() -
424 STM32MP_DDR_S_SIZE -
425 STM32MP_DDR_SHMEM_SIZE;
426 paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE;
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200427#endif /* STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) */
Yann Gautierb3386f72019-04-19 09:41:01 +0200428
Yann Gautier90f84d72021-07-13 14:44:09 +0200429 err = parse_optee_header(&bl_mem_params->ep_info,
430 &pager_mem_params->image_info,
431 &paged_mem_params->image_info);
432 if (err) {
433 ERROR("OPTEE header parse error.\n");
434 panic();
435 }
Yann Gautierb3386f72019-04-19 09:41:01 +0200436
Yann Gautier90f84d72021-07-13 14:44:09 +0200437 /* Set optee boot info from parsed header data */
438 bl_mem_params->ep_info.args.arg0 = paged_mem_params->image_info.image_base;
439 bl_mem_params->ep_info.args.arg1 = 0; /* Unused */
440 bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200441 } else {
442#if !STM32MP_USE_STM32IMAGE
443 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base;
Yann Gautier658775c2021-07-06 10:00:44 +0200444 tos_fw_mem_params = get_bl_mem_params_node(TOS_FW_CONFIG_ID);
445 bl_mem_params->image_info.image_max_size +=
446 tos_fw_mem_params->image_info.image_max_size;
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200447#endif /* !STM32MP_USE_STM32IMAGE */
448 bl_mem_params->ep_info.args.arg0 = 0;
Yann Gautier90f84d72021-07-13 14:44:09 +0200449 }
Yann Gautierb3386f72019-04-19 09:41:01 +0200450 break;
451
452 case BL33_IMAGE_ID:
453 bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
454 assert(bl32_mem_params != NULL);
455 bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
Sughosh Ganu03e2f802021-12-01 15:56:27 +0530456#if !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT
457 stm32mp1_fwu_set_boot_idx();
458#endif /* !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT */
Yann Gautierb3386f72019-04-19 09:41:01 +0200459 break;
460
461 default:
462 /* Do nothing in default case */
463 break;
464 }
465
Yann Gautiera3bd8d12021-06-18 11:33:26 +0200466#if STM32MP_SDMMC || STM32MP_EMMC
467 /*
468 * Invalidate remaining data read from MMC but not flushed by load_image_flush().
469 * We take the worst case which is 2 MMC blocks.
470 */
471 if ((image_id != FW_CONFIG_ID) &&
472 ((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) {
473 inv_dcache_range(bl_mem_params->image_info.image_base +
474 bl_mem_params->image_info.image_size,
475 2U * MMC_BLOCK_SIZE);
476 }
477#endif /* STM32MP_SDMMC || STM32MP_EMMC */
478
Yann Gautierb3386f72019-04-19 09:41:01 +0200479 return err;
480}
Yann Gautierd2d9b962021-08-16 11:58:01 +0200481
482void bl2_el3_plat_prepare_exit(void)
483{
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200484 uint16_t boot_itf = stm32mp_get_boot_itf_selected();
485
486 switch (boot_itf) {
Patrick Delaunaye50571b2021-10-28 13:48:52 +0200487#if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
488 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART:
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200489 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB:
490 /* Invalidate the downloaded buffer used with io_memmap */
491 inv_dcache_range(DWL_BUFFER_BASE, DWL_BUFFER_SIZE);
492 break;
Patrick Delaunaye50571b2021-10-28 13:48:52 +0200493#endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200494 default:
495 /* Do nothing in default case */
496 break;
497 }
498
Yann Gautierd2d9b962021-08-16 11:58:01 +0200499 stm32mp1_security_setup();
500}