developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | /* |
| 3 | * |
| 4 | * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> |
| 5 | * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> |
| 6 | * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> |
| 7 | */ |
| 8 | |
| 9 | #include <linux/of_device.h> |
| 10 | #include <linux/of_mdio.h> |
| 11 | #include <linux/of_net.h> |
| 12 | #include <linux/mfd/syscon.h> |
| 13 | #include <linux/regmap.h> |
| 14 | #include <linux/clk.h> |
| 15 | #include <linux/pm_runtime.h> |
| 16 | #include <linux/if_vlan.h> |
| 17 | #include <linux/reset.h> |
| 18 | #include <linux/tcp.h> |
| 19 | #include <linux/interrupt.h> |
| 20 | #include <linux/pinctrl/devinfo.h> |
| 21 | #include <linux/phylink.h> |
developer | a2613e6 | 2022-07-01 18:29:37 +0800 | [diff] [blame] | 22 | #include <linux/gpio/consumer.h> |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 23 | #include <net/dsa.h> |
| 24 | |
| 25 | #include "mtk_eth_soc.h" |
| 26 | #include "mtk_eth_dbg.h" |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 27 | #include "mtk_eth_reset.h" |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 28 | |
| 29 | #if defined(CONFIG_NET_MEDIATEK_HNAT) || defined(CONFIG_NET_MEDIATEK_HNAT_MODULE) |
| 30 | #include "mtk_hnat/nf_hnat_mtk.h" |
| 31 | #endif |
| 32 | |
developer | 75e4dad | 2022-11-16 15:17:14 +0800 | [diff] [blame] | 33 | #if defined(CONFIG_XFRM_OFFLOAD) |
| 34 | #include <crypto/sha.h> |
| 35 | #include <net/xfrm.h> |
| 36 | #include "mtk_ipsec.h" |
| 37 | #endif |
| 38 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 39 | static int mtk_msg_level = -1; |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 40 | atomic_t reset_lock = ATOMIC_INIT(0); |
| 41 | atomic_t force = ATOMIC_INIT(0); |
| 42 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 43 | module_param_named(msg_level, mtk_msg_level, int, 0); |
| 44 | MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 45 | DECLARE_COMPLETION(wait_ser_done); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 46 | |
| 47 | #define MTK_ETHTOOL_STAT(x) { #x, \ |
| 48 | offsetof(struct mtk_hw_stats, x) / sizeof(u64) } |
| 49 | |
| 50 | /* strings used by ethtool */ |
| 51 | static const struct mtk_ethtool_stats { |
| 52 | char str[ETH_GSTRING_LEN]; |
| 53 | u32 offset; |
| 54 | } mtk_ethtool_stats[] = { |
| 55 | MTK_ETHTOOL_STAT(tx_bytes), |
| 56 | MTK_ETHTOOL_STAT(tx_packets), |
| 57 | MTK_ETHTOOL_STAT(tx_skip), |
| 58 | MTK_ETHTOOL_STAT(tx_collisions), |
| 59 | MTK_ETHTOOL_STAT(rx_bytes), |
| 60 | MTK_ETHTOOL_STAT(rx_packets), |
| 61 | MTK_ETHTOOL_STAT(rx_overflow), |
| 62 | MTK_ETHTOOL_STAT(rx_fcs_errors), |
| 63 | MTK_ETHTOOL_STAT(rx_short_errors), |
| 64 | MTK_ETHTOOL_STAT(rx_long_errors), |
| 65 | MTK_ETHTOOL_STAT(rx_checksum_errors), |
| 66 | MTK_ETHTOOL_STAT(rx_flow_control_packets), |
| 67 | }; |
| 68 | |
| 69 | static const char * const mtk_clks_source_name[] = { |
developer | 1bbcf51 | 2022-11-18 16:09:33 +0800 | [diff] [blame] | 70 | "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "gp3", |
| 71 | "xgp1", "xgp2", "xgp3", "crypto", "fe", "trgpll", |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 72 | "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", |
| 73 | "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", |
| 74 | "sgmii_ck", "eth2pll", "wocpu0","wocpu1", |
developer | 1bbcf51 | 2022-11-18 16:09:33 +0800 | [diff] [blame] | 75 | "usxgmii0_sel", "usxgmii1_sel", "sgm0_sel", "sgm1_sel", |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 76 | }; |
| 77 | |
| 78 | void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) |
| 79 | { |
| 80 | __raw_writel(val, eth->base + reg); |
| 81 | } |
| 82 | |
| 83 | u32 mtk_r32(struct mtk_eth *eth, unsigned reg) |
| 84 | { |
| 85 | return __raw_readl(eth->base + reg); |
| 86 | } |
| 87 | |
| 88 | u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg) |
| 89 | { |
| 90 | u32 val; |
| 91 | |
| 92 | val = mtk_r32(eth, reg); |
| 93 | val &= ~mask; |
| 94 | val |= set; |
| 95 | mtk_w32(eth, val, reg); |
| 96 | return reg; |
| 97 | } |
| 98 | |
| 99 | static int mtk_mdio_busy_wait(struct mtk_eth *eth) |
| 100 | { |
| 101 | unsigned long t_start = jiffies; |
| 102 | |
| 103 | while (1) { |
| 104 | if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) |
| 105 | return 0; |
| 106 | if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) |
| 107 | break; |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 108 | cond_resched(); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 109 | } |
| 110 | |
| 111 | dev_err(eth->dev, "mdio: MDIO timeout\n"); |
| 112 | return -1; |
| 113 | } |
| 114 | |
developer | 599cda4 | 2022-05-24 15:13:31 +0800 | [diff] [blame] | 115 | u32 _mtk_mdio_write(struct mtk_eth *eth, int phy_addr, |
| 116 | int phy_reg, u16 write_data) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 117 | { |
| 118 | if (mtk_mdio_busy_wait(eth)) |
| 119 | return -1; |
| 120 | |
| 121 | write_data &= 0xffff; |
| 122 | |
developer | 599cda4 | 2022-05-24 15:13:31 +0800 | [diff] [blame] | 123 | if (phy_reg & MII_ADDR_C45) { |
| 124 | mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_ADDR_C45 | |
| 125 | ((mdiobus_c45_devad(phy_reg) & 0x1f) << PHY_IAC_REG_SHIFT) | |
| 126 | ((phy_addr & 0x1f) << PHY_IAC_ADDR_SHIFT) | mdiobus_c45_regad(phy_reg), |
| 127 | MTK_PHY_IAC); |
| 128 | |
| 129 | if (mtk_mdio_busy_wait(eth)) |
| 130 | return -1; |
| 131 | |
| 132 | mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_WRITE | |
| 133 | ((mdiobus_c45_devad(phy_reg) & 0x1f) << PHY_IAC_REG_SHIFT) | |
| 134 | ((phy_addr & 0x1f) << PHY_IAC_ADDR_SHIFT) | write_data, |
| 135 | MTK_PHY_IAC); |
| 136 | } else { |
| 137 | mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | |
| 138 | ((phy_reg & 0x1f) << PHY_IAC_REG_SHIFT) | |
| 139 | ((phy_addr & 0x1f) << PHY_IAC_ADDR_SHIFT) | write_data, |
| 140 | MTK_PHY_IAC); |
| 141 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 142 | |
| 143 | if (mtk_mdio_busy_wait(eth)) |
| 144 | return -1; |
| 145 | |
| 146 | return 0; |
| 147 | } |
| 148 | |
developer | 599cda4 | 2022-05-24 15:13:31 +0800 | [diff] [blame] | 149 | u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 150 | { |
| 151 | u32 d; |
| 152 | |
| 153 | if (mtk_mdio_busy_wait(eth)) |
| 154 | return 0xffff; |
| 155 | |
developer | 599cda4 | 2022-05-24 15:13:31 +0800 | [diff] [blame] | 156 | if (phy_reg & MII_ADDR_C45) { |
| 157 | mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_ADDR_C45 | |
| 158 | ((mdiobus_c45_devad(phy_reg) & 0x1f) << PHY_IAC_REG_SHIFT) | |
| 159 | ((phy_addr & 0x1f) << PHY_IAC_ADDR_SHIFT) | mdiobus_c45_regad(phy_reg), |
| 160 | MTK_PHY_IAC); |
| 161 | |
| 162 | if (mtk_mdio_busy_wait(eth)) |
| 163 | return 0xffff; |
| 164 | |
| 165 | mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_READ_C45 | |
| 166 | ((mdiobus_c45_devad(phy_reg) & 0x1f) << PHY_IAC_REG_SHIFT) | |
| 167 | ((phy_addr & 0x1f) << PHY_IAC_ADDR_SHIFT), |
| 168 | MTK_PHY_IAC); |
| 169 | } else { |
| 170 | mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | |
| 171 | ((phy_reg & 0x1f) << PHY_IAC_REG_SHIFT) | |
| 172 | ((phy_addr & 0x1f) << PHY_IAC_ADDR_SHIFT), |
| 173 | MTK_PHY_IAC); |
| 174 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 175 | |
| 176 | if (mtk_mdio_busy_wait(eth)) |
| 177 | return 0xffff; |
| 178 | |
| 179 | d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff; |
| 180 | |
| 181 | return d; |
| 182 | } |
| 183 | |
| 184 | static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, |
| 185 | int phy_reg, u16 val) |
| 186 | { |
| 187 | struct mtk_eth *eth = bus->priv; |
| 188 | |
| 189 | return _mtk_mdio_write(eth, phy_addr, phy_reg, val); |
| 190 | } |
| 191 | |
| 192 | static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) |
| 193 | { |
| 194 | struct mtk_eth *eth = bus->priv; |
| 195 | |
| 196 | return _mtk_mdio_read(eth, phy_addr, phy_reg); |
| 197 | } |
| 198 | |
developer | abeadd5 | 2022-08-15 11:26:44 +0800 | [diff] [blame] | 199 | static int mtk_mdio_reset(struct mii_bus *bus) |
| 200 | { |
| 201 | /* The mdiobus_register will trigger a reset pulse when enabling Bus reset, |
| 202 | * we just need to wait until device ready. |
| 203 | */ |
| 204 | mdelay(20); |
| 205 | |
| 206 | return 0; |
| 207 | } |
| 208 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 209 | static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, |
| 210 | phy_interface_t interface) |
| 211 | { |
developer | 543e792 | 2022-12-01 11:24:47 +0800 | [diff] [blame^] | 212 | u32 val = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 213 | |
| 214 | /* Check DDR memory type. |
| 215 | * Currently TRGMII mode with DDR2 memory is not supported. |
| 216 | */ |
| 217 | regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); |
| 218 | if (interface == PHY_INTERFACE_MODE_TRGMII && |
| 219 | val & SYSCFG_DRAM_TYPE_DDR2) { |
| 220 | dev_err(eth->dev, |
| 221 | "TRGMII mode with DDR2 memory is not supported!\n"); |
| 222 | return -EOPNOTSUPP; |
| 223 | } |
| 224 | |
| 225 | val = (interface == PHY_INTERFACE_MODE_TRGMII) ? |
| 226 | ETHSYS_TRGMII_MT7621_DDR_PLL : 0; |
| 227 | |
| 228 | regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, |
| 229 | ETHSYS_TRGMII_MT7621_MASK, val); |
| 230 | |
| 231 | return 0; |
| 232 | } |
| 233 | |
| 234 | static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, |
| 235 | phy_interface_t interface, int speed) |
| 236 | { |
| 237 | u32 val; |
| 238 | int ret; |
| 239 | |
| 240 | if (interface == PHY_INTERFACE_MODE_TRGMII) { |
| 241 | mtk_w32(eth, TRGMII_MODE, INTF_MODE); |
| 242 | val = 500000000; |
| 243 | ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); |
| 244 | if (ret) |
| 245 | dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); |
| 246 | return; |
| 247 | } |
| 248 | |
| 249 | val = (speed == SPEED_1000) ? |
| 250 | INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; |
| 251 | mtk_w32(eth, val, INTF_MODE); |
| 252 | |
| 253 | regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, |
| 254 | ETHSYS_TRGMII_CLK_SEL362_5, |
| 255 | ETHSYS_TRGMII_CLK_SEL362_5); |
| 256 | |
| 257 | val = (speed == SPEED_1000) ? 250000000 : 500000000; |
| 258 | ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); |
| 259 | if (ret) |
| 260 | dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); |
| 261 | |
| 262 | val = (speed == SPEED_1000) ? |
| 263 | RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; |
| 264 | mtk_w32(eth, val, TRGMII_RCK_CTRL); |
| 265 | |
| 266 | val = (speed == SPEED_1000) ? |
| 267 | TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; |
| 268 | mtk_w32(eth, val, TRGMII_TCK_CTRL); |
| 269 | } |
| 270 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 271 | static void mtk_setup_bridge_switch(struct mtk_eth *eth) |
| 272 | { |
| 273 | int val; |
| 274 | |
| 275 | /* Force Port1 XGMAC Link Up */ |
| 276 | val = mtk_r32(eth, MTK_XGMAC_STS(MTK_GMAC1_ID)); |
| 277 | mtk_w32(eth, val | MTK_XGMAC_FORCE_LINK, |
| 278 | MTK_XGMAC_STS(MTK_GMAC1_ID)); |
| 279 | |
| 280 | /* Adjust GSW bridge IPG to 11*/ |
| 281 | val = mtk_r32(eth, MTK_GSW_CFG); |
| 282 | val &= ~(GSWTX_IPG_MASK | GSWRX_IPG_MASK); |
| 283 | val |= (GSW_IPG_11 << GSWTX_IPG_SHIFT) | |
| 284 | (GSW_IPG_11 << GSWRX_IPG_SHIFT); |
| 285 | mtk_w32(eth, val, MTK_GSW_CFG); |
| 286 | |
| 287 | /* Disable GDM1 RX CRC stripping */ |
| 288 | val = mtk_r32(eth, MTK_GDMA_FWD_CFG(0)); |
| 289 | val &= ~MTK_GDMA_STRP_CRC; |
| 290 | mtk_w32(eth, val, MTK_GDMA_FWD_CFG(0)); |
| 291 | } |
| 292 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 293 | static void mtk_mac_config(struct phylink_config *config, unsigned int mode, |
| 294 | const struct phylink_link_state *state) |
| 295 | { |
| 296 | struct mtk_mac *mac = container_of(config, struct mtk_mac, |
| 297 | phylink_config); |
| 298 | struct mtk_eth *eth = mac->hw; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 299 | u32 sid, i; |
developer | 543e792 | 2022-12-01 11:24:47 +0800 | [diff] [blame^] | 300 | int val = 0, ge_mode, err = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 301 | |
| 302 | /* MT76x8 has no hardware settings between for the MAC */ |
| 303 | if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && |
| 304 | mac->interface != state->interface) { |
| 305 | /* Setup soc pin functions */ |
| 306 | switch (state->interface) { |
| 307 | case PHY_INTERFACE_MODE_TRGMII: |
| 308 | if (mac->id) |
| 309 | goto err_phy; |
| 310 | if (!MTK_HAS_CAPS(mac->hw->soc->caps, |
| 311 | MTK_GMAC1_TRGMII)) |
| 312 | goto err_phy; |
| 313 | /* fall through */ |
| 314 | case PHY_INTERFACE_MODE_RGMII_TXID: |
| 315 | case PHY_INTERFACE_MODE_RGMII_RXID: |
| 316 | case PHY_INTERFACE_MODE_RGMII_ID: |
| 317 | case PHY_INTERFACE_MODE_RGMII: |
| 318 | case PHY_INTERFACE_MODE_MII: |
| 319 | case PHY_INTERFACE_MODE_REVMII: |
| 320 | case PHY_INTERFACE_MODE_RMII: |
| 321 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { |
| 322 | err = mtk_gmac_rgmii_path_setup(eth, mac->id); |
| 323 | if (err) |
| 324 | goto init_err; |
| 325 | } |
| 326 | break; |
| 327 | case PHY_INTERFACE_MODE_1000BASEX: |
| 328 | case PHY_INTERFACE_MODE_2500BASEX: |
| 329 | case PHY_INTERFACE_MODE_SGMII: |
| 330 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { |
| 331 | err = mtk_gmac_sgmii_path_setup(eth, mac->id); |
| 332 | if (err) |
| 333 | goto init_err; |
| 334 | } |
| 335 | break; |
| 336 | case PHY_INTERFACE_MODE_GMII: |
| 337 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { |
| 338 | err = mtk_gmac_gephy_path_setup(eth, mac->id); |
| 339 | if (err) |
| 340 | goto init_err; |
| 341 | } |
| 342 | break; |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 343 | case PHY_INTERFACE_MODE_XGMII: |
| 344 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_XGMII)) { |
| 345 | err = mtk_gmac_xgmii_path_setup(eth, mac->id); |
| 346 | if (err) |
| 347 | goto init_err; |
| 348 | } |
| 349 | break; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 350 | case PHY_INTERFACE_MODE_USXGMII: |
| 351 | case PHY_INTERFACE_MODE_10GKR: |
| 352 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) { |
| 353 | err = mtk_gmac_usxgmii_path_setup(eth, mac->id); |
| 354 | if (err) |
| 355 | goto init_err; |
| 356 | } |
| 357 | break; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 358 | default: |
| 359 | goto err_phy; |
| 360 | } |
| 361 | |
| 362 | /* Setup clock for 1st gmac */ |
| 363 | if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && |
| 364 | !phy_interface_mode_is_8023z(state->interface) && |
| 365 | MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { |
| 366 | if (MTK_HAS_CAPS(mac->hw->soc->caps, |
| 367 | MTK_TRGMII_MT7621_CLK)) { |
| 368 | if (mt7621_gmac0_rgmii_adjust(mac->hw, |
| 369 | state->interface)) |
| 370 | goto err_phy; |
| 371 | } else { |
| 372 | mtk_gmac0_rgmii_adjust(mac->hw, |
| 373 | state->interface, |
| 374 | state->speed); |
| 375 | |
| 376 | /* mt7623_pad_clk_setup */ |
| 377 | for (i = 0 ; i < NUM_TRGMII_CTRL; i++) |
| 378 | mtk_w32(mac->hw, |
| 379 | TD_DM_DRVP(8) | TD_DM_DRVN(8), |
| 380 | TRGMII_TD_ODT(i)); |
| 381 | |
| 382 | /* Assert/release MT7623 RXC reset */ |
| 383 | mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, |
| 384 | TRGMII_RCK_CTRL); |
| 385 | mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); |
| 386 | } |
| 387 | } |
| 388 | |
| 389 | ge_mode = 0; |
| 390 | switch (state->interface) { |
| 391 | case PHY_INTERFACE_MODE_MII: |
| 392 | case PHY_INTERFACE_MODE_GMII: |
| 393 | ge_mode = 1; |
| 394 | break; |
| 395 | case PHY_INTERFACE_MODE_REVMII: |
| 396 | ge_mode = 2; |
| 397 | break; |
| 398 | case PHY_INTERFACE_MODE_RMII: |
| 399 | if (mac->id) |
| 400 | goto err_phy; |
| 401 | ge_mode = 3; |
| 402 | break; |
| 403 | default: |
| 404 | break; |
| 405 | } |
| 406 | |
| 407 | /* put the gmac into the right mode */ |
developer | d82e837 | 2022-02-09 15:00:09 +0800 | [diff] [blame] | 408 | spin_lock(ð->syscfg0_lock); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 409 | regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); |
| 410 | val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); |
| 411 | val |= SYSCFG0_GE_MODE(ge_mode, mac->id); |
| 412 | regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); |
developer | d82e837 | 2022-02-09 15:00:09 +0800 | [diff] [blame] | 413 | spin_unlock(ð->syscfg0_lock); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 414 | |
| 415 | mac->interface = state->interface; |
| 416 | } |
| 417 | |
| 418 | /* SGMII */ |
| 419 | if (state->interface == PHY_INTERFACE_MODE_SGMII || |
| 420 | phy_interface_mode_is_8023z(state->interface)) { |
| 421 | /* The path GMAC to SGMII will be enabled once the SGMIISYS is |
| 422 | * being setup done. |
| 423 | */ |
developer | d82e837 | 2022-02-09 15:00:09 +0800 | [diff] [blame] | 424 | spin_lock(ð->syscfg0_lock); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 425 | regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); |
| 426 | |
| 427 | regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, |
| 428 | SYSCFG0_SGMII_MASK, |
| 429 | ~(u32)SYSCFG0_SGMII_MASK); |
| 430 | |
| 431 | /* Decide how GMAC and SGMIISYS be mapped */ |
| 432 | sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? |
| 433 | 0 : mac->id; |
| 434 | |
| 435 | /* Setup SGMIISYS with the determined property */ |
| 436 | if (state->interface != PHY_INTERFACE_MODE_SGMII) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 437 | err = mtk_sgmii_setup_mode_force(eth->xgmii, sid, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 438 | state); |
developer | 2fbee45 | 2022-08-12 13:58:20 +0800 | [diff] [blame] | 439 | else |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 440 | err = mtk_sgmii_setup_mode_an(eth->xgmii, sid); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 441 | |
developer | d82e837 | 2022-02-09 15:00:09 +0800 | [diff] [blame] | 442 | if (err) { |
| 443 | spin_unlock(ð->syscfg0_lock); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 444 | goto init_err; |
developer | d82e837 | 2022-02-09 15:00:09 +0800 | [diff] [blame] | 445 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 446 | |
| 447 | regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, |
| 448 | SYSCFG0_SGMII_MASK, val); |
developer | d82e837 | 2022-02-09 15:00:09 +0800 | [diff] [blame] | 449 | spin_unlock(ð->syscfg0_lock); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 450 | } else if (state->interface == PHY_INTERFACE_MODE_USXGMII || |
| 451 | state->interface == PHY_INTERFACE_MODE_10GKR) { |
| 452 | sid = mac->id; |
| 453 | |
| 454 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) && |
| 455 | sid != MTK_GMAC1_ID) { |
| 456 | if (phylink_autoneg_inband(mode)) |
| 457 | err = mtk_usxgmii_setup_mode_force(eth->xgmii, sid, |
| 458 | SPEED_10000); |
| 459 | else |
| 460 | err = mtk_usxgmii_setup_mode_an(eth->xgmii, sid, |
| 461 | SPEED_10000); |
| 462 | |
| 463 | if (err) |
| 464 | goto init_err; |
| 465 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 466 | } else if (phylink_autoneg_inband(mode)) { |
| 467 | dev_err(eth->dev, |
| 468 | "In-band mode not supported in non SGMII mode!\n"); |
| 469 | return; |
| 470 | } |
| 471 | |
| 472 | /* Setup gmac */ |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 473 | if (mac->type == MTK_XGDM_TYPE) { |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 474 | mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id)); |
| 475 | mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id)); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 476 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 477 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { |
| 478 | switch (mac->id) { |
| 479 | case MTK_GMAC1_ID: |
| 480 | mtk_setup_bridge_switch(eth); |
| 481 | break; |
| 482 | case MTK_GMAC3_ID: |
| 483 | val = mtk_r32(eth, MTK_XGMAC_STS(mac->id)); |
| 484 | mtk_w32(eth, val | MTK_XGMAC_FORCE_LINK, |
| 485 | MTK_XGMAC_STS(mac->id)); |
| 486 | break; |
| 487 | } |
| 488 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 489 | } |
| 490 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 491 | return; |
| 492 | |
| 493 | err_phy: |
| 494 | dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, |
| 495 | mac->id, phy_modes(state->interface)); |
| 496 | return; |
| 497 | |
| 498 | init_err: |
| 499 | dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, |
| 500 | mac->id, phy_modes(state->interface), err); |
| 501 | } |
| 502 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 503 | static int mtk_mac_pcs_get_state(struct phylink_config *config, |
| 504 | struct phylink_link_state *state) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 505 | { |
| 506 | struct mtk_mac *mac = container_of(config, struct mtk_mac, |
| 507 | phylink_config); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 508 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 509 | if (mac->type == MTK_XGDM_TYPE) { |
| 510 | u32 sts = mtk_r32(mac->hw, MTK_XGMAC_STS(mac->id)); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 511 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 512 | if (mac->id == MTK_GMAC2_ID) |
| 513 | sts = sts >> 16; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 514 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 515 | state->duplex = 1; |
| 516 | |
| 517 | switch (FIELD_GET(MTK_USXGMII_PCS_MODE, sts)) { |
| 518 | case 0: |
| 519 | state->speed = SPEED_10000; |
| 520 | break; |
| 521 | case 1: |
| 522 | state->speed = SPEED_5000; |
| 523 | break; |
| 524 | case 2: |
| 525 | state->speed = SPEED_2500; |
| 526 | break; |
| 527 | case 3: |
| 528 | state->speed = SPEED_1000; |
| 529 | break; |
| 530 | } |
| 531 | |
| 532 | state->link = FIELD_GET(MTK_USXGMII_PCS_LINK, sts); |
| 533 | } else if (mac->type == MTK_GDM_TYPE) { |
| 534 | struct mtk_eth *eth = mac->hw; |
| 535 | struct mtk_xgmii *ss = eth->xgmii; |
| 536 | u32 id = mtk_mac2xgmii_id(eth, mac->id); |
| 537 | u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id)); |
developer | 543e792 | 2022-12-01 11:24:47 +0800 | [diff] [blame^] | 538 | u32 val = 0; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 539 | |
| 540 | regmap_read(ss->regmap_sgmii[id], SGMSYS_PCS_CONTROL_1, &val); |
| 541 | |
| 542 | state->link = FIELD_GET(SGMII_LINK_STATYS, val); |
| 543 | |
| 544 | if (FIELD_GET(SGMII_AN_ENABLE, val)) { |
| 545 | regmap_read(ss->regmap_sgmii[id], SGMII_PCS_SPEED_ABILITY, &val); |
| 546 | |
| 547 | val = val >> 16; |
| 548 | |
| 549 | state->duplex = FIELD_GET(SGMII_PCS_SPEED_DUPLEX, val); |
| 550 | |
| 551 | switch (FIELD_GET(SGMII_PCS_SPEED_MASK, val)) { |
| 552 | case 0: |
| 553 | state->speed = SPEED_10; |
| 554 | break; |
| 555 | case 1: |
| 556 | state->speed = SPEED_100; |
| 557 | break; |
| 558 | case 2: |
| 559 | state->speed = SPEED_1000; |
| 560 | break; |
| 561 | } |
| 562 | } else { |
| 563 | regmap_read(ss->regmap_sgmii[id], SGMSYS_SGMII_MODE, &val); |
| 564 | |
| 565 | state->duplex = !FIELD_GET(SGMII_DUPLEX_FULL, val); |
| 566 | |
| 567 | switch (FIELD_GET(SGMII_SPEED_MASK, val)) { |
| 568 | case 0: |
| 569 | state->speed = SPEED_10; |
| 570 | break; |
| 571 | case 1: |
| 572 | state->speed = SPEED_100; |
| 573 | break; |
| 574 | case 2: |
| 575 | regmap_read(ss->regmap_sgmii[id], ss->ana_rgc3, &val); |
| 576 | state->speed = (FIELD_GET(RG_PHY_SPEED_3_125G, val)) ? SPEED_2500 : SPEED_1000; |
| 577 | break; |
| 578 | } |
| 579 | } |
| 580 | |
| 581 | state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); |
| 582 | if (pmsr & MAC_MSR_RX_FC) |
| 583 | state->pause |= MLO_PAUSE_RX; |
| 584 | if (pmsr & MAC_MSR_TX_FC) |
| 585 | state->pause |= MLO_PAUSE_TX; |
| 586 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 587 | |
| 588 | return 1; |
| 589 | } |
| 590 | |
| 591 | static void mtk_mac_an_restart(struct phylink_config *config) |
| 592 | { |
| 593 | struct mtk_mac *mac = container_of(config, struct mtk_mac, |
| 594 | phylink_config); |
| 595 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 596 | if (mac->type != MTK_XGDM_TYPE) |
| 597 | mtk_sgmii_restart_an(mac->hw, mac->id); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 598 | } |
| 599 | |
| 600 | static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, |
| 601 | phy_interface_t interface) |
| 602 | { |
| 603 | struct mtk_mac *mac = container_of(config, struct mtk_mac, |
| 604 | phylink_config); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 605 | u32 mcr; |
| 606 | |
| 607 | if (mac->type == MTK_GDM_TYPE) { |
| 608 | mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); |
| 609 | mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); |
| 610 | mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); |
| 611 | } else if (mac->type == MTK_XGDM_TYPE && mac->id != MTK_GMAC1_ID) { |
| 612 | mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id)); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 613 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 614 | mcr &= 0xfffffff0; |
| 615 | mcr |= XMAC_MCR_TRX_DISABLE; |
| 616 | mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id)); |
| 617 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 618 | } |
| 619 | |
| 620 | static void mtk_mac_link_up(struct phylink_config *config, unsigned int mode, |
| 621 | phy_interface_t interface, |
| 622 | struct phy_device *phy) |
| 623 | { |
| 624 | struct mtk_mac *mac = container_of(config, struct mtk_mac, |
| 625 | phylink_config); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 626 | u32 mcr, mcr_cur; |
| 627 | |
| 628 | if (mac->type == MTK_GDM_TYPE) { |
| 629 | mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); |
| 630 | mcr = mcr_cur; |
| 631 | mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | |
| 632 | MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | |
| 633 | MAC_MCR_FORCE_RX_FC); |
| 634 | mcr |= MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | |
| 635 | MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK; |
| 636 | |
| 637 | /* Configure speed */ |
| 638 | switch (speed) { |
| 639 | case SPEED_2500: |
| 640 | case SPEED_1000: |
| 641 | mcr |= MAC_MCR_SPEED_1000; |
| 642 | break; |
| 643 | case SPEED_100: |
| 644 | mcr |= MAC_MCR_SPEED_100; |
| 645 | break; |
| 646 | } |
| 647 | |
| 648 | /* Configure duplex */ |
| 649 | if (duplex == DUPLEX_FULL) |
| 650 | mcr |= MAC_MCR_FORCE_DPX; |
| 651 | |
| 652 | /* Configure pause modes - |
| 653 | * phylink will avoid these for half duplex |
| 654 | */ |
| 655 | if (tx_pause) |
| 656 | mcr |= MAC_MCR_FORCE_TX_FC; |
| 657 | if (rx_pause) |
| 658 | mcr |= MAC_MCR_FORCE_RX_FC; |
| 659 | |
| 660 | mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN; |
| 661 | |
| 662 | /* Only update control register when needed! */ |
| 663 | if (mcr != mcr_cur) |
| 664 | mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); |
| 665 | } else if (mac->type == MTK_XGDM_TYPE && mac->id != MTK_GMAC1_ID) { |
| 666 | mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id)); |
| 667 | |
| 668 | mcr &= ~(XMAC_MCR_FORCE_TX_FC | XMAC_MCR_FORCE_RX_FC); |
| 669 | /* Configure pause modes - |
| 670 | * phylink will avoid these for half duplex |
| 671 | */ |
| 672 | if (tx_pause) |
| 673 | mcr |= XMAC_MCR_FORCE_TX_FC; |
| 674 | if (rx_pause) |
| 675 | mcr |= XMAC_MCR_FORCE_RX_FC; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 676 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 677 | mcr &= ~(XMAC_MCR_TRX_DISABLE); |
| 678 | mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id)); |
| 679 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 680 | } |
| 681 | |
| 682 | static void mtk_validate(struct phylink_config *config, |
| 683 | unsigned long *supported, |
| 684 | struct phylink_link_state *state) |
| 685 | { |
| 686 | struct mtk_mac *mac = container_of(config, struct mtk_mac, |
| 687 | phylink_config); |
| 688 | __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; |
| 689 | |
| 690 | if (state->interface != PHY_INTERFACE_MODE_NA && |
| 691 | state->interface != PHY_INTERFACE_MODE_MII && |
| 692 | state->interface != PHY_INTERFACE_MODE_GMII && |
| 693 | !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII) && |
| 694 | phy_interface_mode_is_rgmii(state->interface)) && |
| 695 | !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && |
| 696 | !mac->id && state->interface == PHY_INTERFACE_MODE_TRGMII) && |
| 697 | !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII) && |
| 698 | (state->interface == PHY_INTERFACE_MODE_SGMII || |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 699 | phy_interface_mode_is_8023z(state->interface))) && |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 700 | !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_XGMII) && |
| 701 | (state->interface == PHY_INTERFACE_MODE_XGMII)) && |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 702 | !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_USXGMII) && |
| 703 | (state->interface == PHY_INTERFACE_MODE_USXGMII)) && |
| 704 | !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_USXGMII) && |
| 705 | (state->interface == PHY_INTERFACE_MODE_10GKR))) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 706 | linkmode_zero(supported); |
| 707 | return; |
| 708 | } |
| 709 | |
| 710 | phylink_set_port_modes(mask); |
| 711 | phylink_set(mask, Autoneg); |
| 712 | |
| 713 | switch (state->interface) { |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 714 | case PHY_INTERFACE_MODE_USXGMII: |
| 715 | case PHY_INTERFACE_MODE_10GKR: |
| 716 | phylink_set(mask, 10000baseKR_Full); |
| 717 | phylink_set(mask, 10000baseT_Full); |
| 718 | phylink_set(mask, 10000baseCR_Full); |
| 719 | phylink_set(mask, 10000baseSR_Full); |
| 720 | phylink_set(mask, 10000baseLR_Full); |
| 721 | phylink_set(mask, 10000baseLRM_Full); |
| 722 | phylink_set(mask, 10000baseER_Full); |
| 723 | phylink_set(mask, 100baseT_Half); |
| 724 | phylink_set(mask, 100baseT_Full); |
| 725 | phylink_set(mask, 1000baseT_Half); |
| 726 | phylink_set(mask, 1000baseT_Full); |
| 727 | phylink_set(mask, 1000baseX_Full); |
developer | b88cdb0 | 2022-10-12 18:10:03 +0800 | [diff] [blame] | 728 | phylink_set(mask, 2500baseT_Full); |
| 729 | phylink_set(mask, 5000baseT_Full); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 730 | break; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 731 | case PHY_INTERFACE_MODE_TRGMII: |
| 732 | phylink_set(mask, 1000baseT_Full); |
| 733 | break; |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 734 | case PHY_INTERFACE_MODE_XGMII: |
| 735 | /* fall through */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 736 | case PHY_INTERFACE_MODE_1000BASEX: |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 737 | phylink_set(mask, 1000baseX_Full); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 738 | /* fall through; */ |
| 739 | case PHY_INTERFACE_MODE_2500BASEX: |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 740 | phylink_set(mask, 2500baseX_Full); |
developer | 2fbee45 | 2022-08-12 13:58:20 +0800 | [diff] [blame] | 741 | phylink_set(mask, 2500baseT_Full); |
| 742 | /* fall through; */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 743 | case PHY_INTERFACE_MODE_GMII: |
| 744 | case PHY_INTERFACE_MODE_RGMII: |
| 745 | case PHY_INTERFACE_MODE_RGMII_ID: |
| 746 | case PHY_INTERFACE_MODE_RGMII_RXID: |
| 747 | case PHY_INTERFACE_MODE_RGMII_TXID: |
| 748 | phylink_set(mask, 1000baseT_Half); |
| 749 | /* fall through */ |
| 750 | case PHY_INTERFACE_MODE_SGMII: |
| 751 | phylink_set(mask, 1000baseT_Full); |
| 752 | phylink_set(mask, 1000baseX_Full); |
| 753 | /* fall through */ |
| 754 | case PHY_INTERFACE_MODE_MII: |
| 755 | case PHY_INTERFACE_MODE_RMII: |
| 756 | case PHY_INTERFACE_MODE_REVMII: |
| 757 | case PHY_INTERFACE_MODE_NA: |
| 758 | default: |
| 759 | phylink_set(mask, 10baseT_Half); |
| 760 | phylink_set(mask, 10baseT_Full); |
| 761 | phylink_set(mask, 100baseT_Half); |
| 762 | phylink_set(mask, 100baseT_Full); |
| 763 | break; |
| 764 | } |
| 765 | |
| 766 | if (state->interface == PHY_INTERFACE_MODE_NA) { |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 767 | |
| 768 | if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_USXGMII)) { |
| 769 | phylink_set(mask, 10000baseKR_Full); |
| 770 | phylink_set(mask, 10000baseSR_Full); |
| 771 | phylink_set(mask, 10000baseLR_Full); |
| 772 | phylink_set(mask, 10000baseLRM_Full); |
| 773 | phylink_set(mask, 10000baseER_Full); |
| 774 | phylink_set(mask, 1000baseKX_Full); |
| 775 | phylink_set(mask, 1000baseT_Full); |
| 776 | phylink_set(mask, 1000baseX_Full); |
| 777 | phylink_set(mask, 2500baseX_Full); |
| 778 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 779 | if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { |
| 780 | phylink_set(mask, 1000baseT_Full); |
| 781 | phylink_set(mask, 1000baseX_Full); |
| 782 | phylink_set(mask, 2500baseX_Full); |
| 783 | } |
| 784 | if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) { |
| 785 | phylink_set(mask, 1000baseT_Full); |
| 786 | phylink_set(mask, 1000baseT_Half); |
| 787 | phylink_set(mask, 1000baseX_Full); |
| 788 | } |
| 789 | if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GEPHY)) { |
| 790 | phylink_set(mask, 1000baseT_Full); |
| 791 | phylink_set(mask, 1000baseT_Half); |
| 792 | } |
| 793 | } |
| 794 | |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 795 | if (mac->type == MTK_XGDM_TYPE) { |
| 796 | phylink_clear(mask, 10baseT_Half); |
| 797 | phylink_clear(mask, 100baseT_Half); |
| 798 | phylink_clear(mask, 1000baseT_Half); |
| 799 | } |
| 800 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 801 | phylink_set(mask, Pause); |
| 802 | phylink_set(mask, Asym_Pause); |
| 803 | |
| 804 | linkmode_and(supported, supported, mask); |
| 805 | linkmode_and(state->advertising, state->advertising, mask); |
| 806 | |
| 807 | /* We can only operate at 2500BaseX or 1000BaseX. If requested |
| 808 | * to advertise both, only report advertising at 2500BaseX. |
| 809 | */ |
| 810 | phylink_helper_basex_speed(state); |
| 811 | } |
| 812 | |
| 813 | static const struct phylink_mac_ops mtk_phylink_ops = { |
| 814 | .validate = mtk_validate, |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 815 | .mac_link_state = mtk_mac_pcs_get_state, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 816 | .mac_an_restart = mtk_mac_an_restart, |
| 817 | .mac_config = mtk_mac_config, |
| 818 | .mac_link_down = mtk_mac_link_down, |
| 819 | .mac_link_up = mtk_mac_link_up, |
| 820 | }; |
| 821 | |
| 822 | static int mtk_mdio_init(struct mtk_eth *eth) |
| 823 | { |
| 824 | struct device_node *mii_np; |
developer | c8acd8d | 2022-11-10 09:07:10 +0800 | [diff] [blame] | 825 | int clk = 25000000, max_clk = 2500000, divider = 1; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 826 | int ret; |
developer | c8acd8d | 2022-11-10 09:07:10 +0800 | [diff] [blame] | 827 | u32 val; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 828 | |
| 829 | mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); |
| 830 | if (!mii_np) { |
| 831 | dev_err(eth->dev, "no %s child node found", "mdio-bus"); |
| 832 | return -ENODEV; |
| 833 | } |
| 834 | |
| 835 | if (!of_device_is_available(mii_np)) { |
| 836 | ret = -ENODEV; |
| 837 | goto err_put_node; |
| 838 | } |
| 839 | |
| 840 | eth->mii_bus = devm_mdiobus_alloc(eth->dev); |
| 841 | if (!eth->mii_bus) { |
| 842 | ret = -ENOMEM; |
| 843 | goto err_put_node; |
| 844 | } |
| 845 | |
| 846 | eth->mii_bus->name = "mdio"; |
| 847 | eth->mii_bus->read = mtk_mdio_read; |
| 848 | eth->mii_bus->write = mtk_mdio_write; |
developer | abeadd5 | 2022-08-15 11:26:44 +0800 | [diff] [blame] | 849 | eth->mii_bus->reset = mtk_mdio_reset; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 850 | eth->mii_bus->priv = eth; |
| 851 | eth->mii_bus->parent = eth->dev; |
| 852 | |
developer | 6fd4656 | 2021-10-14 15:04:34 +0800 | [diff] [blame] | 853 | if(snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np) < 0) { |
developer | fb556ca | 2021-10-13 10:52:09 +0800 | [diff] [blame] | 854 | ret = -ENOMEM; |
| 855 | goto err_put_node; |
| 856 | } |
developer | c8acd8d | 2022-11-10 09:07:10 +0800 | [diff] [blame] | 857 | |
| 858 | if (!of_property_read_u32(mii_np, "mdc-max-frequency", &val)) |
| 859 | max_clk = val; |
| 860 | |
| 861 | while (clk / divider > max_clk) { |
| 862 | if (divider >= 63) |
| 863 | break; |
| 864 | |
| 865 | divider++; |
| 866 | }; |
| 867 | |
| 868 | /* Configure MDC Turbo Mode */ |
| 869 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { |
| 870 | val = mtk_r32(eth, MTK_MAC_MISC); |
| 871 | val |= MISC_MDC_TURBO; |
| 872 | mtk_w32(eth, val, MTK_MAC_MISC); |
| 873 | } else { |
| 874 | val = mtk_r32(eth, MTK_PPSC); |
| 875 | val |= PPSC_MDC_TURBO; |
| 876 | mtk_w32(eth, val, MTK_PPSC); |
| 877 | } |
| 878 | |
| 879 | /* Configure MDC Divider */ |
| 880 | val = mtk_r32(eth, MTK_PPSC); |
| 881 | val &= ~PPSC_MDC_CFG; |
| 882 | val |= FIELD_PREP(PPSC_MDC_CFG, divider); |
| 883 | mtk_w32(eth, val, MTK_PPSC); |
| 884 | |
| 885 | dev_info(eth->dev, "MDC is running on %d Hz\n", clk / divider); |
| 886 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 887 | ret = of_mdiobus_register(eth->mii_bus, mii_np); |
| 888 | |
| 889 | err_put_node: |
| 890 | of_node_put(mii_np); |
| 891 | return ret; |
| 892 | } |
| 893 | |
| 894 | static void mtk_mdio_cleanup(struct mtk_eth *eth) |
| 895 | { |
| 896 | if (!eth->mii_bus) |
| 897 | return; |
| 898 | |
| 899 | mdiobus_unregister(eth->mii_bus); |
| 900 | } |
| 901 | |
| 902 | static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) |
| 903 | { |
| 904 | unsigned long flags; |
| 905 | u32 val; |
| 906 | |
| 907 | spin_lock_irqsave(ð->tx_irq_lock, flags); |
| 908 | val = mtk_r32(eth, eth->tx_int_mask_reg); |
| 909 | mtk_w32(eth, val & ~mask, eth->tx_int_mask_reg); |
| 910 | spin_unlock_irqrestore(ð->tx_irq_lock, flags); |
| 911 | } |
| 912 | |
| 913 | static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) |
| 914 | { |
| 915 | unsigned long flags; |
| 916 | u32 val; |
| 917 | |
| 918 | spin_lock_irqsave(ð->tx_irq_lock, flags); |
| 919 | val = mtk_r32(eth, eth->tx_int_mask_reg); |
| 920 | mtk_w32(eth, val | mask, eth->tx_int_mask_reg); |
| 921 | spin_unlock_irqrestore(ð->tx_irq_lock, flags); |
| 922 | } |
| 923 | |
| 924 | static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) |
| 925 | { |
| 926 | unsigned long flags; |
| 927 | u32 val; |
| 928 | |
| 929 | spin_lock_irqsave(ð->rx_irq_lock, flags); |
| 930 | val = mtk_r32(eth, MTK_PDMA_INT_MASK); |
| 931 | mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK); |
| 932 | spin_unlock_irqrestore(ð->rx_irq_lock, flags); |
| 933 | } |
| 934 | |
| 935 | static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) |
| 936 | { |
| 937 | unsigned long flags; |
| 938 | u32 val; |
| 939 | |
| 940 | spin_lock_irqsave(ð->rx_irq_lock, flags); |
| 941 | val = mtk_r32(eth, MTK_PDMA_INT_MASK); |
| 942 | mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK); |
| 943 | spin_unlock_irqrestore(ð->rx_irq_lock, flags); |
| 944 | } |
| 945 | |
| 946 | static int mtk_set_mac_address(struct net_device *dev, void *p) |
| 947 | { |
| 948 | int ret = eth_mac_addr(dev, p); |
| 949 | struct mtk_mac *mac = netdev_priv(dev); |
| 950 | struct mtk_eth *eth = mac->hw; |
| 951 | const char *macaddr = dev->dev_addr; |
| 952 | |
| 953 | if (ret) |
| 954 | return ret; |
| 955 | |
| 956 | if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) |
| 957 | return -EBUSY; |
| 958 | |
| 959 | spin_lock_bh(&mac->hw->page_lock); |
| 960 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { |
| 961 | mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], |
| 962 | MT7628_SDM_MAC_ADRH); |
| 963 | mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | |
| 964 | (macaddr[4] << 8) | macaddr[5], |
| 965 | MT7628_SDM_MAC_ADRL); |
| 966 | } else { |
| 967 | mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], |
| 968 | MTK_GDMA_MAC_ADRH(mac->id)); |
| 969 | mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | |
| 970 | (macaddr[4] << 8) | macaddr[5], |
| 971 | MTK_GDMA_MAC_ADRL(mac->id)); |
| 972 | } |
| 973 | spin_unlock_bh(&mac->hw->page_lock); |
| 974 | |
| 975 | return 0; |
| 976 | } |
| 977 | |
| 978 | void mtk_stats_update_mac(struct mtk_mac *mac) |
| 979 | { |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 980 | struct mtk_eth *eth = mac->hw; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 981 | struct mtk_hw_stats *hw_stats = mac->hw_stats; |
| 982 | unsigned int base = MTK_GDM1_TX_GBCNT; |
| 983 | u64 stats; |
| 984 | |
| 985 | base += hw_stats->reg_offset; |
| 986 | |
| 987 | u64_stats_update_begin(&hw_stats->syncp); |
| 988 | |
| 989 | hw_stats->rx_bytes += mtk_r32(mac->hw, base); |
| 990 | stats = mtk_r32(mac->hw, base + 0x04); |
| 991 | if (stats) |
| 992 | hw_stats->rx_bytes += (stats << 32); |
| 993 | hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08); |
| 994 | hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10); |
| 995 | hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14); |
| 996 | hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18); |
| 997 | hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c); |
| 998 | hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20); |
| 999 | hw_stats->rx_flow_control_packets += |
| 1000 | mtk_r32(mac->hw, base + 0x24); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1001 | |
| 1002 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { |
| 1003 | hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x50); |
| 1004 | hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x54); |
| 1005 | hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x40); |
| 1006 | stats = mtk_r32(mac->hw, base + 0x44); |
| 1007 | if (stats) |
| 1008 | hw_stats->tx_bytes += (stats << 32); |
| 1009 | hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x48); |
| 1010 | u64_stats_update_end(&hw_stats->syncp); |
| 1011 | } else { |
| 1012 | hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28); |
| 1013 | hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c); |
| 1014 | hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30); |
| 1015 | stats = mtk_r32(mac->hw, base + 0x34); |
| 1016 | if (stats) |
| 1017 | hw_stats->tx_bytes += (stats << 32); |
| 1018 | hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38); |
| 1019 | u64_stats_update_end(&hw_stats->syncp); |
| 1020 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1021 | } |
| 1022 | |
| 1023 | static void mtk_stats_update(struct mtk_eth *eth) |
| 1024 | { |
| 1025 | int i; |
| 1026 | |
| 1027 | for (i = 0; i < MTK_MAC_COUNT; i++) { |
| 1028 | if (!eth->mac[i] || !eth->mac[i]->hw_stats) |
| 1029 | continue; |
| 1030 | if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { |
| 1031 | mtk_stats_update_mac(eth->mac[i]); |
| 1032 | spin_unlock(ð->mac[i]->hw_stats->stats_lock); |
| 1033 | } |
| 1034 | } |
| 1035 | } |
| 1036 | |
| 1037 | static void mtk_get_stats64(struct net_device *dev, |
| 1038 | struct rtnl_link_stats64 *storage) |
| 1039 | { |
| 1040 | struct mtk_mac *mac = netdev_priv(dev); |
| 1041 | struct mtk_hw_stats *hw_stats = mac->hw_stats; |
| 1042 | unsigned int start; |
| 1043 | |
| 1044 | if (netif_running(dev) && netif_device_present(dev)) { |
| 1045 | if (spin_trylock_bh(&hw_stats->stats_lock)) { |
| 1046 | mtk_stats_update_mac(mac); |
| 1047 | spin_unlock_bh(&hw_stats->stats_lock); |
| 1048 | } |
| 1049 | } |
| 1050 | |
| 1051 | do { |
| 1052 | start = u64_stats_fetch_begin_irq(&hw_stats->syncp); |
| 1053 | storage->rx_packets = hw_stats->rx_packets; |
| 1054 | storage->tx_packets = hw_stats->tx_packets; |
| 1055 | storage->rx_bytes = hw_stats->rx_bytes; |
| 1056 | storage->tx_bytes = hw_stats->tx_bytes; |
| 1057 | storage->collisions = hw_stats->tx_collisions; |
| 1058 | storage->rx_length_errors = hw_stats->rx_short_errors + |
| 1059 | hw_stats->rx_long_errors; |
| 1060 | storage->rx_over_errors = hw_stats->rx_overflow; |
| 1061 | storage->rx_crc_errors = hw_stats->rx_fcs_errors; |
| 1062 | storage->rx_errors = hw_stats->rx_checksum_errors; |
| 1063 | storage->tx_aborted_errors = hw_stats->tx_skip; |
| 1064 | } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start)); |
| 1065 | |
| 1066 | storage->tx_errors = dev->stats.tx_errors; |
| 1067 | storage->rx_dropped = dev->stats.rx_dropped; |
| 1068 | storage->tx_dropped = dev->stats.tx_dropped; |
| 1069 | } |
| 1070 | |
| 1071 | static inline int mtk_max_frag_size(int mtu) |
| 1072 | { |
| 1073 | /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ |
| 1074 | if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH) |
| 1075 | mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; |
| 1076 | |
| 1077 | return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + |
| 1078 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); |
| 1079 | } |
| 1080 | |
| 1081 | static inline int mtk_max_buf_size(int frag_size) |
| 1082 | { |
| 1083 | int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - |
| 1084 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); |
| 1085 | |
| 1086 | WARN_ON(buf_size < MTK_MAX_RX_LENGTH); |
| 1087 | |
| 1088 | return buf_size; |
| 1089 | } |
| 1090 | |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1091 | static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd, |
| 1092 | struct mtk_rx_dma_v2 *dma_rxd) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1093 | { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1094 | rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1095 | if (!(rxd->rxd2 & RX_DMA_DONE)) |
| 1096 | return false; |
| 1097 | |
| 1098 | rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1099 | rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); |
| 1100 | rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1101 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1102 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) || |
| 1103 | MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1104 | rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); |
| 1105 | rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); |
developer | 006325c | 2022-10-06 16:39:50 +0800 | [diff] [blame] | 1106 | rxd->rxd7 = READ_ONCE(dma_rxd->rxd7); |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1107 | } |
| 1108 | |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1109 | return true; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1110 | } |
| 1111 | |
| 1112 | /* the qdma core needs scratch memory to be setup */ |
| 1113 | static int mtk_init_fq_dma(struct mtk_eth *eth) |
| 1114 | { |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1115 | const struct mtk_soc_data *soc = eth->soc; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1116 | dma_addr_t phy_ring_tail; |
| 1117 | int cnt = MTK_DMA_SIZE; |
| 1118 | dma_addr_t dma_addr; |
| 1119 | int i; |
| 1120 | |
| 1121 | if (!eth->soc->has_sram) { |
| 1122 | eth->scratch_ring = dma_alloc_coherent(eth->dev, |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1123 | cnt * soc->txrx.txd_size, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1124 | ð->phy_scratch_ring, |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1125 | GFP_KERNEL); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1126 | } else { |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1127 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) |
| 1128 | eth->scratch_ring = eth->sram_base; |
| 1129 | else if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) |
| 1130 | eth->scratch_ring = eth->base + MTK_ETH_SRAM_OFFSET; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1131 | } |
| 1132 | |
| 1133 | if (unlikely(!eth->scratch_ring)) |
| 1134 | return -ENOMEM; |
| 1135 | |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1136 | eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, GFP_KERNEL); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1137 | if (unlikely(!eth->scratch_head)) |
| 1138 | return -ENOMEM; |
| 1139 | |
| 1140 | dma_addr = dma_map_single(eth->dev, |
| 1141 | eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, |
| 1142 | DMA_FROM_DEVICE); |
| 1143 | if (unlikely(dma_mapping_error(eth->dev, dma_addr))) |
| 1144 | return -ENOMEM; |
| 1145 | |
developer | 8b6f240 | 2022-11-28 13:42:34 +0800 | [diff] [blame] | 1146 | phy_ring_tail = eth->phy_scratch_ring + |
| 1147 | (dma_addr_t)soc->txrx.txd_size * (cnt - 1); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1148 | |
| 1149 | for (i = 0; i < cnt; i++) { |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1150 | struct mtk_tx_dma_v2 *txd; |
| 1151 | |
| 1152 | txd = eth->scratch_ring + i * soc->txrx.txd_size; |
| 1153 | txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1154 | if (i < cnt - 1) |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1155 | txd->txd2 = eth->phy_scratch_ring + |
| 1156 | (i + 1) * soc->txrx.txd_size; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1157 | |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1158 | txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); |
| 1159 | txd->txd4 = 0; |
| 1160 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1161 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) || |
| 1162 | MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1163 | txd->txd5 = 0; |
| 1164 | txd->txd6 = 0; |
| 1165 | txd->txd7 = 0; |
| 1166 | txd->txd8 = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1167 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1168 | } |
| 1169 | |
| 1170 | mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD); |
| 1171 | mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL); |
| 1172 | mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT); |
| 1173 | mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN); |
| 1174 | |
| 1175 | return 0; |
| 1176 | } |
| 1177 | |
| 1178 | static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) |
| 1179 | { |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1180 | return ring->dma + (desc - ring->phys); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1181 | } |
| 1182 | |
| 1183 | static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1184 | void *txd, u32 txd_size) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1185 | { |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1186 | int idx = (txd - ring->dma) / txd_size; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1187 | |
| 1188 | return &ring->buf[idx]; |
| 1189 | } |
| 1190 | |
| 1191 | static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1192 | void *dma) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1193 | { |
| 1194 | return ring->dma_pdma - ring->dma + dma; |
| 1195 | } |
| 1196 | |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1197 | static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1198 | { |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1199 | return (dma - ring->dma) / txd_size; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1200 | } |
| 1201 | |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1202 | static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, |
| 1203 | bool napi) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1204 | { |
| 1205 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
| 1206 | if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { |
| 1207 | dma_unmap_single(eth->dev, |
| 1208 | dma_unmap_addr(tx_buf, dma_addr0), |
| 1209 | dma_unmap_len(tx_buf, dma_len0), |
| 1210 | DMA_TO_DEVICE); |
| 1211 | } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { |
| 1212 | dma_unmap_page(eth->dev, |
| 1213 | dma_unmap_addr(tx_buf, dma_addr0), |
| 1214 | dma_unmap_len(tx_buf, dma_len0), |
| 1215 | DMA_TO_DEVICE); |
| 1216 | } |
| 1217 | } else { |
| 1218 | if (dma_unmap_len(tx_buf, dma_len0)) { |
| 1219 | dma_unmap_page(eth->dev, |
| 1220 | dma_unmap_addr(tx_buf, dma_addr0), |
| 1221 | dma_unmap_len(tx_buf, dma_len0), |
| 1222 | DMA_TO_DEVICE); |
| 1223 | } |
| 1224 | |
| 1225 | if (dma_unmap_len(tx_buf, dma_len1)) { |
| 1226 | dma_unmap_page(eth->dev, |
| 1227 | dma_unmap_addr(tx_buf, dma_addr1), |
| 1228 | dma_unmap_len(tx_buf, dma_len1), |
| 1229 | DMA_TO_DEVICE); |
| 1230 | } |
| 1231 | } |
| 1232 | |
| 1233 | tx_buf->flags = 0; |
| 1234 | if (tx_buf->skb && |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1235 | (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) { |
| 1236 | if (napi) |
| 1237 | napi_consume_skb(tx_buf->skb, napi); |
| 1238 | else |
| 1239 | dev_kfree_skb_any(tx_buf->skb); |
| 1240 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1241 | tx_buf->skb = NULL; |
| 1242 | } |
| 1243 | |
| 1244 | static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, |
| 1245 | struct mtk_tx_dma *txd, dma_addr_t mapped_addr, |
| 1246 | size_t size, int idx) |
| 1247 | { |
| 1248 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
| 1249 | dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); |
| 1250 | dma_unmap_len_set(tx_buf, dma_len0, size); |
| 1251 | } else { |
| 1252 | if (idx & 1) { |
| 1253 | txd->txd3 = mapped_addr; |
| 1254 | txd->txd2 |= TX_DMA_PLEN1(size); |
| 1255 | dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr); |
| 1256 | dma_unmap_len_set(tx_buf, dma_len1, size); |
| 1257 | } else { |
| 1258 | tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; |
| 1259 | txd->txd1 = mapped_addr; |
| 1260 | txd->txd2 = TX_DMA_PLEN0(size); |
| 1261 | dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); |
| 1262 | dma_unmap_len_set(tx_buf, dma_len0, size); |
| 1263 | } |
| 1264 | } |
| 1265 | } |
| 1266 | |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1267 | static void mtk_tx_set_dma_desc_v1(struct sk_buff *skb, struct net_device *dev, void *txd, |
| 1268 | struct mtk_tx_dma_desc_info *info) |
| 1269 | { |
| 1270 | struct mtk_mac *mac = netdev_priv(dev); |
| 1271 | struct mtk_eth *eth = mac->hw; |
| 1272 | struct mtk_tx_dma *desc = txd; |
| 1273 | u32 data; |
| 1274 | |
| 1275 | WRITE_ONCE(desc->txd1, info->addr); |
| 1276 | |
| 1277 | data = TX_DMA_SWC | QID_LOW_BITS(info->qid) | TX_DMA_PLEN0(info->size); |
| 1278 | if (info->last) |
| 1279 | data |= TX_DMA_LS0; |
| 1280 | WRITE_ONCE(desc->txd3, data); |
| 1281 | |
| 1282 | data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */ |
| 1283 | data |= QID_HIGH_BITS(info->qid); |
| 1284 | if (info->first) { |
| 1285 | if (info->gso) |
| 1286 | data |= TX_DMA_TSO; |
| 1287 | /* tx checksum offload */ |
| 1288 | if (info->csum) |
| 1289 | data |= TX_DMA_CHKSUM; |
| 1290 | /* vlan header offload */ |
| 1291 | if (info->vlan) |
| 1292 | data |= TX_DMA_INS_VLAN | info->vlan_tci; |
| 1293 | } |
| 1294 | |
| 1295 | #if defined(CONFIG_NET_MEDIATEK_HNAT) || defined(CONFIG_NET_MEDIATEK_HNAT_MODULE) |
| 1296 | if (HNAT_SKB_CB2(skb)->magic == 0x78681415) { |
| 1297 | data &= ~(0x7 << TX_DMA_FPORT_SHIFT); |
| 1298 | data |= 0x4 << TX_DMA_FPORT_SHIFT; |
| 1299 | } |
| 1300 | |
| 1301 | trace_printk("[%s] skb_shinfo(skb)->nr_frags=%x HNAT_SKB_CB2(skb)->magic=%x txd4=%x<-----\n", |
| 1302 | __func__, skb_shinfo(skb)->nr_frags, HNAT_SKB_CB2(skb)->magic, data); |
| 1303 | #endif |
| 1304 | WRITE_ONCE(desc->txd4, data); |
| 1305 | } |
| 1306 | |
| 1307 | static void mtk_tx_set_dma_desc_v2(struct sk_buff *skb, struct net_device *dev, void *txd, |
| 1308 | struct mtk_tx_dma_desc_info *info) |
| 1309 | { |
| 1310 | struct mtk_mac *mac = netdev_priv(dev); |
| 1311 | struct mtk_eth *eth = mac->hw; |
| 1312 | struct mtk_tx_dma_v2 *desc = txd; |
developer | ce08bca | 2022-10-06 16:21:13 +0800 | [diff] [blame] | 1313 | u32 data = 0; |
| 1314 | |
| 1315 | if (!info->qid && mac->id) |
| 1316 | info->qid = MTK_QDMA_GMAC2_QID; |
| 1317 | |
| 1318 | WRITE_ONCE(desc->txd1, info->addr); |
| 1319 | |
| 1320 | data = TX_DMA_PLEN0(info->size); |
| 1321 | if (info->last) |
| 1322 | data |= TX_DMA_LS0; |
| 1323 | WRITE_ONCE(desc->txd3, data); |
| 1324 | |
| 1325 | data = ((mac->id == MTK_GMAC3_ID) ? |
| 1326 | PSE_GDM3_PORT : (mac->id + 1)) << TX_DMA_FPORT_SHIFT_V2; /* forward port */ |
| 1327 | data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); |
| 1328 | #if defined(CONFIG_NET_MEDIATEK_HNAT) || defined(CONFIG_NET_MEDIATEK_HNAT_MODULE) |
| 1329 | if (HNAT_SKB_CB2(skb)->magic == 0x78681415) { |
| 1330 | data &= ~(0xf << TX_DMA_FPORT_SHIFT_V2); |
| 1331 | data |= 0x4 << TX_DMA_FPORT_SHIFT_V2; |
| 1332 | } |
| 1333 | |
| 1334 | trace_printk("[%s] skb_shinfo(skb)->nr_frags=%x HNAT_SKB_CB2(skb)->magic=%x txd4=%x<-----\n", |
| 1335 | __func__, skb_shinfo(skb)->nr_frags, HNAT_SKB_CB2(skb)->magic, data); |
| 1336 | #endif |
| 1337 | WRITE_ONCE(desc->txd4, data); |
| 1338 | |
| 1339 | data = 0; |
| 1340 | if (info->first) { |
| 1341 | if (info->gso) |
| 1342 | data |= TX_DMA_TSO_V2; |
| 1343 | /* tx checksum offload */ |
| 1344 | if (info->csum) |
| 1345 | data |= TX_DMA_CHKSUM_V2; |
| 1346 | } |
| 1347 | WRITE_ONCE(desc->txd5, data); |
| 1348 | |
| 1349 | data = 0; |
| 1350 | if (info->first && info->vlan) |
| 1351 | data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci; |
| 1352 | WRITE_ONCE(desc->txd6, data); |
| 1353 | |
| 1354 | WRITE_ONCE(desc->txd7, 0); |
| 1355 | WRITE_ONCE(desc->txd8, 0); |
| 1356 | } |
| 1357 | |
| 1358 | static void mtk_tx_set_dma_desc_v3(struct sk_buff *skb, struct net_device *dev, void *txd, |
| 1359 | struct mtk_tx_dma_desc_info *info) |
| 1360 | { |
| 1361 | struct mtk_mac *mac = netdev_priv(dev); |
| 1362 | struct mtk_eth *eth = mac->hw; |
| 1363 | struct mtk_tx_dma_v2 *desc = txd; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1364 | u64 addr64 = 0; |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1365 | u32 data = 0; |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1366 | |
developer | ce08bca | 2022-10-06 16:21:13 +0800 | [diff] [blame] | 1367 | if (!info->qid && mac->id) |
developer | b946301 | 2022-09-14 10:28:45 +0800 | [diff] [blame] | 1368 | info->qid = MTK_QDMA_GMAC2_QID; |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1369 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1370 | addr64 = (MTK_HAS_CAPS(eth->soc->caps, MTK_8GB_ADDRESSING)) ? |
| 1371 | TX_DMA_SDP1(info->addr) : 0; |
| 1372 | |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1373 | WRITE_ONCE(desc->txd1, info->addr); |
| 1374 | |
| 1375 | data = TX_DMA_PLEN0(info->size); |
| 1376 | if (info->last) |
| 1377 | data |= TX_DMA_LS0; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1378 | WRITE_ONCE(desc->txd3, data | addr64); |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1379 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1380 | data = ((mac->id == MTK_GMAC3_ID) ? |
| 1381 | PSE_GDM3_PORT : (mac->id + 1)) << TX_DMA_FPORT_SHIFT_V2; /* forward port */ |
developer | b946301 | 2022-09-14 10:28:45 +0800 | [diff] [blame] | 1382 | data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1383 | #if defined(CONFIG_NET_MEDIATEK_HNAT) || defined(CONFIG_NET_MEDIATEK_HNAT_MODULE) |
| 1384 | if (HNAT_SKB_CB2(skb)->magic == 0x78681415) { |
| 1385 | data &= ~(0xf << TX_DMA_FPORT_SHIFT_V2); |
| 1386 | data |= 0x4 << TX_DMA_FPORT_SHIFT_V2; |
| 1387 | } |
| 1388 | |
| 1389 | trace_printk("[%s] skb_shinfo(skb)->nr_frags=%x HNAT_SKB_CB2(skb)->magic=%x txd4=%x<-----\n", |
| 1390 | __func__, skb_shinfo(skb)->nr_frags, HNAT_SKB_CB2(skb)->magic, data); |
| 1391 | #endif |
| 1392 | WRITE_ONCE(desc->txd4, data); |
| 1393 | |
| 1394 | data = 0; |
| 1395 | if (info->first) { |
| 1396 | if (info->gso) |
| 1397 | data |= TX_DMA_TSO_V2; |
| 1398 | /* tx checksum offload */ |
| 1399 | if (info->csum) |
| 1400 | data |= TX_DMA_CHKSUM_V2; |
developer | ce08bca | 2022-10-06 16:21:13 +0800 | [diff] [blame] | 1401 | |
| 1402 | if (netdev_uses_dsa(dev)) |
| 1403 | data |= TX_DMA_SPTAG_V3; |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1404 | } |
| 1405 | WRITE_ONCE(desc->txd5, data); |
| 1406 | |
| 1407 | data = 0; |
| 1408 | if (info->first && info->vlan) |
| 1409 | data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci; |
| 1410 | WRITE_ONCE(desc->txd6, data); |
| 1411 | |
| 1412 | WRITE_ONCE(desc->txd7, 0); |
| 1413 | WRITE_ONCE(desc->txd8, 0); |
| 1414 | } |
| 1415 | |
| 1416 | static void mtk_tx_set_dma_desc(struct sk_buff *skb, struct net_device *dev, void *txd, |
| 1417 | struct mtk_tx_dma_desc_info *info) |
| 1418 | { |
| 1419 | struct mtk_mac *mac = netdev_priv(dev); |
| 1420 | struct mtk_eth *eth = mac->hw; |
| 1421 | |
developer | ce08bca | 2022-10-06 16:21:13 +0800 | [diff] [blame] | 1422 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) |
| 1423 | mtk_tx_set_dma_desc_v3(skb, dev, txd, info); |
| 1424 | else if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1425 | mtk_tx_set_dma_desc_v2(skb, dev, txd, info); |
| 1426 | else |
| 1427 | mtk_tx_set_dma_desc_v1(skb, dev, txd, info); |
| 1428 | } |
| 1429 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1430 | static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, |
| 1431 | int tx_num, struct mtk_tx_ring *ring, bool gso) |
| 1432 | { |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1433 | struct mtk_tx_dma_desc_info txd_info = { |
| 1434 | .size = skb_headlen(skb), |
| 1435 | .qid = skb->mark & MTK_QDMA_TX_MASK, |
| 1436 | .gso = gso, |
| 1437 | .csum = skb->ip_summed == CHECKSUM_PARTIAL, |
| 1438 | .vlan = skb_vlan_tag_present(skb), |
| 1439 | .vlan_tci = skb_vlan_tag_get(skb), |
| 1440 | .first = true, |
| 1441 | .last = !skb_is_nonlinear(skb), |
| 1442 | }; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1443 | struct mtk_mac *mac = netdev_priv(dev); |
| 1444 | struct mtk_eth *eth = mac->hw; |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1445 | const struct mtk_soc_data *soc = eth->soc; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1446 | struct mtk_tx_dma *itxd, *txd; |
| 1447 | struct mtk_tx_dma *itxd_pdma, *txd_pdma; |
| 1448 | struct mtk_tx_buf *itx_buf, *tx_buf; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1449 | int i, n_desc = 1; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1450 | int k = 0; |
| 1451 | |
| 1452 | itxd = ring->next_free; |
| 1453 | itxd_pdma = qdma_to_pdma(ring, itxd); |
| 1454 | if (itxd == ring->last_free) |
| 1455 | return -ENOMEM; |
| 1456 | |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1457 | itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1458 | memset(itx_buf, 0, sizeof(*itx_buf)); |
| 1459 | |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1460 | txd_info.addr = dma_map_single(eth->dev, skb->data, txd_info.size, |
| 1461 | DMA_TO_DEVICE); |
| 1462 | if (unlikely(dma_mapping_error(eth->dev, txd_info.addr))) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1463 | return -ENOMEM; |
| 1464 | |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1465 | mtk_tx_set_dma_desc(skb, dev, itxd, &txd_info); |
| 1466 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1467 | itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1468 | itx_buf->flags |= (mac->id == MTK_GMAC1_ID) ? MTK_TX_FLAGS_FPORT0 : |
| 1469 | (mac->id == MTK_GMAC2_ID) ? MTK_TX_FLAGS_FPORT1 : |
| 1470 | MTK_TX_FLAGS_FPORT2; |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1471 | setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1472 | k++); |
| 1473 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1474 | /* TX SG offload */ |
| 1475 | txd = itxd; |
| 1476 | txd_pdma = qdma_to_pdma(ring, txd); |
| 1477 | |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1478 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1479 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
| 1480 | unsigned int offset = 0; |
| 1481 | int frag_size = skb_frag_size(frag); |
| 1482 | |
| 1483 | while (frag_size) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1484 | bool new_desc = true; |
| 1485 | |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1486 | if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1487 | (i & 0x1)) { |
| 1488 | txd = mtk_qdma_phys_to_virt(ring, txd->txd2); |
| 1489 | txd_pdma = qdma_to_pdma(ring, txd); |
| 1490 | if (txd == ring->last_free) |
| 1491 | goto err_dma; |
| 1492 | |
| 1493 | n_desc++; |
| 1494 | } else { |
| 1495 | new_desc = false; |
| 1496 | } |
| 1497 | |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1498 | memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); |
| 1499 | txd_info.size = min(frag_size, MTK_TX_DMA_BUF_LEN); |
| 1500 | txd_info.qid = skb->mark & MTK_QDMA_TX_MASK; |
| 1501 | txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 && |
| 1502 | !(frag_size - txd_info.size); |
| 1503 | txd_info.addr = skb_frag_dma_map(eth->dev, frag, |
| 1504 | offset, txd_info.size, |
| 1505 | DMA_TO_DEVICE); |
| 1506 | if (unlikely(dma_mapping_error(eth->dev, txd_info.addr))) |
| 1507 | goto err_dma; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1508 | |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1509 | mtk_tx_set_dma_desc(skb, dev, txd, &txd_info); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1510 | |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1511 | tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1512 | if (new_desc) |
| 1513 | memset(tx_buf, 0, sizeof(*tx_buf)); |
| 1514 | tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; |
| 1515 | tx_buf->flags |= MTK_TX_FLAGS_PAGE0; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1516 | tx_buf->flags |= |
| 1517 | (mac->id == MTK_GMAC1_ID) ? MTK_TX_FLAGS_FPORT0 : |
| 1518 | (mac->id == MTK_GMAC2_ID) ? MTK_TX_FLAGS_FPORT1 : |
| 1519 | MTK_TX_FLAGS_FPORT2; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1520 | |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1521 | setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr, |
| 1522 | txd_info.size, k++); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1523 | |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1524 | frag_size -= txd_info.size; |
| 1525 | offset += txd_info.size; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1526 | } |
| 1527 | } |
| 1528 | |
| 1529 | /* store skb to cleanup */ |
| 1530 | itx_buf->skb = skb; |
| 1531 | |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1532 | if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1533 | if (k & 0x1) |
| 1534 | txd_pdma->txd2 |= TX_DMA_LS0; |
| 1535 | else |
| 1536 | txd_pdma->txd2 |= TX_DMA_LS1; |
| 1537 | } |
| 1538 | |
| 1539 | netdev_sent_queue(dev, skb->len); |
| 1540 | skb_tx_timestamp(skb); |
| 1541 | |
| 1542 | ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); |
| 1543 | atomic_sub(n_desc, &ring->free_count); |
| 1544 | |
| 1545 | /* make sure that all changes to the dma ring are flushed before we |
| 1546 | * continue |
| 1547 | */ |
| 1548 | wmb(); |
| 1549 | |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1550 | if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1551 | if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || |
| 1552 | !netdev_xmit_more()) |
| 1553 | mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); |
| 1554 | } else { |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1555 | int next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size), |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1556 | ring->dma_size); |
| 1557 | mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); |
| 1558 | } |
| 1559 | |
| 1560 | return 0; |
| 1561 | |
| 1562 | err_dma: |
| 1563 | do { |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1564 | tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1565 | |
| 1566 | /* unmap dma */ |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1567 | mtk_tx_unmap(eth, tx_buf, false); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1568 | |
| 1569 | itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1570 | if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1571 | itxd_pdma->txd2 = TX_DMA_DESP2_DEF; |
| 1572 | |
| 1573 | itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); |
| 1574 | itxd_pdma = qdma_to_pdma(ring, itxd); |
| 1575 | } while (itxd != txd); |
| 1576 | |
| 1577 | return -ENOMEM; |
| 1578 | } |
| 1579 | |
| 1580 | static inline int mtk_cal_txd_req(struct sk_buff *skb) |
| 1581 | { |
| 1582 | int i, nfrags; |
| 1583 | skb_frag_t *frag; |
| 1584 | |
| 1585 | nfrags = 1; |
| 1586 | if (skb_is_gso(skb)) { |
| 1587 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { |
| 1588 | frag = &skb_shinfo(skb)->frags[i]; |
| 1589 | nfrags += DIV_ROUND_UP(skb_frag_size(frag), |
| 1590 | MTK_TX_DMA_BUF_LEN); |
| 1591 | } |
| 1592 | } else { |
| 1593 | nfrags += skb_shinfo(skb)->nr_frags; |
| 1594 | } |
| 1595 | |
| 1596 | return nfrags; |
| 1597 | } |
| 1598 | |
| 1599 | static int mtk_queue_stopped(struct mtk_eth *eth) |
| 1600 | { |
| 1601 | int i; |
| 1602 | |
| 1603 | for (i = 0; i < MTK_MAC_COUNT; i++) { |
| 1604 | if (!eth->netdev[i]) |
| 1605 | continue; |
| 1606 | if (netif_queue_stopped(eth->netdev[i])) |
| 1607 | return 1; |
| 1608 | } |
| 1609 | |
| 1610 | return 0; |
| 1611 | } |
| 1612 | |
| 1613 | static void mtk_wake_queue(struct mtk_eth *eth) |
| 1614 | { |
| 1615 | int i; |
| 1616 | |
| 1617 | for (i = 0; i < MTK_MAC_COUNT; i++) { |
| 1618 | if (!eth->netdev[i]) |
| 1619 | continue; |
| 1620 | netif_wake_queue(eth->netdev[i]); |
| 1621 | } |
| 1622 | } |
| 1623 | |
| 1624 | static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) |
| 1625 | { |
| 1626 | struct mtk_mac *mac = netdev_priv(dev); |
| 1627 | struct mtk_eth *eth = mac->hw; |
| 1628 | struct mtk_tx_ring *ring = ð->tx_ring; |
| 1629 | struct net_device_stats *stats = &dev->stats; |
| 1630 | bool gso = false; |
| 1631 | int tx_num; |
| 1632 | |
| 1633 | /* normally we can rely on the stack not calling this more than once, |
| 1634 | * however we have 2 queues running on the same ring so we need to lock |
| 1635 | * the ring access |
| 1636 | */ |
| 1637 | spin_lock(ð->page_lock); |
| 1638 | |
| 1639 | if (unlikely(test_bit(MTK_RESETTING, ð->state))) |
| 1640 | goto drop; |
| 1641 | |
| 1642 | tx_num = mtk_cal_txd_req(skb); |
| 1643 | if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { |
| 1644 | netif_stop_queue(dev); |
| 1645 | netif_err(eth, tx_queued, dev, |
| 1646 | "Tx Ring full when queue awake!\n"); |
| 1647 | spin_unlock(ð->page_lock); |
| 1648 | return NETDEV_TX_BUSY; |
| 1649 | } |
| 1650 | |
| 1651 | /* TSO: fill MSS info in tcp checksum field */ |
| 1652 | if (skb_is_gso(skb)) { |
| 1653 | if (skb_cow_head(skb, 0)) { |
| 1654 | netif_warn(eth, tx_err, dev, |
| 1655 | "GSO expand head fail.\n"); |
| 1656 | goto drop; |
| 1657 | } |
| 1658 | |
| 1659 | if (skb_shinfo(skb)->gso_type & |
| 1660 | (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { |
| 1661 | gso = true; |
| 1662 | tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); |
| 1663 | } |
| 1664 | } |
| 1665 | |
| 1666 | if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) |
| 1667 | goto drop; |
| 1668 | |
| 1669 | if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) |
| 1670 | netif_stop_queue(dev); |
| 1671 | |
| 1672 | spin_unlock(ð->page_lock); |
| 1673 | |
| 1674 | return NETDEV_TX_OK; |
| 1675 | |
| 1676 | drop: |
| 1677 | spin_unlock(ð->page_lock); |
| 1678 | stats->tx_dropped++; |
| 1679 | dev_kfree_skb_any(skb); |
| 1680 | return NETDEV_TX_OK; |
| 1681 | } |
| 1682 | |
| 1683 | static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) |
| 1684 | { |
| 1685 | int i; |
| 1686 | struct mtk_rx_ring *ring; |
| 1687 | int idx; |
| 1688 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1689 | for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1690 | struct mtk_rx_dma *rxd; |
| 1691 | |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 1692 | if (!IS_NORMAL_RING(i) && !IS_HW_LRO_RING(i)) |
| 1693 | continue; |
| 1694 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1695 | ring = ð->rx_ring[i]; |
| 1696 | idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1697 | rxd = ring->dma + idx * eth->soc->txrx.rxd_size; |
| 1698 | if (rxd->rxd2 & RX_DMA_DONE) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1699 | ring->calc_idx_update = true; |
| 1700 | return ring; |
| 1701 | } |
| 1702 | } |
| 1703 | |
| 1704 | return NULL; |
| 1705 | } |
| 1706 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 1707 | static void mtk_update_rx_cpu_idx(struct mtk_eth *eth, struct mtk_rx_ring *ring) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1708 | { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1709 | int i; |
| 1710 | |
developer | fb556ca | 2021-10-13 10:52:09 +0800 | [diff] [blame] | 1711 | if (!eth->hwlro) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1712 | mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); |
developer | fb556ca | 2021-10-13 10:52:09 +0800 | [diff] [blame] | 1713 | else { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1714 | for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { |
| 1715 | ring = ð->rx_ring[i]; |
| 1716 | if (ring->calc_idx_update) { |
| 1717 | ring->calc_idx_update = false; |
| 1718 | mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); |
| 1719 | } |
| 1720 | } |
| 1721 | } |
| 1722 | } |
| 1723 | |
| 1724 | static int mtk_poll_rx(struct napi_struct *napi, int budget, |
| 1725 | struct mtk_eth *eth) |
| 1726 | { |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 1727 | struct mtk_napi *rx_napi = container_of(napi, struct mtk_napi, napi); |
| 1728 | struct mtk_rx_ring *ring = rx_napi->rx_ring; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1729 | int idx; |
| 1730 | struct sk_buff *skb; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1731 | u64 addr64 = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1732 | u8 *data, *new_data; |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1733 | struct mtk_rx_dma_v2 *rxd, trxd; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1734 | int done = 0; |
| 1735 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 1736 | if (unlikely(!ring)) |
| 1737 | goto rx_done; |
| 1738 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1739 | while (done < budget) { |
developer | 006325c | 2022-10-06 16:39:50 +0800 | [diff] [blame] | 1740 | struct net_device *netdev = NULL; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1741 | unsigned int pktlen; |
developer | 8b6f240 | 2022-11-28 13:42:34 +0800 | [diff] [blame] | 1742 | dma_addr_t dma_addr = 0; |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1743 | int mac = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1744 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 1745 | if (eth->hwlro) |
| 1746 | ring = mtk_get_rx_ring(eth); |
| 1747 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1748 | if (unlikely(!ring)) |
| 1749 | goto rx_done; |
| 1750 | |
| 1751 | idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1752 | rxd = ring->dma + idx * eth->soc->txrx.rxd_size; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1753 | data = ring->data[idx]; |
| 1754 | |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1755 | if (!mtk_rx_get_desc(eth, &trxd, rxd)) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1756 | break; |
| 1757 | |
| 1758 | /* find out which mac the packet come from. values start at 1 */ |
| 1759 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { |
| 1760 | mac = 0; |
| 1761 | } else { |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1762 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) || |
| 1763 | MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { |
| 1764 | switch (RX_DMA_GET_SPORT_V2(trxd.rxd5)) { |
| 1765 | case PSE_GDM1_PORT: |
| 1766 | case PSE_GDM2_PORT: |
| 1767 | mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1; |
| 1768 | break; |
| 1769 | case PSE_GDM3_PORT: |
| 1770 | mac = MTK_GMAC3_ID; |
| 1771 | break; |
| 1772 | } |
| 1773 | } else |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1774 | mac = (trxd.rxd4 & RX_DMA_SPECIAL_TAG) ? |
| 1775 | 0 : RX_DMA_GET_SPORT(trxd.rxd4) - 1; |
| 1776 | } |
| 1777 | |
| 1778 | if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || |
| 1779 | !eth->netdev[mac])) |
| 1780 | goto release_desc; |
| 1781 | |
| 1782 | netdev = eth->netdev[mac]; |
| 1783 | |
| 1784 | if (unlikely(test_bit(MTK_RESETTING, ð->state))) |
| 1785 | goto release_desc; |
| 1786 | |
| 1787 | /* alloc new buffer */ |
| 1788 | new_data = napi_alloc_frag(ring->frag_size); |
| 1789 | if (unlikely(!new_data)) { |
| 1790 | netdev->stats.rx_dropped++; |
| 1791 | goto release_desc; |
| 1792 | } |
| 1793 | dma_addr = dma_map_single(eth->dev, |
| 1794 | new_data + NET_SKB_PAD + |
| 1795 | eth->ip_align, |
| 1796 | ring->buf_size, |
| 1797 | DMA_FROM_DEVICE); |
| 1798 | if (unlikely(dma_mapping_error(eth->dev, dma_addr))) { |
| 1799 | skb_free_frag(new_data); |
| 1800 | netdev->stats.rx_dropped++; |
| 1801 | goto release_desc; |
| 1802 | } |
| 1803 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1804 | addr64 = (MTK_HAS_CAPS(eth->soc->caps, MTK_8GB_ADDRESSING)) ? |
| 1805 | ((u64)(trxd.rxd2 & 0xf)) << 32 : 0; |
| 1806 | |
| 1807 | dma_unmap_single(eth->dev, |
| 1808 | (u64)(trxd.rxd1 | addr64), |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1809 | ring->buf_size, DMA_FROM_DEVICE); |
| 1810 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1811 | /* receive data */ |
| 1812 | skb = build_skb(data, ring->frag_size); |
| 1813 | if (unlikely(!skb)) { |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1814 | skb_free_frag(data); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1815 | netdev->stats.rx_dropped++; |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1816 | goto skip_rx; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1817 | } |
| 1818 | skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); |
| 1819 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1820 | pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); |
| 1821 | skb->dev = netdev; |
| 1822 | skb_put(skb, pktlen); |
| 1823 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1824 | if ((MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1) && |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1825 | (trxd.rxd4 & eth->rx_dma_l4_valid)) || |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1826 | (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1) && |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1827 | (trxd.rxd3 & eth->rx_dma_l4_valid))) |
| 1828 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
| 1829 | else |
| 1830 | skb_checksum_none_assert(skb); |
| 1831 | skb->protocol = eth_type_trans(skb, netdev); |
| 1832 | |
| 1833 | if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1834 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) || |
| 1835 | MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { |
developer | 255bba2 | 2021-07-27 15:16:33 +0800 | [diff] [blame] | 1836 | if (trxd.rxd3 & RX_DMA_VTAG_V2) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1837 | __vlan_hwaccel_put_tag(skb, |
developer | 255bba2 | 2021-07-27 15:16:33 +0800 | [diff] [blame] | 1838 | htons(RX_DMA_VPID_V2(trxd.rxd4)), |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1839 | RX_DMA_VID_V2(trxd.rxd4)); |
| 1840 | } else { |
| 1841 | if (trxd.rxd2 & RX_DMA_VTAG) |
| 1842 | __vlan_hwaccel_put_tag(skb, |
| 1843 | htons(RX_DMA_VPID(trxd.rxd3)), |
| 1844 | RX_DMA_VID(trxd.rxd3)); |
| 1845 | } |
| 1846 | |
| 1847 | /* If netdev is attached to dsa switch, the special |
| 1848 | * tag inserted in VLAN field by switch hardware can |
| 1849 | * be offload by RX HW VLAN offload. Clears the VLAN |
| 1850 | * information from @skb to avoid unexpected 8021d |
| 1851 | * handler before packet enter dsa framework. |
| 1852 | */ |
| 1853 | if (netdev_uses_dsa(netdev)) |
| 1854 | __vlan_hwaccel_clear_tag(skb); |
| 1855 | } |
| 1856 | |
| 1857 | #if defined(CONFIG_NET_MEDIATEK_HNAT) || defined(CONFIG_NET_MEDIATEK_HNAT_MODULE) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1858 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) || |
| 1859 | MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1860 | *(u32 *)(skb->head) = trxd.rxd5; |
| 1861 | else |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1862 | *(u32 *)(skb->head) = trxd.rxd4; |
| 1863 | |
| 1864 | skb_hnat_alg(skb) = 0; |
developer | fdfe157 | 2021-09-13 16:56:33 +0800 | [diff] [blame] | 1865 | skb_hnat_filled(skb) = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1866 | skb_hnat_magic_tag(skb) = HNAT_MAGIC_TAG; |
| 1867 | |
| 1868 | if (skb_hnat_reason(skb) == HIT_BIND_FORCE_TO_CPU) { |
| 1869 | trace_printk("[%s] reason=0x%x(force to CPU) from WAN to Ext\n", |
| 1870 | __func__, skb_hnat_reason(skb)); |
| 1871 | skb->pkt_type = PACKET_HOST; |
| 1872 | } |
| 1873 | |
| 1874 | trace_printk("[%s] rxd:(entry=%x,sport=%x,reason=%x,alg=%x\n", |
| 1875 | __func__, skb_hnat_entry(skb), skb_hnat_sport(skb), |
| 1876 | skb_hnat_reason(skb), skb_hnat_alg(skb)); |
| 1877 | #endif |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 1878 | if (mtk_hwlro_stats_ebl && |
| 1879 | IS_HW_LRO_RING(ring->ring_no) && eth->hwlro) { |
| 1880 | hw_lro_stats_update(ring->ring_no, &trxd); |
| 1881 | hw_lro_flush_stats_update(ring->ring_no, &trxd); |
| 1882 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1883 | |
| 1884 | skb_record_rx_queue(skb, 0); |
| 1885 | napi_gro_receive(napi, skb); |
| 1886 | |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1887 | skip_rx: |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1888 | ring->data[idx] = new_data; |
| 1889 | rxd->rxd1 = (unsigned int)dma_addr; |
| 1890 | |
| 1891 | release_desc: |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1892 | addr64 = (MTK_HAS_CAPS(eth->soc->caps, MTK_8GB_ADDRESSING)) ? |
| 1893 | RX_DMA_SDP1(dma_addr) : 0; |
| 1894 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1895 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) |
| 1896 | rxd->rxd2 = RX_DMA_LSO; |
| 1897 | else |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1898 | rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size) | addr64; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1899 | |
| 1900 | ring->calc_idx = idx; |
| 1901 | |
| 1902 | done++; |
| 1903 | } |
| 1904 | |
| 1905 | rx_done: |
| 1906 | if (done) { |
| 1907 | /* make sure that all changes to the dma ring are flushed before |
| 1908 | * we continue |
| 1909 | */ |
| 1910 | wmb(); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 1911 | mtk_update_rx_cpu_idx(eth, ring); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1912 | } |
| 1913 | |
| 1914 | return done; |
| 1915 | } |
| 1916 | |
developer | fb556ca | 2021-10-13 10:52:09 +0800 | [diff] [blame] | 1917 | static void mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1918 | unsigned int *done, unsigned int *bytes) |
| 1919 | { |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1920 | const struct mtk_soc_data *soc = eth->soc; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1921 | struct mtk_tx_ring *ring = ð->tx_ring; |
| 1922 | struct mtk_tx_dma *desc; |
| 1923 | struct sk_buff *skb; |
| 1924 | struct mtk_tx_buf *tx_buf; |
| 1925 | u32 cpu, dma; |
| 1926 | |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1927 | cpu = ring->last_free_ptr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1928 | dma = mtk_r32(eth, MTK_QTX_DRX_PTR); |
| 1929 | |
| 1930 | desc = mtk_qdma_phys_to_virt(ring, cpu); |
| 1931 | |
| 1932 | while ((cpu != dma) && budget) { |
| 1933 | u32 next_cpu = desc->txd2; |
| 1934 | int mac = 0; |
| 1935 | |
| 1936 | if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) |
| 1937 | break; |
| 1938 | |
| 1939 | desc = mtk_qdma_phys_to_virt(ring, desc->txd2); |
| 1940 | |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1941 | tx_buf = mtk_desc_to_tx_buf(ring, desc, soc->txrx.txd_size); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1942 | if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1943 | mac = MTK_GMAC2_ID; |
| 1944 | else if (tx_buf->flags & MTK_TX_FLAGS_FPORT2) |
| 1945 | mac = MTK_GMAC3_ID; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1946 | |
| 1947 | skb = tx_buf->skb; |
| 1948 | if (!skb) |
| 1949 | break; |
| 1950 | |
| 1951 | if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { |
| 1952 | bytes[mac] += skb->len; |
| 1953 | done[mac]++; |
| 1954 | budget--; |
| 1955 | } |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1956 | mtk_tx_unmap(eth, tx_buf, true); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1957 | |
| 1958 | ring->last_free = desc; |
| 1959 | atomic_inc(&ring->free_count); |
| 1960 | |
| 1961 | cpu = next_cpu; |
| 1962 | } |
| 1963 | |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1964 | ring->last_free_ptr = cpu; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1965 | mtk_w32(eth, cpu, MTK_QTX_CRX_PTR); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1966 | } |
| 1967 | |
developer | fb556ca | 2021-10-13 10:52:09 +0800 | [diff] [blame] | 1968 | static void mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1969 | unsigned int *done, unsigned int *bytes) |
| 1970 | { |
| 1971 | struct mtk_tx_ring *ring = ð->tx_ring; |
| 1972 | struct mtk_tx_dma *desc; |
| 1973 | struct sk_buff *skb; |
| 1974 | struct mtk_tx_buf *tx_buf; |
| 1975 | u32 cpu, dma; |
| 1976 | |
| 1977 | cpu = ring->cpu_idx; |
| 1978 | dma = mtk_r32(eth, MT7628_TX_DTX_IDX0); |
| 1979 | |
| 1980 | while ((cpu != dma) && budget) { |
| 1981 | tx_buf = &ring->buf[cpu]; |
| 1982 | skb = tx_buf->skb; |
| 1983 | if (!skb) |
| 1984 | break; |
| 1985 | |
| 1986 | if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { |
| 1987 | bytes[0] += skb->len; |
| 1988 | done[0]++; |
| 1989 | budget--; |
| 1990 | } |
| 1991 | |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 1992 | mtk_tx_unmap(eth, tx_buf, true); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1993 | |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 1994 | desc = ring->dma + cpu * eth->soc->txrx.txd_size; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1995 | ring->last_free = desc; |
| 1996 | atomic_inc(&ring->free_count); |
| 1997 | |
| 1998 | cpu = NEXT_DESP_IDX(cpu, ring->dma_size); |
| 1999 | } |
| 2000 | |
| 2001 | ring->cpu_idx = cpu; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2002 | } |
| 2003 | |
| 2004 | static int mtk_poll_tx(struct mtk_eth *eth, int budget) |
| 2005 | { |
| 2006 | struct mtk_tx_ring *ring = ð->tx_ring; |
| 2007 | unsigned int done[MTK_MAX_DEVS]; |
| 2008 | unsigned int bytes[MTK_MAX_DEVS]; |
| 2009 | int total = 0, i; |
| 2010 | |
| 2011 | memset(done, 0, sizeof(done)); |
| 2012 | memset(bytes, 0, sizeof(bytes)); |
| 2013 | |
| 2014 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) |
developer | fb556ca | 2021-10-13 10:52:09 +0800 | [diff] [blame] | 2015 | mtk_poll_tx_qdma(eth, budget, done, bytes); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2016 | else |
developer | fb556ca | 2021-10-13 10:52:09 +0800 | [diff] [blame] | 2017 | mtk_poll_tx_pdma(eth, budget, done, bytes); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2018 | |
| 2019 | for (i = 0; i < MTK_MAC_COUNT; i++) { |
| 2020 | if (!eth->netdev[i] || !done[i]) |
| 2021 | continue; |
| 2022 | netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); |
| 2023 | total += done[i]; |
| 2024 | } |
| 2025 | |
| 2026 | if (mtk_queue_stopped(eth) && |
| 2027 | (atomic_read(&ring->free_count) > ring->thresh)) |
| 2028 | mtk_wake_queue(eth); |
| 2029 | |
| 2030 | return total; |
| 2031 | } |
| 2032 | |
| 2033 | static void mtk_handle_status_irq(struct mtk_eth *eth) |
| 2034 | { |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 2035 | u32 status2 = mtk_r32(eth, MTK_FE_INT_STATUS); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2036 | |
| 2037 | if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { |
| 2038 | mtk_stats_update(eth); |
| 2039 | mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 2040 | MTK_FE_INT_STATUS); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2041 | } |
| 2042 | } |
| 2043 | |
| 2044 | static int mtk_napi_tx(struct napi_struct *napi, int budget) |
| 2045 | { |
| 2046 | struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); |
| 2047 | u32 status, mask; |
| 2048 | int tx_done = 0; |
| 2049 | |
| 2050 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) |
| 2051 | mtk_handle_status_irq(eth); |
| 2052 | mtk_w32(eth, MTK_TX_DONE_INT, eth->tx_int_status_reg); |
| 2053 | tx_done = mtk_poll_tx(eth, budget); |
| 2054 | |
| 2055 | if (unlikely(netif_msg_intr(eth))) { |
| 2056 | status = mtk_r32(eth, eth->tx_int_status_reg); |
| 2057 | mask = mtk_r32(eth, eth->tx_int_mask_reg); |
| 2058 | dev_info(eth->dev, |
| 2059 | "done tx %d, intr 0x%08x/0x%x\n", |
| 2060 | tx_done, status, mask); |
| 2061 | } |
| 2062 | |
| 2063 | if (tx_done == budget) |
| 2064 | return budget; |
| 2065 | |
| 2066 | status = mtk_r32(eth, eth->tx_int_status_reg); |
| 2067 | if (status & MTK_TX_DONE_INT) |
| 2068 | return budget; |
| 2069 | |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 2070 | if (napi_complete(napi)) |
| 2071 | mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2072 | |
| 2073 | return tx_done; |
| 2074 | } |
| 2075 | |
| 2076 | static int mtk_napi_rx(struct napi_struct *napi, int budget) |
| 2077 | { |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2078 | struct mtk_napi *rx_napi = container_of(napi, struct mtk_napi, napi); |
| 2079 | struct mtk_eth *eth = rx_napi->eth; |
| 2080 | struct mtk_rx_ring *ring = rx_napi->rx_ring; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2081 | u32 status, mask; |
| 2082 | int rx_done = 0; |
| 2083 | int remain_budget = budget; |
| 2084 | |
| 2085 | mtk_handle_status_irq(eth); |
| 2086 | |
| 2087 | poll_again: |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2088 | mtk_w32(eth, MTK_RX_DONE_INT(ring->ring_no), MTK_PDMA_INT_STATUS); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2089 | rx_done = mtk_poll_rx(napi, remain_budget, eth); |
| 2090 | |
| 2091 | if (unlikely(netif_msg_intr(eth))) { |
| 2092 | status = mtk_r32(eth, MTK_PDMA_INT_STATUS); |
| 2093 | mask = mtk_r32(eth, MTK_PDMA_INT_MASK); |
| 2094 | dev_info(eth->dev, |
| 2095 | "done rx %d, intr 0x%08x/0x%x\n", |
| 2096 | rx_done, status, mask); |
| 2097 | } |
| 2098 | if (rx_done == remain_budget) |
| 2099 | return budget; |
| 2100 | |
| 2101 | status = mtk_r32(eth, MTK_PDMA_INT_STATUS); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2102 | if (status & MTK_RX_DONE_INT(ring->ring_no)) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2103 | remain_budget -= rx_done; |
| 2104 | goto poll_again; |
| 2105 | } |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 2106 | |
| 2107 | if (napi_complete(napi)) |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2108 | mtk_rx_irq_enable(eth, MTK_RX_DONE_INT(ring->ring_no)); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2109 | |
| 2110 | return rx_done + budget - remain_budget; |
| 2111 | } |
| 2112 | |
| 2113 | static int mtk_tx_alloc(struct mtk_eth *eth) |
| 2114 | { |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 2115 | const struct mtk_soc_data *soc = eth->soc; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2116 | struct mtk_tx_ring *ring = ð->tx_ring; |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 2117 | int i, sz = soc->txrx.txd_size; |
| 2118 | struct mtk_tx_dma_v2 *txd, *pdma_txd; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2119 | |
| 2120 | ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), |
| 2121 | GFP_KERNEL); |
| 2122 | if (!ring->buf) |
| 2123 | goto no_tx_mem; |
| 2124 | |
| 2125 | if (!eth->soc->has_sram) |
| 2126 | ring->dma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz, |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 2127 | &ring->phys, GFP_KERNEL); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2128 | else { |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 2129 | ring->dma = eth->scratch_ring + MTK_DMA_SIZE * sz; |
developer | 8b6f240 | 2022-11-28 13:42:34 +0800 | [diff] [blame] | 2130 | ring->phys = eth->phy_scratch_ring + |
| 2131 | MTK_DMA_SIZE * (dma_addr_t)sz; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2132 | } |
| 2133 | |
| 2134 | if (!ring->dma) |
| 2135 | goto no_tx_mem; |
| 2136 | |
| 2137 | for (i = 0; i < MTK_DMA_SIZE; i++) { |
| 2138 | int next = (i + 1) % MTK_DMA_SIZE; |
| 2139 | u32 next_ptr = ring->phys + next * sz; |
| 2140 | |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 2141 | txd = ring->dma + i * sz; |
| 2142 | txd->txd2 = next_ptr; |
| 2143 | txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; |
| 2144 | txd->txd4 = 0; |
| 2145 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 2146 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) || |
| 2147 | MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 2148 | txd->txd5 = 0; |
| 2149 | txd->txd6 = 0; |
| 2150 | txd->txd7 = 0; |
| 2151 | txd->txd8 = 0; |
| 2152 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2153 | } |
| 2154 | |
| 2155 | /* On MT7688 (PDMA only) this driver uses the ring->dma structs |
| 2156 | * only as the framework. The real HW descriptors are the PDMA |
| 2157 | * descriptors in ring->dma_pdma. |
| 2158 | */ |
| 2159 | if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
| 2160 | ring->dma_pdma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz, |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 2161 | &ring->phys_pdma, GFP_KERNEL); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2162 | if (!ring->dma_pdma) |
| 2163 | goto no_tx_mem; |
| 2164 | |
| 2165 | for (i = 0; i < MTK_DMA_SIZE; i++) { |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 2166 | pdma_txd = ring->dma_pdma + i *sz; |
| 2167 | |
| 2168 | pdma_txd->txd2 = TX_DMA_DESP2_DEF; |
| 2169 | pdma_txd->txd4 = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2170 | } |
| 2171 | } |
| 2172 | |
| 2173 | ring->dma_size = MTK_DMA_SIZE; |
| 2174 | atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 2175 | ring->next_free = ring->dma; |
| 2176 | ring->last_free = (void *)txd; |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 2177 | ring->last_free_ptr = (u32)(ring->phys + ((MTK_DMA_SIZE - 1) * sz)); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2178 | ring->thresh = MAX_SKB_FRAGS; |
| 2179 | |
| 2180 | /* make sure that all changes to the dma ring are flushed before we |
| 2181 | * continue |
| 2182 | */ |
| 2183 | wmb(); |
| 2184 | |
| 2185 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
| 2186 | mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR); |
| 2187 | mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR); |
| 2188 | mtk_w32(eth, |
| 2189 | ring->phys + ((MTK_DMA_SIZE - 1) * sz), |
| 2190 | MTK_QTX_CRX_PTR); |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 2191 | mtk_w32(eth, ring->last_free_ptr, MTK_QTX_DRX_PTR); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2192 | mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, |
| 2193 | MTK_QTX_CFG(0)); |
| 2194 | } else { |
| 2195 | mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); |
| 2196 | mtk_w32(eth, MTK_DMA_SIZE, MT7628_TX_MAX_CNT0); |
| 2197 | mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); |
| 2198 | mtk_w32(eth, MT7628_PST_DTX_IDX0, MTK_PDMA_RST_IDX); |
| 2199 | } |
| 2200 | |
| 2201 | return 0; |
| 2202 | |
| 2203 | no_tx_mem: |
| 2204 | return -ENOMEM; |
| 2205 | } |
| 2206 | |
| 2207 | static void mtk_tx_clean(struct mtk_eth *eth) |
| 2208 | { |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 2209 | const struct mtk_soc_data *soc = eth->soc; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2210 | struct mtk_tx_ring *ring = ð->tx_ring; |
| 2211 | int i; |
| 2212 | |
| 2213 | if (ring->buf) { |
| 2214 | for (i = 0; i < MTK_DMA_SIZE; i++) |
developer | c4671b2 | 2021-05-28 13:16:42 +0800 | [diff] [blame] | 2215 | mtk_tx_unmap(eth, &ring->buf[i], false); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2216 | kfree(ring->buf); |
| 2217 | ring->buf = NULL; |
| 2218 | } |
| 2219 | |
| 2220 | if (!eth->soc->has_sram && ring->dma) { |
| 2221 | dma_free_coherent(eth->dev, |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 2222 | MTK_DMA_SIZE * soc->txrx.txd_size, |
| 2223 | ring->dma, ring->phys); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2224 | ring->dma = NULL; |
| 2225 | } |
| 2226 | |
| 2227 | if (ring->dma_pdma) { |
| 2228 | dma_free_coherent(eth->dev, |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 2229 | MTK_DMA_SIZE * soc->txrx.txd_size, |
| 2230 | ring->dma_pdma, ring->phys_pdma); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2231 | ring->dma_pdma = NULL; |
| 2232 | } |
| 2233 | } |
| 2234 | |
| 2235 | static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) |
| 2236 | { |
| 2237 | struct mtk_rx_ring *ring; |
| 2238 | int rx_data_len, rx_dma_size; |
| 2239 | int i; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 2240 | u64 addr64 = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2241 | |
| 2242 | if (rx_flag == MTK_RX_FLAGS_QDMA) { |
| 2243 | if (ring_no) |
| 2244 | return -EINVAL; |
| 2245 | ring = ð->rx_ring_qdma; |
| 2246 | } else { |
| 2247 | ring = ð->rx_ring[ring_no]; |
| 2248 | } |
| 2249 | |
| 2250 | if (rx_flag == MTK_RX_FLAGS_HWLRO) { |
| 2251 | rx_data_len = MTK_MAX_LRO_RX_LENGTH; |
| 2252 | rx_dma_size = MTK_HW_LRO_DMA_SIZE; |
| 2253 | } else { |
| 2254 | rx_data_len = ETH_DATA_LEN; |
| 2255 | rx_dma_size = MTK_DMA_SIZE; |
| 2256 | } |
| 2257 | |
| 2258 | ring->frag_size = mtk_max_frag_size(rx_data_len); |
| 2259 | ring->buf_size = mtk_max_buf_size(ring->frag_size); |
| 2260 | ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), |
| 2261 | GFP_KERNEL); |
| 2262 | if (!ring->data) |
| 2263 | return -ENOMEM; |
| 2264 | |
| 2265 | for (i = 0; i < rx_dma_size; i++) { |
| 2266 | ring->data[i] = netdev_alloc_frag(ring->frag_size); |
| 2267 | if (!ring->data[i]) |
| 2268 | return -ENOMEM; |
| 2269 | } |
| 2270 | |
| 2271 | if ((!eth->soc->has_sram) || (eth->soc->has_sram |
| 2272 | && (rx_flag != MTK_RX_FLAGS_NORMAL))) |
| 2273 | ring->dma = dma_alloc_coherent(eth->dev, |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 2274 | rx_dma_size * eth->soc->txrx.rxd_size, |
| 2275 | &ring->phys, GFP_KERNEL); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2276 | else { |
| 2277 | struct mtk_tx_ring *tx_ring = ð->tx_ring; |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 2278 | ring->dma = tx_ring->dma + MTK_DMA_SIZE * |
| 2279 | eth->soc->txrx.rxd_size * (ring_no + 1); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2280 | ring->phys = tx_ring->phys + MTK_DMA_SIZE * |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 2281 | eth->soc->txrx.rxd_size * (ring_no + 1); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2282 | } |
| 2283 | |
| 2284 | if (!ring->dma) |
| 2285 | return -ENOMEM; |
| 2286 | |
| 2287 | for (i = 0; i < rx_dma_size; i++) { |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 2288 | struct mtk_rx_dma_v2 *rxd; |
| 2289 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2290 | dma_addr_t dma_addr = dma_map_single(eth->dev, |
| 2291 | ring->data[i] + NET_SKB_PAD + eth->ip_align, |
| 2292 | ring->buf_size, |
| 2293 | DMA_FROM_DEVICE); |
| 2294 | if (unlikely(dma_mapping_error(eth->dev, dma_addr))) |
| 2295 | return -ENOMEM; |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 2296 | |
| 2297 | rxd = ring->dma + i * eth->soc->txrx.rxd_size; |
| 2298 | rxd->rxd1 = (unsigned int)dma_addr; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2299 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 2300 | addr64 = (MTK_HAS_CAPS(eth->soc->caps, MTK_8GB_ADDRESSING)) ? |
| 2301 | RX_DMA_SDP1(dma_addr) : 0; |
| 2302 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2303 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 2304 | rxd->rxd2 = RX_DMA_LSO; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2305 | else |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 2306 | rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size) | addr64; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2307 | |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 2308 | rxd->rxd3 = 0; |
| 2309 | rxd->rxd4 = 0; |
| 2310 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 2311 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) || |
| 2312 | MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 2313 | rxd->rxd5 = 0; |
| 2314 | rxd->rxd6 = 0; |
| 2315 | rxd->rxd7 = 0; |
| 2316 | rxd->rxd8 = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2317 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2318 | } |
| 2319 | ring->dma_size = rx_dma_size; |
| 2320 | ring->calc_idx_update = false; |
| 2321 | ring->calc_idx = rx_dma_size - 1; |
| 2322 | ring->crx_idx_reg = (rx_flag == MTK_RX_FLAGS_QDMA) ? |
| 2323 | MTK_QRX_CRX_IDX_CFG(ring_no) : |
| 2324 | MTK_PRX_CRX_IDX_CFG(ring_no); |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2325 | ring->ring_no = ring_no; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2326 | /* make sure that all changes to the dma ring are flushed before we |
| 2327 | * continue |
| 2328 | */ |
| 2329 | wmb(); |
| 2330 | |
| 2331 | if (rx_flag == MTK_RX_FLAGS_QDMA) { |
| 2332 | mtk_w32(eth, ring->phys, MTK_QRX_BASE_PTR_CFG(ring_no)); |
| 2333 | mtk_w32(eth, rx_dma_size, MTK_QRX_MAX_CNT_CFG(ring_no)); |
| 2334 | mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); |
| 2335 | mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_QDMA_RST_IDX); |
| 2336 | } else { |
| 2337 | mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no)); |
| 2338 | mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no)); |
| 2339 | mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); |
| 2340 | mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX); |
| 2341 | } |
| 2342 | |
| 2343 | return 0; |
| 2344 | } |
| 2345 | |
| 2346 | static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, int in_sram) |
| 2347 | { |
| 2348 | int i; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 2349 | u64 addr64 = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2350 | |
| 2351 | if (ring->data && ring->dma) { |
| 2352 | for (i = 0; i < ring->dma_size; i++) { |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 2353 | struct mtk_rx_dma *rxd; |
| 2354 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2355 | if (!ring->data[i]) |
| 2356 | continue; |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 2357 | |
| 2358 | rxd = ring->dma + i * eth->soc->txrx.rxd_size; |
| 2359 | if (!rxd->rxd1) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2360 | continue; |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 2361 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 2362 | addr64 = (MTK_HAS_CAPS(eth->soc->caps, |
| 2363 | MTK_8GB_ADDRESSING)) ? |
| 2364 | ((u64)(rxd->rxd2 & 0xf)) << 32 : 0; |
| 2365 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2366 | dma_unmap_single(eth->dev, |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 2367 | (u64)(rxd->rxd1 | addr64), |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2368 | ring->buf_size, |
| 2369 | DMA_FROM_DEVICE); |
| 2370 | skb_free_frag(ring->data[i]); |
| 2371 | } |
| 2372 | kfree(ring->data); |
| 2373 | ring->data = NULL; |
| 2374 | } |
| 2375 | |
| 2376 | if(in_sram) |
| 2377 | return; |
| 2378 | |
| 2379 | if (ring->dma) { |
| 2380 | dma_free_coherent(eth->dev, |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 2381 | ring->dma_size * eth->soc->txrx.rxd_size, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2382 | ring->dma, |
| 2383 | ring->phys); |
| 2384 | ring->dma = NULL; |
| 2385 | } |
| 2386 | } |
| 2387 | |
| 2388 | static int mtk_hwlro_rx_init(struct mtk_eth *eth) |
| 2389 | { |
| 2390 | int i; |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2391 | u32 val; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2392 | u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; |
| 2393 | u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; |
| 2394 | |
| 2395 | /* set LRO rings to auto-learn modes */ |
| 2396 | ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; |
| 2397 | |
| 2398 | /* validate LRO ring */ |
| 2399 | ring_ctrl_dw2 |= MTK_RING_VLD; |
| 2400 | |
| 2401 | /* set AGE timer (unit: 20us) */ |
| 2402 | ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; |
| 2403 | ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; |
| 2404 | |
| 2405 | /* set max AGG timer (unit: 20us) */ |
| 2406 | ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; |
| 2407 | |
| 2408 | /* set max LRO AGG count */ |
| 2409 | ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; |
| 2410 | ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; |
| 2411 | |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2412 | for (i = 1; i <= MTK_HW_LRO_RING_NUM; i++) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2413 | mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); |
| 2414 | mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); |
| 2415 | mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); |
| 2416 | } |
| 2417 | |
| 2418 | /* IPv4 checksum update enable */ |
| 2419 | lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; |
| 2420 | |
| 2421 | /* switch priority comparison to packet count mode */ |
| 2422 | lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; |
| 2423 | |
| 2424 | /* bandwidth threshold setting */ |
| 2425 | mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); |
| 2426 | |
| 2427 | /* auto-learn score delta setting */ |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2428 | mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_LRO_ALT_SCORE_DELTA); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2429 | |
| 2430 | /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ |
| 2431 | mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, |
| 2432 | MTK_PDMA_LRO_ALT_REFRESH_TIMER); |
| 2433 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2434 | /* the minimal remaining room of SDL0 in RXD for lro aggregation */ |
| 2435 | lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; |
| 2436 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 2437 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) || |
| 2438 | MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2439 | val = mtk_r32(eth, MTK_PDMA_RX_CFG); |
| 2440 | mtk_w32(eth, val | (MTK_PDMA_LRO_SDL << MTK_RX_CFG_SDL_OFFSET), |
| 2441 | MTK_PDMA_RX_CFG); |
| 2442 | |
| 2443 | lro_ctrl_dw0 |= MTK_PDMA_LRO_SDL << MTK_CTRL_DW0_SDL_OFFSET; |
| 2444 | } else { |
| 2445 | /* set HW LRO mode & the max aggregation count for rx packets */ |
| 2446 | lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); |
| 2447 | } |
| 2448 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2449 | /* enable HW LRO */ |
| 2450 | lro_ctrl_dw0 |= MTK_LRO_EN; |
| 2451 | |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2452 | /* enable cpu reason black list */ |
| 2453 | lro_ctrl_dw0 |= MTK_LRO_CRSN_BNW; |
| 2454 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2455 | mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); |
| 2456 | mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); |
| 2457 | |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2458 | /* no use PPE cpu reason */ |
| 2459 | mtk_w32(eth, 0xffffffff, MTK_PDMA_LRO_CTRL_DW1); |
| 2460 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2461 | return 0; |
| 2462 | } |
| 2463 | |
| 2464 | static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) |
| 2465 | { |
| 2466 | int i; |
| 2467 | u32 val; |
| 2468 | |
| 2469 | /* relinquish lro rings, flush aggregated packets */ |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2470 | mtk_w32(eth, MTK_LRO_RING_RELINGUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2471 | |
| 2472 | /* wait for relinquishments done */ |
| 2473 | for (i = 0; i < 10; i++) { |
| 2474 | val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2475 | if (val & MTK_LRO_RING_RELINGUISH_DONE) { |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 2476 | mdelay(20); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2477 | continue; |
| 2478 | } |
| 2479 | break; |
| 2480 | } |
| 2481 | |
| 2482 | /* invalidate lro rings */ |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2483 | for (i = 1; i <= MTK_HW_LRO_RING_NUM; i++) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2484 | mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); |
| 2485 | |
| 2486 | /* disable HW LRO */ |
| 2487 | mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); |
| 2488 | } |
| 2489 | |
| 2490 | static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) |
| 2491 | { |
| 2492 | u32 reg_val; |
| 2493 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 2494 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) || |
| 2495 | MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2496 | idx += 1; |
| 2497 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2498 | reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); |
| 2499 | |
| 2500 | /* invalidate the IP setting */ |
| 2501 | mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); |
| 2502 | |
| 2503 | mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); |
| 2504 | |
| 2505 | /* validate the IP setting */ |
| 2506 | mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); |
| 2507 | } |
| 2508 | |
| 2509 | static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) |
| 2510 | { |
| 2511 | u32 reg_val; |
| 2512 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 2513 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) || |
| 2514 | MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2515 | idx += 1; |
| 2516 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2517 | reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); |
| 2518 | |
| 2519 | /* invalidate the IP setting */ |
| 2520 | mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); |
| 2521 | |
| 2522 | mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); |
| 2523 | } |
| 2524 | |
| 2525 | static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) |
| 2526 | { |
| 2527 | int cnt = 0; |
| 2528 | int i; |
| 2529 | |
| 2530 | for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { |
| 2531 | if (mac->hwlro_ip[i]) |
| 2532 | cnt++; |
| 2533 | } |
| 2534 | |
| 2535 | return cnt; |
| 2536 | } |
| 2537 | |
| 2538 | static int mtk_hwlro_add_ipaddr(struct net_device *dev, |
| 2539 | struct ethtool_rxnfc *cmd) |
| 2540 | { |
| 2541 | struct ethtool_rx_flow_spec *fsp = |
| 2542 | (struct ethtool_rx_flow_spec *)&cmd->fs; |
| 2543 | struct mtk_mac *mac = netdev_priv(dev); |
| 2544 | struct mtk_eth *eth = mac->hw; |
| 2545 | int hwlro_idx; |
| 2546 | |
| 2547 | if ((fsp->flow_type != TCP_V4_FLOW) || |
| 2548 | (!fsp->h_u.tcp_ip4_spec.ip4dst) || |
| 2549 | (fsp->location > 1)) |
| 2550 | return -EINVAL; |
| 2551 | |
| 2552 | mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); |
| 2553 | hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; |
| 2554 | |
| 2555 | mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); |
| 2556 | |
| 2557 | mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); |
| 2558 | |
| 2559 | return 0; |
| 2560 | } |
| 2561 | |
| 2562 | static int mtk_hwlro_del_ipaddr(struct net_device *dev, |
| 2563 | struct ethtool_rxnfc *cmd) |
| 2564 | { |
| 2565 | struct ethtool_rx_flow_spec *fsp = |
| 2566 | (struct ethtool_rx_flow_spec *)&cmd->fs; |
| 2567 | struct mtk_mac *mac = netdev_priv(dev); |
| 2568 | struct mtk_eth *eth = mac->hw; |
| 2569 | int hwlro_idx; |
| 2570 | |
| 2571 | if (fsp->location > 1) |
| 2572 | return -EINVAL; |
| 2573 | |
| 2574 | mac->hwlro_ip[fsp->location] = 0; |
| 2575 | hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; |
| 2576 | |
| 2577 | mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); |
| 2578 | |
| 2579 | mtk_hwlro_inval_ipaddr(eth, hwlro_idx); |
| 2580 | |
| 2581 | return 0; |
| 2582 | } |
| 2583 | |
| 2584 | static void mtk_hwlro_netdev_disable(struct net_device *dev) |
| 2585 | { |
| 2586 | struct mtk_mac *mac = netdev_priv(dev); |
| 2587 | struct mtk_eth *eth = mac->hw; |
| 2588 | int i, hwlro_idx; |
| 2589 | |
| 2590 | for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { |
| 2591 | mac->hwlro_ip[i] = 0; |
| 2592 | hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; |
| 2593 | |
| 2594 | mtk_hwlro_inval_ipaddr(eth, hwlro_idx); |
| 2595 | } |
| 2596 | |
| 2597 | mac->hwlro_ip_cnt = 0; |
| 2598 | } |
| 2599 | |
| 2600 | static int mtk_hwlro_get_fdir_entry(struct net_device *dev, |
| 2601 | struct ethtool_rxnfc *cmd) |
| 2602 | { |
| 2603 | struct mtk_mac *mac = netdev_priv(dev); |
| 2604 | struct ethtool_rx_flow_spec *fsp = |
| 2605 | (struct ethtool_rx_flow_spec *)&cmd->fs; |
| 2606 | |
| 2607 | /* only tcp dst ipv4 is meaningful, others are meaningless */ |
| 2608 | fsp->flow_type = TCP_V4_FLOW; |
| 2609 | fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); |
| 2610 | fsp->m_u.tcp_ip4_spec.ip4dst = 0; |
| 2611 | |
| 2612 | fsp->h_u.tcp_ip4_spec.ip4src = 0; |
| 2613 | fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; |
| 2614 | fsp->h_u.tcp_ip4_spec.psrc = 0; |
| 2615 | fsp->m_u.tcp_ip4_spec.psrc = 0xffff; |
| 2616 | fsp->h_u.tcp_ip4_spec.pdst = 0; |
| 2617 | fsp->m_u.tcp_ip4_spec.pdst = 0xffff; |
| 2618 | fsp->h_u.tcp_ip4_spec.tos = 0; |
| 2619 | fsp->m_u.tcp_ip4_spec.tos = 0xff; |
| 2620 | |
| 2621 | return 0; |
| 2622 | } |
| 2623 | |
| 2624 | static int mtk_hwlro_get_fdir_all(struct net_device *dev, |
| 2625 | struct ethtool_rxnfc *cmd, |
| 2626 | u32 *rule_locs) |
| 2627 | { |
| 2628 | struct mtk_mac *mac = netdev_priv(dev); |
| 2629 | int cnt = 0; |
| 2630 | int i; |
| 2631 | |
| 2632 | for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { |
| 2633 | if (mac->hwlro_ip[i]) { |
| 2634 | rule_locs[cnt] = i; |
| 2635 | cnt++; |
| 2636 | } |
| 2637 | } |
| 2638 | |
| 2639 | cmd->rule_cnt = cnt; |
| 2640 | |
| 2641 | return 0; |
| 2642 | } |
| 2643 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2644 | static int mtk_rss_init(struct mtk_eth *eth) |
| 2645 | { |
| 2646 | u32 val; |
| 2647 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 2648 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2649 | /* Set RSS rings to PSE modes */ |
| 2650 | val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(1)); |
| 2651 | val |= MTK_RING_PSE_MODE; |
| 2652 | mtk_w32(eth, val, MTK_LRO_CTRL_DW2_CFG(1)); |
| 2653 | |
| 2654 | /* Enable non-lro multiple rx */ |
| 2655 | val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); |
| 2656 | val |= MTK_NON_LRO_MULTI_EN; |
| 2657 | mtk_w32(eth, val, MTK_PDMA_LRO_CTRL_DW0); |
| 2658 | |
| 2659 | /* Enable RSS dly int supoort */ |
| 2660 | val |= MTK_LRO_DLY_INT_EN; |
| 2661 | mtk_w32(eth, val, MTK_PDMA_LRO_CTRL_DW0); |
| 2662 | |
| 2663 | /* Set RSS delay config int ring1 */ |
| 2664 | mtk_w32(eth, MTK_MAX_DELAY_INT, MTK_LRO_RX1_DLY_INT); |
| 2665 | } |
| 2666 | |
| 2667 | /* Hash Type */ |
| 2668 | val = mtk_r32(eth, MTK_PDMA_RSS_GLO_CFG); |
| 2669 | val |= MTK_RSS_IPV4_STATIC_HASH; |
| 2670 | val |= MTK_RSS_IPV6_STATIC_HASH; |
| 2671 | mtk_w32(eth, val, MTK_PDMA_RSS_GLO_CFG); |
| 2672 | |
| 2673 | /* Select the size of indirection table */ |
| 2674 | mtk_w32(eth, MTK_RSS_INDR_TABLE_SIZE4, MTK_RSS_INDR_TABLE_DW0); |
| 2675 | mtk_w32(eth, MTK_RSS_INDR_TABLE_SIZE4, MTK_RSS_INDR_TABLE_DW1); |
| 2676 | mtk_w32(eth, MTK_RSS_INDR_TABLE_SIZE4, MTK_RSS_INDR_TABLE_DW2); |
| 2677 | mtk_w32(eth, MTK_RSS_INDR_TABLE_SIZE4, MTK_RSS_INDR_TABLE_DW3); |
| 2678 | mtk_w32(eth, MTK_RSS_INDR_TABLE_SIZE4, MTK_RSS_INDR_TABLE_DW4); |
| 2679 | mtk_w32(eth, MTK_RSS_INDR_TABLE_SIZE4, MTK_RSS_INDR_TABLE_DW5); |
| 2680 | mtk_w32(eth, MTK_RSS_INDR_TABLE_SIZE4, MTK_RSS_INDR_TABLE_DW6); |
| 2681 | mtk_w32(eth, MTK_RSS_INDR_TABLE_SIZE4, MTK_RSS_INDR_TABLE_DW7); |
| 2682 | |
| 2683 | /* Pause */ |
| 2684 | val |= MTK_RSS_CFG_REQ; |
| 2685 | mtk_w32(eth, val, MTK_PDMA_RSS_GLO_CFG); |
| 2686 | |
| 2687 | /* Enable RSS*/ |
| 2688 | val |= MTK_RSS_EN; |
| 2689 | mtk_w32(eth, val, MTK_PDMA_RSS_GLO_CFG); |
| 2690 | |
| 2691 | /* Release pause */ |
| 2692 | val &= ~(MTK_RSS_CFG_REQ); |
| 2693 | mtk_w32(eth, val, MTK_PDMA_RSS_GLO_CFG); |
| 2694 | |
| 2695 | /* Set perRSS GRP INT */ |
| 2696 | mtk_w32(eth, MTK_RX_DONE_INT(MTK_RSS_RING1), MTK_PDMA_INT_GRP3); |
| 2697 | |
| 2698 | /* Set GRP INT */ |
| 2699 | mtk_w32(eth, 0x21021030, MTK_FE_INT_GRP); |
| 2700 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 2701 | /* Enable RSS delay interrupt */ |
| 2702 | mtk_w32(eth, 0x8f0f8f0f, MTK_PDMA_RSS_DELAY_INT); |
| 2703 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2704 | return 0; |
| 2705 | } |
| 2706 | |
| 2707 | static void mtk_rss_uninit(struct mtk_eth *eth) |
| 2708 | { |
| 2709 | u32 val; |
| 2710 | |
| 2711 | /* Pause */ |
| 2712 | val = mtk_r32(eth, MTK_PDMA_RSS_GLO_CFG); |
| 2713 | val |= MTK_RSS_CFG_REQ; |
| 2714 | mtk_w32(eth, val, MTK_PDMA_RSS_GLO_CFG); |
| 2715 | |
| 2716 | /* Disable RSS*/ |
| 2717 | val &= ~(MTK_RSS_EN); |
| 2718 | mtk_w32(eth, val, MTK_PDMA_RSS_GLO_CFG); |
| 2719 | |
| 2720 | /* Release pause */ |
| 2721 | val &= ~(MTK_RSS_CFG_REQ); |
| 2722 | mtk_w32(eth, val, MTK_PDMA_RSS_GLO_CFG); |
| 2723 | } |
| 2724 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2725 | static netdev_features_t mtk_fix_features(struct net_device *dev, |
| 2726 | netdev_features_t features) |
| 2727 | { |
| 2728 | if (!(features & NETIF_F_LRO)) { |
| 2729 | struct mtk_mac *mac = netdev_priv(dev); |
| 2730 | int ip_cnt = mtk_hwlro_get_ip_cnt(mac); |
| 2731 | |
| 2732 | if (ip_cnt) { |
| 2733 | netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); |
| 2734 | |
| 2735 | features |= NETIF_F_LRO; |
| 2736 | } |
| 2737 | } |
| 2738 | |
| 2739 | if ((features & NETIF_F_HW_VLAN_CTAG_TX) && netdev_uses_dsa(dev)) { |
| 2740 | netdev_info(dev, "TX vlan offload cannot be enabled when dsa is attached.\n"); |
| 2741 | |
| 2742 | features &= ~NETIF_F_HW_VLAN_CTAG_TX; |
| 2743 | } |
| 2744 | |
| 2745 | return features; |
| 2746 | } |
| 2747 | |
| 2748 | static int mtk_set_features(struct net_device *dev, netdev_features_t features) |
| 2749 | { |
| 2750 | struct mtk_mac *mac = netdev_priv(dev); |
| 2751 | struct mtk_eth *eth = mac->hw; |
| 2752 | int err = 0; |
| 2753 | |
| 2754 | if (!((dev->features ^ features) & MTK_SET_FEATURES)) |
| 2755 | return 0; |
| 2756 | |
| 2757 | if (!(features & NETIF_F_LRO)) |
| 2758 | mtk_hwlro_netdev_disable(dev); |
| 2759 | |
| 2760 | if (!(features & NETIF_F_HW_VLAN_CTAG_RX)) |
| 2761 | mtk_w32(eth, 0, MTK_CDMP_EG_CTRL); |
| 2762 | else |
| 2763 | mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); |
| 2764 | |
| 2765 | return err; |
| 2766 | } |
| 2767 | |
| 2768 | /* wait for DMA to finish whatever it is doing before we start using it again */ |
| 2769 | static int mtk_dma_busy_wait(struct mtk_eth *eth) |
| 2770 | { |
| 2771 | unsigned long t_start = jiffies; |
| 2772 | |
| 2773 | while (1) { |
| 2774 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
| 2775 | if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) & |
| 2776 | (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) |
| 2777 | return 0; |
| 2778 | } else { |
| 2779 | if (!(mtk_r32(eth, MTK_PDMA_GLO_CFG) & |
| 2780 | (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) |
| 2781 | return 0; |
| 2782 | } |
| 2783 | |
| 2784 | if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT)) |
| 2785 | break; |
| 2786 | } |
| 2787 | |
| 2788 | dev_err(eth->dev, "DMA init timeout\n"); |
| 2789 | return -1; |
| 2790 | } |
| 2791 | |
| 2792 | static int mtk_dma_init(struct mtk_eth *eth) |
| 2793 | { |
| 2794 | int err; |
| 2795 | u32 i; |
| 2796 | |
| 2797 | if (mtk_dma_busy_wait(eth)) |
| 2798 | return -EBUSY; |
| 2799 | |
| 2800 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
| 2801 | /* QDMA needs scratch memory for internal reordering of the |
| 2802 | * descriptors |
| 2803 | */ |
| 2804 | err = mtk_init_fq_dma(eth); |
| 2805 | if (err) |
| 2806 | return err; |
| 2807 | } |
| 2808 | |
| 2809 | err = mtk_tx_alloc(eth); |
| 2810 | if (err) |
| 2811 | return err; |
| 2812 | |
| 2813 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
| 2814 | err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); |
| 2815 | if (err) |
| 2816 | return err; |
| 2817 | } |
| 2818 | |
| 2819 | err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); |
| 2820 | if (err) |
| 2821 | return err; |
| 2822 | |
| 2823 | if (eth->hwlro) { |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 2824 | i = (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) ? 1 : 4; |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2825 | for (; i < MTK_MAX_RX_RING_NUM; i++) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2826 | err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); |
| 2827 | if (err) |
| 2828 | return err; |
| 2829 | } |
| 2830 | err = mtk_hwlro_rx_init(eth); |
| 2831 | if (err) |
| 2832 | return err; |
| 2833 | } |
| 2834 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2835 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSS)) { |
| 2836 | for (i = 1; i < MTK_RX_NAPI_NUM; i++) { |
| 2837 | err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_NORMAL); |
| 2838 | if (err) |
| 2839 | return err; |
| 2840 | } |
| 2841 | err = mtk_rss_init(eth); |
| 2842 | if (err) |
| 2843 | return err; |
| 2844 | } |
| 2845 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2846 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
| 2847 | /* Enable random early drop and set drop threshold |
| 2848 | * automatically |
| 2849 | */ |
| 2850 | mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | |
| 2851 | FC_THRES_MIN, MTK_QDMA_FC_THRES); |
| 2852 | mtk_w32(eth, 0x0, MTK_QDMA_HRED2); |
| 2853 | } |
| 2854 | |
| 2855 | return 0; |
| 2856 | } |
| 2857 | |
| 2858 | static void mtk_dma_free(struct mtk_eth *eth) |
| 2859 | { |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 2860 | const struct mtk_soc_data *soc = eth->soc; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2861 | int i; |
| 2862 | |
| 2863 | for (i = 0; i < MTK_MAC_COUNT; i++) |
| 2864 | if (eth->netdev[i]) |
| 2865 | netdev_reset_queue(eth->netdev[i]); |
| 2866 | if ( !eth->soc->has_sram && eth->scratch_ring) { |
| 2867 | dma_free_coherent(eth->dev, |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 2868 | MTK_DMA_SIZE * soc->txrx.txd_size, |
| 2869 | eth->scratch_ring, eth->phy_scratch_ring); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2870 | eth->scratch_ring = NULL; |
| 2871 | eth->phy_scratch_ring = 0; |
| 2872 | } |
| 2873 | mtk_tx_clean(eth); |
developer | b3ce86f | 2022-06-30 13:31:47 +0800 | [diff] [blame] | 2874 | mtk_rx_clean(eth, ð->rx_ring[0],eth->soc->has_sram); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2875 | mtk_rx_clean(eth, ð->rx_ring_qdma,0); |
| 2876 | |
| 2877 | if (eth->hwlro) { |
| 2878 | mtk_hwlro_rx_uninit(eth); |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2879 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 2880 | i = (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) ? 1 : 4; |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 2881 | for (; i < MTK_MAX_RX_RING_NUM; i++) |
| 2882 | mtk_rx_clean(eth, ð->rx_ring[i], 0); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2883 | } |
| 2884 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2885 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSS)) { |
| 2886 | mtk_rss_uninit(eth); |
| 2887 | |
| 2888 | for (i = 1; i < MTK_RX_NAPI_NUM; i++) |
| 2889 | mtk_rx_clean(eth, ð->rx_ring[i], 1); |
| 2890 | } |
| 2891 | |
developer | 94008d9 | 2021-09-23 09:47:41 +0800 | [diff] [blame] | 2892 | if (eth->scratch_head) { |
| 2893 | kfree(eth->scratch_head); |
| 2894 | eth->scratch_head = NULL; |
| 2895 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2896 | } |
| 2897 | |
| 2898 | static void mtk_tx_timeout(struct net_device *dev) |
| 2899 | { |
| 2900 | struct mtk_mac *mac = netdev_priv(dev); |
| 2901 | struct mtk_eth *eth = mac->hw; |
| 2902 | |
| 2903 | eth->netdev[mac->id]->stats.tx_errors++; |
| 2904 | netif_err(eth, tx_err, dev, |
| 2905 | "transmit timed out\n"); |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 2906 | |
| 2907 | if (atomic_read(&reset_lock) == 0) |
| 2908 | schedule_work(ð->pending_work); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2909 | } |
| 2910 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2911 | static irqreturn_t mtk_handle_irq_rx(int irq, void *priv) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2912 | { |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2913 | struct mtk_napi *rx_napi = priv; |
| 2914 | struct mtk_eth *eth = rx_napi->eth; |
| 2915 | struct mtk_rx_ring *ring = rx_napi->rx_ring; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2916 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2917 | if (likely(napi_schedule_prep(&rx_napi->napi))) { |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2918 | mtk_rx_irq_disable(eth, MTK_RX_DONE_INT(ring->ring_no)); |
developer | 6bbe70d | 2021-08-06 09:34:55 +0800 | [diff] [blame] | 2919 | __napi_schedule(&rx_napi->napi); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2920 | } |
| 2921 | |
| 2922 | return IRQ_HANDLED; |
| 2923 | } |
| 2924 | |
| 2925 | static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) |
| 2926 | { |
| 2927 | struct mtk_eth *eth = _eth; |
| 2928 | |
| 2929 | if (likely(napi_schedule_prep(ð->tx_napi))) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2930 | mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); |
developer | 6bbe70d | 2021-08-06 09:34:55 +0800 | [diff] [blame] | 2931 | __napi_schedule(ð->tx_napi); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2932 | } |
| 2933 | |
| 2934 | return IRQ_HANDLED; |
| 2935 | } |
| 2936 | |
| 2937 | static irqreturn_t mtk_handle_irq(int irq, void *_eth) |
| 2938 | { |
| 2939 | struct mtk_eth *eth = _eth; |
| 2940 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2941 | if (mtk_r32(eth, MTK_PDMA_INT_MASK) & MTK_RX_DONE_INT(0)) { |
| 2942 | if (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT(0)) |
| 2943 | mtk_handle_irq_rx(irq, ð->rx_napi[0]); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2944 | } |
| 2945 | if (mtk_r32(eth, eth->tx_int_mask_reg) & MTK_TX_DONE_INT) { |
| 2946 | if (mtk_r32(eth, eth->tx_int_status_reg) & MTK_TX_DONE_INT) |
| 2947 | mtk_handle_irq_tx(irq, _eth); |
| 2948 | } |
| 2949 | |
| 2950 | return IRQ_HANDLED; |
| 2951 | } |
| 2952 | |
developer | a2613e6 | 2022-07-01 18:29:37 +0800 | [diff] [blame] | 2953 | static irqreturn_t mtk_handle_irq_fixed_link(int irq, void *_mac) |
| 2954 | { |
| 2955 | struct mtk_mac *mac = _mac; |
| 2956 | struct mtk_eth *eth = mac->hw; |
| 2957 | struct mtk_phylink_priv *phylink_priv = &mac->phylink_priv; |
| 2958 | struct net_device *dev = phylink_priv->dev; |
| 2959 | int link_old, link_new; |
| 2960 | |
| 2961 | // clear interrupt status for gpy211 |
| 2962 | _mtk_mdio_read(eth, phylink_priv->phyaddr, 0x1A); |
| 2963 | |
| 2964 | link_old = phylink_priv->link; |
| 2965 | link_new = _mtk_mdio_read(eth, phylink_priv->phyaddr, MII_BMSR) & BMSR_LSTATUS; |
| 2966 | |
| 2967 | if (link_old != link_new) { |
| 2968 | phylink_priv->link = link_new; |
| 2969 | if (link_new) { |
| 2970 | printk("phylink.%d %s: Link is Up\n", phylink_priv->id, dev->name); |
| 2971 | if (dev) |
| 2972 | netif_carrier_on(dev); |
| 2973 | } else { |
| 2974 | printk("phylink.%d %s: Link is Down\n", phylink_priv->id, dev->name); |
| 2975 | if (dev) |
| 2976 | netif_carrier_off(dev); |
| 2977 | } |
| 2978 | } |
| 2979 | |
| 2980 | return IRQ_HANDLED; |
| 2981 | } |
| 2982 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2983 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 2984 | static void mtk_poll_controller(struct net_device *dev) |
| 2985 | { |
| 2986 | struct mtk_mac *mac = netdev_priv(dev); |
| 2987 | struct mtk_eth *eth = mac->hw; |
| 2988 | |
| 2989 | mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2990 | mtk_rx_irq_disable(eth, MTK_RX_DONE_INT(0)); |
| 2991 | mtk_handle_irq_rx(eth->irq[2], ð->rx_napi[0]); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2992 | mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 2993 | mtk_rx_irq_enable(eth, MTK_RX_DONE_INT(0)); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 2994 | } |
| 2995 | #endif |
| 2996 | |
| 2997 | static int mtk_start_dma(struct mtk_eth *eth) |
| 2998 | { |
| 2999 | u32 rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 3000 | int val, err; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3001 | |
| 3002 | err = mtk_dma_init(eth); |
| 3003 | if (err) { |
| 3004 | mtk_dma_free(eth); |
| 3005 | return err; |
| 3006 | } |
| 3007 | |
| 3008 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
developer | 15d0d28 | 2021-07-14 16:40:44 +0800 | [diff] [blame] | 3009 | val = mtk_r32(eth, MTK_QDMA_GLO_CFG); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 3010 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) || |
| 3011 | MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { |
developer | 19d8456 | 2022-04-21 17:01:06 +0800 | [diff] [blame] | 3012 | val &= ~MTK_RESV_BUF_MASK; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3013 | mtk_w32(eth, |
developer | 15d0d28 | 2021-07-14 16:40:44 +0800 | [diff] [blame] | 3014 | val | MTK_TX_DMA_EN | MTK_RX_DMA_EN | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3015 | MTK_DMA_SIZE_32DWORDS | MTK_TX_WB_DDONE | |
| 3016 | MTK_NDP_CO_PRO | MTK_MUTLI_CNT | |
| 3017 | MTK_RESV_BUF | MTK_WCOMP_EN | |
| 3018 | MTK_DMAD_WR_WDONE | MTK_CHK_DDONE_EN | |
developer | 1ac6593 | 2022-07-19 17:23:32 +0800 | [diff] [blame] | 3019 | MTK_RX_2B_OFFSET, MTK_QDMA_GLO_CFG); |
developer | 19d8456 | 2022-04-21 17:01:06 +0800 | [diff] [blame] | 3020 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3021 | else |
| 3022 | mtk_w32(eth, |
developer | 15d0d28 | 2021-07-14 16:40:44 +0800 | [diff] [blame] | 3023 | val | MTK_TX_DMA_EN | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3024 | MTK_DMA_SIZE_32DWORDS | MTK_NDP_CO_PRO | |
| 3025 | MTK_RX_DMA_EN | MTK_RX_2B_OFFSET | |
| 3026 | MTK_RX_BT_32DWORDS, |
| 3027 | MTK_QDMA_GLO_CFG); |
| 3028 | |
developer | 15d0d28 | 2021-07-14 16:40:44 +0800 | [diff] [blame] | 3029 | val = mtk_r32(eth, MTK_PDMA_GLO_CFG); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3030 | mtk_w32(eth, |
developer | 15d0d28 | 2021-07-14 16:40:44 +0800 | [diff] [blame] | 3031 | val | MTK_RX_DMA_EN | rx_2b_offset | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3032 | MTK_RX_BT_32DWORDS | MTK_MULTI_EN, |
| 3033 | MTK_PDMA_GLO_CFG); |
| 3034 | } else { |
| 3035 | mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | |
| 3036 | MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS, |
| 3037 | MTK_PDMA_GLO_CFG); |
| 3038 | } |
| 3039 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 3040 | if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1) && eth->hwlro) { |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 3041 | val = mtk_r32(eth, MTK_PDMA_GLO_CFG); |
| 3042 | mtk_w32(eth, val | MTK_RX_DMA_LRO_EN, MTK_PDMA_GLO_CFG); |
| 3043 | } |
| 3044 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3045 | return 0; |
| 3046 | } |
| 3047 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3048 | void mtk_gdm_config(struct mtk_eth *eth, u32 config) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3049 | { |
| 3050 | int i; |
| 3051 | |
| 3052 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) |
| 3053 | return; |
| 3054 | |
| 3055 | for (i = 0; i < MTK_MAC_COUNT; i++) { |
| 3056 | u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); |
| 3057 | |
| 3058 | /* default setup the forward port to send frame to PDMA */ |
| 3059 | val &= ~0xffff; |
| 3060 | |
| 3061 | /* Enable RX checksum */ |
| 3062 | val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; |
| 3063 | |
| 3064 | val |= config; |
| 3065 | |
| 3066 | if (eth->netdev[i] && netdev_uses_dsa(eth->netdev[i])) |
| 3067 | val |= MTK_GDMA_SPECIAL_TAG; |
| 3068 | |
| 3069 | mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); |
| 3070 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3071 | } |
| 3072 | |
developer | 7cd7e5e | 2022-11-17 13:57:32 +0800 | [diff] [blame] | 3073 | void mtk_set_pse_drop(u32 config) |
| 3074 | { |
| 3075 | struct mtk_eth *eth = g_eth; |
| 3076 | |
| 3077 | if (eth) |
| 3078 | mtk_w32(eth, config, PSE_PPE0_DROP); |
| 3079 | } |
| 3080 | EXPORT_SYMBOL(mtk_set_pse_drop); |
| 3081 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3082 | static int mtk_open(struct net_device *dev) |
| 3083 | { |
| 3084 | struct mtk_mac *mac = netdev_priv(dev); |
| 3085 | struct mtk_eth *eth = mac->hw; |
developer | a2613e6 | 2022-07-01 18:29:37 +0800 | [diff] [blame] | 3086 | struct mtk_phylink_priv *phylink_priv = &mac->phylink_priv; |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 3087 | int err, i; |
developer | 3a5969e | 2022-02-09 15:36:36 +0800 | [diff] [blame] | 3088 | struct device_node *phy_node; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3089 | |
| 3090 | err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); |
| 3091 | if (err) { |
| 3092 | netdev_err(dev, "%s: could not attach PHY: %d\n", __func__, |
| 3093 | err); |
| 3094 | return err; |
| 3095 | } |
| 3096 | |
| 3097 | /* we run 2 netdevs on the same dma ring so we only bring it up once */ |
| 3098 | if (!refcount_read(ð->dma_refcnt)) { |
| 3099 | int err = mtk_start_dma(eth); |
| 3100 | |
| 3101 | if (err) |
| 3102 | return err; |
| 3103 | |
| 3104 | mtk_gdm_config(eth, MTK_GDMA_TO_PDMA); |
| 3105 | |
| 3106 | /* Indicates CDM to parse the MTK special tag from CPU */ |
| 3107 | if (netdev_uses_dsa(dev)) { |
| 3108 | u32 val; |
| 3109 | val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); |
| 3110 | mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); |
| 3111 | val = mtk_r32(eth, MTK_CDMP_IG_CTRL); |
| 3112 | mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL); |
| 3113 | } |
| 3114 | |
| 3115 | napi_enable(ð->tx_napi); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 3116 | napi_enable(ð->rx_napi[0].napi); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3117 | mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 3118 | mtk_rx_irq_enable(eth, MTK_RX_DONE_INT(0)); |
| 3119 | |
| 3120 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSS)) { |
| 3121 | for (i = 1; i < MTK_RX_NAPI_NUM; i++) { |
| 3122 | napi_enable(ð->rx_napi[i].napi); |
| 3123 | mtk_rx_irq_enable(eth, MTK_RX_DONE_INT(i)); |
| 3124 | } |
| 3125 | } |
| 3126 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3127 | refcount_set(ð->dma_refcnt, 1); |
| 3128 | } |
| 3129 | else |
| 3130 | refcount_inc(ð->dma_refcnt); |
| 3131 | |
developer | a2613e6 | 2022-07-01 18:29:37 +0800 | [diff] [blame] | 3132 | if (phylink_priv->desc) { |
| 3133 | /*Notice: This programming sequence is only for GPY211 single PHY chip. |
| 3134 | If single PHY chip is not GPY211, the following step you should do: |
| 3135 | 1. Contact your Single PHY chip vendor and get the details of |
| 3136 | - how to enables link status change interrupt |
| 3137 | - how to clears interrupt source |
| 3138 | */ |
| 3139 | |
| 3140 | // clear interrupt source for gpy211 |
| 3141 | _mtk_mdio_read(eth, phylink_priv->phyaddr, 0x1A); |
| 3142 | |
| 3143 | // enable link status change interrupt for gpy211 |
| 3144 | _mtk_mdio_write(eth, phylink_priv->phyaddr, 0x19, 0x0001); |
| 3145 | |
| 3146 | phylink_priv->dev = dev; |
| 3147 | |
| 3148 | // override dev pointer for single PHY chip 0 |
| 3149 | if (phylink_priv->id == 0) { |
| 3150 | struct net_device *tmp; |
| 3151 | |
| 3152 | tmp = __dev_get_by_name(&init_net, phylink_priv->label); |
| 3153 | if (tmp) |
| 3154 | phylink_priv->dev = tmp; |
| 3155 | else |
| 3156 | phylink_priv->dev = NULL; |
| 3157 | } |
| 3158 | } |
| 3159 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3160 | phylink_start(mac->phylink); |
| 3161 | netif_start_queue(dev); |
developer | 3a5969e | 2022-02-09 15:36:36 +0800 | [diff] [blame] | 3162 | phy_node = of_parse_phandle(mac->of_node, "phy-handle", 0); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 3163 | if (!phy_node && eth->xgmii->regmap_sgmii[mac->id]) |
| 3164 | regmap_write(eth->xgmii->regmap_sgmii[mac->id], SGMSYS_QPHY_PWR_STATE_CTRL, 0); |
| 3165 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3166 | return 0; |
| 3167 | } |
| 3168 | |
| 3169 | static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) |
| 3170 | { |
| 3171 | u32 val; |
| 3172 | int i; |
| 3173 | |
| 3174 | /* stop the dma engine */ |
| 3175 | spin_lock_bh(ð->page_lock); |
| 3176 | val = mtk_r32(eth, glo_cfg); |
| 3177 | mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), |
| 3178 | glo_cfg); |
| 3179 | spin_unlock_bh(ð->page_lock); |
| 3180 | |
| 3181 | /* wait for dma stop */ |
| 3182 | for (i = 0; i < 10; i++) { |
| 3183 | val = mtk_r32(eth, glo_cfg); |
| 3184 | if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3185 | mdelay(20); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3186 | continue; |
| 3187 | } |
| 3188 | break; |
| 3189 | } |
| 3190 | } |
| 3191 | |
| 3192 | static int mtk_stop(struct net_device *dev) |
| 3193 | { |
| 3194 | struct mtk_mac *mac = netdev_priv(dev); |
| 3195 | struct mtk_eth *eth = mac->hw; |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 3196 | int i; |
developer | 3a5969e | 2022-02-09 15:36:36 +0800 | [diff] [blame] | 3197 | u32 val = 0; |
| 3198 | struct device_node *phy_node; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3199 | |
| 3200 | netif_tx_disable(dev); |
| 3201 | |
developer | 3a5969e | 2022-02-09 15:36:36 +0800 | [diff] [blame] | 3202 | phy_node = of_parse_phandle(mac->of_node, "phy-handle", 0); |
| 3203 | if (phy_node) { |
| 3204 | val = _mtk_mdio_read(eth, 0, 0); |
| 3205 | val |= BMCR_PDOWN; |
| 3206 | _mtk_mdio_write(eth, 0, 0, val); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 3207 | } else if (eth->xgmii->regmap_sgmii[mac->id]) { |
| 3208 | regmap_read(eth->xgmii->regmap_sgmii[mac->id], SGMSYS_QPHY_PWR_STATE_CTRL, &val); |
developer | 3a5969e | 2022-02-09 15:36:36 +0800 | [diff] [blame] | 3209 | val |= SGMII_PHYA_PWD; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 3210 | regmap_write(eth->xgmii->regmap_sgmii[mac->id], SGMSYS_QPHY_PWR_STATE_CTRL, val); |
developer | 3a5969e | 2022-02-09 15:36:36 +0800 | [diff] [blame] | 3211 | } |
| 3212 | |
| 3213 | //GMAC RX disable |
| 3214 | val = mtk_r32(eth, MTK_MAC_MCR(mac->id)); |
| 3215 | mtk_w32(eth, val & ~(MAC_MCR_RX_EN), MTK_MAC_MCR(mac->id)); |
| 3216 | |
| 3217 | phylink_stop(mac->phylink); |
| 3218 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3219 | phylink_disconnect_phy(mac->phylink); |
| 3220 | |
| 3221 | /* only shutdown DMA if this is the last user */ |
| 3222 | if (!refcount_dec_and_test(ð->dma_refcnt)) |
| 3223 | return 0; |
| 3224 | |
| 3225 | mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); |
| 3226 | |
| 3227 | mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 3228 | mtk_rx_irq_disable(eth, MTK_RX_DONE_INT(0)); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3229 | napi_disable(ð->tx_napi); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 3230 | napi_disable(ð->rx_napi[0].napi); |
| 3231 | |
| 3232 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSS)) { |
| 3233 | for (i = 1; i < MTK_RX_NAPI_NUM; i++) { |
| 3234 | mtk_rx_irq_disable(eth, MTK_RX_DONE_INT(i)); |
| 3235 | napi_disable(ð->rx_napi[i].napi); |
| 3236 | } |
| 3237 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3238 | |
| 3239 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) |
| 3240 | mtk_stop_dma(eth, MTK_QDMA_GLO_CFG); |
| 3241 | mtk_stop_dma(eth, MTK_PDMA_GLO_CFG); |
| 3242 | |
| 3243 | mtk_dma_free(eth); |
| 3244 | |
| 3245 | return 0; |
| 3246 | } |
| 3247 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3248 | void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3249 | { |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3250 | u32 val = 0, i = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3251 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3252 | regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3253 | reset_bits, reset_bits); |
| 3254 | |
| 3255 | while (i++ < 5000) { |
| 3256 | mdelay(1); |
| 3257 | regmap_read(eth->ethsys, ETHSYS_RSTCTRL, &val); |
| 3258 | |
| 3259 | if ((val & reset_bits) == reset_bits) { |
| 3260 | mtk_reset_event_update(eth, MTK_EVENT_COLD_CNT); |
| 3261 | regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, |
| 3262 | reset_bits, ~reset_bits); |
| 3263 | break; |
| 3264 | } |
| 3265 | } |
| 3266 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3267 | mdelay(10); |
| 3268 | } |
| 3269 | |
| 3270 | static void mtk_clk_disable(struct mtk_eth *eth) |
| 3271 | { |
| 3272 | int clk; |
| 3273 | |
| 3274 | for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) |
| 3275 | clk_disable_unprepare(eth->clks[clk]); |
| 3276 | } |
| 3277 | |
| 3278 | static int mtk_clk_enable(struct mtk_eth *eth) |
| 3279 | { |
| 3280 | int clk, ret; |
| 3281 | |
| 3282 | for (clk = 0; clk < MTK_CLK_MAX ; clk++) { |
| 3283 | ret = clk_prepare_enable(eth->clks[clk]); |
| 3284 | if (ret) |
| 3285 | goto err_disable_clks; |
| 3286 | } |
| 3287 | |
| 3288 | return 0; |
| 3289 | |
| 3290 | err_disable_clks: |
| 3291 | while (--clk >= 0) |
| 3292 | clk_disable_unprepare(eth->clks[clk]); |
| 3293 | |
| 3294 | return ret; |
| 3295 | } |
| 3296 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 3297 | static int mtk_napi_init(struct mtk_eth *eth) |
| 3298 | { |
| 3299 | struct mtk_napi *rx_napi = ð->rx_napi[0]; |
| 3300 | int i; |
| 3301 | |
| 3302 | rx_napi->eth = eth; |
| 3303 | rx_napi->rx_ring = ð->rx_ring[0]; |
| 3304 | rx_napi->irq_grp_no = 2; |
| 3305 | |
| 3306 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSS)) { |
| 3307 | for (i = 1; i < MTK_RX_NAPI_NUM; i++) { |
| 3308 | rx_napi = ð->rx_napi[i]; |
| 3309 | rx_napi->eth = eth; |
| 3310 | rx_napi->rx_ring = ð->rx_ring[i]; |
| 3311 | rx_napi->irq_grp_no = 2 + i; |
| 3312 | } |
| 3313 | } |
| 3314 | |
| 3315 | return 0; |
| 3316 | } |
| 3317 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3318 | static int mtk_hw_init(struct mtk_eth *eth, u32 type) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3319 | { |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3320 | int i, ret = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3321 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3322 | pr_info("[%s] reset_lock:%d, force:%d\n", __func__, |
| 3323 | atomic_read(&reset_lock), atomic_read(&force)); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3324 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3325 | if (atomic_read(&reset_lock) == 0) { |
| 3326 | if (test_and_set_bit(MTK_HW_INIT, ð->state)) |
| 3327 | return 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3328 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3329 | pm_runtime_enable(eth->dev); |
| 3330 | pm_runtime_get_sync(eth->dev); |
| 3331 | |
| 3332 | ret = mtk_clk_enable(eth); |
| 3333 | if (ret) |
| 3334 | goto err_disable_pm; |
| 3335 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3336 | |
| 3337 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { |
| 3338 | ret = device_reset(eth->dev); |
| 3339 | if (ret) { |
| 3340 | dev_err(eth->dev, "MAC reset failed!\n"); |
| 3341 | goto err_disable_pm; |
| 3342 | } |
| 3343 | |
| 3344 | /* enable interrupt delay for RX */ |
| 3345 | mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT); |
| 3346 | |
| 3347 | /* disable delay and normal interrupt */ |
| 3348 | mtk_tx_irq_disable(eth, ~0); |
| 3349 | mtk_rx_irq_disable(eth, ~0); |
| 3350 | |
| 3351 | return 0; |
| 3352 | } |
| 3353 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3354 | pr_info("[%s] execute fe %s reset\n", __func__, |
| 3355 | (type == MTK_TYPE_WARM_RESET) ? "warm" : "cold"); |
developer | 545abf0 | 2021-07-15 17:47:01 +0800 | [diff] [blame] | 3356 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3357 | if (type == MTK_TYPE_WARM_RESET) |
| 3358 | mtk_eth_warm_reset(eth); |
developer | 545abf0 | 2021-07-15 17:47:01 +0800 | [diff] [blame] | 3359 | else |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3360 | mtk_eth_cold_reset(eth); |
developer | 545abf0 | 2021-07-15 17:47:01 +0800 | [diff] [blame] | 3361 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 3362 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) || |
| 3363 | MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { |
developer | 545abf0 | 2021-07-15 17:47:01 +0800 | [diff] [blame] | 3364 | /* Set FE to PDMAv2 if necessary */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3365 | mtk_w32(eth, mtk_r32(eth, MTK_FE_GLO_MISC) | MTK_PDMA_V2, MTK_FE_GLO_MISC); |
developer | 545abf0 | 2021-07-15 17:47:01 +0800 | [diff] [blame] | 3366 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3367 | |
| 3368 | if (eth->pctl) { |
| 3369 | /* Set GE2 driving and slew rate */ |
| 3370 | regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); |
| 3371 | |
| 3372 | /* set GE2 TDSEL */ |
| 3373 | regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); |
| 3374 | |
| 3375 | /* set GE2 TUNE */ |
| 3376 | regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); |
| 3377 | } |
| 3378 | |
| 3379 | /* Set linkdown as the default for each GMAC. Its own MCR would be set |
| 3380 | * up with the more appropriate value when mtk_mac_config call is being |
| 3381 | * invoked. |
| 3382 | */ |
| 3383 | for (i = 0; i < MTK_MAC_COUNT; i++) |
| 3384 | mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); |
| 3385 | |
| 3386 | /* Enable RX VLan Offloading */ |
developer | 41294e3 | 2021-05-07 16:11:23 +0800 | [diff] [blame] | 3387 | if (eth->soc->hw_features & NETIF_F_HW_VLAN_CTAG_RX) |
| 3388 | mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); |
| 3389 | else |
| 3390 | mtk_w32(eth, 0, MTK_CDMP_EG_CTRL); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3391 | |
| 3392 | /* enable interrupt delay for RX/TX */ |
| 3393 | mtk_w32(eth, 0x8f0f8f0f, MTK_PDMA_DELAY_INT); |
| 3394 | mtk_w32(eth, 0x8f0f8f0f, MTK_QDMA_DELAY_INT); |
| 3395 | |
| 3396 | mtk_tx_irq_disable(eth, ~0); |
| 3397 | mtk_rx_irq_disable(eth, ~0); |
| 3398 | |
| 3399 | /* FE int grouping */ |
| 3400 | mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 3401 | mtk_w32(eth, MTK_RX_DONE_INT(0), MTK_PDMA_INT_GRP2); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3402 | mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 3403 | mtk_w32(eth, MTK_RX_DONE_INT(0), MTK_QDMA_INT_GRP2); |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3404 | mtk_w32(eth, 0x21021003, MTK_FE_INT_GRP); |
developer | be97172 | 2022-05-23 13:51:05 +0800 | [diff] [blame] | 3405 | mtk_w32(eth, MTK_FE_INT_TSO_FAIL | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3406 | MTK_FE_INT_TSO_ILLEGAL | MTK_FE_INT_TSO_ALIGN | |
| 3407 | MTK_FE_INT_RFIFO_OV | MTK_FE_INT_RFIFO_UF, MTK_FE_INT_ENABLE); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3408 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 3409 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { |
| 3410 | /* PSE should not drop port1, port8 and port9 packets */ |
| 3411 | mtk_w32(eth, 0x00000302, PSE_NO_DROP_CFG); |
| 3412 | |
developer | 15f760a | 2022-10-12 15:57:21 +0800 | [diff] [blame] | 3413 | /* PSE should drop p8 and p9 packets when WDMA Rx ring full*/ |
| 3414 | mtk_w32(eth, 0x00000300, PSE_PPE0_DROP); |
| 3415 | |
developer | 84d1e83 | 2022-11-24 11:25:05 +0800 | [diff] [blame] | 3416 | /* PSE free buffer drop threshold */ |
| 3417 | mtk_w32(eth, 0x00600009, PSE_IQ_REV(8)); |
| 3418 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 3419 | /* GDM and CDM Threshold */ |
| 3420 | mtk_w32(eth, 0x00000707, MTK_CDMW0_THRES); |
| 3421 | mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES); |
| 3422 | |
| 3423 | /* PSE GDM3 MIB counter has incorrect hw default values, |
| 3424 | * so the driver ought to read clear the values beforehand |
| 3425 | * in case ethtool retrieve wrong mib values. |
| 3426 | */ |
| 3427 | for (i = 0; i < MTK_STAT_OFFSET; i += 0x4) |
| 3428 | mtk_r32(eth, |
| 3429 | MTK_GDM1_TX_GBCNT + MTK_STAT_OFFSET * 2 + i); |
| 3430 | } else if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { |
developer | fef9efd | 2021-06-16 18:28:09 +0800 | [diff] [blame] | 3431 | /* PSE Free Queue Flow Control */ |
| 3432 | mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2); |
| 3433 | |
developer | 459b78e | 2022-07-01 17:25:10 +0800 | [diff] [blame] | 3434 | /* PSE should not drop port8 and port9 packets from WDMA Tx */ |
| 3435 | mtk_w32(eth, 0x00000300, PSE_NO_DROP_CFG); |
| 3436 | |
| 3437 | /* PSE should drop p8 and p9 packets when WDMA Rx ring full*/ |
| 3438 | mtk_w32(eth, 0x00000300, PSE_PPE0_DROP); |
developer | 81bcad3 | 2021-07-15 14:14:38 +0800 | [diff] [blame] | 3439 | |
developer | fef9efd | 2021-06-16 18:28:09 +0800 | [diff] [blame] | 3440 | /* PSE config input queue threshold */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3441 | mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1)); |
| 3442 | mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2)); |
| 3443 | mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3)); |
| 3444 | mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4)); |
| 3445 | mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5)); |
| 3446 | mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6)); |
| 3447 | mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7)); |
developer | fd5f915 | 2022-01-05 16:29:42 +0800 | [diff] [blame] | 3448 | mtk_w32(eth, 0x002a000e, PSE_IQ_REV(8)); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3449 | |
developer | fef9efd | 2021-06-16 18:28:09 +0800 | [diff] [blame] | 3450 | /* PSE config output queue threshold */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3451 | mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1)); |
| 3452 | mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2)); |
| 3453 | mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3)); |
| 3454 | mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4)); |
| 3455 | mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5)); |
| 3456 | mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6)); |
| 3457 | mtk_w32(eth, 0x00060006, PSE_OQ_TH(7)); |
| 3458 | mtk_w32(eth, 0x00060006, PSE_OQ_TH(8)); |
developer | fef9efd | 2021-06-16 18:28:09 +0800 | [diff] [blame] | 3459 | |
| 3460 | /* GDM and CDM Threshold */ |
| 3461 | mtk_w32(eth, 0x00000004, MTK_GDM2_THRES); |
| 3462 | mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES); |
| 3463 | mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES); |
| 3464 | mtk_w32(eth, 0x00000004, MTK_CDME0_THRES); |
| 3465 | mtk_w32(eth, 0x00000004, MTK_CDME1_THRES); |
| 3466 | mtk_w32(eth, 0x00000004, MTK_CDMM_THRES); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3467 | } |
| 3468 | |
| 3469 | return 0; |
| 3470 | |
| 3471 | err_disable_pm: |
| 3472 | pm_runtime_put_sync(eth->dev); |
| 3473 | pm_runtime_disable(eth->dev); |
| 3474 | |
| 3475 | return ret; |
| 3476 | } |
| 3477 | |
| 3478 | static int mtk_hw_deinit(struct mtk_eth *eth) |
| 3479 | { |
| 3480 | if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) |
| 3481 | return 0; |
| 3482 | |
| 3483 | mtk_clk_disable(eth); |
| 3484 | |
| 3485 | pm_runtime_put_sync(eth->dev); |
| 3486 | pm_runtime_disable(eth->dev); |
| 3487 | |
| 3488 | return 0; |
| 3489 | } |
| 3490 | |
| 3491 | static int __init mtk_init(struct net_device *dev) |
| 3492 | { |
| 3493 | struct mtk_mac *mac = netdev_priv(dev); |
| 3494 | struct mtk_eth *eth = mac->hw; |
| 3495 | const char *mac_addr; |
| 3496 | |
| 3497 | mac_addr = of_get_mac_address(mac->of_node); |
| 3498 | if (!IS_ERR(mac_addr)) |
| 3499 | ether_addr_copy(dev->dev_addr, mac_addr); |
| 3500 | |
| 3501 | /* If the mac address is invalid, use random mac address */ |
| 3502 | if (!is_valid_ether_addr(dev->dev_addr)) { |
| 3503 | eth_hw_addr_random(dev); |
| 3504 | dev_err(eth->dev, "generated random MAC address %pM\n", |
| 3505 | dev->dev_addr); |
| 3506 | } |
| 3507 | |
| 3508 | return 0; |
| 3509 | } |
| 3510 | |
| 3511 | static void mtk_uninit(struct net_device *dev) |
| 3512 | { |
| 3513 | struct mtk_mac *mac = netdev_priv(dev); |
| 3514 | struct mtk_eth *eth = mac->hw; |
| 3515 | |
| 3516 | phylink_disconnect_phy(mac->phylink); |
| 3517 | mtk_tx_irq_disable(eth, ~0); |
| 3518 | mtk_rx_irq_disable(eth, ~0); |
| 3519 | } |
| 3520 | |
| 3521 | static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
| 3522 | { |
| 3523 | struct mtk_mac *mac = netdev_priv(dev); |
| 3524 | |
| 3525 | switch (cmd) { |
| 3526 | case SIOCGMIIPHY: |
| 3527 | case SIOCGMIIREG: |
| 3528 | case SIOCSMIIREG: |
| 3529 | return phylink_mii_ioctl(mac->phylink, ifr, cmd); |
| 3530 | default: |
| 3531 | /* default invoke the mtk_eth_dbg handler */ |
| 3532 | return mtk_do_priv_ioctl(dev, ifr, cmd); |
| 3533 | break; |
| 3534 | } |
| 3535 | |
| 3536 | return -EOPNOTSUPP; |
| 3537 | } |
| 3538 | |
| 3539 | static void mtk_pending_work(struct work_struct *work) |
| 3540 | { |
| 3541 | struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3542 | struct device_node *phy_node = NULL; |
| 3543 | struct mtk_mac *mac = NULL; |
| 3544 | int err, i = 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3545 | unsigned long restart = 0; |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3546 | u32 val = 0; |
| 3547 | |
| 3548 | atomic_inc(&reset_lock); |
| 3549 | val = mtk_r32(eth, MTK_FE_INT_STATUS); |
| 3550 | if (!mtk_check_reset_event(eth, val)) { |
| 3551 | atomic_dec(&reset_lock); |
| 3552 | pr_info("[%s] No need to do FE reset !\n", __func__); |
| 3553 | return; |
| 3554 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3555 | |
| 3556 | rtnl_lock(); |
| 3557 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3558 | /* Disabe FE P3 and P4 */ |
| 3559 | val = mtk_r32(eth, MTK_FE_GLO_CFG); |
| 3560 | val |= MTK_FE_LINK_DOWN_P3; |
| 3561 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) |
| 3562 | val |= MTK_FE_LINK_DOWN_P4; |
| 3563 | mtk_w32(eth, val, MTK_FE_GLO_CFG); |
| 3564 | |
| 3565 | /* Adjust PPE configurations to prepare for reset */ |
| 3566 | mtk_prepare_reset_ppe(eth, 0); |
| 3567 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) |
| 3568 | mtk_prepare_reset_ppe(eth, 1); |
| 3569 | |
| 3570 | /* Adjust FE configurations to prepare for reset */ |
| 3571 | mtk_prepare_reset_fe(eth); |
| 3572 | |
| 3573 | /* Trigger Wifi SER reset */ |
developer | 6bb3f3a | 2022-11-22 09:59:14 +0800 | [diff] [blame] | 3574 | for (i = 0; i < MTK_MAC_COUNT; i++) { |
| 3575 | if (!eth->netdev[i]) |
| 3576 | continue; |
| 3577 | call_netdevice_notifiers(MTK_FE_START_RESET, eth->netdev[i]); |
| 3578 | rtnl_unlock(); |
developer | 543e792 | 2022-12-01 11:24:47 +0800 | [diff] [blame^] | 3579 | if (!wait_for_completion_timeout(&wait_ser_done, 5000)) |
| 3580 | pr_warn("[%s] wait for MTK_FE_START_RESET failed\n", |
| 3581 | __func__); |
developer | 6bb3f3a | 2022-11-22 09:59:14 +0800 | [diff] [blame] | 3582 | rtnl_lock(); |
| 3583 | break; |
| 3584 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3585 | |
| 3586 | while (test_and_set_bit_lock(MTK_RESETTING, ð->state)) |
| 3587 | cpu_relax(); |
| 3588 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3589 | del_timer_sync(ð->mtk_dma_monitor_timer); |
| 3590 | pr_info("[%s] mtk_stop starts !\n", __func__); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3591 | /* stop all devices to make sure that dma is properly shut down */ |
| 3592 | for (i = 0; i < MTK_MAC_COUNT; i++) { |
| 3593 | if (!eth->netdev[i]) |
| 3594 | continue; |
| 3595 | mtk_stop(eth->netdev[i]); |
| 3596 | __set_bit(i, &restart); |
| 3597 | } |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3598 | pr_info("[%s] mtk_stop ends !\n", __func__); |
| 3599 | mdelay(15); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3600 | |
| 3601 | if (eth->dev->pins) |
| 3602 | pinctrl_select_state(eth->dev->pins->p, |
| 3603 | eth->dev->pins->default_state); |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3604 | |
| 3605 | pr_info("[%s] mtk_hw_init starts !\n", __func__); |
| 3606 | mtk_hw_init(eth, MTK_TYPE_WARM_RESET); |
| 3607 | pr_info("[%s] mtk_hw_init ends !\n", __func__); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3608 | |
| 3609 | /* restart DMA and enable IRQs */ |
| 3610 | for (i = 0; i < MTK_MAC_COUNT; i++) { |
developer | 6bb3f3a | 2022-11-22 09:59:14 +0800 | [diff] [blame] | 3611 | if (!test_bit(i, &restart) || !eth->netdev[i]) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3612 | continue; |
| 3613 | err = mtk_open(eth->netdev[i]); |
| 3614 | if (err) { |
| 3615 | netif_alert(eth, ifup, eth->netdev[i], |
| 3616 | "Driver up/down cycle failed, closing device.\n"); |
| 3617 | dev_close(eth->netdev[i]); |
| 3618 | } |
| 3619 | } |
| 3620 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3621 | /* Set KA tick select */ |
| 3622 | mtk_m32(eth, MTK_PPE_TICK_SEL_MASK, 0, MTK_PPE_TB_CFG(0)); |
| 3623 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) |
| 3624 | mtk_m32(eth, MTK_PPE_TICK_SEL_MASK, 0, MTK_PPE_TB_CFG(1)); |
| 3625 | |
| 3626 | /* Enabe FE P3 and P4*/ |
| 3627 | val = mtk_r32(eth, MTK_FE_GLO_CFG); |
| 3628 | val &= ~MTK_FE_LINK_DOWN_P3; |
| 3629 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) |
| 3630 | val &= ~MTK_FE_LINK_DOWN_P4; |
| 3631 | mtk_w32(eth, val, MTK_FE_GLO_CFG); |
| 3632 | |
| 3633 | /* Power up sgmii */ |
| 3634 | for (i = 0; i < MTK_MAC_COUNT; i++) { |
developer | 6bb3f3a | 2022-11-22 09:59:14 +0800 | [diff] [blame] | 3635 | if (!eth->netdev[i]) |
| 3636 | continue; |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3637 | mac = netdev_priv(eth->netdev[i]); |
| 3638 | phy_node = of_parse_phandle(mac->of_node, "phy-handle", 0); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 3639 | if (!phy_node && eth->xgmii->regmap_sgmii[i]) { |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3640 | mtk_gmac_sgmii_path_setup(eth, i); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 3641 | regmap_write(eth->xgmii->regmap_sgmii[i], SGMSYS_QPHY_PWR_STATE_CTRL, 0); |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3642 | } |
| 3643 | } |
| 3644 | |
developer | 6bb3f3a | 2022-11-22 09:59:14 +0800 | [diff] [blame] | 3645 | for (i = 0; i < MTK_MAC_COUNT; i++) { |
| 3646 | if (!eth->netdev[i]) |
| 3647 | continue; |
| 3648 | call_netdevice_notifiers(MTK_FE_RESET_NAT_DONE, eth->netdev[i]); |
| 3649 | pr_info("[%s] HNAT reset done !\n", __func__); |
| 3650 | call_netdevice_notifiers(MTK_FE_RESET_DONE, eth->netdev[i]); |
| 3651 | pr_info("[%s] WiFi SER reset done !\n", __func__); |
| 3652 | break; |
| 3653 | } |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 3654 | |
| 3655 | atomic_dec(&reset_lock); |
| 3656 | if (atomic_read(&force) > 0) |
| 3657 | atomic_dec(&force); |
| 3658 | |
| 3659 | timer_setup(ð->mtk_dma_monitor_timer, mtk_dma_monitor, 0); |
| 3660 | eth->mtk_dma_monitor_timer.expires = jiffies; |
| 3661 | add_timer(ð->mtk_dma_monitor_timer); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3662 | clear_bit_unlock(MTK_RESETTING, ð->state); |
| 3663 | |
| 3664 | rtnl_unlock(); |
| 3665 | } |
| 3666 | |
| 3667 | static int mtk_free_dev(struct mtk_eth *eth) |
| 3668 | { |
| 3669 | int i; |
| 3670 | |
| 3671 | for (i = 0; i < MTK_MAC_COUNT; i++) { |
| 3672 | if (!eth->netdev[i]) |
| 3673 | continue; |
| 3674 | free_netdev(eth->netdev[i]); |
| 3675 | } |
| 3676 | |
| 3677 | return 0; |
| 3678 | } |
| 3679 | |
| 3680 | static int mtk_unreg_dev(struct mtk_eth *eth) |
| 3681 | { |
| 3682 | int i; |
| 3683 | |
| 3684 | for (i = 0; i < MTK_MAC_COUNT; i++) { |
| 3685 | if (!eth->netdev[i]) |
| 3686 | continue; |
| 3687 | unregister_netdev(eth->netdev[i]); |
| 3688 | } |
| 3689 | |
| 3690 | return 0; |
| 3691 | } |
| 3692 | |
| 3693 | static int mtk_cleanup(struct mtk_eth *eth) |
| 3694 | { |
| 3695 | mtk_unreg_dev(eth); |
| 3696 | mtk_free_dev(eth); |
| 3697 | cancel_work_sync(ð->pending_work); |
| 3698 | |
| 3699 | return 0; |
| 3700 | } |
| 3701 | |
| 3702 | static int mtk_get_link_ksettings(struct net_device *ndev, |
| 3703 | struct ethtool_link_ksettings *cmd) |
| 3704 | { |
| 3705 | struct mtk_mac *mac = netdev_priv(ndev); |
| 3706 | |
| 3707 | if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) |
| 3708 | return -EBUSY; |
| 3709 | |
| 3710 | return phylink_ethtool_ksettings_get(mac->phylink, cmd); |
| 3711 | } |
| 3712 | |
| 3713 | static int mtk_set_link_ksettings(struct net_device *ndev, |
| 3714 | const struct ethtool_link_ksettings *cmd) |
| 3715 | { |
| 3716 | struct mtk_mac *mac = netdev_priv(ndev); |
| 3717 | |
| 3718 | if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) |
| 3719 | return -EBUSY; |
| 3720 | |
| 3721 | return phylink_ethtool_ksettings_set(mac->phylink, cmd); |
| 3722 | } |
| 3723 | |
| 3724 | static void mtk_get_drvinfo(struct net_device *dev, |
| 3725 | struct ethtool_drvinfo *info) |
| 3726 | { |
| 3727 | struct mtk_mac *mac = netdev_priv(dev); |
| 3728 | |
| 3729 | strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); |
| 3730 | strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); |
| 3731 | info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); |
| 3732 | } |
| 3733 | |
| 3734 | static u32 mtk_get_msglevel(struct net_device *dev) |
| 3735 | { |
| 3736 | struct mtk_mac *mac = netdev_priv(dev); |
| 3737 | |
| 3738 | return mac->hw->msg_enable; |
| 3739 | } |
| 3740 | |
| 3741 | static void mtk_set_msglevel(struct net_device *dev, u32 value) |
| 3742 | { |
| 3743 | struct mtk_mac *mac = netdev_priv(dev); |
| 3744 | |
| 3745 | mac->hw->msg_enable = value; |
| 3746 | } |
| 3747 | |
| 3748 | static int mtk_nway_reset(struct net_device *dev) |
| 3749 | { |
| 3750 | struct mtk_mac *mac = netdev_priv(dev); |
| 3751 | |
| 3752 | if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) |
| 3753 | return -EBUSY; |
| 3754 | |
| 3755 | if (!mac->phylink) |
| 3756 | return -ENOTSUPP; |
| 3757 | |
| 3758 | return phylink_ethtool_nway_reset(mac->phylink); |
| 3759 | } |
| 3760 | |
| 3761 | static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
| 3762 | { |
| 3763 | int i; |
| 3764 | |
| 3765 | switch (stringset) { |
| 3766 | case ETH_SS_STATS: |
| 3767 | for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { |
| 3768 | memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); |
| 3769 | data += ETH_GSTRING_LEN; |
| 3770 | } |
| 3771 | break; |
| 3772 | } |
| 3773 | } |
| 3774 | |
| 3775 | static int mtk_get_sset_count(struct net_device *dev, int sset) |
| 3776 | { |
| 3777 | switch (sset) { |
| 3778 | case ETH_SS_STATS: |
| 3779 | return ARRAY_SIZE(mtk_ethtool_stats); |
| 3780 | default: |
| 3781 | return -EOPNOTSUPP; |
| 3782 | } |
| 3783 | } |
| 3784 | |
| 3785 | static void mtk_get_ethtool_stats(struct net_device *dev, |
| 3786 | struct ethtool_stats *stats, u64 *data) |
| 3787 | { |
| 3788 | struct mtk_mac *mac = netdev_priv(dev); |
| 3789 | struct mtk_hw_stats *hwstats = mac->hw_stats; |
| 3790 | u64 *data_src, *data_dst; |
| 3791 | unsigned int start; |
| 3792 | int i; |
| 3793 | |
| 3794 | if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) |
| 3795 | return; |
| 3796 | |
| 3797 | if (netif_running(dev) && netif_device_present(dev)) { |
| 3798 | if (spin_trylock_bh(&hwstats->stats_lock)) { |
| 3799 | mtk_stats_update_mac(mac); |
| 3800 | spin_unlock_bh(&hwstats->stats_lock); |
| 3801 | } |
| 3802 | } |
| 3803 | |
| 3804 | data_src = (u64 *)hwstats; |
| 3805 | |
| 3806 | do { |
| 3807 | data_dst = data; |
| 3808 | start = u64_stats_fetch_begin_irq(&hwstats->syncp); |
| 3809 | |
| 3810 | for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) |
| 3811 | *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); |
| 3812 | } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); |
| 3813 | } |
| 3814 | |
| 3815 | static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, |
| 3816 | u32 *rule_locs) |
| 3817 | { |
| 3818 | int ret = -EOPNOTSUPP; |
| 3819 | |
| 3820 | switch (cmd->cmd) { |
| 3821 | case ETHTOOL_GRXRINGS: |
| 3822 | if (dev->hw_features & NETIF_F_LRO) { |
| 3823 | cmd->data = MTK_MAX_RX_RING_NUM; |
| 3824 | ret = 0; |
| 3825 | } |
| 3826 | break; |
| 3827 | case ETHTOOL_GRXCLSRLCNT: |
| 3828 | if (dev->hw_features & NETIF_F_LRO) { |
| 3829 | struct mtk_mac *mac = netdev_priv(dev); |
| 3830 | |
| 3831 | cmd->rule_cnt = mac->hwlro_ip_cnt; |
| 3832 | ret = 0; |
| 3833 | } |
| 3834 | break; |
| 3835 | case ETHTOOL_GRXCLSRULE: |
| 3836 | if (dev->hw_features & NETIF_F_LRO) |
| 3837 | ret = mtk_hwlro_get_fdir_entry(dev, cmd); |
| 3838 | break; |
| 3839 | case ETHTOOL_GRXCLSRLALL: |
| 3840 | if (dev->hw_features & NETIF_F_LRO) |
| 3841 | ret = mtk_hwlro_get_fdir_all(dev, cmd, |
| 3842 | rule_locs); |
| 3843 | break; |
| 3844 | default: |
| 3845 | break; |
| 3846 | } |
| 3847 | |
| 3848 | return ret; |
| 3849 | } |
| 3850 | |
| 3851 | static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) |
| 3852 | { |
| 3853 | int ret = -EOPNOTSUPP; |
| 3854 | |
| 3855 | switch (cmd->cmd) { |
| 3856 | case ETHTOOL_SRXCLSRLINS: |
| 3857 | if (dev->hw_features & NETIF_F_LRO) |
| 3858 | ret = mtk_hwlro_add_ipaddr(dev, cmd); |
| 3859 | break; |
| 3860 | case ETHTOOL_SRXCLSRLDEL: |
| 3861 | if (dev->hw_features & NETIF_F_LRO) |
| 3862 | ret = mtk_hwlro_del_ipaddr(dev, cmd); |
| 3863 | break; |
| 3864 | default: |
| 3865 | break; |
| 3866 | } |
| 3867 | |
| 3868 | return ret; |
| 3869 | } |
| 3870 | |
developer | 6c5cbb5 | 2022-08-12 11:37:45 +0800 | [diff] [blame] | 3871 | static void mtk_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *pause) |
| 3872 | { |
| 3873 | struct mtk_mac *mac = netdev_priv(dev); |
| 3874 | |
| 3875 | phylink_ethtool_get_pauseparam(mac->phylink, pause); |
| 3876 | } |
| 3877 | |
| 3878 | static int mtk_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *pause) |
| 3879 | { |
| 3880 | struct mtk_mac *mac = netdev_priv(dev); |
| 3881 | |
| 3882 | return phylink_ethtool_set_pauseparam(mac->phylink, pause); |
| 3883 | } |
| 3884 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3885 | static const struct ethtool_ops mtk_ethtool_ops = { |
| 3886 | .get_link_ksettings = mtk_get_link_ksettings, |
| 3887 | .set_link_ksettings = mtk_set_link_ksettings, |
| 3888 | .get_drvinfo = mtk_get_drvinfo, |
| 3889 | .get_msglevel = mtk_get_msglevel, |
| 3890 | .set_msglevel = mtk_set_msglevel, |
| 3891 | .nway_reset = mtk_nway_reset, |
| 3892 | .get_link = ethtool_op_get_link, |
| 3893 | .get_strings = mtk_get_strings, |
| 3894 | .get_sset_count = mtk_get_sset_count, |
| 3895 | .get_ethtool_stats = mtk_get_ethtool_stats, |
| 3896 | .get_rxnfc = mtk_get_rxnfc, |
| 3897 | .set_rxnfc = mtk_set_rxnfc, |
developer | 6c5cbb5 | 2022-08-12 11:37:45 +0800 | [diff] [blame] | 3898 | .get_pauseparam = mtk_get_pauseparam, |
| 3899 | .set_pauseparam = mtk_set_pauseparam, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3900 | }; |
| 3901 | |
| 3902 | static const struct net_device_ops mtk_netdev_ops = { |
| 3903 | .ndo_init = mtk_init, |
| 3904 | .ndo_uninit = mtk_uninit, |
| 3905 | .ndo_open = mtk_open, |
| 3906 | .ndo_stop = mtk_stop, |
| 3907 | .ndo_start_xmit = mtk_start_xmit, |
| 3908 | .ndo_set_mac_address = mtk_set_mac_address, |
| 3909 | .ndo_validate_addr = eth_validate_addr, |
| 3910 | .ndo_do_ioctl = mtk_do_ioctl, |
| 3911 | .ndo_tx_timeout = mtk_tx_timeout, |
| 3912 | .ndo_get_stats64 = mtk_get_stats64, |
| 3913 | .ndo_fix_features = mtk_fix_features, |
| 3914 | .ndo_set_features = mtk_set_features, |
| 3915 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 3916 | .ndo_poll_controller = mtk_poll_controller, |
| 3917 | #endif |
| 3918 | }; |
| 3919 | |
| 3920 | static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) |
| 3921 | { |
| 3922 | const __be32 *_id = of_get_property(np, "reg", NULL); |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 3923 | const char *label; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3924 | struct phylink *phylink; |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 3925 | int mac_type, phy_mode, id, err; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3926 | struct mtk_mac *mac; |
developer | a2613e6 | 2022-07-01 18:29:37 +0800 | [diff] [blame] | 3927 | struct mtk_phylink_priv *phylink_priv; |
| 3928 | struct fwnode_handle *fixed_node; |
| 3929 | struct gpio_desc *desc; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3930 | |
| 3931 | if (!_id) { |
| 3932 | dev_err(eth->dev, "missing mac id\n"); |
| 3933 | return -EINVAL; |
| 3934 | } |
| 3935 | |
| 3936 | id = be32_to_cpup(_id); |
developer | fb556ca | 2021-10-13 10:52:09 +0800 | [diff] [blame] | 3937 | if (id < 0 || id >= MTK_MAC_COUNT) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 3938 | dev_err(eth->dev, "%d is not a valid mac id\n", id); |
| 3939 | return -EINVAL; |
| 3940 | } |
| 3941 | |
| 3942 | if (eth->netdev[id]) { |
| 3943 | dev_err(eth->dev, "duplicate mac id found: %d\n", id); |
| 3944 | return -EINVAL; |
| 3945 | } |
| 3946 | |
| 3947 | eth->netdev[id] = alloc_etherdev(sizeof(*mac)); |
| 3948 | if (!eth->netdev[id]) { |
| 3949 | dev_err(eth->dev, "alloc_etherdev failed\n"); |
| 3950 | return -ENOMEM; |
| 3951 | } |
| 3952 | mac = netdev_priv(eth->netdev[id]); |
| 3953 | eth->mac[id] = mac; |
| 3954 | mac->id = id; |
| 3955 | mac->hw = eth; |
| 3956 | mac->of_node = np; |
| 3957 | |
| 3958 | memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); |
| 3959 | mac->hwlro_ip_cnt = 0; |
| 3960 | |
| 3961 | mac->hw_stats = devm_kzalloc(eth->dev, |
| 3962 | sizeof(*mac->hw_stats), |
| 3963 | GFP_KERNEL); |
| 3964 | if (!mac->hw_stats) { |
| 3965 | dev_err(eth->dev, "failed to allocate counter memory\n"); |
| 3966 | err = -ENOMEM; |
| 3967 | goto free_netdev; |
| 3968 | } |
| 3969 | spin_lock_init(&mac->hw_stats->stats_lock); |
| 3970 | u64_stats_init(&mac->hw_stats->syncp); |
| 3971 | mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; |
| 3972 | |
| 3973 | /* phylink create */ |
| 3974 | phy_mode = of_get_phy_mode(np); |
| 3975 | if (phy_mode < 0) { |
| 3976 | dev_err(eth->dev, "incorrect phy-mode\n"); |
| 3977 | err = -EINVAL; |
| 3978 | goto free_netdev; |
| 3979 | } |
| 3980 | |
| 3981 | /* mac config is not set */ |
| 3982 | mac->interface = PHY_INTERFACE_MODE_NA; |
| 3983 | mac->mode = MLO_AN_PHY; |
| 3984 | mac->speed = SPEED_UNKNOWN; |
| 3985 | |
| 3986 | mac->phylink_config.dev = ð->netdev[id]->dev; |
| 3987 | mac->phylink_config.type = PHYLINK_NETDEV; |
| 3988 | |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 3989 | mac->type = 0; |
| 3990 | if (!of_property_read_string(np, "mac-type", &label)) { |
| 3991 | for (mac_type = 0; mac_type < MTK_GDM_TYPE_MAX; mac_type++) { |
| 3992 | if (!strcasecmp(label, gdm_type(mac_type))) |
| 3993 | break; |
| 3994 | } |
| 3995 | |
| 3996 | switch (mac_type) { |
| 3997 | case 0: |
| 3998 | mac->type = MTK_GDM_TYPE; |
| 3999 | break; |
| 4000 | case 1: |
| 4001 | mac->type = MTK_XGDM_TYPE; |
| 4002 | break; |
| 4003 | default: |
| 4004 | dev_warn(eth->dev, "incorrect mac-type\n"); |
| 4005 | break; |
| 4006 | }; |
| 4007 | } |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 4008 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4009 | phylink = phylink_create(&mac->phylink_config, |
| 4010 | of_fwnode_handle(mac->of_node), |
| 4011 | phy_mode, &mtk_phylink_ops); |
| 4012 | if (IS_ERR(phylink)) { |
| 4013 | err = PTR_ERR(phylink); |
| 4014 | goto free_netdev; |
| 4015 | } |
| 4016 | |
| 4017 | mac->phylink = phylink; |
| 4018 | |
developer | a2613e6 | 2022-07-01 18:29:37 +0800 | [diff] [blame] | 4019 | fixed_node = fwnode_get_named_child_node(of_fwnode_handle(mac->of_node), |
| 4020 | "fixed-link"); |
| 4021 | if (fixed_node) { |
| 4022 | desc = fwnode_get_named_gpiod(fixed_node, "link-gpio", |
| 4023 | 0, GPIOD_IN, "?"); |
| 4024 | if (!IS_ERR(desc)) { |
| 4025 | struct device_node *phy_np; |
| 4026 | const char *label; |
| 4027 | int irq, phyaddr; |
| 4028 | |
| 4029 | phylink_priv = &mac->phylink_priv; |
| 4030 | |
| 4031 | phylink_priv->desc = desc; |
| 4032 | phylink_priv->id = id; |
| 4033 | phylink_priv->link = -1; |
| 4034 | |
| 4035 | irq = gpiod_to_irq(desc); |
| 4036 | if (irq > 0) { |
| 4037 | devm_request_irq(eth->dev, irq, mtk_handle_irq_fixed_link, |
| 4038 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, |
| 4039 | "ethernet:fixed link", mac); |
| 4040 | } |
| 4041 | |
developer | 8b6f240 | 2022-11-28 13:42:34 +0800 | [diff] [blame] | 4042 | if (!of_property_read_string(to_of_node(fixed_node), |
| 4043 | "label", &label)) { |
| 4044 | if (strlen(label) < 16) |
| 4045 | strcpy(phylink_priv->label, label); |
| 4046 | else |
| 4047 | dev_err(eth->dev, "insufficient space for label!\n"); |
| 4048 | } |
developer | a2613e6 | 2022-07-01 18:29:37 +0800 | [diff] [blame] | 4049 | |
| 4050 | phy_np = of_parse_phandle(to_of_node(fixed_node), "phy-handle", 0); |
| 4051 | if (phy_np) { |
| 4052 | if (!of_property_read_u32(phy_np, "reg", &phyaddr)) |
| 4053 | phylink_priv->phyaddr = phyaddr; |
| 4054 | } |
| 4055 | } |
| 4056 | fwnode_handle_put(fixed_node); |
| 4057 | } |
| 4058 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4059 | SET_NETDEV_DEV(eth->netdev[id], eth->dev); |
| 4060 | eth->netdev[id]->watchdog_timeo = 5 * HZ; |
| 4061 | eth->netdev[id]->netdev_ops = &mtk_netdev_ops; |
| 4062 | eth->netdev[id]->base_addr = (unsigned long)eth->base; |
| 4063 | |
| 4064 | eth->netdev[id]->hw_features = eth->soc->hw_features; |
| 4065 | if (eth->hwlro) |
| 4066 | eth->netdev[id]->hw_features |= NETIF_F_LRO; |
| 4067 | |
| 4068 | eth->netdev[id]->vlan_features = eth->soc->hw_features & |
| 4069 | ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); |
| 4070 | eth->netdev[id]->features |= eth->soc->hw_features; |
| 4071 | eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; |
| 4072 | |
| 4073 | eth->netdev[id]->irq = eth->irq[0]; |
| 4074 | eth->netdev[id]->dev.of_node = np; |
| 4075 | |
| 4076 | return 0; |
| 4077 | |
| 4078 | free_netdev: |
| 4079 | free_netdev(eth->netdev[id]); |
| 4080 | return err; |
| 4081 | } |
| 4082 | |
| 4083 | static int mtk_probe(struct platform_device *pdev) |
| 4084 | { |
| 4085 | struct device_node *mac_np; |
| 4086 | struct mtk_eth *eth; |
| 4087 | int err, i; |
| 4088 | |
| 4089 | eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); |
| 4090 | if (!eth) |
| 4091 | return -ENOMEM; |
| 4092 | |
| 4093 | eth->soc = of_device_get_match_data(&pdev->dev); |
| 4094 | |
| 4095 | eth->dev = &pdev->dev; |
| 4096 | eth->base = devm_platform_ioremap_resource(pdev, 0); |
| 4097 | if (IS_ERR(eth->base)) |
| 4098 | return PTR_ERR(eth->base); |
| 4099 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 4100 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { |
| 4101 | eth->sram_base = devm_platform_ioremap_resource(pdev, 1); |
| 4102 | if (IS_ERR(eth->sram_base)) |
| 4103 | return PTR_ERR(eth->sram_base); |
| 4104 | } |
| 4105 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4106 | if(eth->soc->has_sram) { |
| 4107 | struct resource *res; |
| 4108 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
developer | 4c32b7a | 2021-11-13 16:46:43 +0800 | [diff] [blame] | 4109 | if (unlikely(!res)) |
| 4110 | return -EINVAL; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4111 | eth->phy_scratch_ring = res->start + MTK_ETH_SRAM_OFFSET; |
| 4112 | } |
| 4113 | |
| 4114 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { |
| 4115 | eth->tx_int_mask_reg = MTK_QDMA_INT_MASK; |
| 4116 | eth->tx_int_status_reg = MTK_QDMA_INT_STATUS; |
| 4117 | } else { |
| 4118 | eth->tx_int_mask_reg = MTK_PDMA_INT_MASK; |
| 4119 | eth->tx_int_status_reg = MTK_PDMA_INT_STATUS; |
| 4120 | } |
| 4121 | |
| 4122 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { |
| 4123 | eth->rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA; |
| 4124 | eth->ip_align = NET_IP_ALIGN; |
| 4125 | } else { |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 4126 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) || |
| 4127 | MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4128 | eth->rx_dma_l4_valid = RX_DMA_L4_VALID_V2; |
| 4129 | else |
| 4130 | eth->rx_dma_l4_valid = RX_DMA_L4_VALID; |
| 4131 | } |
| 4132 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 4133 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_8GB_ADDRESSING)) { |
| 4134 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36)); |
| 4135 | if (!err) { |
| 4136 | err = dma_set_coherent_mask(&pdev->dev, |
| 4137 | DMA_BIT_MASK(36)); |
| 4138 | if (err) { |
| 4139 | dev_err(&pdev->dev, "Wrong DMA config\n"); |
| 4140 | return -EINVAL; |
| 4141 | } |
| 4142 | } |
| 4143 | } |
| 4144 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4145 | spin_lock_init(ð->page_lock); |
| 4146 | spin_lock_init(ð->tx_irq_lock); |
| 4147 | spin_lock_init(ð->rx_irq_lock); |
developer | d82e837 | 2022-02-09 15:00:09 +0800 | [diff] [blame] | 4148 | spin_lock_init(ð->syscfg0_lock); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4149 | |
| 4150 | if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { |
| 4151 | eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, |
| 4152 | "mediatek,ethsys"); |
| 4153 | if (IS_ERR(eth->ethsys)) { |
| 4154 | dev_err(&pdev->dev, "no ethsys regmap found\n"); |
| 4155 | return PTR_ERR(eth->ethsys); |
| 4156 | } |
| 4157 | } |
| 4158 | |
| 4159 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { |
| 4160 | eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, |
| 4161 | "mediatek,infracfg"); |
| 4162 | if (IS_ERR(eth->infra)) { |
| 4163 | dev_err(&pdev->dev, "no infracfg regmap found\n"); |
| 4164 | return PTR_ERR(eth->infra); |
| 4165 | } |
| 4166 | } |
| 4167 | |
| 4168 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 4169 | eth->xgmii = devm_kzalloc(eth->dev, sizeof(*eth->xgmii), |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4170 | GFP_KERNEL); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 4171 | if (!eth->xgmii) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4172 | return -ENOMEM; |
| 4173 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 4174 | eth->xgmii->eth = eth; |
| 4175 | err = mtk_sgmii_init(eth->xgmii, pdev->dev.of_node, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4176 | eth->soc->ana_rgc3); |
| 4177 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 4178 | if (err) |
| 4179 | return err; |
| 4180 | } |
| 4181 | |
| 4182 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) { |
| 4183 | err = mtk_usxgmii_init(eth->xgmii, pdev->dev.of_node); |
| 4184 | if (err) |
| 4185 | return err; |
| 4186 | |
| 4187 | err = mtk_xfi_pextp_init(eth->xgmii, pdev->dev.of_node); |
| 4188 | if (err) |
| 4189 | return err; |
| 4190 | |
| 4191 | err = mtk_xfi_pll_init(eth->xgmii, pdev->dev.of_node); |
| 4192 | if (err) |
| 4193 | return err; |
| 4194 | |
| 4195 | err = mtk_toprgu_init(eth, pdev->dev.of_node); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4196 | if (err) |
| 4197 | return err; |
| 4198 | } |
| 4199 | |
| 4200 | if (eth->soc->required_pctl) { |
| 4201 | eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, |
| 4202 | "mediatek,pctl"); |
| 4203 | if (IS_ERR(eth->pctl)) { |
| 4204 | dev_err(&pdev->dev, "no pctl regmap found\n"); |
| 4205 | return PTR_ERR(eth->pctl); |
| 4206 | } |
| 4207 | } |
| 4208 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 4209 | for (i = 0; i < MTK_MAX_IRQ_NUM; i++) { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4210 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) |
| 4211 | eth->irq[i] = eth->irq[0]; |
| 4212 | else |
| 4213 | eth->irq[i] = platform_get_irq(pdev, i); |
| 4214 | if (eth->irq[i] < 0) { |
| 4215 | dev_err(&pdev->dev, "no IRQ%d resource found\n", i); |
| 4216 | return -ENXIO; |
| 4217 | } |
| 4218 | } |
| 4219 | |
| 4220 | for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { |
| 4221 | eth->clks[i] = devm_clk_get(eth->dev, |
| 4222 | mtk_clks_source_name[i]); |
| 4223 | if (IS_ERR(eth->clks[i])) { |
| 4224 | if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) |
| 4225 | return -EPROBE_DEFER; |
| 4226 | if (eth->soc->required_clks & BIT(i)) { |
| 4227 | dev_err(&pdev->dev, "clock %s not found\n", |
| 4228 | mtk_clks_source_name[i]); |
| 4229 | return -EINVAL; |
| 4230 | } |
| 4231 | eth->clks[i] = NULL; |
| 4232 | } |
| 4233 | } |
| 4234 | |
| 4235 | eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); |
| 4236 | INIT_WORK(ð->pending_work, mtk_pending_work); |
| 4237 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 4238 | err = mtk_hw_init(eth, MTK_TYPE_COLD_RESET); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4239 | if (err) |
| 4240 | return err; |
| 4241 | |
| 4242 | eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); |
| 4243 | |
| 4244 | for_each_child_of_node(pdev->dev.of_node, mac_np) { |
| 4245 | if (!of_device_is_compatible(mac_np, |
| 4246 | "mediatek,eth-mac")) |
| 4247 | continue; |
| 4248 | |
| 4249 | if (!of_device_is_available(mac_np)) |
| 4250 | continue; |
| 4251 | |
| 4252 | err = mtk_add_mac(eth, mac_np); |
| 4253 | if (err) { |
| 4254 | of_node_put(mac_np); |
| 4255 | goto err_deinit_hw; |
| 4256 | } |
| 4257 | } |
| 4258 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 4259 | err = mtk_napi_init(eth); |
| 4260 | if (err) |
| 4261 | goto err_free_dev; |
| 4262 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4263 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { |
| 4264 | err = devm_request_irq(eth->dev, eth->irq[0], |
| 4265 | mtk_handle_irq, 0, |
| 4266 | dev_name(eth->dev), eth); |
| 4267 | } else { |
| 4268 | err = devm_request_irq(eth->dev, eth->irq[1], |
| 4269 | mtk_handle_irq_tx, 0, |
| 4270 | dev_name(eth->dev), eth); |
| 4271 | if (err) |
| 4272 | goto err_free_dev; |
| 4273 | |
| 4274 | err = devm_request_irq(eth->dev, eth->irq[2], |
| 4275 | mtk_handle_irq_rx, 0, |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 4276 | dev_name(eth->dev), ð->rx_napi[0]); |
| 4277 | if (err) |
| 4278 | goto err_free_dev; |
| 4279 | |
developer | 793f7b4 | 2022-05-20 13:54:51 +0800 | [diff] [blame] | 4280 | if (MTK_MAX_IRQ_NUM > 3) { |
| 4281 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSS)) { |
| 4282 | for (i = 1; i < MTK_RX_NAPI_NUM; i++) { |
| 4283 | err = devm_request_irq(eth->dev, |
| 4284 | eth->irq[2 + i], |
| 4285 | mtk_handle_irq_rx, 0, |
| 4286 | dev_name(eth->dev), |
| 4287 | ð->rx_napi[i]); |
| 4288 | if (err) |
| 4289 | goto err_free_dev; |
| 4290 | } |
| 4291 | } else { |
| 4292 | err = devm_request_irq(eth->dev, eth->irq[3], |
| 4293 | mtk_handle_fe_irq, 0, |
| 4294 | dev_name(eth->dev), eth); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 4295 | if (err) |
| 4296 | goto err_free_dev; |
| 4297 | } |
| 4298 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4299 | } |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 4300 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4301 | if (err) |
| 4302 | goto err_free_dev; |
| 4303 | |
| 4304 | /* No MT7628/88 support yet */ |
| 4305 | if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { |
| 4306 | err = mtk_mdio_init(eth); |
| 4307 | if (err) |
| 4308 | goto err_free_dev; |
| 4309 | } |
| 4310 | |
| 4311 | for (i = 0; i < MTK_MAX_DEVS; i++) { |
| 4312 | if (!eth->netdev[i]) |
| 4313 | continue; |
| 4314 | |
| 4315 | err = register_netdev(eth->netdev[i]); |
| 4316 | if (err) { |
| 4317 | dev_err(eth->dev, "error bringing up device\n"); |
| 4318 | goto err_deinit_mdio; |
| 4319 | } else |
| 4320 | netif_info(eth, probe, eth->netdev[i], |
| 4321 | "mediatek frame engine at 0x%08lx, irq %d\n", |
| 4322 | eth->netdev[i]->base_addr, eth->irq[0]); |
| 4323 | } |
| 4324 | |
| 4325 | /* we run 2 devices on the same DMA ring so we need a dummy device |
| 4326 | * for NAPI to work |
| 4327 | */ |
| 4328 | init_dummy_netdev(ð->dummy_dev); |
| 4329 | netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx, |
| 4330 | MTK_NAPI_WEIGHT); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 4331 | netif_napi_add(ð->dummy_dev, ð->rx_napi[0].napi, mtk_napi_rx, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4332 | MTK_NAPI_WEIGHT); |
| 4333 | |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 4334 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSS)) { |
| 4335 | for (i = 1; i < MTK_RX_NAPI_NUM; i++) |
| 4336 | netif_napi_add(ð->dummy_dev, ð->rx_napi[i].napi, |
| 4337 | mtk_napi_rx, MTK_NAPI_WEIGHT); |
| 4338 | } |
| 4339 | |
developer | 75e4dad | 2022-11-16 15:17:14 +0800 | [diff] [blame] | 4340 | #if defined(CONFIG_XFRM_OFFLOAD) |
| 4341 | mtk_ipsec_offload_init(eth); |
| 4342 | #endif |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4343 | mtketh_debugfs_init(eth); |
| 4344 | debug_proc_init(eth); |
| 4345 | |
| 4346 | platform_set_drvdata(pdev, eth); |
| 4347 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 4348 | register_netdevice_notifier(&mtk_eth_netdevice_nb); |
developer | 793f7b4 | 2022-05-20 13:54:51 +0800 | [diff] [blame] | 4349 | #if defined(CONFIG_MEDIATEK_NETSYS_V2) |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 4350 | timer_setup(ð->mtk_dma_monitor_timer, mtk_dma_monitor, 0); |
| 4351 | eth->mtk_dma_monitor_timer.expires = jiffies; |
| 4352 | add_timer(ð->mtk_dma_monitor_timer); |
developer | 793f7b4 | 2022-05-20 13:54:51 +0800 | [diff] [blame] | 4353 | #endif |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 4354 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4355 | return 0; |
| 4356 | |
| 4357 | err_deinit_mdio: |
| 4358 | mtk_mdio_cleanup(eth); |
| 4359 | err_free_dev: |
| 4360 | mtk_free_dev(eth); |
| 4361 | err_deinit_hw: |
| 4362 | mtk_hw_deinit(eth); |
| 4363 | |
| 4364 | return err; |
| 4365 | } |
| 4366 | |
| 4367 | static int mtk_remove(struct platform_device *pdev) |
| 4368 | { |
| 4369 | struct mtk_eth *eth = platform_get_drvdata(pdev); |
| 4370 | struct mtk_mac *mac; |
| 4371 | int i; |
| 4372 | |
| 4373 | /* stop all devices to make sure that dma is properly shut down */ |
| 4374 | for (i = 0; i < MTK_MAC_COUNT; i++) { |
| 4375 | if (!eth->netdev[i]) |
| 4376 | continue; |
| 4377 | mtk_stop(eth->netdev[i]); |
| 4378 | mac = netdev_priv(eth->netdev[i]); |
| 4379 | phylink_disconnect_phy(mac->phylink); |
| 4380 | } |
| 4381 | |
| 4382 | mtk_hw_deinit(eth); |
| 4383 | |
| 4384 | netif_napi_del(ð->tx_napi); |
developer | 18f46a8 | 2021-07-20 21:08:21 +0800 | [diff] [blame] | 4385 | netif_napi_del(ð->rx_napi[0].napi); |
| 4386 | |
| 4387 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSS)) { |
| 4388 | for (i = 1; i < MTK_RX_NAPI_NUM; i++) |
| 4389 | netif_napi_del(ð->rx_napi[i].napi); |
| 4390 | } |
| 4391 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4392 | mtk_cleanup(eth); |
| 4393 | mtk_mdio_cleanup(eth); |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 4394 | unregister_netdevice_notifier(&mtk_eth_netdevice_nb); |
| 4395 | del_timer_sync(ð->mtk_dma_monitor_timer); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4396 | |
| 4397 | return 0; |
| 4398 | } |
| 4399 | |
| 4400 | static const struct mtk_soc_data mt2701_data = { |
| 4401 | .caps = MT7623_CAPS | MTK_HWLRO, |
| 4402 | .hw_features = MTK_HW_FEATURES, |
| 4403 | .required_clks = MT7623_CLKS_BITMAP, |
| 4404 | .required_pctl = true, |
| 4405 | .has_sram = false, |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 4406 | .txrx = { |
| 4407 | .txd_size = sizeof(struct mtk_tx_dma), |
| 4408 | .rxd_size = sizeof(struct mtk_rx_dma), |
| 4409 | .dma_max_len = MTK_TX_DMA_BUF_LEN, |
| 4410 | .dma_len_offset = MTK_TX_DMA_BUF_SHIFT, |
| 4411 | }, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4412 | }; |
| 4413 | |
| 4414 | static const struct mtk_soc_data mt7621_data = { |
| 4415 | .caps = MT7621_CAPS, |
| 4416 | .hw_features = MTK_HW_FEATURES, |
| 4417 | .required_clks = MT7621_CLKS_BITMAP, |
| 4418 | .required_pctl = false, |
| 4419 | .has_sram = false, |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 4420 | .txrx = { |
| 4421 | .txd_size = sizeof(struct mtk_tx_dma), |
| 4422 | .rxd_size = sizeof(struct mtk_rx_dma), |
| 4423 | .dma_max_len = MTK_TX_DMA_BUF_LEN, |
| 4424 | .dma_len_offset = MTK_TX_DMA_BUF_SHIFT, |
| 4425 | }, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4426 | }; |
| 4427 | |
| 4428 | static const struct mtk_soc_data mt7622_data = { |
| 4429 | .ana_rgc3 = 0x2028, |
| 4430 | .caps = MT7622_CAPS | MTK_HWLRO, |
| 4431 | .hw_features = MTK_HW_FEATURES, |
| 4432 | .required_clks = MT7622_CLKS_BITMAP, |
| 4433 | .required_pctl = false, |
| 4434 | .has_sram = false, |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 4435 | .txrx = { |
| 4436 | .txd_size = sizeof(struct mtk_tx_dma), |
| 4437 | .rxd_size = sizeof(struct mtk_rx_dma), |
| 4438 | .dma_max_len = MTK_TX_DMA_BUF_LEN, |
| 4439 | .dma_len_offset = MTK_TX_DMA_BUF_SHIFT, |
| 4440 | }, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4441 | }; |
| 4442 | |
| 4443 | static const struct mtk_soc_data mt7623_data = { |
| 4444 | .caps = MT7623_CAPS | MTK_HWLRO, |
| 4445 | .hw_features = MTK_HW_FEATURES, |
| 4446 | .required_clks = MT7623_CLKS_BITMAP, |
| 4447 | .required_pctl = true, |
| 4448 | .has_sram = false, |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 4449 | .txrx = { |
| 4450 | .txd_size = sizeof(struct mtk_tx_dma), |
| 4451 | .rxd_size = sizeof(struct mtk_rx_dma), |
| 4452 | .dma_max_len = MTK_TX_DMA_BUF_LEN, |
| 4453 | .dma_len_offset = MTK_TX_DMA_BUF_SHIFT, |
| 4454 | }, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4455 | }; |
| 4456 | |
| 4457 | static const struct mtk_soc_data mt7629_data = { |
| 4458 | .ana_rgc3 = 0x128, |
| 4459 | .caps = MT7629_CAPS | MTK_HWLRO, |
| 4460 | .hw_features = MTK_HW_FEATURES, |
| 4461 | .required_clks = MT7629_CLKS_BITMAP, |
| 4462 | .required_pctl = false, |
| 4463 | .has_sram = false, |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 4464 | .txrx = { |
| 4465 | .txd_size = sizeof(struct mtk_tx_dma), |
| 4466 | .rxd_size = sizeof(struct mtk_rx_dma), |
| 4467 | .dma_max_len = MTK_TX_DMA_BUF_LEN, |
| 4468 | .dma_len_offset = MTK_TX_DMA_BUF_SHIFT, |
| 4469 | }, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4470 | }; |
| 4471 | |
| 4472 | static const struct mtk_soc_data mt7986_data = { |
| 4473 | .ana_rgc3 = 0x128, |
| 4474 | .caps = MT7986_CAPS, |
developer | cba5f4e | 2021-05-06 14:01:53 +0800 | [diff] [blame] | 4475 | .hw_features = MTK_HW_FEATURES, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4476 | .required_clks = MT7986_CLKS_BITMAP, |
| 4477 | .required_pctl = false, |
| 4478 | .has_sram = true, |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 4479 | .txrx = { |
| 4480 | .txd_size = sizeof(struct mtk_tx_dma_v2), |
| 4481 | .rxd_size = sizeof(struct mtk_rx_dma_v2), |
| 4482 | .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, |
| 4483 | .dma_len_offset = MTK_TX_DMA_BUF_SHIFT_V2, |
| 4484 | }, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4485 | }; |
| 4486 | |
developer | 255bba2 | 2021-07-27 15:16:33 +0800 | [diff] [blame] | 4487 | static const struct mtk_soc_data mt7981_data = { |
| 4488 | .ana_rgc3 = 0x128, |
| 4489 | .caps = MT7981_CAPS, |
developer | 7377b0b | 2021-11-18 14:54:47 +0800 | [diff] [blame] | 4490 | .hw_features = MTK_HW_FEATURES, |
developer | 255bba2 | 2021-07-27 15:16:33 +0800 | [diff] [blame] | 4491 | .required_clks = MT7981_CLKS_BITMAP, |
| 4492 | .required_pctl = false, |
| 4493 | .has_sram = true, |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 4494 | .txrx = { |
| 4495 | .txd_size = sizeof(struct mtk_tx_dma_v2), |
| 4496 | .rxd_size = sizeof(struct mtk_rx_dma_v2), |
| 4497 | .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, |
| 4498 | .dma_len_offset = MTK_TX_DMA_BUF_SHIFT_V2, |
| 4499 | }, |
developer | 255bba2 | 2021-07-27 15:16:33 +0800 | [diff] [blame] | 4500 | }; |
| 4501 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 4502 | static const struct mtk_soc_data mt7988_data = { |
| 4503 | .ana_rgc3 = 0x128, |
| 4504 | .caps = MT7988_CAPS, |
| 4505 | .hw_features = MTK_HW_FEATURES, |
| 4506 | .required_clks = MT7988_CLKS_BITMAP, |
| 4507 | .required_pctl = false, |
| 4508 | .has_sram = true, |
| 4509 | .txrx = { |
| 4510 | .txd_size = sizeof(struct mtk_tx_dma_v2), |
| 4511 | .rxd_size = sizeof(struct mtk_rx_dma_v2), |
| 4512 | .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, |
| 4513 | .dma_len_offset = MTK_TX_DMA_BUF_SHIFT_V2, |
| 4514 | }, |
| 4515 | }; |
| 4516 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4517 | static const struct mtk_soc_data rt5350_data = { |
| 4518 | .caps = MT7628_CAPS, |
| 4519 | .hw_features = MTK_HW_FEATURES_MT7628, |
| 4520 | .required_clks = MT7628_CLKS_BITMAP, |
| 4521 | .required_pctl = false, |
| 4522 | .has_sram = false, |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 4523 | .txrx = { |
| 4524 | .txd_size = sizeof(struct mtk_tx_dma), |
| 4525 | .rxd_size = sizeof(struct mtk_rx_dma), |
| 4526 | .dma_max_len = MTK_TX_DMA_BUF_LEN, |
| 4527 | .dma_len_offset = MTK_TX_DMA_BUF_SHIFT, |
| 4528 | }, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4529 | }; |
| 4530 | |
| 4531 | const struct of_device_id of_mtk_match[] = { |
| 4532 | { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, |
| 4533 | { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, |
| 4534 | { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, |
| 4535 | { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, |
| 4536 | { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, |
| 4537 | { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data}, |
developer | 255bba2 | 2021-07-27 15:16:33 +0800 | [diff] [blame] | 4538 | { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data}, |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 4539 | { .compatible = "mediatek,mt7988-eth", .data = &mt7988_data}, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 4540 | { .compatible = "ralink,rt5350-eth", .data = &rt5350_data}, |
| 4541 | {}, |
| 4542 | }; |
| 4543 | MODULE_DEVICE_TABLE(of, of_mtk_match); |
| 4544 | |
| 4545 | static struct platform_driver mtk_driver = { |
| 4546 | .probe = mtk_probe, |
| 4547 | .remove = mtk_remove, |
| 4548 | .driver = { |
| 4549 | .name = "mtk_soc_eth", |
| 4550 | .of_match_table = of_mtk_match, |
| 4551 | }, |
| 4552 | }; |
| 4553 | |
| 4554 | module_platform_driver(mtk_driver); |
| 4555 | |
| 4556 | MODULE_LICENSE("GPL"); |
| 4557 | MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); |
| 4558 | MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); |