| commit | b88cdb0c5ad252dae946447ea6d73cbe0712f2ea | [log] [tgz] |
|---|---|---|
| author | developer <developer@mediatek.com> | Wed Oct 12 18:10:03 2022 +0800 |
| committer | developer <developer@mediatek.com> | Thu Oct 13 11:17:05 2022 +0800 |
| tree | 2ee5bddeefc7cc7ef2d1764cfcd4f1d07fd00052 | |
| parent | 720571aa710ace737a8b7caa3c6fbd6cbf760e1c [diff] [blame] |
[][kernel][common][eth][Add 2500baseT_Full/5000baseT_Full capabilities to USXGMII] [Description] Add 2500baseT_Full/5000baseT_Full capabilities to USXGMII. If without this patch, USXGMII cannot link up 2.5G/5G. [Release-log] N/A Change-Id: Ia591273e6360616dd3494c8dadb690d45250fddc Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6622639 Build: srv_hbgsm110
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 5806723..7fe3713 100755 --- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -709,6 +709,8 @@ phylink_set(mask, 1000baseT_Half); phylink_set(mask, 1000baseT_Full); phylink_set(mask, 1000baseX_Full); + phylink_set(mask, 2500baseT_Full); + phylink_set(mask, 5000baseT_Full); break; case PHY_INTERFACE_MODE_TRGMII: phylink_set(mask, 1000baseT_Full);