blob: b8f3012873ea4ed55359ad08ce8c8395421c6cfc [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Eddie James1a55a7a2023-10-24 10:43:51 -050012#include <config.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010013#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010015#include <dt-bindings/input/input.h>
Heiko Schocher350d2522025-01-28 14:52:46 +010016#include <dt-bindings/leds/common.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040017#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053018#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010019
Simon Glassb2c1cac2014-02-26 15:59:21 -070020/ {
21 model = "sandbox";
22 compatible = "sandbox";
23 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060024 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070025
Simon Glassfef72b72014-07-23 06:55:03 -060026 aliases {
27 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010028 ethernet0 = "/eth@10002000";
29 ethernet2 = &swp_0;
30 ethernet3 = &eth_3;
31 ethernet4 = &dsa_eth0;
32 ethernet5 = &eth_5;
Sean Anderson67d93a42022-05-05 13:11:30 -040033 ethernet6 = "/eth@10004000";
34 ethernet7 = &swp_1;
35 ethernet8 = &phy_eth0;
Simon Glass5620cf82018-10-01 12:22:40 -060036 gpio1 = &gpio_a;
37 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010038 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070039 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060040 mmc0 = "/mmc0";
41 mmc1 = "/mmc1";
Simon Glassf1eba352022-10-20 18:23:20 -060042 mmc2 = "/mmc2";
43 mmc3 = "/mmc3";
Simon Glassfff928c2023-08-24 13:55:41 -060044 mmc4 = "/mmc4";
45 mmc5 = "/mmc5";
Alexander Gendin038cb022023-10-09 01:24:36 +000046 mmc6 = "/mmc6";
Mattijs Korpershoekd77f8152024-07-10 10:40:06 +020047 mmc7 = "/mmc7";
Guillaume La Roque368ad9e2024-11-26 09:06:13 +010048 mmc8 = "/mmc8";
Bin Meng408e5902018-08-03 01:14:41 -070049 pci0 = &pci0;
50 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070051 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020052 remoteproc0 = &rproc_1;
53 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060054 rtc0 = &rtc_0;
55 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060056 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020057 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070058 testbus3 = "/some-bus";
59 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070060 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070061 testfdt3 = "/b-test";
62 testfdt5 = "/some-bus/c-test@5";
63 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070064 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020065 fdt-dummy0 = "/translation-test@8000/dev@0,0";
66 fdt-dummy1 = "/translation-test@8000/dev@1,100";
67 fdt-dummy2 = "/translation-test@8000/dev@2,200";
68 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060069 usb0 = &usb_0;
70 usb1 = &usb_1;
71 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020072 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020073 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060074 };
75
Eddie James1a55a7a2023-10-24 10:43:51 -050076 reserved-memory {
77 #address-cells = <1>;
78 #size-cells = <1>;
79 ranges;
80
81 event_log: tcg_event_log {
82 no-map;
Sughosh Ganu3f768682024-08-26 17:29:32 +053083 reg = <(CFG_SYS_SDRAM_BASE + 0x100000) 0x2000>;
Eddie James1a55a7a2023-10-24 10:43:51 -050084 };
85 };
86
Simon Glass5e135d32022-10-20 18:23:15 -060087 binman: binman {
Philippe Reynes462d1632022-03-28 22:56:53 +020088 };
89
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020090 config {
Simon Glass0034d962021-08-07 07:24:01 -060091 testing-bool;
92 testing-int = <123>;
93 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020094 environment {
95 from_fdt = "yes";
96 fdt_env_path = "";
97 };
98 };
99
Michal Simek43c42bd2023-08-31 08:59:05 +0200100 options {
101 u-boot {
102 compatible = "u-boot,config";
103 bootscr-ram-offset = /bits/ 64 <0x12345678>;
Michal Simek6a7c1ce2023-08-31 09:04:27 +0200104 bootscr-flash-offset = /bits/ 64 <0>;
105 bootscr-flash-size = /bits/ 64 <0x2000>;
Christian Marangifd53ad42024-11-10 12:50:27 +0100106 boot-led = <&sandbox_led_green>;
107 activity-led = <&sandbox_led_red>;
Christian Marangicdc38152024-10-01 14:24:44 +0200108 testing-bool;
109 testing-int = <123>;
110 testing-str = "testing";
Christian Marangi81ce47e2024-11-10 12:50:25 +0100111 testing-phandle = <&phandle_node_1>;
Michal Simek43c42bd2023-08-31 08:59:05 +0200112 };
113 };
114
Simon Glassb255efc2022-04-24 23:31:24 -0600115 bootstd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700116 bootph-verify;
Simon Glassb255efc2022-04-24 23:31:24 -0600117 compatible = "u-boot,boot-std";
118
119 filename-prefixes = "/", "/boot/";
120 bootdev-order = "mmc2", "mmc1";
121
Simon Glassb71d7f72023-05-10 16:34:46 -0600122 extlinux {
123 compatible = "u-boot,extlinux";
Simon Glassb255efc2022-04-24 23:31:24 -0600124 };
125
126 efi {
127 compatible = "u-boot,distro-efi";
128 };
Simon Glassa9289612022-10-20 18:23:14 -0600129
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600130 theme {
131 font-size = <30>;
Simon Glass86f1ac52023-06-01 10:23:00 -0600132 menu-inset = <3>;
133 menuitem-gap-y = <1>;
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600134 };
135
Simon Glass82adc292023-08-14 16:40:30 -0600136 cedit-theme {
137 font-size = <30>;
138 menu-inset = <3>;
139 menuitem-gap-y = <1>;
140 };
141
Simon Glassf1eba352022-10-20 18:23:20 -0600142 /*
143 * This is used for the VBE OS-request tests. A FAT filesystem
144 * created in a partition with the VBE information appearing
Michal Simek33224372023-09-07 14:55:48 +0200145 * before the partition starts
Simon Glassf1eba352022-10-20 18:23:20 -0600146 */
Simon Glassa9289612022-10-20 18:23:14 -0600147 firmware0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700148 bootph-verify;
Simon Glassa9289612022-10-20 18:23:14 -0600149 compatible = "fwupd,vbe-simple";
150 storage = "mmc1";
151 skip-offset = <0x200>;
152 area-start = <0x400>;
153 area-size = <0x1000>;
154 state-offset = <0x400>;
155 state-size = <0x40>;
156 version-offset = <0x800>;
157 version-size = <0x100>;
158 };
Simon Glassf1eba352022-10-20 18:23:20 -0600159
160 /*
161 * This is used for the VBE VPL tests. The MMC device holds the
162 * binman image.bin file. The test progresses through each phase
163 * of U-Boot, loading each in turn from MMC.
164 *
165 * Note that the test enables this node (and mmc3) before
166 * running U-Boot
167 */
168 firmware1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700169 bootph-verify;
Simon Glassf1eba352022-10-20 18:23:20 -0600170 status = "disabled";
171 compatible = "fwupd,vbe-simple";
172 storage = "mmc3";
Simon Glass9bb73e32023-04-02 14:01:24 +1200173 skip-offset = <0x800000>;
Simon Glassf1eba352022-10-20 18:23:20 -0600174 area-start = <0>;
175 area-size = <0xe00000>;
176 state-offset = <0xdffc00>;
177 state-size = <0x40>;
178 version-offset = <0xdffe00>;
179 version-size = <0x100>;
180 };
Simon Glassb255efc2022-04-24 23:31:24 -0600181 };
182
Simon Glass61300722023-06-01 10:23:01 -0600183 cedit: cedit {
184 };
185
Andrew Scull451b8b12022-05-30 10:00:12 +0000186 fuzzing-engine {
187 compatible = "sandbox,fuzzing-engine";
188 };
189
Nandor Han6521e5d2021-06-10 16:56:44 +0300190 reboot-mode0 {
191 compatible = "reboot-mode-gpio";
192 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
193 u-boot,env-variable = "bootstatus";
194 mode-test = <0x01>;
195 mode-download = <0x03>;
196 };
197
Nandor Han7e4067a2021-06-10 16:56:45 +0300198 reboot_mode1: reboot-mode@14 {
199 compatible = "reboot-mode-rtc";
200 rtc = <&rtc_0>;
201 reg = <0x30 4>;
202 u-boot,env-variable = "bootstatus";
203 big-endian;
204 mode-test = <0x21969147>;
205 mode-download = <0x51939147>;
206 };
207
Simon Glassed96cde2018-12-10 10:37:33 -0700208 audio: audio-codec {
209 compatible = "sandbox,audio-codec";
210 #sound-dai-cells = <1>;
211 };
212
Philippe Reynes1ee26482020-07-24 18:19:51 +0200213 buttons {
214 compatible = "gpio-keys";
215
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200216 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200217 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200218 label = "button1";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300219 linux,code = <BTN_1>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200220 };
221
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200222 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200223 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200224 label = "button2";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300225 linux,code = <BTN_2>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200226 };
227 };
228
Marek Szyprowskiad398592021-02-18 11:33:18 +0100229 buttons2 {
230 compatible = "adc-keys";
231 io-channels = <&adc 3>;
232 keyup-threshold-microvolt = <3000000>;
233
234 button-up {
235 label = "button3";
236 linux,code = <KEY_F3>;
237 press-threshold-microvolt = <1500000>;
238 };
239
240 button-down {
241 label = "button4";
242 linux,code = <KEY_F4>;
243 press-threshold-microvolt = <1000000>;
244 };
245
246 button-enter {
247 label = "button5";
248 linux,code = <KEY_F5>;
249 press-threshold-microvolt = <500000>;
250 };
251 };
252
Simon Glassc953aaf2018-12-10 10:37:34 -0700253 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600254 reg = <0 0>;
255 compatible = "google,cros-ec-sandbox";
256
257 /*
258 * This describes the flash memory within the EC. Note
259 * that the STM32L flash erases to 0, not 0xff.
260 */
261 flash {
262 image-pos = <0x08000000>;
263 size = <0x20000>;
264 erase-value = <0>;
265
266 /* Information for sandbox */
267 ro {
268 image-pos = <0>;
269 size = <0xf000>;
270 };
271 wp-ro {
272 image-pos = <0xf000>;
273 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700274 used = <0x884>;
275 compress = "lz4";
276 uncomp-size = <0xcf8>;
277 hash {
278 algo = "sha256";
279 value = [00 01 02 03 04 05 06 07
280 08 09 0a 0b 0c 0d 0e 0f
281 10 11 12 13 14 15 16 17
282 18 19 1a 1b 1c 1d 1e 1f];
283 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600284 };
285 rw {
286 image-pos = <0x10000>;
287 size = <0x10000>;
288 };
289 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300290
291 cros_ec_pwm: cros-ec-pwm {
292 compatible = "google,cros-ec-pwm";
293 #pwm-cells = <1>;
294 };
295
Simon Glass699c9ca2018-10-01 12:22:08 -0600296 };
297
Yannick Fertré9712c822019-10-07 15:29:05 +0200298 dsi_host: dsi_host {
299 compatible = "sandbox,dsi-host";
300 };
301
Christian Marangia1a1e0e2024-11-10 12:50:23 +0100302 phandle_node_1: phandle-node-1 {
303 };
304
305 phandle_node_2: phandle-node-2 {
306 };
307
Simon Glassb2c1cac2014-02-26 15:59:21 -0700308 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600309 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700310 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600311 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700312 ping-add = <0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700313 bootph-all;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100314 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
315 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700316 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100317 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
318 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
319 <&gpio_b 7 GPIO_IN 3 2 1>,
320 <&gpio_b 8 GPIO_OUT 3 2 1>,
321 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100322 test3-gpios =
323 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
324 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
325 <&gpio_c 2 GPIO_OUT>,
326 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
327 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200328 <&gpio_c 5 GPIO_IN>,
329 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
330 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530331 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
332 test5-gpios = <&gpio_a 19>;
333
Simon Glass73025392021-10-23 17:26:04 -0600334 bool-value;
Stefan Herbrechtsmeier1b090e62022-06-14 15:21:30 +0200335 int8-value = /bits/ 8 <0x12>;
336 int16-value = /bits/ 16 <0x1234>;
Simon Glass6df01f92018-12-10 10:37:37 -0700337 int-value = <1234>;
338 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200339 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200340 int-array = <5678 9123 4567>;
Michal Simek08a194e2023-08-25 11:37:46 +0200341 int64-array = /bits/ 64 <0x1111222233334444 0x4444333322221111>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600342 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700343 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600344 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200345 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Christian Marangia1a1e0e2024-11-10 12:50:23 +0100346 phandle-nodes = <&phandle_node_1>, <&phandle_node_2>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530347
348 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
349 <&muxcontroller0 2>, <&muxcontroller0 3>,
350 <&muxcontroller1>;
351 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
352 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100353 display-timings {
354 timing0: 240x320 {
355 clock-frequency = <6500000>;
356 hactive = <240>;
357 vactive = <320>;
358 hfront-porch = <6>;
359 hback-porch = <7>;
360 hsync-len = <1>;
361 vback-porch = <5>;
362 vfront-porch = <8>;
363 vsync-len = <2>;
364 hsync-active = <1>;
365 vsync-active = <0>;
366 de-active = <1>;
367 pixelclk-active = <1>;
368 interlaced;
369 doublescan;
370 doubleclk;
371 };
372 timing1: 480x800 {
373 clock-frequency = <9000000>;
374 hactive = <480>;
375 vactive = <800>;
376 hfront-porch = <10>;
377 hback-porch = <59>;
378 hsync-len = <12>;
379 vback-porch = <15>;
380 vfront-porch = <17>;
381 vsync-len = <16>;
382 hsync-active = <0>;
383 vsync-active = <1>;
384 de-active = <0>;
385 pixelclk-active = <0>;
386 };
387 timing2: 800x480 {
388 clock-frequency = <33500000>;
389 hactive = <800>;
390 vactive = <480>;
391 hback-porch = <89>;
392 hfront-porch = <164>;
393 vback-porch = <23>;
394 vfront-porch = <10>;
395 hsync-len = <11>;
396 vsync-len = <13>;
397 };
398 };
Raphael Gallais-Poua853b922023-05-11 16:36:52 +0200399 panel-timing {
Nikhil M Jainbb9d1312023-01-31 15:35:15 +0530400 clock-frequency = <6500000>;
401 hactive = <240>;
402 vactive = <320>;
403 hfront-porch = <6>;
404 hback-porch = <7>;
405 hsync-len = <1>;
406 vback-porch = <5>;
407 vfront-porch = <8>;
408 vsync-len = <2>;
409 hsync-active = <1>;
410 vsync-active = <0>;
411 de-active = <1>;
412 pixelclk-active = <1>;
413 interlaced;
414 doublescan;
415 doubleclk;
416 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700417 };
418
419 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600420 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700421 compatible = "not,compatible";
422 };
423
424 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600425 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700426 };
427
Simon Glass5620cf82018-10-01 12:22:40 -0600428 backlight: backlight {
429 compatible = "pwm-backlight";
430 enable-gpios = <&gpio_a 1>;
431 power-supply = <&ldo_1>;
432 pwms = <&pwm 0 1000>;
433 default-brightness-level = <5>;
434 brightness-levels = <0 16 32 64 128 170 202 234 255>;
435 };
436
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200437 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200438 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200439 bind-test-child1 {
440 compatible = "sandbox,phy";
441 #phy-cells = <1>;
442 };
443
444 bind-test-child2 {
445 compatible = "simple-bus";
446 };
447 };
448
Simon Glassb2c1cac2014-02-26 15:59:21 -0700449 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600450 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700451 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600452 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700453 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530454
455 mux-controls = <&muxcontroller0 0>;
456 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700457 };
458
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200459 phy_provider0: gen_phy@0 {
460 compatible = "sandbox,phy";
461 #phy-cells = <1>;
462 };
463
464 phy_provider1: gen_phy@1 {
465 compatible = "sandbox,phy";
466 #phy-cells = <0>;
467 broken;
468 };
469
developer71092972020-05-02 11:35:12 +0200470 phy_provider2: gen_phy@2 {
471 compatible = "sandbox,phy";
472 #phy-cells = <0>;
473 };
474
Jonas Karlman9f89e682023-08-31 22:16:35 +0000475 phy_provider3: gen_phy@3 {
476 compatible = "sandbox,phy";
477 #phy-cells = <2>;
478 };
479
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200480 gen_phy_user: gen_phy_user {
481 compatible = "simple-bus";
482 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
483 phy-names = "phy1", "phy2", "phy3";
484 };
485
developer71092972020-05-02 11:35:12 +0200486 gen_phy_user1: gen_phy_user1 {
487 compatible = "simple-bus";
488 phys = <&phy_provider0 0>, <&phy_provider2>;
489 phy-names = "phy1", "phy2";
490 };
491
Jonas Karlman9f89e682023-08-31 22:16:35 +0000492 gen_phy_user2: gen_phy_user2 {
493 compatible = "simple-bus";
494 phys = <&phy_provider3 0 0>;
495 phy-names = "phy1";
496 };
497
Simon Glassb2c1cac2014-02-26 15:59:21 -0700498 some-bus {
499 #address-cells = <1>;
500 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600501 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600502 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600503 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700504 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600505 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700506 compatible = "denx,u-boot-fdt-test";
507 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600508 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700509 ping-add = <5>;
510 };
Simon Glass40717422014-07-23 06:55:18 -0600511 c-test@0 {
512 compatible = "denx,u-boot-fdt-test";
513 reg = <0>;
514 ping-expect = <6>;
515 ping-add = <6>;
516 };
517 c-test@1 {
518 compatible = "denx,u-boot-fdt-test";
519 reg = <1>;
520 ping-expect = <7>;
521 ping-add = <7>;
522 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700523 };
524
525 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600526 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600527 ping-expect = <6>;
528 ping-add = <6>;
529 compatible = "google,another-fdt-test";
530 };
531
532 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600533 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600534 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700535 ping-add = <6>;
536 compatible = "google,another-fdt-test";
537 };
538
Simon Glass0ccb0972015-01-25 08:27:05 -0700539 f-test {
Patrick Rudolph0fe88cc2024-10-23 15:20:05 +0200540 #interrupt-cells = <2>;
541 interrupt-parent = <&irq>;
542 interrupts = <4 0>;
Simon Glass0ccb0972015-01-25 08:27:05 -0700543 compatible = "denx,u-boot-fdt-test";
544 };
545
546 g-test {
547 compatible = "denx,u-boot-fdt-test";
548 };
549
Bin Mengd9d24782018-10-10 22:07:01 -0700550 h-test {
551 compatible = "denx,u-boot-fdt-test1";
552 };
553
developercf8bc132020-05-02 11:35:10 +0200554 i-test {
555 compatible = "mediatek,u-boot-fdt-test";
556 #address-cells = <1>;
557 #size-cells = <0>;
558
559 subnode@0 {
560 reg = <0>;
561 };
562
563 subnode@1 {
564 reg = <1>;
565 };
566
567 subnode@2 {
568 reg = <2>;
569 };
570 };
571
Simon Glass204675c2019-12-29 21:19:25 -0700572 devres-test {
573 compatible = "denx,u-boot-devres-test";
574 };
575
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530576 another-test {
577 reg = <0 2>;
578 compatible = "denx,u-boot-fdt-test";
579 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
580 test5-gpios = <&gpio_a 19>;
581 };
582
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100583 mmio-bus@0 {
584 #address-cells = <1>;
585 #size-cells = <1>;
586 compatible = "denx,u-boot-test-bus";
587 dma-ranges = <0x10000000 0x00000000 0x00040000>;
588
589 subnode@0 {
590 compatible = "denx,u-boot-fdt-test";
591 };
592 };
593
594 mmio-bus@1 {
595 #address-cells = <1>;
596 #size-cells = <1>;
597 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100598
599 subnode@0 {
600 compatible = "denx,u-boot-fdt-test";
601 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100602 };
603
Simon Glass3c601b12020-07-07 13:12:06 -0600604 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600605 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600606 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600607 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600608 child {
609 compatible = "denx,u-boot-acpi-test";
610 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600611 };
612
Simon Glass3c601b12020-07-07 13:12:06 -0600613 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600614 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600615 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600616 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600617 };
618
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200619 clocks {
620 clk_fixed: clk-fixed {
621 compatible = "fixed-clock";
622 #clock-cells = <0>;
623 clock-frequency = <1234>;
624 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000625
626 clk_fixed_factor: clk-fixed-factor {
627 compatible = "fixed-factor-clock";
628 #clock-cells = <0>;
629 clock-div = <3>;
630 clock-mult = <2>;
631 clocks = <&clk_fixed>;
632 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200633
634 osc {
635 compatible = "fixed-clock";
636 #clock-cells = <0>;
637 clock-frequency = <20000000>;
638 };
Stephen Warrena9622432016-06-17 09:44:00 -0600639 };
640
641 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600642 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600643 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200644 assigned-clocks = <&clk_sandbox 3>;
645 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600646 };
647
648 clk-test {
649 compatible = "sandbox,clk-test";
650 clocks = <&clk_fixed>,
651 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200652 <&clk_sandbox 0>,
Yang Xiwene89289c2023-12-16 02:28:52 +0800653 <&ccf 11>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200654 <&clk_sandbox 3>,
655 <&clk_sandbox 2>;
Yang Xiwene89289c2023-12-16 02:28:52 +0800656 clock-names = "fixed", "i2c", "spi", "i2c_root", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600657 };
658
Ashok Reddy Soma8f03cef2023-08-30 10:31:42 +0200659 clk-test2 {
660 compatible = "sandbox,clk-test";
661 assigned-clock-rates = <321>;
662 };
663
664 clk-test3 {
665 compatible = "sandbox,clk-test";
666 assigned-clocks = <&clk_sandbox 1>;
667 };
668
669 clk-test4 {
670 compatible = "sandbox,clk-test";
671 assigned-clock-rates = <654>, <321>;
672 assigned-clocks = <&clk_sandbox 1>;
673 };
674
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200675 ccf: clk-ccf {
676 compatible = "sandbox,clk-ccf";
Yang Xiwene89289c2023-12-16 02:28:52 +0800677 #clock-cells = <1>;
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200678 };
679
Simon Glass507ab962021-12-04 08:56:31 -0700680 efi-media {
681 compatible = "sandbox,efi-media";
682 };
683
Simon Glass5b968632015-05-22 15:42:15 -0600684 eth@10002000 {
685 compatible = "sandbox,eth";
686 reg = <0x10002000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600687 };
688
689 eth_5: eth@10003000 {
690 compatible = "sandbox,eth";
691 reg = <0x10003000 0x1000>;
Sean Anderson13652b82022-05-05 13:11:44 -0400692 nvmem-cells = <&eth5_addr>;
693 nvmem-cell-names = "mac-address";
Simon Glass5b968632015-05-22 15:42:15 -0600694 };
695
Bin Meng04a11cb2015-08-27 22:25:53 -0700696 eth_3: sbe5 {
697 compatible = "sandbox,eth";
698 reg = <0x10005000 0x1000>;
Sean Andersone2dc0e62022-05-05 13:11:42 -0400699 nvmem-cells = <&eth3_addr>;
700 nvmem-cell-names = "mac-address";
Bin Meng04a11cb2015-08-27 22:25:53 -0700701 };
702
Simon Glass5b968632015-05-22 15:42:15 -0600703 eth@10004000 {
704 compatible = "sandbox,eth";
705 reg = <0x10004000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600706 };
707
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200708 phy_eth0: phy-test-eth {
709 compatible = "sandbox,eth";
710 reg = <0x10007000 0x1000>;
Sean Anderson24b1b8d2022-05-05 13:11:35 -0400711 mac-address = [ 02 00 11 22 33 49 ];
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200712 phy-handle = <&ethphy1>;
Marek Behúnbc194772022-04-07 00:33:01 +0200713 phy-mode = "2500base-x";
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200714 };
715
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800716 dsa_eth0: dsa-test-eth {
717 compatible = "sandbox,eth";
718 reg = <0x10006000 0x1000>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400719 nvmem-cells = <&eth4_addr>;
720 nvmem-cell-names = "mac-address";
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800721 };
722
723 dsa-test {
724 compatible = "sandbox,dsa";
725
726 ports {
727 #address-cells = <1>;
728 #size-cells = <0>;
729 swp_0: port@0 {
730 reg = <0>;
731 label = "lan0";
732 phy-mode = "rgmii-rxid";
733
734 fixed-link {
735 speed = <100>;
736 full-duplex;
737 };
738 };
739
740 swp_1: port@1 {
741 reg = <1>;
742 label = "lan1";
743 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800744 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800745 };
746
747 port@2 {
748 reg = <2>;
749 ethernet = <&dsa_eth0>;
750
751 fixed-link {
752 speed = <1000>;
753 full-duplex;
754 };
755 };
756 };
757 };
758
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700759 firmware {
760 sandbox_firmware: sandbox-firmware {
761 compatible = "sandbox,firmware";
762 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200763
Etienne Carriere09665cb2022-02-21 09:22:39 +0100764 scmi {
Etienne Carriere02fd1262020-09-09 18:44:00 +0200765 compatible = "sandbox,scmi-agent";
766 #address-cells = <1>;
767 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200768
AKASHI Takahiro535a7bd2023-10-16 14:39:45 +0900769 pwrdom_scmi: protocol@11 {
770 reg = <0x11>;
771 #power-domain-cells = <1>;
772 };
773
Etienne Carriere09665cb2022-02-21 09:22:39 +0100774 clk_scmi: protocol@14 {
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200775 reg = <0x14>;
776 #clock-cells = <1>;
AKASHI Takahirocc4ecda2023-10-11 19:06:59 +0900777 linaro,sandbox-channel-id = <0x14>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200778 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200779
Etienne Carriere09665cb2022-02-21 09:22:39 +0100780 reset_scmi: protocol@16 {
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200781 reg = <0x16>;
782 #reset-cells = <1>;
783 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100784
785 protocol@17 {
786 reg = <0x17>;
787
788 regulators {
789 #address-cells = <1>;
790 #size-cells = <0>;
791
Etienne Carriere09665cb2022-02-21 09:22:39 +0100792 regul0_scmi: reg@0 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100793 reg = <0>;
794 regulator-name = "sandbox-voltd0";
795 regulator-min-microvolt = <1100000>;
796 regulator-max-microvolt = <3300000>;
797 };
Etienne Carriere09665cb2022-02-21 09:22:39 +0100798 regul1_scmi: reg@1 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100799 reg = <0x1>;
800 regulator-name = "sandbox-voltd1";
801 regulator-min-microvolt = <1800000>;
802 };
803 };
804 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200805 };
Alexey Romanov9dc617d2023-09-21 11:13:36 +0300806
807 sm: secure-monitor {
808 compatible = "sandbox,sm";
809 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700810 };
811
Alexander Dahl6ac319d2022-09-30 14:04:30 +0200812 fpga {
813 compatible = "sandbox,fpga";
814 };
815
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100816 pinctrl-gpio {
817 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700818
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100819 gpio_a: base-gpios {
820 compatible = "sandbox,gpio";
821 gpio-controller;
822 #gpio-cells = <1>;
823 gpio-bank-name = "a";
Heiko Schocher350d2522025-01-28 14:52:46 +0100824 sandbox,gpio-count = <25>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200825 hog_input_active_low {
826 gpio-hog;
827 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200828 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200829 };
830 hog_input_active_high {
831 gpio-hog;
832 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200833 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200834 };
835 hog_output_low {
836 gpio-hog;
837 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200838 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200839 };
840 hog_output_high {
841 gpio-hog;
842 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200843 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200844 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100845 };
846
847 gpio_b: extra-gpios {
848 compatible = "sandbox,gpio";
849 gpio-controller;
850 #gpio-cells = <5>;
851 gpio-bank-name = "b";
852 sandbox,gpio-count = <10>;
853 };
Simon Glass25348a42014-10-13 23:42:11 -0600854
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100855 gpio_c: pinmux-gpios {
856 compatible = "sandbox,gpio";
857 gpio-controller;
858 #gpio-cells = <2>;
859 gpio-bank-name = "c";
860 sandbox,gpio-count = <10>;
861 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100862 };
863
Simon Glass7df766e2014-12-10 08:55:55 -0700864 i2c@0 {
865 #address-cells = <1>;
866 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600867 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700868 compatible = "sandbox,i2c";
869 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200870 pinctrl-names = "default";
871 pinctrl-0 = <&pinmux_i2c0_pins>;
872
Simon Glass7df766e2014-12-10 08:55:55 -0700873 eeprom@2c {
Sean Andersone2dc0e62022-05-05 13:11:42 -0400874 #address-cells = <1>;
875 #size-cells = <1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700876 reg = <0x2c>;
877 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700878 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200879 partitions {
880 compatible = "fixed-partitions";
881 #address-cells = <1>;
882 #size-cells = <1>;
883 bootcount_i2c: bootcount@10 {
884 reg = <10 2>;
885 };
886 };
Sean Andersone2dc0e62022-05-05 13:11:42 -0400887
888 eth3_addr: mac-address@24 {
889 reg = <24 6>;
890 };
Simon Glass7df766e2014-12-10 08:55:55 -0700891 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200892
Simon Glass336b2952015-05-22 15:42:17 -0600893 rtc_0: rtc@43 {
Sean Anderson5768e8b2022-05-05 13:11:43 -0400894 #address-cells = <1>;
895 #size-cells = <1>;
Simon Glass336b2952015-05-22 15:42:17 -0600896 reg = <0x43>;
897 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700898 sandbox,emul = <&emul0>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400899
900 eth4_addr: mac-address@40 {
901 reg = <0x40 6>;
902 };
Simon Glass336b2952015-05-22 15:42:17 -0600903 };
904
905 rtc_1: rtc@61 {
906 reg = <0x61>;
907 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700908 sandbox,emul = <&emul1>;
909 };
910
911 i2c_emul: emul {
912 reg = <0xff>;
913 compatible = "sandbox,i2c-emul-parent";
914 emul_eeprom: emul-eeprom {
915 compatible = "sandbox,i2c-eeprom";
916 sandbox,filename = "i2c.bin";
917 sandbox,size = <256>;
918 };
919 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700920 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700921 };
922 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700923 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600924 };
925 };
926
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200927 sandbox_pmic: sandbox_pmic {
928 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700929 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200930 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200931
932 mc34708: pmic@41 {
933 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700934 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200935 };
Simon Glass7df766e2014-12-10 08:55:55 -0700936 };
937
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100938 bootcount@0 {
939 compatible = "u-boot,bootcount-rtc";
940 rtc = <&rtc_1>;
941 offset = <0x13>;
942 };
943
Michal Simek4f18f922020-05-28 11:48:55 +0200944 bootcount {
945 compatible = "u-boot,bootcount-i2c-eeprom";
946 i2c-eeprom = <&bootcount_i2c>;
947 };
948
Nandor Han88895812021-06-10 15:40:38 +0300949 bootcount_4@0 {
950 compatible = "u-boot,bootcount-syscon";
951 syscon = <&syscon0>;
952 reg = <0x0 0x04>, <0x0 0x04>;
953 reg-names = "syscon_reg", "offset";
954 };
955
956 bootcount_2@0 {
957 compatible = "u-boot,bootcount-syscon";
958 syscon = <&syscon0>;
959 reg = <0x0 0x04>, <0x0 0x02> ;
960 reg-names = "syscon_reg", "offset";
961 };
962
Marek Szyprowskiad398592021-02-18 11:33:18 +0100963 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100964 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100965 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100966 vdd-supply = <&buck2>;
967 vss-microvolts = <0>;
968 };
969
Mark Kettenis67748ee2021-10-23 16:58:02 +0200970 iommu: iommu@0 {
971 compatible = "sandbox,iommu";
972 #iommu-cells = <0>;
973 };
974
Simon Glass515dcff2020-02-06 09:55:00 -0700975 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700976 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700977 interrupt-controller;
978 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700979 };
980
Simon Glass90b6fef2016-01-18 19:52:26 -0700981 lcd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700982 bootph-all;
Simon Glass90b6fef2016-01-18 19:52:26 -0700983 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200984 pinctrl-names = "default";
985 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700986 xres = <1366>;
987 yres = <768>;
988 };
989
Simon Glassd783eb32015-07-06 12:54:34 -0600990 leds {
991 compatible = "gpio-leds";
992
Christian Marangifd53ad42024-11-10 12:50:27 +0100993 sandbox_led_red: iracibble {
Simon Glassd783eb32015-07-06 12:54:34 -0600994 gpios = <&gpio_a 1 0>;
995 label = "sandbox:red";
996 };
997
Christian Marangifd53ad42024-11-10 12:50:27 +0100998 sandbox_led_green: martinet {
Simon Glassd783eb32015-07-06 12:54:34 -0600999 gpios = <&gpio_a 2 0>;
1000 label = "sandbox:green";
1001 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +02001002
1003 default_on {
1004 gpios = <&gpio_a 5 0>;
1005 label = "sandbox:default_on";
1006 default-state = "on";
1007 };
1008
1009 default_off {
1010 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -04001011 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +02001012 default-state = "off";
1013 };
Heiko Schocher350d2522025-01-28 14:52:46 +01001014
1015 led-20 {
1016 gpios = <&gpio_a 20 0>;
1017 /* label intentionally omitted */
1018 function = LED_FUNCTION_STATUS;
1019 color = <LED_COLOR_ID_RED>;
1020 function-enumerator = <20>;
1021 };
1022
1023 led-21 {
1024 gpios = <&gpio_a 21 0>;
1025 /* label intentionally omitted */
1026 function = LED_FUNCTION_STATUS;
1027 color = <LED_COLOR_ID_GREEN>;
1028 };
1029
1030 led-22 {
1031 gpios = <&gpio_a 22 0>;
1032 /* label intentionally omitted */
1033 function = LED_FUNCTION_STATUS;
1034 };
1035
1036 led-23 {
1037 gpios = <&gpio_a 23 0>;
1038 /* label intentionally omitted */
1039 color = <LED_COLOR_ID_GREEN>;
1040 };
1041
1042 led-24 {
1043 gpios = <&gpio_a 24 0>;
1044 label = "sandbox:function";
1045 function = LED_FUNCTION_STATUS;
1046 color = <LED_COLOR_ID_GREEN>;
1047 };
Simon Glassd783eb32015-07-06 12:54:34 -06001048 };
1049
Paul Doelle709f0372022-07-04 09:00:25 +00001050 wdt-gpio-toggle {
Simon Glasse0f8cd22023-08-10 09:53:13 -06001051 gpios = <&gpio_a 8 0>;
Rasmus Villemoes2b673872021-08-19 11:57:05 +02001052 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001053 hw_margin_ms = <100>;
Paul Doelle709f0372022-07-04 09:00:25 +00001054 hw_algo = "toggle";
1055 always-running;
1056 };
1057
1058 wdt-gpio-level {
1059 gpios = <&gpio_a 7 0>;
1060 compatible = "linux,wdt-gpio";
1061 hw_margin_ms = <100>;
1062 hw_algo = "level";
Rasmus Villemoes2b673872021-08-19 11:57:05 +02001063 always-running;
1064 };
1065
Stephen Warren62f2c902016-05-16 17:41:37 -06001066 mbox: mbox {
1067 compatible = "sandbox,mbox";
1068 #mbox-cells = <1>;
1069 };
1070
1071 mbox-test {
1072 compatible = "sandbox,mbox-test";
1073 mboxes = <&mbox 100>, <&mbox 1>;
1074 mbox-names = "other", "test";
1075 };
1076
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001077 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001078 #address-cells = <1>;
1079 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -04001080 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001081 cpu1: cpu@1 {
1082 device_type = "cpu";
1083 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -04001084 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001085 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001086 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001087 };
Mario Sixdea5df72018-08-06 10:23:44 +02001088
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001089 cpu2: cpu@2 {
1090 device_type = "cpu";
1091 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001092 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001093 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001094 };
Mario Sixdea5df72018-08-06 10:23:44 +02001095
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001096 cpu3: cpu@3 {
1097 device_type = "cpu";
1098 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001099 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001100 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001101 };
Mario Sixdea5df72018-08-06 10:23:44 +02001102 };
1103
Dave Gerlach75dbdfc2020-07-15 23:39:58 -05001104 chipid: chipid {
1105 compatible = "sandbox,soc";
1106 };
1107
Simon Glassc953aaf2018-12-10 10:37:34 -07001108 i2s: i2s {
1109 compatible = "sandbox,i2s";
1110 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -07001111 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -07001112 };
1113
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +02001114 nop-test_0 {
1115 compatible = "sandbox,nop_sandbox1";
1116 nop-test_1 {
1117 compatible = "sandbox,nop_sandbox2";
1118 bind = "True";
1119 };
1120 nop-test_2 {
1121 compatible = "sandbox,nop_sandbox2";
1122 bind = "False";
1123 };
1124 };
1125
Roger Quadrosb0679a72022-10-20 16:30:46 +03001126 memory-controller {
1127 compatible = "sandbox,memory";
1128 };
1129
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001130 misc-test {
Sean Anderson13652b82022-05-05 13:11:44 -04001131 #address-cells = <1>;
1132 #size-cells = <1>;
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001133 compatible = "sandbox,misc_sandbox";
Sean Anderson13652b82022-05-05 13:11:44 -04001134
1135 eth5_addr: mac-address@10 {
1136 reg = <0x10 6>;
1137 };
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001138 };
1139
Simon Glasse4fef742017-04-23 20:02:07 -06001140 mmc2 {
1141 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -06001142 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -06001143 };
1144
Simon Glassb255efc2022-04-24 23:31:24 -06001145 /* This is used for the bootdev tests */
Simon Glasse4fef742017-04-23 20:02:07 -06001146 mmc1 {
1147 compatible = "sandbox,mmc";
Simon Glassb255efc2022-04-24 23:31:24 -06001148 filename = "mmc1.img";
Simon Glasse4fef742017-04-23 20:02:07 -06001149 };
1150
Simon Glassb255efc2022-04-24 23:31:24 -06001151 /* This is used for the fastboot tests */
Sughosh Ganu77079e72022-10-21 18:16:05 +05301152 mmc0: mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -06001153 compatible = "sandbox,mmc";
1154 };
1155
Simon Glassf1eba352022-10-20 18:23:20 -06001156 /* This is used for VBE VPL tests */
1157 mmc3 {
1158 status = "disabled";
1159 compatible = "sandbox,mmc";
1160 filename = "image.bin";
1161 non-removable;
1162 };
1163
Simon Glassd2bc33ed2023-01-06 08:52:41 -06001164 /* This is used for bootstd bootmenu tests */
1165 mmc4 {
1166 status = "disabled";
1167 compatible = "sandbox,mmc";
1168 filename = "mmc4.img";
1169 };
1170
Simon Glassfff928c2023-08-24 13:55:41 -06001171 /* This is used for ChromiumOS tests */
1172 mmc5 {
1173 status = "disabled";
1174 compatible = "sandbox,mmc";
1175 filename = "mmc5.img";
1176 };
1177
Alexander Gendin038cb022023-10-09 01:24:36 +00001178 /* This is used for mbr tests */
1179 mmc6 {
1180 status = "disabled";
1181 compatible = "sandbox,mmc";
1182 filename = "mmc6.img";
1183 };
1184
Guillaume La Roque368ad9e2024-11-26 09:06:13 +01001185 /* This is used for Android boot image v4 tests */
Mattijs Korpershoekd77f8152024-07-10 10:40:06 +02001186 mmc7 {
1187 status = "disabled";
1188 compatible = "sandbox,mmc";
1189 filename = "mmc7.img";
1190 };
1191
Guillaume La Roque368ad9e2024-11-26 09:06:13 +01001192 /* This is used for Android boot image v2 tests. */
1193 mmc8 {
1194 status = "disabled";
1195 compatible = "sandbox,mmc";
1196 filename = "mmc8.img";
1197 };
1198
Simon Glass53a68b32019-02-16 20:24:50 -07001199 pch {
1200 compatible = "sandbox,pch";
1201 };
1202
Tom Rini4a3ca482020-02-11 12:41:23 -05001203 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -07001204 compatible = "sandbox,pci";
1205 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001206 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001207 #address-cells = <3>;
1208 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -06001209 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -07001210 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Mark Kettenis5dfd4ec2023-01-21 20:27:57 +01001211 iommu-map = <0x0010 &iommu 0 1>;
1212 iommu-map-mask = <0xfffffff8>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001213 pci@0,0 {
1214 compatible = "pci-generic";
1215 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001216 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001217 };
Alex Margineanf1274432019-06-07 11:24:24 +03001218 pci@1,0 {
1219 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001220 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
Simon Glass4289c262023-09-26 08:14:58 -06001221 reg = <0x02000814 0 0 0x80 0
1222 0x01000810 0 0 0xc0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001223 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +03001224 };
Simon Glass937bb472019-12-06 21:41:57 -07001225 p2sb-pci@2,0 {
1226 compatible = "sandbox,p2sb";
1227 reg = <0x02001010 0 0 0 0>;
1228 sandbox,emul = <&p2sb_emul>;
1229
1230 adder {
1231 intel,p2sb-port-id = <3>;
1232 compatible = "sandbox,adder";
1233 };
1234 };
Simon Glass8c501022019-12-06 21:41:54 -07001235 pci@1e,0 {
1236 compatible = "sandbox,pmc";
1237 reg = <0xf000 0 0 0 0>;
1238 sandbox,emul = <&pmc_emul1e>;
1239 acpi-base = <0x400>;
1240 gpe0-dwx-mask = <0xf>;
1241 gpe0-dwx-shift-base = <4>;
1242 gpe0-dw = <6 7 9>;
1243 gpe0-sts = <0x20>;
1244 gpe0-en = <0x30>;
1245 };
Simon Glass3a6eae62015-03-05 12:25:34 -07001246 pci@1f,0 {
1247 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001248 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
Simon Glass4289c262023-09-26 08:14:58 -06001249 reg = <0x0100f810 0 0 0x100 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001250 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001251 };
1252 };
1253
Simon Glassb98ba4c2019-09-25 08:56:10 -06001254 pci-emul0 {
1255 compatible = "sandbox,pci-emul-parent";
1256 swap_case_emul0_0: emul0@0,0 {
1257 compatible = "sandbox,swap-case";
1258 };
1259 swap_case_emul0_1: emul0@1,0 {
1260 compatible = "sandbox,swap-case";
1261 use-ea;
1262 };
1263 swap_case_emul0_1f: emul0@1f,0 {
1264 compatible = "sandbox,swap-case";
1265 };
Simon Glass937bb472019-12-06 21:41:57 -07001266 p2sb_emul: emul@2,0 {
1267 compatible = "sandbox,p2sb-emul";
1268 };
Simon Glass8c501022019-12-06 21:41:54 -07001269 pmc_emul1e: emul@1e,0 {
1270 compatible = "sandbox,pmc-emul";
1271 };
Simon Glassb98ba4c2019-09-25 08:56:10 -06001272 };
1273
Tom Rini4a3ca482020-02-11 12:41:23 -05001274 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -07001275 compatible = "sandbox,pci";
1276 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001277 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -07001278 #address-cells = <3>;
1279 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001280 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scullc7456a42022-04-21 16:11:09 +00001281 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001282 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -07001283 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +02001284 0x0c 0x00 0x1234 0x5678
1285 0x10 0x00 0x1234 0x5678>;
1286 pci@10,0 {
1287 reg = <0x8000 0 0 0 0>;
1288 };
Bin Meng408e5902018-08-03 01:14:41 -07001289 };
1290
Tom Rini4a3ca482020-02-11 12:41:23 -05001291 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -07001292 compatible = "sandbox,pci";
1293 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001294 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -07001295 #address-cells = <3>;
1296 #size-cells = <2>;
1297 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1298 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1299 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1300 pci@1f,0 {
1301 compatible = "pci-generic";
1302 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001303 sandbox,emul = <&swap_case_emul2_1f>;
1304 };
1305 };
1306
1307 pci-emul2 {
1308 compatible = "sandbox,pci-emul-parent";
1309 swap_case_emul2_1f: emul2@1f,0 {
1310 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001311 };
1312 };
1313
Ramon Friedc64f19b2019-04-27 11:15:23 +03001314 pci_ep: pci_ep {
1315 compatible = "sandbox,pci_ep";
1316 };
1317
Simon Glass9c433fe2017-04-23 20:10:44 -06001318 probing {
1319 compatible = "simple-bus";
1320 test1 {
1321 compatible = "denx,u-boot-probe-test";
1322 };
1323
1324 test2 {
1325 compatible = "denx,u-boot-probe-test";
1326 };
1327
1328 test3 {
1329 compatible = "denx,u-boot-probe-test";
1330 };
1331
1332 test4 {
1333 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001334 first-syscon = <&syscon0>;
1335 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001336 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001337 };
1338 };
1339
Stephen Warren92c67fa2016-07-13 13:45:31 -06001340 pwrdom: power-domain {
1341 compatible = "sandbox,power-domain";
1342 #power-domain-cells = <1>;
1343 };
1344
1345 power-domain-test {
1346 compatible = "sandbox,power-domain-test";
1347 power-domains = <&pwrdom 2>;
1348 };
1349
Simon Glass5620cf82018-10-01 12:22:40 -06001350 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001351 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001352 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001353 pinctrl-names = "default";
1354 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001355 };
1356
1357 pwm2 {
1358 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001359 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001360 };
1361
Simon Glass3d355e62015-07-06 12:54:31 -06001362 ram {
1363 compatible = "sandbox,ram";
1364 };
1365
Simon Glassd860f222015-07-06 12:54:29 -06001366 reset@0 {
1367 compatible = "sandbox,warm-reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001368 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001369 };
1370
1371 reset@1 {
1372 compatible = "sandbox,reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001373 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001374 };
1375
Stephen Warren6488e642016-06-17 09:43:59 -06001376 resetc: reset-ctl {
1377 compatible = "sandbox,reset-ctl";
1378 #reset-cells = <1>;
1379 };
1380
1381 reset-ctl-test {
1382 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001383 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1384 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001385 };
1386
Sughosh Ganu23e37512019-12-28 23:58:31 +05301387 rng {
1388 compatible = "sandbox,sandbox-rng";
1389 };
1390
Nishanth Menonedf85812015-09-17 15:42:41 -05001391 rproc_1: rproc@1 {
1392 compatible = "sandbox,test-processor";
1393 remoteproc-name = "remoteproc-test-dev1";
1394 };
1395
1396 rproc_2: rproc@2 {
1397 compatible = "sandbox,test-processor";
1398 internal-memory-mapped;
1399 remoteproc-name = "remoteproc-test-dev2";
1400 };
1401
Simon Glass5620cf82018-10-01 12:22:40 -06001402 panel {
1403 compatible = "simple-panel";
1404 backlight = <&backlight 0 100>;
1405 };
1406
Simon Glass509f32e2022-09-21 16:21:47 +02001407 scsi {
1408 compatible = "sandbox,scsi";
1409 sandbox,filepath = "scsi.img";
1410 };
1411
Ramon Fried26ed32e2018-07-02 02:57:59 +03001412 smem@0 {
1413 compatible = "sandbox,smem";
1414 };
1415
Simon Glass76072ac2018-12-10 10:37:36 -07001416 sound {
1417 compatible = "sandbox,sound";
1418 cpu {
1419 sound-dai = <&i2s 0>;
1420 };
1421
1422 codec {
1423 sound-dai = <&audio 0>;
1424 };
1425 };
1426
Simon Glass25348a42014-10-13 23:42:11 -06001427 spi@0 {
1428 #address-cells = <1>;
1429 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001430 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001431 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001432 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001433 pinctrl-names = "default";
1434 pinctrl-0 = <&pinmux_spi0_pins>;
1435
Simon Glass25348a42014-10-13 23:42:11 -06001436 spi.bin@0 {
1437 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001438 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001439 spi-max-frequency = <40000000>;
1440 sandbox,filename = "spi.bin";
1441 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001442 spi.bin@1 {
1443 reg = <1>;
1444 compatible = "spansion,m25p16", "jedec,spi-nor";
1445 spi-max-frequency = <50000000>;
1446 sandbox,filename = "spi.bin";
1447 spi-cpol;
1448 spi-cpha;
1449 };
Simon Glass25348a42014-10-13 23:42:11 -06001450 };
1451
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001452 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001453 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001454 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001455 };
1456
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001457 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001458 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001459 reg = <0x20 5
1460 0x28 6
1461 0x30 7
1462 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001463 };
1464
Patrick Delaunayee010432019-03-07 09:57:13 +01001465 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001466 compatible = "simple-mfd", "syscon";
1467 reg = <0x40 5
1468 0x48 6
1469 0x50 7
1470 0x58 8>;
1471 };
1472
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301473 syscon3: syscon@3 {
1474 compatible = "simple-mfd", "syscon";
1475 reg = <0x000100 0x10>;
1476
1477 muxcontroller0: a-mux-controller {
1478 compatible = "mmio-mux";
1479 #mux-control-cells = <1>;
1480
1481 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1482 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1483 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1484 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1485 u-boot,mux-autoprobe;
1486 };
1487 };
1488
1489 muxcontroller1: emul-mux-controller {
1490 compatible = "mux-emul";
1491 #mux-control-cells = <0>;
1492 u-boot,mux-autoprobe;
1493 idle-state = <0xabcd>;
1494 };
1495
Simon Glass791a17f2020-12-16 21:20:27 -07001496 testfdtm0 {
1497 compatible = "denx,u-boot-fdtm-test";
1498 };
1499
1500 testfdtm1: testfdtm1 {
1501 compatible = "denx,u-boot-fdtm-test";
1502 };
1503
1504 testfdtm2 {
1505 compatible = "denx,u-boot-fdtm-test";
1506 };
1507
Sean Anderson79d3bba2020-09-28 10:52:23 -04001508 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001509 compatible = "sandbox,timer";
1510 clock-frequency = <1000000>;
1511 };
1512
Sean Anderson79d3bba2020-09-28 10:52:23 -04001513 timer@1 {
1514 compatible = "sandbox,timer";
1515 sandbox,timebase-frequency-fallback;
1516 };
1517
Miquel Raynal80938c12018-05-15 11:57:27 +02001518 tpm2 {
1519 compatible = "sandbox,tpm2";
Eddie James1a55a7a2023-10-24 10:43:51 -05001520 memory-region = <&event_log>;
Miquel Raynal80938c12018-05-15 11:57:27 +02001521 };
1522
Simon Glasseef107e2023-02-21 06:24:51 -07001523 tpm {
1524 compatible = "google,sandbox-tpm";
1525 };
1526
Simon Glass5b968632015-05-22 15:42:15 -06001527 uart0: serial {
1528 compatible = "sandbox,serial";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001529 bootph-all;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001530 pinctrl-names = "default";
1531 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001532 };
1533
Simon Glass31680482015-03-25 12:23:05 -06001534 usb_0: usb@0 {
1535 compatible = "sandbox,usb";
1536 status = "disabled";
1537 hub {
1538 compatible = "sandbox,usb-hub";
1539 #address-cells = <1>;
1540 #size-cells = <0>;
1541 flash-stick {
1542 reg = <0>;
1543 compatible = "sandbox,usb-flash";
1544 };
1545 };
1546 };
1547
1548 usb_1: usb@1 {
1549 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001550 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001551 hub {
1552 compatible = "usb-hub";
1553 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001554 #address-cells = <1>;
1555 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001556 hub-emul {
1557 compatible = "sandbox,usb-hub";
1558 #address-cells = <1>;
1559 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001560 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001561 reg = <0>;
1562 compatible = "sandbox,usb-flash";
1563 sandbox,filepath = "testflash.bin";
1564 };
1565
Simon Glass4700fe52015-11-08 23:48:01 -07001566 flash-stick@1 {
1567 reg = <1>;
1568 compatible = "sandbox,usb-flash";
Simon Glass64c63252024-11-07 14:31:49 -07001569 sandbox,filepath = "flash1.img";
Simon Glass4700fe52015-11-08 23:48:01 -07001570 };
1571
1572 flash-stick@2 {
1573 reg = <2>;
1574 compatible = "sandbox,usb-flash";
1575 sandbox,filepath = "testflash2.bin";
1576 };
1577
Simon Glassc0ccc722015-11-08 23:48:08 -07001578 keyb@3 {
1579 reg = <3>;
1580 compatible = "sandbox,usb-keyb";
1581 };
1582
Simon Glass31680482015-03-25 12:23:05 -06001583 };
Michael Walle7c961322020-06-02 01:47:07 +02001584
1585 usbstor@1 {
1586 reg = <1>;
1587 };
1588 usbstor@3 {
1589 reg = <3>;
1590 };
Simon Glass31680482015-03-25 12:23:05 -06001591 };
1592 };
1593
1594 usb_2: usb@2 {
1595 compatible = "sandbox,usb";
1596 status = "disabled";
1597 };
1598
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001599 spmi: spmi@0 {
1600 compatible = "sandbox,spmi";
1601 #address-cells = <0x1>;
1602 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001603 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001604 pm8916@0 {
1605 compatible = "qcom,spmi-pmic";
1606 reg = <0x0 0x1>;
1607 #address-cells = <0x1>;
1608 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001609 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001610
1611 spmi_gpios: gpios@c000 {
1612 compatible = "qcom,pm8916-gpio";
1613 reg = <0xc000 0x400>;
Caleb Connolly1edc45f2024-01-08 15:30:51 +00001614 gpio-ranges = <&spmi_gpios 0 0 4>;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001615 gpio-controller;
1616 gpio-count = <4>;
1617 #gpio-cells = <2>;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001618 };
1619 };
1620 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001621
1622 wdt0: wdt@0 {
1623 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001624 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001625 };
Rob Clarka471b672018-01-10 11:33:30 +01001626
Mario Six95922152018-08-09 14:51:19 +02001627 axi: axi@0 {
1628 compatible = "sandbox,axi";
1629 #address-cells = <0x1>;
1630 #size-cells = <0x1>;
1631 store@0 {
1632 compatible = "sandbox,sandbox_store";
1633 reg = <0x0 0x400>;
1634 };
1635 };
1636
Rob Clarka471b672018-01-10 11:33:30 +01001637 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001638 #address-cells = <1>;
1639 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001640 setting = "sunrise ohoka";
1641 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001642 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001643 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Algapally Santosh Sagardf178992023-09-21 16:50:43 +05301644 stdout-path = "serial0:115200n8";
Rob Clarka471b672018-01-10 11:33:30 +01001645 chosen-test {
1646 compatible = "denx,u-boot-fdt-test";
1647 reg = <9 1>;
1648 };
1649 };
Mario Six35616ef2018-03-12 14:53:33 +01001650
1651 translation-test@8000 {
1652 compatible = "simple-bus";
1653 reg = <0x8000 0x4000>;
1654
1655 #address-cells = <0x2>;
1656 #size-cells = <0x1>;
1657
1658 ranges = <0 0x0 0x8000 0x1000
1659 1 0x100 0x9000 0x1000
1660 2 0x200 0xA000 0x1000
1661 3 0x300 0xB000 0x1000
1662 >;
1663
Fabien Dessenne22236e02019-05-31 15:11:30 +02001664 dma-ranges = <0 0x000 0x10000000 0x1000
1665 1 0x100 0x20000000 0x1000
1666 >;
1667
Mario Six35616ef2018-03-12 14:53:33 +01001668 dev@0,0 {
1669 compatible = "denx,u-boot-fdt-dummy";
1670 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +01001671 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001672 };
1673
1674 dev@1,100 {
1675 compatible = "denx,u-boot-fdt-dummy";
1676 reg = <1 0x100 0x1000>;
1677
1678 };
1679
1680 dev@2,200 {
1681 compatible = "denx,u-boot-fdt-dummy";
1682 reg = <2 0x200 0x1000>;
1683 };
1684
1685
1686 noxlatebus@3,300 {
1687 compatible = "simple-bus";
1688 reg = <3 0x300 0x1000>;
1689
1690 #address-cells = <0x1>;
1691 #size-cells = <0x0>;
1692
1693 dev@42 {
1694 compatible = "denx,u-boot-fdt-dummy";
1695 reg = <0x42>;
1696 };
1697 };
1698 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001699
Dzmitry Sankouski54f4c832023-01-22 18:21:23 +03001700 ofnode-foreach {
1701 compatible = "foreach";
1702
1703 first {
1704 prop1 = <1>;
1705 prop2 = <2>;
1706 };
1707
1708 second {
1709 prop1 = <1>;
1710 prop2 = <2>;
1711 };
1712 };
1713
Mario Six02ad6fb2018-09-27 09:19:31 +02001714 osd {
1715 compatible = "sandbox,sandbox_osd";
1716 };
Tom Rinib93eea72018-09-30 18:16:51 -04001717
Jens Wiklander86afaa62018-09-25 16:40:16 +02001718 sandbox_tee {
1719 compatible = "sandbox,tee";
1720 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001721
1722 sandbox_virtio1 {
1723 compatible = "sandbox,virtio1";
Simon Glass8de5a542023-01-17 10:47:51 -07001724 virtio-type = <4>; /* rng */
Bin Meng1bb290d2018-10-15 02:21:26 -07001725 };
1726
1727 sandbox_virtio2 {
1728 compatible = "sandbox,virtio2";
1729 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001730
Simon Glass8de5a542023-01-17 10:47:51 -07001731 sandbox-virtio-blk {
1732 compatible = "sandbox,virtio1";
1733 virtio-type = <2>; /* block */
1734 };
1735
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001736 sandbox_scmi {
1737 compatible = "sandbox,scmi-devices";
AKASHI Takahiro535a7bd2023-10-16 14:39:45 +09001738 power-domains = <&pwrdom_scmi 2>;
Etienne Carrierebf1f1322022-02-21 09:22:41 +01001739 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere09665cb2022-02-21 09:22:39 +01001740 resets = <&reset_scmi 3>;
1741 regul0-supply = <&regul0_scmi>;
1742 regul1-supply = <&regul1_scmi>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001743 };
1744
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001745 pinctrl {
1746 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001747
Sean Anderson3438e3b2020-09-14 11:01:57 -04001748 pinctrl-names = "default", "alternate";
1749 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1750 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001751
Sean Anderson3438e3b2020-09-14 11:01:57 -04001752 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001753 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001754 pins = "P5";
1755 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001756 bias-pull-up;
1757 input-disable;
1758 };
1759 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001760 pins = "P6";
1761 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001762 output-high;
1763 drive-open-drain;
1764 };
1765 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001766 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001767 bias-pull-down;
1768 input-enable;
1769 };
1770 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001771 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001772 bias-disable;
1773 };
1774 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001775
1776 pinctrl_i2c: i2c {
1777 groups {
1778 groups = "I2C_UART";
1779 function = "I2C";
1780 };
1781
1782 pins {
1783 pins = "P0", "P1";
1784 drive-open-drain;
1785 };
1786 };
1787
1788 pinctrl_i2s: i2s {
1789 groups = "SPI_I2S";
1790 function = "I2S";
1791 };
1792
1793 pinctrl_spi: spi {
1794 groups = "SPI_I2S";
1795 function = "SPI";
1796
1797 cs {
1798 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1799 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1800 };
1801 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001802 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001803
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001804 pinctrl-single-no-width {
1805 compatible = "pinctrl-single";
1806 reg = <0x0000 0x238>;
1807 #pinctrl-cells = <1>;
1808 pinctrl-single,function-mask = <0x7f>;
1809 };
1810
1811 pinctrl-single-pins {
1812 compatible = "pinctrl-single";
1813 reg = <0x0000 0x238>;
1814 #pinctrl-cells = <1>;
1815 pinctrl-single,register-width = <32>;
1816 pinctrl-single,function-mask = <0x7f>;
1817
1818 pinmux_pwm_pins: pinmux_pwm_pins {
1819 pinctrl-single,pins = < 0x48 0x06 >;
1820 };
1821
1822 pinmux_spi0_pins: pinmux_spi0_pins {
1823 pinctrl-single,pins = <
1824 0x190 0x0c
1825 0x194 0x0c
1826 0x198 0x23
1827 0x19c 0x0c
1828 >;
1829 };
1830
1831 pinmux_uart0_pins: pinmux_uart0_pins {
1832 pinctrl-single,pins = <
1833 0x70 0x30
1834 0x74 0x00
1835 >;
1836 };
1837 };
1838
1839 pinctrl-single-bits {
1840 compatible = "pinctrl-single";
1841 reg = <0x0000 0x50>;
1842 #pinctrl-cells = <2>;
1843 pinctrl-single,bit-per-mux;
1844 pinctrl-single,register-width = <32>;
1845 pinctrl-single,function-mask = <0xf>;
1846
1847 pinmux_i2c0_pins: pinmux_i2c0_pins {
1848 pinctrl-single,bits = <
1849 0x10 0x00002200 0x0000ff00
1850 >;
1851 };
1852
1853 pinmux_lcd_pins: pinmux_lcd_pins {
1854 pinctrl-single,bits = <
1855 0x40 0x22222200 0xffffff00
1856 0x44 0x22222222 0xffffffff
1857 0x48 0x00000022 0x000000ff
1858 0x48 0x02000000 0x0f000000
1859 0x4c 0x02000022 0x0f0000ff
1860 >;
1861 };
1862 };
1863
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001864 hwspinlock@0 {
1865 compatible = "sandbox,hwspinlock";
1866 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001867
1868 dma: dma {
1869 compatible = "sandbox,dma";
1870 #dma-cells = <1>;
1871
1872 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1873 dma-names = "m2m", "tx0", "rx0";
1874 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001875
Alex Marginean0649be52019-07-12 10:13:53 +03001876 /*
1877 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1878 * end of the test. If parent mdio is removed first, clean-up of the
1879 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1880 * active at the end of the test. That it turn doesn't allow the mdio
1881 * class to be destroyed, triggering an error.
1882 */
1883 mdio-mux-test {
1884 compatible = "sandbox,mdio-mux";
1885 #address-cells = <1>;
1886 #size-cells = <0>;
1887 mdio-parent-bus = <&mdio>;
1888
1889 mdio-ch-test@0 {
1890 reg = <0>;
1891 };
1892 mdio-ch-test@1 {
1893 reg = <1>;
1894 };
1895 };
1896
1897 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001898 compatible = "sandbox,mdio";
Marek Behúnf4f1ddc2022-04-07 00:32:57 +02001899 #address-cells = <1>;
1900 #size-cells = <0>;
1901
1902 ethphy1: ethernet-phy@1 {
1903 reg = <1>;
1904 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001905 };
Sean Andersonb7860542020-06-24 06:41:12 -04001906
1907 pm-bus-test {
1908 compatible = "simple-pm-bus";
1909 clocks = <&clk_sandbox 4>;
1910 power-domains = <&pwrdom 1>;
1911 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001912
1913 resetc2: syscon-reset {
1914 compatible = "syscon-reset";
1915 #reset-cells = <1>;
1916 regmap = <&syscon0>;
1917 offset = <1>;
1918 mask = <0x27FFFFFF>;
1919 assert-high = <0>;
1920 };
1921
1922 syscon-reset-test {
1923 compatible = "sandbox,misc_sandbox";
1924 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1925 reset-names = "valid", "no_mask", "out_of_range";
1926 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301927
Simon Glass458b66a2020-11-05 06:32:05 -07001928 sysinfo {
1929 compatible = "sandbox,sysinfo-sandbox";
1930 };
1931
Sean Anderson1c830672021-04-20 10:50:58 -04001932 sysinfo-gpio {
1933 compatible = "gpio-sysinfo";
1934 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1935 revisions = <19>, <5>;
1936 names = "rev_a", "foo";
1937 };
1938
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301939 some_regmapped-bus {
1940 #address-cells = <0x1>;
1941 #size-cells = <0x1>;
1942
1943 ranges = <0x0 0x0 0x10>;
1944 compatible = "simple-bus";
1945
1946 regmap-test_0 {
1947 reg = <0 0x10>;
1948 compatible = "sandbox,regmap_test";
1949 };
1950 };
Robert Marko9cf87122022-09-06 13:30:35 +02001951
1952 thermal {
1953 compatible = "sandbox,thermal";
1954 };
Sughosh Ganu77079e72022-10-21 18:16:05 +05301955
1956 fwu-mdata {
1957 compatible = "u-boot,fwu-mdata-gpt";
1958 fwu-mdata-store = <&mmc0>;
1959 };
Abdellatif El Khlifi6b005872023-04-17 10:11:55 +01001960
1961 nvmxip-qspi1@08000000 {
1962 compatible = "nvmxip,qspi";
1963 reg = <0x08000000 0x00200000>;
1964 lba_shift = <9>;
1965 lba = <4096>;
1966 };
1967
1968 nvmxip-qspi2@08200000 {
1969 compatible = "nvmxip,qspi";
1970 reg = <0x08200000 0x00100000>;
1971 lba_shift = <9>;
1972 lba = <2048>;
1973 };
Svyatoslav Ryhel669f5c82023-04-25 10:57:21 +03001974
1975 extcon {
1976 compatible = "sandbox,extcon";
1977 };
Abdellatif El Khlifi4970d5b2023-08-04 14:33:41 +01001978
1979 arm-ffa-emul {
1980 compatible = "sandbox,arm-ffa-emul";
1981
1982 sandbox-arm-ffa {
1983 compatible = "sandbox,arm-ffa";
1984 };
1985 };
Sean Anderson326422b2023-11-04 16:37:52 -04001986
1987 nand-controller {
1988 #address-cells = <1>;
1989 #size-cells = <0>;
1990 compatible = "sandbox,nand";
1991
1992 nand@0 {
1993 reg = <0>;
1994 nand-ecc-mode = "soft";
1995 sandbox,id = [00 e3];
1996 sandbox,erasesize = <(8 * 1024)>;
1997 sandbox,oobsize = <16>;
1998 sandbox,pagesize = <512>;
1999 sandbox,pages = <0x2000>;
2000 sandbox,err-count = <1>;
2001 sandbox,err-step-size = <512>;
2002 };
2003
2004 /* MT29F64G08AKABA */
2005 nand@1 {
2006 reg = <1>;
2007 nand-ecc-mode = "soft_bch";
2008 sandbox,id = [2C 48 00 26 89 00 00 00];
2009 sandbox,onfi = [
2010 4f 4e 46 49 0e 00 5a 00
2011 ff 01 00 00 00 00 03 00
2012 00 00 00 00 00 00 00 00
2013 00 00 00 00 00 00 00 00
2014 4d 49 43 52 4f 4e 20 20
2015 20 20 20 20 4d 54 32 39
2016 46 36 34 47 30 38 41 4b
2017 41 42 41 43 35 20 20 20
2018 2c 00 00 00 00 00 00 00
2019 00 00 00 00 00 00 00 00
2020 00 10 00 00 e0 00 00 02
2021 00 00 1c 00 80 00 00 00
2022 00 10 00 00 02 23 01 50
2023 00 01 05 01 00 00 04 00
2024 04 01 1e 00 00 00 00 00
2025 00 00 00 00 00 00 00 00
2026 0e 1f 00 1f 00 f4 01 ac
2027 0d 19 00 c8 00 00 00 00
2028 00 00 00 00 00 00 0a 07
2029 19 00 00 00 00 00 00 00
2030 00 00 00 00 01 00 01 00
2031 00 00 04 10 01 81 04 02
2032 02 01 1e 90 00 00 00 00
2033 00 00 00 00 00 00 00 00
2034 00 00 00 00 00 00 00 00
2035 00 00 00 00 00 00 00 00
2036 00 00 00 00 00 00 00 00
2037 00 00 00 00 00 00 00 00
2038 00 00 00 00 00 00 00 00
2039 00 00 00 00 00 00 00 00
2040 00 00 00 00 00 00 00 00
2041 00 00 00 00 00 03 20 7d
2042 ];
2043 sandbox,erasesize = <(512 * 1024)>;
2044 sandbox,oobsize = <224>;
2045 sandbox,pagesize = <4096>;
2046 sandbox,pages = <0x200000>;
2047 sandbox,err-count = <3>;
2048 sandbox,err-step-size = <512>;
2049 };
2050 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07002051};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02002052
2053#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01002054#include "cros-ec-keyboard.dtsi"
Simon Glass5e135d32022-10-20 18:23:15 -06002055
2056#ifdef CONFIG_SANDBOX_VPL
2057#include "sandbox_vpl.dtsi"
2058#endif
Simon Glass61300722023-06-01 10:23:01 -06002059
Sughosh Ganu05137922024-03-27 16:19:00 +05302060#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
2061#include "sandbox_capsule.dtsi"
2062#endif
2063
Simon Glass61300722023-06-01 10:23:01 -06002064#include "cedit.dtsi"