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Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Eddie James1a55a7a2023-10-24 10:43:51 -050012#include <config.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010013#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010015#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040016#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053017#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010018
Simon Glassb2c1cac2014-02-26 15:59:21 -070019/ {
20 model = "sandbox";
21 compatible = "sandbox";
22 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060023 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070024
Simon Glassfef72b72014-07-23 06:55:03 -060025 aliases {
26 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010027 ethernet0 = "/eth@10002000";
28 ethernet2 = &swp_0;
29 ethernet3 = &eth_3;
30 ethernet4 = &dsa_eth0;
31 ethernet5 = &eth_5;
Sean Anderson67d93a42022-05-05 13:11:30 -040032 ethernet6 = "/eth@10004000";
33 ethernet7 = &swp_1;
34 ethernet8 = &phy_eth0;
Simon Glass5620cf82018-10-01 12:22:40 -060035 gpio1 = &gpio_a;
36 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010037 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070038 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060039 mmc0 = "/mmc0";
40 mmc1 = "/mmc1";
Simon Glassf1eba352022-10-20 18:23:20 -060041 mmc2 = "/mmc2";
42 mmc3 = "/mmc3";
Simon Glassfff928c2023-08-24 13:55:41 -060043 mmc4 = "/mmc4";
44 mmc5 = "/mmc5";
Alexander Gendin038cb022023-10-09 01:24:36 +000045 mmc6 = "/mmc6";
Mattijs Korpershoekd77f8152024-07-10 10:40:06 +020046 mmc7 = "/mmc7";
Guillaume La Roque368ad9e2024-11-26 09:06:13 +010047 mmc8 = "/mmc8";
Bin Meng408e5902018-08-03 01:14:41 -070048 pci0 = &pci0;
49 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070050 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020051 remoteproc0 = &rproc_1;
52 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060053 rtc0 = &rtc_0;
54 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060055 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020056 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070057 testbus3 = "/some-bus";
58 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070059 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070060 testfdt3 = "/b-test";
61 testfdt5 = "/some-bus/c-test@5";
62 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070063 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020064 fdt-dummy0 = "/translation-test@8000/dev@0,0";
65 fdt-dummy1 = "/translation-test@8000/dev@1,100";
66 fdt-dummy2 = "/translation-test@8000/dev@2,200";
67 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060068 usb0 = &usb_0;
69 usb1 = &usb_1;
70 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020071 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020072 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060073 };
74
Eddie James1a55a7a2023-10-24 10:43:51 -050075 reserved-memory {
76 #address-cells = <1>;
77 #size-cells = <1>;
78 ranges;
79
80 event_log: tcg_event_log {
81 no-map;
Sughosh Ganu3f768682024-08-26 17:29:32 +053082 reg = <(CFG_SYS_SDRAM_BASE + 0x100000) 0x2000>;
Eddie James1a55a7a2023-10-24 10:43:51 -050083 };
84 };
85
Simon Glass5e135d32022-10-20 18:23:15 -060086 binman: binman {
Philippe Reynes462d1632022-03-28 22:56:53 +020087 };
88
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020089 config {
Simon Glass0034d962021-08-07 07:24:01 -060090 testing-bool;
91 testing-int = <123>;
92 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020093 environment {
94 from_fdt = "yes";
95 fdt_env_path = "";
96 };
97 };
98
Michal Simek43c42bd2023-08-31 08:59:05 +020099 options {
100 u-boot {
101 compatible = "u-boot,config";
102 bootscr-ram-offset = /bits/ 64 <0x12345678>;
Michal Simek6a7c1ce2023-08-31 09:04:27 +0200103 bootscr-flash-offset = /bits/ 64 <0>;
104 bootscr-flash-size = /bits/ 64 <0x2000>;
Christian Marangifd53ad42024-11-10 12:50:27 +0100105 boot-led = <&sandbox_led_green>;
106 activity-led = <&sandbox_led_red>;
Christian Marangicdc38152024-10-01 14:24:44 +0200107 testing-bool;
108 testing-int = <123>;
109 testing-str = "testing";
Christian Marangi81ce47e2024-11-10 12:50:25 +0100110 testing-phandle = <&phandle_node_1>;
Michal Simek43c42bd2023-08-31 08:59:05 +0200111 };
112 };
113
Simon Glassb255efc2022-04-24 23:31:24 -0600114 bootstd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700115 bootph-verify;
Simon Glassb255efc2022-04-24 23:31:24 -0600116 compatible = "u-boot,boot-std";
117
118 filename-prefixes = "/", "/boot/";
119 bootdev-order = "mmc2", "mmc1";
120
Simon Glassb71d7f72023-05-10 16:34:46 -0600121 extlinux {
122 compatible = "u-boot,extlinux";
Simon Glassb255efc2022-04-24 23:31:24 -0600123 };
124
125 efi {
126 compatible = "u-boot,distro-efi";
127 };
Simon Glassa9289612022-10-20 18:23:14 -0600128
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600129 theme {
130 font-size = <30>;
Simon Glass86f1ac52023-06-01 10:23:00 -0600131 menu-inset = <3>;
132 menuitem-gap-y = <1>;
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600133 };
134
Simon Glass82adc292023-08-14 16:40:30 -0600135 cedit-theme {
136 font-size = <30>;
137 menu-inset = <3>;
138 menuitem-gap-y = <1>;
139 };
140
Simon Glassf1eba352022-10-20 18:23:20 -0600141 /*
142 * This is used for the VBE OS-request tests. A FAT filesystem
143 * created in a partition with the VBE information appearing
Michal Simek33224372023-09-07 14:55:48 +0200144 * before the partition starts
Simon Glassf1eba352022-10-20 18:23:20 -0600145 */
Simon Glassa9289612022-10-20 18:23:14 -0600146 firmware0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700147 bootph-verify;
Simon Glassa9289612022-10-20 18:23:14 -0600148 compatible = "fwupd,vbe-simple";
149 storage = "mmc1";
150 skip-offset = <0x200>;
151 area-start = <0x400>;
152 area-size = <0x1000>;
153 state-offset = <0x400>;
154 state-size = <0x40>;
155 version-offset = <0x800>;
156 version-size = <0x100>;
157 };
Simon Glassf1eba352022-10-20 18:23:20 -0600158
159 /*
160 * This is used for the VBE VPL tests. The MMC device holds the
161 * binman image.bin file. The test progresses through each phase
162 * of U-Boot, loading each in turn from MMC.
163 *
164 * Note that the test enables this node (and mmc3) before
165 * running U-Boot
166 */
167 firmware1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700168 bootph-verify;
Simon Glassf1eba352022-10-20 18:23:20 -0600169 status = "disabled";
170 compatible = "fwupd,vbe-simple";
171 storage = "mmc3";
Simon Glass9bb73e32023-04-02 14:01:24 +1200172 skip-offset = <0x800000>;
Simon Glassf1eba352022-10-20 18:23:20 -0600173 area-start = <0>;
174 area-size = <0xe00000>;
175 state-offset = <0xdffc00>;
176 state-size = <0x40>;
177 version-offset = <0xdffe00>;
178 version-size = <0x100>;
179 };
Simon Glassb255efc2022-04-24 23:31:24 -0600180 };
181
Simon Glass61300722023-06-01 10:23:01 -0600182 cedit: cedit {
183 };
184
Andrew Scull451b8b12022-05-30 10:00:12 +0000185 fuzzing-engine {
186 compatible = "sandbox,fuzzing-engine";
187 };
188
Nandor Han6521e5d2021-06-10 16:56:44 +0300189 reboot-mode0 {
190 compatible = "reboot-mode-gpio";
191 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
192 u-boot,env-variable = "bootstatus";
193 mode-test = <0x01>;
194 mode-download = <0x03>;
195 };
196
Nandor Han7e4067a2021-06-10 16:56:45 +0300197 reboot_mode1: reboot-mode@14 {
198 compatible = "reboot-mode-rtc";
199 rtc = <&rtc_0>;
200 reg = <0x30 4>;
201 u-boot,env-variable = "bootstatus";
202 big-endian;
203 mode-test = <0x21969147>;
204 mode-download = <0x51939147>;
205 };
206
Simon Glassed96cde2018-12-10 10:37:33 -0700207 audio: audio-codec {
208 compatible = "sandbox,audio-codec";
209 #sound-dai-cells = <1>;
210 };
211
Philippe Reynes1ee26482020-07-24 18:19:51 +0200212 buttons {
213 compatible = "gpio-keys";
214
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200215 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200216 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200217 label = "button1";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300218 linux,code = <BTN_1>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200219 };
220
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200221 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200222 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200223 label = "button2";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300224 linux,code = <BTN_2>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200225 };
226 };
227
Marek Szyprowskiad398592021-02-18 11:33:18 +0100228 buttons2 {
229 compatible = "adc-keys";
230 io-channels = <&adc 3>;
231 keyup-threshold-microvolt = <3000000>;
232
233 button-up {
234 label = "button3";
235 linux,code = <KEY_F3>;
236 press-threshold-microvolt = <1500000>;
237 };
238
239 button-down {
240 label = "button4";
241 linux,code = <KEY_F4>;
242 press-threshold-microvolt = <1000000>;
243 };
244
245 button-enter {
246 label = "button5";
247 linux,code = <KEY_F5>;
248 press-threshold-microvolt = <500000>;
249 };
250 };
251
Simon Glassc953aaf2018-12-10 10:37:34 -0700252 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600253 reg = <0 0>;
254 compatible = "google,cros-ec-sandbox";
255
256 /*
257 * This describes the flash memory within the EC. Note
258 * that the STM32L flash erases to 0, not 0xff.
259 */
260 flash {
261 image-pos = <0x08000000>;
262 size = <0x20000>;
263 erase-value = <0>;
264
265 /* Information for sandbox */
266 ro {
267 image-pos = <0>;
268 size = <0xf000>;
269 };
270 wp-ro {
271 image-pos = <0xf000>;
272 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700273 used = <0x884>;
274 compress = "lz4";
275 uncomp-size = <0xcf8>;
276 hash {
277 algo = "sha256";
278 value = [00 01 02 03 04 05 06 07
279 08 09 0a 0b 0c 0d 0e 0f
280 10 11 12 13 14 15 16 17
281 18 19 1a 1b 1c 1d 1e 1f];
282 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600283 };
284 rw {
285 image-pos = <0x10000>;
286 size = <0x10000>;
287 };
288 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300289
290 cros_ec_pwm: cros-ec-pwm {
291 compatible = "google,cros-ec-pwm";
292 #pwm-cells = <1>;
293 };
294
Simon Glass699c9ca2018-10-01 12:22:08 -0600295 };
296
Yannick Fertré9712c822019-10-07 15:29:05 +0200297 dsi_host: dsi_host {
298 compatible = "sandbox,dsi-host";
299 };
300
Christian Marangia1a1e0e2024-11-10 12:50:23 +0100301 phandle_node_1: phandle-node-1 {
302 };
303
304 phandle_node_2: phandle-node-2 {
305 };
306
Simon Glassb2c1cac2014-02-26 15:59:21 -0700307 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600308 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700309 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600310 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700311 ping-add = <0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700312 bootph-all;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100313 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
314 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700315 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100316 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
317 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
318 <&gpio_b 7 GPIO_IN 3 2 1>,
319 <&gpio_b 8 GPIO_OUT 3 2 1>,
320 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100321 test3-gpios =
322 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
323 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
324 <&gpio_c 2 GPIO_OUT>,
325 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
326 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200327 <&gpio_c 5 GPIO_IN>,
328 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
329 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530330 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
331 test5-gpios = <&gpio_a 19>;
332
Simon Glass73025392021-10-23 17:26:04 -0600333 bool-value;
Stefan Herbrechtsmeier1b090e62022-06-14 15:21:30 +0200334 int8-value = /bits/ 8 <0x12>;
335 int16-value = /bits/ 16 <0x1234>;
Simon Glass6df01f92018-12-10 10:37:37 -0700336 int-value = <1234>;
337 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200338 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200339 int-array = <5678 9123 4567>;
Michal Simek08a194e2023-08-25 11:37:46 +0200340 int64-array = /bits/ 64 <0x1111222233334444 0x4444333322221111>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600341 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700342 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600343 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200344 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Christian Marangia1a1e0e2024-11-10 12:50:23 +0100345 phandle-nodes = <&phandle_node_1>, <&phandle_node_2>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530346
347 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
348 <&muxcontroller0 2>, <&muxcontroller0 3>,
349 <&muxcontroller1>;
350 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
351 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100352 display-timings {
353 timing0: 240x320 {
354 clock-frequency = <6500000>;
355 hactive = <240>;
356 vactive = <320>;
357 hfront-porch = <6>;
358 hback-porch = <7>;
359 hsync-len = <1>;
360 vback-porch = <5>;
361 vfront-porch = <8>;
362 vsync-len = <2>;
363 hsync-active = <1>;
364 vsync-active = <0>;
365 de-active = <1>;
366 pixelclk-active = <1>;
367 interlaced;
368 doublescan;
369 doubleclk;
370 };
371 timing1: 480x800 {
372 clock-frequency = <9000000>;
373 hactive = <480>;
374 vactive = <800>;
375 hfront-porch = <10>;
376 hback-porch = <59>;
377 hsync-len = <12>;
378 vback-porch = <15>;
379 vfront-porch = <17>;
380 vsync-len = <16>;
381 hsync-active = <0>;
382 vsync-active = <1>;
383 de-active = <0>;
384 pixelclk-active = <0>;
385 };
386 timing2: 800x480 {
387 clock-frequency = <33500000>;
388 hactive = <800>;
389 vactive = <480>;
390 hback-porch = <89>;
391 hfront-porch = <164>;
392 vback-porch = <23>;
393 vfront-porch = <10>;
394 hsync-len = <11>;
395 vsync-len = <13>;
396 };
397 };
Raphael Gallais-Poua853b922023-05-11 16:36:52 +0200398 panel-timing {
Nikhil M Jainbb9d1312023-01-31 15:35:15 +0530399 clock-frequency = <6500000>;
400 hactive = <240>;
401 vactive = <320>;
402 hfront-porch = <6>;
403 hback-porch = <7>;
404 hsync-len = <1>;
405 vback-porch = <5>;
406 vfront-porch = <8>;
407 vsync-len = <2>;
408 hsync-active = <1>;
409 vsync-active = <0>;
410 de-active = <1>;
411 pixelclk-active = <1>;
412 interlaced;
413 doublescan;
414 doubleclk;
415 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700416 };
417
418 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600419 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700420 compatible = "not,compatible";
421 };
422
423 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600424 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700425 };
426
Simon Glass5620cf82018-10-01 12:22:40 -0600427 backlight: backlight {
428 compatible = "pwm-backlight";
429 enable-gpios = <&gpio_a 1>;
430 power-supply = <&ldo_1>;
431 pwms = <&pwm 0 1000>;
432 default-brightness-level = <5>;
433 brightness-levels = <0 16 32 64 128 170 202 234 255>;
434 };
435
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200436 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200437 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200438 bind-test-child1 {
439 compatible = "sandbox,phy";
440 #phy-cells = <1>;
441 };
442
443 bind-test-child2 {
444 compatible = "simple-bus";
445 };
446 };
447
Simon Glassb2c1cac2014-02-26 15:59:21 -0700448 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600449 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700450 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600451 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700452 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530453
454 mux-controls = <&muxcontroller0 0>;
455 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700456 };
457
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200458 phy_provider0: gen_phy@0 {
459 compatible = "sandbox,phy";
460 #phy-cells = <1>;
461 };
462
463 phy_provider1: gen_phy@1 {
464 compatible = "sandbox,phy";
465 #phy-cells = <0>;
466 broken;
467 };
468
developer71092972020-05-02 11:35:12 +0200469 phy_provider2: gen_phy@2 {
470 compatible = "sandbox,phy";
471 #phy-cells = <0>;
472 };
473
Jonas Karlman9f89e682023-08-31 22:16:35 +0000474 phy_provider3: gen_phy@3 {
475 compatible = "sandbox,phy";
476 #phy-cells = <2>;
477 };
478
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200479 gen_phy_user: gen_phy_user {
480 compatible = "simple-bus";
481 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
482 phy-names = "phy1", "phy2", "phy3";
483 };
484
developer71092972020-05-02 11:35:12 +0200485 gen_phy_user1: gen_phy_user1 {
486 compatible = "simple-bus";
487 phys = <&phy_provider0 0>, <&phy_provider2>;
488 phy-names = "phy1", "phy2";
489 };
490
Jonas Karlman9f89e682023-08-31 22:16:35 +0000491 gen_phy_user2: gen_phy_user2 {
492 compatible = "simple-bus";
493 phys = <&phy_provider3 0 0>;
494 phy-names = "phy1";
495 };
496
Simon Glassb2c1cac2014-02-26 15:59:21 -0700497 some-bus {
498 #address-cells = <1>;
499 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600500 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600501 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600502 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700503 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600504 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700505 compatible = "denx,u-boot-fdt-test";
506 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600507 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700508 ping-add = <5>;
509 };
Simon Glass40717422014-07-23 06:55:18 -0600510 c-test@0 {
511 compatible = "denx,u-boot-fdt-test";
512 reg = <0>;
513 ping-expect = <6>;
514 ping-add = <6>;
515 };
516 c-test@1 {
517 compatible = "denx,u-boot-fdt-test";
518 reg = <1>;
519 ping-expect = <7>;
520 ping-add = <7>;
521 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700522 };
523
524 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600525 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600526 ping-expect = <6>;
527 ping-add = <6>;
528 compatible = "google,another-fdt-test";
529 };
530
531 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600532 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600533 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700534 ping-add = <6>;
535 compatible = "google,another-fdt-test";
536 };
537
Simon Glass0ccb0972015-01-25 08:27:05 -0700538 f-test {
Patrick Rudolph0fe88cc2024-10-23 15:20:05 +0200539 #interrupt-cells = <2>;
540 interrupt-parent = <&irq>;
541 interrupts = <4 0>;
Simon Glass0ccb0972015-01-25 08:27:05 -0700542 compatible = "denx,u-boot-fdt-test";
543 };
544
545 g-test {
546 compatible = "denx,u-boot-fdt-test";
547 };
548
Bin Mengd9d24782018-10-10 22:07:01 -0700549 h-test {
550 compatible = "denx,u-boot-fdt-test1";
551 };
552
developercf8bc132020-05-02 11:35:10 +0200553 i-test {
554 compatible = "mediatek,u-boot-fdt-test";
555 #address-cells = <1>;
556 #size-cells = <0>;
557
558 subnode@0 {
559 reg = <0>;
560 };
561
562 subnode@1 {
563 reg = <1>;
564 };
565
566 subnode@2 {
567 reg = <2>;
568 };
569 };
570
Simon Glass204675c2019-12-29 21:19:25 -0700571 devres-test {
572 compatible = "denx,u-boot-devres-test";
573 };
574
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530575 another-test {
576 reg = <0 2>;
577 compatible = "denx,u-boot-fdt-test";
578 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
579 test5-gpios = <&gpio_a 19>;
580 };
581
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100582 mmio-bus@0 {
583 #address-cells = <1>;
584 #size-cells = <1>;
585 compatible = "denx,u-boot-test-bus";
586 dma-ranges = <0x10000000 0x00000000 0x00040000>;
587
588 subnode@0 {
589 compatible = "denx,u-boot-fdt-test";
590 };
591 };
592
593 mmio-bus@1 {
594 #address-cells = <1>;
595 #size-cells = <1>;
596 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100597
598 subnode@0 {
599 compatible = "denx,u-boot-fdt-test";
600 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100601 };
602
Simon Glass3c601b12020-07-07 13:12:06 -0600603 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600604 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600605 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600606 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600607 child {
608 compatible = "denx,u-boot-acpi-test";
609 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600610 };
611
Simon Glass3c601b12020-07-07 13:12:06 -0600612 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600613 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600614 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600615 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600616 };
617
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200618 clocks {
619 clk_fixed: clk-fixed {
620 compatible = "fixed-clock";
621 #clock-cells = <0>;
622 clock-frequency = <1234>;
623 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000624
625 clk_fixed_factor: clk-fixed-factor {
626 compatible = "fixed-factor-clock";
627 #clock-cells = <0>;
628 clock-div = <3>;
629 clock-mult = <2>;
630 clocks = <&clk_fixed>;
631 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200632
633 osc {
634 compatible = "fixed-clock";
635 #clock-cells = <0>;
636 clock-frequency = <20000000>;
637 };
Stephen Warrena9622432016-06-17 09:44:00 -0600638 };
639
640 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600641 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600642 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200643 assigned-clocks = <&clk_sandbox 3>;
644 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600645 };
646
647 clk-test {
648 compatible = "sandbox,clk-test";
649 clocks = <&clk_fixed>,
650 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200651 <&clk_sandbox 0>,
Yang Xiwene89289c2023-12-16 02:28:52 +0800652 <&ccf 11>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200653 <&clk_sandbox 3>,
654 <&clk_sandbox 2>;
Yang Xiwene89289c2023-12-16 02:28:52 +0800655 clock-names = "fixed", "i2c", "spi", "i2c_root", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600656 };
657
Ashok Reddy Soma8f03cef2023-08-30 10:31:42 +0200658 clk-test2 {
659 compatible = "sandbox,clk-test";
660 assigned-clock-rates = <321>;
661 };
662
663 clk-test3 {
664 compatible = "sandbox,clk-test";
665 assigned-clocks = <&clk_sandbox 1>;
666 };
667
668 clk-test4 {
669 compatible = "sandbox,clk-test";
670 assigned-clock-rates = <654>, <321>;
671 assigned-clocks = <&clk_sandbox 1>;
672 };
673
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200674 ccf: clk-ccf {
675 compatible = "sandbox,clk-ccf";
Yang Xiwene89289c2023-12-16 02:28:52 +0800676 #clock-cells = <1>;
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200677 };
678
Simon Glass507ab962021-12-04 08:56:31 -0700679 efi-media {
680 compatible = "sandbox,efi-media";
681 };
682
Simon Glass5b968632015-05-22 15:42:15 -0600683 eth@10002000 {
684 compatible = "sandbox,eth";
685 reg = <0x10002000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600686 };
687
688 eth_5: eth@10003000 {
689 compatible = "sandbox,eth";
690 reg = <0x10003000 0x1000>;
Sean Anderson13652b82022-05-05 13:11:44 -0400691 nvmem-cells = <&eth5_addr>;
692 nvmem-cell-names = "mac-address";
Simon Glass5b968632015-05-22 15:42:15 -0600693 };
694
Bin Meng04a11cb2015-08-27 22:25:53 -0700695 eth_3: sbe5 {
696 compatible = "sandbox,eth";
697 reg = <0x10005000 0x1000>;
Sean Andersone2dc0e62022-05-05 13:11:42 -0400698 nvmem-cells = <&eth3_addr>;
699 nvmem-cell-names = "mac-address";
Bin Meng04a11cb2015-08-27 22:25:53 -0700700 };
701
Simon Glass5b968632015-05-22 15:42:15 -0600702 eth@10004000 {
703 compatible = "sandbox,eth";
704 reg = <0x10004000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600705 };
706
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200707 phy_eth0: phy-test-eth {
708 compatible = "sandbox,eth";
709 reg = <0x10007000 0x1000>;
Sean Anderson24b1b8d2022-05-05 13:11:35 -0400710 mac-address = [ 02 00 11 22 33 49 ];
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200711 phy-handle = <&ethphy1>;
Marek Behúnbc194772022-04-07 00:33:01 +0200712 phy-mode = "2500base-x";
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200713 };
714
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800715 dsa_eth0: dsa-test-eth {
716 compatible = "sandbox,eth";
717 reg = <0x10006000 0x1000>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400718 nvmem-cells = <&eth4_addr>;
719 nvmem-cell-names = "mac-address";
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800720 };
721
722 dsa-test {
723 compatible = "sandbox,dsa";
724
725 ports {
726 #address-cells = <1>;
727 #size-cells = <0>;
728 swp_0: port@0 {
729 reg = <0>;
730 label = "lan0";
731 phy-mode = "rgmii-rxid";
732
733 fixed-link {
734 speed = <100>;
735 full-duplex;
736 };
737 };
738
739 swp_1: port@1 {
740 reg = <1>;
741 label = "lan1";
742 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800743 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800744 };
745
746 port@2 {
747 reg = <2>;
748 ethernet = <&dsa_eth0>;
749
750 fixed-link {
751 speed = <1000>;
752 full-duplex;
753 };
754 };
755 };
756 };
757
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700758 firmware {
759 sandbox_firmware: sandbox-firmware {
760 compatible = "sandbox,firmware";
761 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200762
Etienne Carriere09665cb2022-02-21 09:22:39 +0100763 scmi {
Etienne Carriere02fd1262020-09-09 18:44:00 +0200764 compatible = "sandbox,scmi-agent";
765 #address-cells = <1>;
766 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200767
AKASHI Takahiro535a7bd2023-10-16 14:39:45 +0900768 pwrdom_scmi: protocol@11 {
769 reg = <0x11>;
770 #power-domain-cells = <1>;
771 };
772
Etienne Carriere09665cb2022-02-21 09:22:39 +0100773 clk_scmi: protocol@14 {
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200774 reg = <0x14>;
775 #clock-cells = <1>;
AKASHI Takahirocc4ecda2023-10-11 19:06:59 +0900776 linaro,sandbox-channel-id = <0x14>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200777 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200778
Etienne Carriere09665cb2022-02-21 09:22:39 +0100779 reset_scmi: protocol@16 {
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200780 reg = <0x16>;
781 #reset-cells = <1>;
782 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100783
784 protocol@17 {
785 reg = <0x17>;
786
787 regulators {
788 #address-cells = <1>;
789 #size-cells = <0>;
790
Etienne Carriere09665cb2022-02-21 09:22:39 +0100791 regul0_scmi: reg@0 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100792 reg = <0>;
793 regulator-name = "sandbox-voltd0";
794 regulator-min-microvolt = <1100000>;
795 regulator-max-microvolt = <3300000>;
796 };
Etienne Carriere09665cb2022-02-21 09:22:39 +0100797 regul1_scmi: reg@1 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100798 reg = <0x1>;
799 regulator-name = "sandbox-voltd1";
800 regulator-min-microvolt = <1800000>;
801 };
802 };
803 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200804 };
Alexey Romanov9dc617d2023-09-21 11:13:36 +0300805
806 sm: secure-monitor {
807 compatible = "sandbox,sm";
808 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700809 };
810
Alexander Dahl6ac319d2022-09-30 14:04:30 +0200811 fpga {
812 compatible = "sandbox,fpga";
813 };
814
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100815 pinctrl-gpio {
816 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700817
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100818 gpio_a: base-gpios {
819 compatible = "sandbox,gpio";
820 gpio-controller;
821 #gpio-cells = <1>;
822 gpio-bank-name = "a";
823 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200824 hog_input_active_low {
825 gpio-hog;
826 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200827 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200828 };
829 hog_input_active_high {
830 gpio-hog;
831 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200832 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200833 };
834 hog_output_low {
835 gpio-hog;
836 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200837 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200838 };
839 hog_output_high {
840 gpio-hog;
841 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200842 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200843 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100844 };
845
846 gpio_b: extra-gpios {
847 compatible = "sandbox,gpio";
848 gpio-controller;
849 #gpio-cells = <5>;
850 gpio-bank-name = "b";
851 sandbox,gpio-count = <10>;
852 };
Simon Glass25348a42014-10-13 23:42:11 -0600853
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100854 gpio_c: pinmux-gpios {
855 compatible = "sandbox,gpio";
856 gpio-controller;
857 #gpio-cells = <2>;
858 gpio-bank-name = "c";
859 sandbox,gpio-count = <10>;
860 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100861 };
862
Simon Glass7df766e2014-12-10 08:55:55 -0700863 i2c@0 {
864 #address-cells = <1>;
865 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600866 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700867 compatible = "sandbox,i2c";
868 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200869 pinctrl-names = "default";
870 pinctrl-0 = <&pinmux_i2c0_pins>;
871
Simon Glass7df766e2014-12-10 08:55:55 -0700872 eeprom@2c {
Sean Andersone2dc0e62022-05-05 13:11:42 -0400873 #address-cells = <1>;
874 #size-cells = <1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700875 reg = <0x2c>;
876 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700877 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200878 partitions {
879 compatible = "fixed-partitions";
880 #address-cells = <1>;
881 #size-cells = <1>;
882 bootcount_i2c: bootcount@10 {
883 reg = <10 2>;
884 };
885 };
Sean Andersone2dc0e62022-05-05 13:11:42 -0400886
887 eth3_addr: mac-address@24 {
888 reg = <24 6>;
889 };
Simon Glass7df766e2014-12-10 08:55:55 -0700890 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200891
Simon Glass336b2952015-05-22 15:42:17 -0600892 rtc_0: rtc@43 {
Sean Anderson5768e8b2022-05-05 13:11:43 -0400893 #address-cells = <1>;
894 #size-cells = <1>;
Simon Glass336b2952015-05-22 15:42:17 -0600895 reg = <0x43>;
896 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700897 sandbox,emul = <&emul0>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400898
899 eth4_addr: mac-address@40 {
900 reg = <0x40 6>;
901 };
Simon Glass336b2952015-05-22 15:42:17 -0600902 };
903
904 rtc_1: rtc@61 {
905 reg = <0x61>;
906 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700907 sandbox,emul = <&emul1>;
908 };
909
910 i2c_emul: emul {
911 reg = <0xff>;
912 compatible = "sandbox,i2c-emul-parent";
913 emul_eeprom: emul-eeprom {
914 compatible = "sandbox,i2c-eeprom";
915 sandbox,filename = "i2c.bin";
916 sandbox,size = <256>;
917 };
918 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700919 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700920 };
921 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700922 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600923 };
924 };
925
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200926 sandbox_pmic: sandbox_pmic {
927 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700928 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200929 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200930
931 mc34708: pmic@41 {
932 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700933 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200934 };
Simon Glass7df766e2014-12-10 08:55:55 -0700935 };
936
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100937 bootcount@0 {
938 compatible = "u-boot,bootcount-rtc";
939 rtc = <&rtc_1>;
940 offset = <0x13>;
941 };
942
Michal Simek4f18f922020-05-28 11:48:55 +0200943 bootcount {
944 compatible = "u-boot,bootcount-i2c-eeprom";
945 i2c-eeprom = <&bootcount_i2c>;
946 };
947
Nandor Han88895812021-06-10 15:40:38 +0300948 bootcount_4@0 {
949 compatible = "u-boot,bootcount-syscon";
950 syscon = <&syscon0>;
951 reg = <0x0 0x04>, <0x0 0x04>;
952 reg-names = "syscon_reg", "offset";
953 };
954
955 bootcount_2@0 {
956 compatible = "u-boot,bootcount-syscon";
957 syscon = <&syscon0>;
958 reg = <0x0 0x04>, <0x0 0x02> ;
959 reg-names = "syscon_reg", "offset";
960 };
961
Marek Szyprowskiad398592021-02-18 11:33:18 +0100962 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100963 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100964 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100965 vdd-supply = <&buck2>;
966 vss-microvolts = <0>;
967 };
968
Mark Kettenis67748ee2021-10-23 16:58:02 +0200969 iommu: iommu@0 {
970 compatible = "sandbox,iommu";
971 #iommu-cells = <0>;
972 };
973
Simon Glass515dcff2020-02-06 09:55:00 -0700974 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700975 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700976 interrupt-controller;
977 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700978 };
979
Simon Glass90b6fef2016-01-18 19:52:26 -0700980 lcd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700981 bootph-all;
Simon Glass90b6fef2016-01-18 19:52:26 -0700982 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200983 pinctrl-names = "default";
984 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700985 xres = <1366>;
986 yres = <768>;
987 };
988
Simon Glassd783eb32015-07-06 12:54:34 -0600989 leds {
990 compatible = "gpio-leds";
991
Christian Marangifd53ad42024-11-10 12:50:27 +0100992 sandbox_led_red: iracibble {
Simon Glassd783eb32015-07-06 12:54:34 -0600993 gpios = <&gpio_a 1 0>;
994 label = "sandbox:red";
995 };
996
Christian Marangifd53ad42024-11-10 12:50:27 +0100997 sandbox_led_green: martinet {
Simon Glassd783eb32015-07-06 12:54:34 -0600998 gpios = <&gpio_a 2 0>;
999 label = "sandbox:green";
1000 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +02001001
1002 default_on {
1003 gpios = <&gpio_a 5 0>;
1004 label = "sandbox:default_on";
1005 default-state = "on";
1006 };
1007
1008 default_off {
1009 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -04001010 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +02001011 default-state = "off";
1012 };
Simon Glassd783eb32015-07-06 12:54:34 -06001013 };
1014
Paul Doelle709f0372022-07-04 09:00:25 +00001015 wdt-gpio-toggle {
Simon Glasse0f8cd22023-08-10 09:53:13 -06001016 gpios = <&gpio_a 8 0>;
Rasmus Villemoes2b673872021-08-19 11:57:05 +02001017 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001018 hw_margin_ms = <100>;
Paul Doelle709f0372022-07-04 09:00:25 +00001019 hw_algo = "toggle";
1020 always-running;
1021 };
1022
1023 wdt-gpio-level {
1024 gpios = <&gpio_a 7 0>;
1025 compatible = "linux,wdt-gpio";
1026 hw_margin_ms = <100>;
1027 hw_algo = "level";
Rasmus Villemoes2b673872021-08-19 11:57:05 +02001028 always-running;
1029 };
1030
Stephen Warren62f2c902016-05-16 17:41:37 -06001031 mbox: mbox {
1032 compatible = "sandbox,mbox";
1033 #mbox-cells = <1>;
1034 };
1035
1036 mbox-test {
1037 compatible = "sandbox,mbox-test";
1038 mboxes = <&mbox 100>, <&mbox 1>;
1039 mbox-names = "other", "test";
1040 };
1041
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001042 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001043 #address-cells = <1>;
1044 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -04001045 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001046 cpu1: cpu@1 {
1047 device_type = "cpu";
1048 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -04001049 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001050 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001051 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001052 };
Mario Sixdea5df72018-08-06 10:23:44 +02001053
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001054 cpu2: cpu@2 {
1055 device_type = "cpu";
1056 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001057 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001058 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001059 };
Mario Sixdea5df72018-08-06 10:23:44 +02001060
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001061 cpu3: cpu@3 {
1062 device_type = "cpu";
1063 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001064 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001065 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001066 };
Mario Sixdea5df72018-08-06 10:23:44 +02001067 };
1068
Dave Gerlach75dbdfc2020-07-15 23:39:58 -05001069 chipid: chipid {
1070 compatible = "sandbox,soc";
1071 };
1072
Simon Glassc953aaf2018-12-10 10:37:34 -07001073 i2s: i2s {
1074 compatible = "sandbox,i2s";
1075 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -07001076 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -07001077 };
1078
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +02001079 nop-test_0 {
1080 compatible = "sandbox,nop_sandbox1";
1081 nop-test_1 {
1082 compatible = "sandbox,nop_sandbox2";
1083 bind = "True";
1084 };
1085 nop-test_2 {
1086 compatible = "sandbox,nop_sandbox2";
1087 bind = "False";
1088 };
1089 };
1090
Roger Quadrosb0679a72022-10-20 16:30:46 +03001091 memory-controller {
1092 compatible = "sandbox,memory";
1093 };
1094
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001095 misc-test {
Sean Anderson13652b82022-05-05 13:11:44 -04001096 #address-cells = <1>;
1097 #size-cells = <1>;
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001098 compatible = "sandbox,misc_sandbox";
Sean Anderson13652b82022-05-05 13:11:44 -04001099
1100 eth5_addr: mac-address@10 {
1101 reg = <0x10 6>;
1102 };
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001103 };
1104
Simon Glasse4fef742017-04-23 20:02:07 -06001105 mmc2 {
1106 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -06001107 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -06001108 };
1109
Simon Glassb255efc2022-04-24 23:31:24 -06001110 /* This is used for the bootdev tests */
Simon Glasse4fef742017-04-23 20:02:07 -06001111 mmc1 {
1112 compatible = "sandbox,mmc";
Simon Glassb255efc2022-04-24 23:31:24 -06001113 filename = "mmc1.img";
Simon Glasse4fef742017-04-23 20:02:07 -06001114 };
1115
Simon Glassb255efc2022-04-24 23:31:24 -06001116 /* This is used for the fastboot tests */
Sughosh Ganu77079e72022-10-21 18:16:05 +05301117 mmc0: mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -06001118 compatible = "sandbox,mmc";
1119 };
1120
Simon Glassf1eba352022-10-20 18:23:20 -06001121 /* This is used for VBE VPL tests */
1122 mmc3 {
1123 status = "disabled";
1124 compatible = "sandbox,mmc";
1125 filename = "image.bin";
1126 non-removable;
1127 };
1128
Simon Glassd2bc33ed2023-01-06 08:52:41 -06001129 /* This is used for bootstd bootmenu tests */
1130 mmc4 {
1131 status = "disabled";
1132 compatible = "sandbox,mmc";
1133 filename = "mmc4.img";
1134 };
1135
Simon Glassfff928c2023-08-24 13:55:41 -06001136 /* This is used for ChromiumOS tests */
1137 mmc5 {
1138 status = "disabled";
1139 compatible = "sandbox,mmc";
1140 filename = "mmc5.img";
1141 };
1142
Alexander Gendin038cb022023-10-09 01:24:36 +00001143 /* This is used for mbr tests */
1144 mmc6 {
1145 status = "disabled";
1146 compatible = "sandbox,mmc";
1147 filename = "mmc6.img";
1148 };
1149
Guillaume La Roque368ad9e2024-11-26 09:06:13 +01001150 /* This is used for Android boot image v4 tests */
Mattijs Korpershoekd77f8152024-07-10 10:40:06 +02001151 mmc7 {
1152 status = "disabled";
1153 compatible = "sandbox,mmc";
1154 filename = "mmc7.img";
1155 };
1156
Guillaume La Roque368ad9e2024-11-26 09:06:13 +01001157 /* This is used for Android boot image v2 tests. */
1158 mmc8 {
1159 status = "disabled";
1160 compatible = "sandbox,mmc";
1161 filename = "mmc8.img";
1162 };
1163
Simon Glass53a68b32019-02-16 20:24:50 -07001164 pch {
1165 compatible = "sandbox,pch";
1166 };
1167
Tom Rini4a3ca482020-02-11 12:41:23 -05001168 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -07001169 compatible = "sandbox,pci";
1170 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001171 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001172 #address-cells = <3>;
1173 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -06001174 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -07001175 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Mark Kettenis5dfd4ec2023-01-21 20:27:57 +01001176 iommu-map = <0x0010 &iommu 0 1>;
1177 iommu-map-mask = <0xfffffff8>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001178 pci@0,0 {
1179 compatible = "pci-generic";
1180 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001181 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001182 };
Alex Margineanf1274432019-06-07 11:24:24 +03001183 pci@1,0 {
1184 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001185 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
Simon Glass4289c262023-09-26 08:14:58 -06001186 reg = <0x02000814 0 0 0x80 0
1187 0x01000810 0 0 0xc0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001188 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +03001189 };
Simon Glass937bb472019-12-06 21:41:57 -07001190 p2sb-pci@2,0 {
1191 compatible = "sandbox,p2sb";
1192 reg = <0x02001010 0 0 0 0>;
1193 sandbox,emul = <&p2sb_emul>;
1194
1195 adder {
1196 intel,p2sb-port-id = <3>;
1197 compatible = "sandbox,adder";
1198 };
1199 };
Simon Glass8c501022019-12-06 21:41:54 -07001200 pci@1e,0 {
1201 compatible = "sandbox,pmc";
1202 reg = <0xf000 0 0 0 0>;
1203 sandbox,emul = <&pmc_emul1e>;
1204 acpi-base = <0x400>;
1205 gpe0-dwx-mask = <0xf>;
1206 gpe0-dwx-shift-base = <4>;
1207 gpe0-dw = <6 7 9>;
1208 gpe0-sts = <0x20>;
1209 gpe0-en = <0x30>;
1210 };
Simon Glass3a6eae62015-03-05 12:25:34 -07001211 pci@1f,0 {
1212 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001213 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
Simon Glass4289c262023-09-26 08:14:58 -06001214 reg = <0x0100f810 0 0 0x100 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001215 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001216 };
1217 };
1218
Simon Glassb98ba4c2019-09-25 08:56:10 -06001219 pci-emul0 {
1220 compatible = "sandbox,pci-emul-parent";
1221 swap_case_emul0_0: emul0@0,0 {
1222 compatible = "sandbox,swap-case";
1223 };
1224 swap_case_emul0_1: emul0@1,0 {
1225 compatible = "sandbox,swap-case";
1226 use-ea;
1227 };
1228 swap_case_emul0_1f: emul0@1f,0 {
1229 compatible = "sandbox,swap-case";
1230 };
Simon Glass937bb472019-12-06 21:41:57 -07001231 p2sb_emul: emul@2,0 {
1232 compatible = "sandbox,p2sb-emul";
1233 };
Simon Glass8c501022019-12-06 21:41:54 -07001234 pmc_emul1e: emul@1e,0 {
1235 compatible = "sandbox,pmc-emul";
1236 };
Simon Glassb98ba4c2019-09-25 08:56:10 -06001237 };
1238
Tom Rini4a3ca482020-02-11 12:41:23 -05001239 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -07001240 compatible = "sandbox,pci";
1241 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001242 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -07001243 #address-cells = <3>;
1244 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001245 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scullc7456a42022-04-21 16:11:09 +00001246 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001247 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -07001248 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +02001249 0x0c 0x00 0x1234 0x5678
1250 0x10 0x00 0x1234 0x5678>;
1251 pci@10,0 {
1252 reg = <0x8000 0 0 0 0>;
1253 };
Bin Meng408e5902018-08-03 01:14:41 -07001254 };
1255
Tom Rini4a3ca482020-02-11 12:41:23 -05001256 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -07001257 compatible = "sandbox,pci";
1258 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001259 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -07001260 #address-cells = <3>;
1261 #size-cells = <2>;
1262 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1263 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1264 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1265 pci@1f,0 {
1266 compatible = "pci-generic";
1267 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001268 sandbox,emul = <&swap_case_emul2_1f>;
1269 };
1270 };
1271
1272 pci-emul2 {
1273 compatible = "sandbox,pci-emul-parent";
1274 swap_case_emul2_1f: emul2@1f,0 {
1275 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001276 };
1277 };
1278
Ramon Friedc64f19b2019-04-27 11:15:23 +03001279 pci_ep: pci_ep {
1280 compatible = "sandbox,pci_ep";
1281 };
1282
Simon Glass9c433fe2017-04-23 20:10:44 -06001283 probing {
1284 compatible = "simple-bus";
1285 test1 {
1286 compatible = "denx,u-boot-probe-test";
1287 };
1288
1289 test2 {
1290 compatible = "denx,u-boot-probe-test";
1291 };
1292
1293 test3 {
1294 compatible = "denx,u-boot-probe-test";
1295 };
1296
1297 test4 {
1298 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001299 first-syscon = <&syscon0>;
1300 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001301 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001302 };
1303 };
1304
Stephen Warren92c67fa2016-07-13 13:45:31 -06001305 pwrdom: power-domain {
1306 compatible = "sandbox,power-domain";
1307 #power-domain-cells = <1>;
1308 };
1309
1310 power-domain-test {
1311 compatible = "sandbox,power-domain-test";
1312 power-domains = <&pwrdom 2>;
1313 };
1314
Simon Glass5620cf82018-10-01 12:22:40 -06001315 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001316 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001317 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001318 pinctrl-names = "default";
1319 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001320 };
1321
1322 pwm2 {
1323 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001324 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001325 };
1326
Simon Glass3d355e62015-07-06 12:54:31 -06001327 ram {
1328 compatible = "sandbox,ram";
1329 };
1330
Simon Glassd860f222015-07-06 12:54:29 -06001331 reset@0 {
1332 compatible = "sandbox,warm-reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001333 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001334 };
1335
1336 reset@1 {
1337 compatible = "sandbox,reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001338 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001339 };
1340
Stephen Warren6488e642016-06-17 09:43:59 -06001341 resetc: reset-ctl {
1342 compatible = "sandbox,reset-ctl";
1343 #reset-cells = <1>;
1344 };
1345
1346 reset-ctl-test {
1347 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001348 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1349 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001350 };
1351
Sughosh Ganu23e37512019-12-28 23:58:31 +05301352 rng {
1353 compatible = "sandbox,sandbox-rng";
1354 };
1355
Nishanth Menonedf85812015-09-17 15:42:41 -05001356 rproc_1: rproc@1 {
1357 compatible = "sandbox,test-processor";
1358 remoteproc-name = "remoteproc-test-dev1";
1359 };
1360
1361 rproc_2: rproc@2 {
1362 compatible = "sandbox,test-processor";
1363 internal-memory-mapped;
1364 remoteproc-name = "remoteproc-test-dev2";
1365 };
1366
Simon Glass5620cf82018-10-01 12:22:40 -06001367 panel {
1368 compatible = "simple-panel";
1369 backlight = <&backlight 0 100>;
1370 };
1371
Simon Glass509f32e2022-09-21 16:21:47 +02001372 scsi {
1373 compatible = "sandbox,scsi";
1374 sandbox,filepath = "scsi.img";
1375 };
1376
Ramon Fried26ed32e2018-07-02 02:57:59 +03001377 smem@0 {
1378 compatible = "sandbox,smem";
1379 };
1380
Simon Glass76072ac2018-12-10 10:37:36 -07001381 sound {
1382 compatible = "sandbox,sound";
1383 cpu {
1384 sound-dai = <&i2s 0>;
1385 };
1386
1387 codec {
1388 sound-dai = <&audio 0>;
1389 };
1390 };
1391
Simon Glass25348a42014-10-13 23:42:11 -06001392 spi@0 {
1393 #address-cells = <1>;
1394 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001395 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001396 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001397 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001398 pinctrl-names = "default";
1399 pinctrl-0 = <&pinmux_spi0_pins>;
1400
Simon Glass25348a42014-10-13 23:42:11 -06001401 spi.bin@0 {
1402 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001403 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001404 spi-max-frequency = <40000000>;
1405 sandbox,filename = "spi.bin";
1406 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001407 spi.bin@1 {
1408 reg = <1>;
1409 compatible = "spansion,m25p16", "jedec,spi-nor";
1410 spi-max-frequency = <50000000>;
1411 sandbox,filename = "spi.bin";
1412 spi-cpol;
1413 spi-cpha;
1414 };
Simon Glass25348a42014-10-13 23:42:11 -06001415 };
1416
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001417 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001418 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001419 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001420 };
1421
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001422 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001423 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001424 reg = <0x20 5
1425 0x28 6
1426 0x30 7
1427 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001428 };
1429
Patrick Delaunayee010432019-03-07 09:57:13 +01001430 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001431 compatible = "simple-mfd", "syscon";
1432 reg = <0x40 5
1433 0x48 6
1434 0x50 7
1435 0x58 8>;
1436 };
1437
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301438 syscon3: syscon@3 {
1439 compatible = "simple-mfd", "syscon";
1440 reg = <0x000100 0x10>;
1441
1442 muxcontroller0: a-mux-controller {
1443 compatible = "mmio-mux";
1444 #mux-control-cells = <1>;
1445
1446 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1447 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1448 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1449 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1450 u-boot,mux-autoprobe;
1451 };
1452 };
1453
1454 muxcontroller1: emul-mux-controller {
1455 compatible = "mux-emul";
1456 #mux-control-cells = <0>;
1457 u-boot,mux-autoprobe;
1458 idle-state = <0xabcd>;
1459 };
1460
Simon Glass791a17f2020-12-16 21:20:27 -07001461 testfdtm0 {
1462 compatible = "denx,u-boot-fdtm-test";
1463 };
1464
1465 testfdtm1: testfdtm1 {
1466 compatible = "denx,u-boot-fdtm-test";
1467 };
1468
1469 testfdtm2 {
1470 compatible = "denx,u-boot-fdtm-test";
1471 };
1472
Sean Anderson79d3bba2020-09-28 10:52:23 -04001473 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001474 compatible = "sandbox,timer";
1475 clock-frequency = <1000000>;
1476 };
1477
Sean Anderson79d3bba2020-09-28 10:52:23 -04001478 timer@1 {
1479 compatible = "sandbox,timer";
1480 sandbox,timebase-frequency-fallback;
1481 };
1482
Miquel Raynal80938c12018-05-15 11:57:27 +02001483 tpm2 {
1484 compatible = "sandbox,tpm2";
Eddie James1a55a7a2023-10-24 10:43:51 -05001485 memory-region = <&event_log>;
Miquel Raynal80938c12018-05-15 11:57:27 +02001486 };
1487
Simon Glasseef107e2023-02-21 06:24:51 -07001488 tpm {
1489 compatible = "google,sandbox-tpm";
1490 };
1491
Simon Glass5b968632015-05-22 15:42:15 -06001492 uart0: serial {
1493 compatible = "sandbox,serial";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001494 bootph-all;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001495 pinctrl-names = "default";
1496 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001497 };
1498
Simon Glass31680482015-03-25 12:23:05 -06001499 usb_0: usb@0 {
1500 compatible = "sandbox,usb";
1501 status = "disabled";
1502 hub {
1503 compatible = "sandbox,usb-hub";
1504 #address-cells = <1>;
1505 #size-cells = <0>;
1506 flash-stick {
1507 reg = <0>;
1508 compatible = "sandbox,usb-flash";
1509 };
1510 };
1511 };
1512
1513 usb_1: usb@1 {
1514 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001515 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001516 hub {
1517 compatible = "usb-hub";
1518 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001519 #address-cells = <1>;
1520 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001521 hub-emul {
1522 compatible = "sandbox,usb-hub";
1523 #address-cells = <1>;
1524 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001525 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001526 reg = <0>;
1527 compatible = "sandbox,usb-flash";
1528 sandbox,filepath = "testflash.bin";
1529 };
1530
Simon Glass4700fe52015-11-08 23:48:01 -07001531 flash-stick@1 {
1532 reg = <1>;
1533 compatible = "sandbox,usb-flash";
Simon Glass64c63252024-11-07 14:31:49 -07001534 sandbox,filepath = "flash1.img";
Simon Glass4700fe52015-11-08 23:48:01 -07001535 };
1536
1537 flash-stick@2 {
1538 reg = <2>;
1539 compatible = "sandbox,usb-flash";
1540 sandbox,filepath = "testflash2.bin";
1541 };
1542
Simon Glassc0ccc722015-11-08 23:48:08 -07001543 keyb@3 {
1544 reg = <3>;
1545 compatible = "sandbox,usb-keyb";
1546 };
1547
Simon Glass31680482015-03-25 12:23:05 -06001548 };
Michael Walle7c961322020-06-02 01:47:07 +02001549
1550 usbstor@1 {
1551 reg = <1>;
1552 };
1553 usbstor@3 {
1554 reg = <3>;
1555 };
Simon Glass31680482015-03-25 12:23:05 -06001556 };
1557 };
1558
1559 usb_2: usb@2 {
1560 compatible = "sandbox,usb";
1561 status = "disabled";
1562 };
1563
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001564 spmi: spmi@0 {
1565 compatible = "sandbox,spmi";
1566 #address-cells = <0x1>;
1567 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001568 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001569 pm8916@0 {
1570 compatible = "qcom,spmi-pmic";
1571 reg = <0x0 0x1>;
1572 #address-cells = <0x1>;
1573 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001574 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001575
1576 spmi_gpios: gpios@c000 {
1577 compatible = "qcom,pm8916-gpio";
1578 reg = <0xc000 0x400>;
Caleb Connolly1edc45f2024-01-08 15:30:51 +00001579 gpio-ranges = <&spmi_gpios 0 0 4>;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001580 gpio-controller;
1581 gpio-count = <4>;
1582 #gpio-cells = <2>;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001583 };
1584 };
1585 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001586
1587 wdt0: wdt@0 {
1588 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001589 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001590 };
Rob Clarka471b672018-01-10 11:33:30 +01001591
Mario Six95922152018-08-09 14:51:19 +02001592 axi: axi@0 {
1593 compatible = "sandbox,axi";
1594 #address-cells = <0x1>;
1595 #size-cells = <0x1>;
1596 store@0 {
1597 compatible = "sandbox,sandbox_store";
1598 reg = <0x0 0x400>;
1599 };
1600 };
1601
Rob Clarka471b672018-01-10 11:33:30 +01001602 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001603 #address-cells = <1>;
1604 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001605 setting = "sunrise ohoka";
1606 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001607 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001608 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Algapally Santosh Sagardf178992023-09-21 16:50:43 +05301609 stdout-path = "serial0:115200n8";
Rob Clarka471b672018-01-10 11:33:30 +01001610 chosen-test {
1611 compatible = "denx,u-boot-fdt-test";
1612 reg = <9 1>;
1613 };
1614 };
Mario Six35616ef2018-03-12 14:53:33 +01001615
1616 translation-test@8000 {
1617 compatible = "simple-bus";
1618 reg = <0x8000 0x4000>;
1619
1620 #address-cells = <0x2>;
1621 #size-cells = <0x1>;
1622
1623 ranges = <0 0x0 0x8000 0x1000
1624 1 0x100 0x9000 0x1000
1625 2 0x200 0xA000 0x1000
1626 3 0x300 0xB000 0x1000
1627 >;
1628
Fabien Dessenne22236e02019-05-31 15:11:30 +02001629 dma-ranges = <0 0x000 0x10000000 0x1000
1630 1 0x100 0x20000000 0x1000
1631 >;
1632
Mario Six35616ef2018-03-12 14:53:33 +01001633 dev@0,0 {
1634 compatible = "denx,u-boot-fdt-dummy";
1635 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +01001636 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001637 };
1638
1639 dev@1,100 {
1640 compatible = "denx,u-boot-fdt-dummy";
1641 reg = <1 0x100 0x1000>;
1642
1643 };
1644
1645 dev@2,200 {
1646 compatible = "denx,u-boot-fdt-dummy";
1647 reg = <2 0x200 0x1000>;
1648 };
1649
1650
1651 noxlatebus@3,300 {
1652 compatible = "simple-bus";
1653 reg = <3 0x300 0x1000>;
1654
1655 #address-cells = <0x1>;
1656 #size-cells = <0x0>;
1657
1658 dev@42 {
1659 compatible = "denx,u-boot-fdt-dummy";
1660 reg = <0x42>;
1661 };
1662 };
1663 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001664
Dzmitry Sankouski54f4c832023-01-22 18:21:23 +03001665 ofnode-foreach {
1666 compatible = "foreach";
1667
1668 first {
1669 prop1 = <1>;
1670 prop2 = <2>;
1671 };
1672
1673 second {
1674 prop1 = <1>;
1675 prop2 = <2>;
1676 };
1677 };
1678
Mario Six02ad6fb2018-09-27 09:19:31 +02001679 osd {
1680 compatible = "sandbox,sandbox_osd";
1681 };
Tom Rinib93eea72018-09-30 18:16:51 -04001682
Jens Wiklander86afaa62018-09-25 16:40:16 +02001683 sandbox_tee {
1684 compatible = "sandbox,tee";
1685 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001686
1687 sandbox_virtio1 {
1688 compatible = "sandbox,virtio1";
Simon Glass8de5a542023-01-17 10:47:51 -07001689 virtio-type = <4>; /* rng */
Bin Meng1bb290d2018-10-15 02:21:26 -07001690 };
1691
1692 sandbox_virtio2 {
1693 compatible = "sandbox,virtio2";
1694 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001695
Simon Glass8de5a542023-01-17 10:47:51 -07001696 sandbox-virtio-blk {
1697 compatible = "sandbox,virtio1";
1698 virtio-type = <2>; /* block */
1699 };
1700
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001701 sandbox_scmi {
1702 compatible = "sandbox,scmi-devices";
AKASHI Takahiro535a7bd2023-10-16 14:39:45 +09001703 power-domains = <&pwrdom_scmi 2>;
Etienne Carrierebf1f1322022-02-21 09:22:41 +01001704 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere09665cb2022-02-21 09:22:39 +01001705 resets = <&reset_scmi 3>;
1706 regul0-supply = <&regul0_scmi>;
1707 regul1-supply = <&regul1_scmi>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001708 };
1709
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001710 pinctrl {
1711 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001712
Sean Anderson3438e3b2020-09-14 11:01:57 -04001713 pinctrl-names = "default", "alternate";
1714 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1715 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001716
Sean Anderson3438e3b2020-09-14 11:01:57 -04001717 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001718 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001719 pins = "P5";
1720 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001721 bias-pull-up;
1722 input-disable;
1723 };
1724 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001725 pins = "P6";
1726 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001727 output-high;
1728 drive-open-drain;
1729 };
1730 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001731 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001732 bias-pull-down;
1733 input-enable;
1734 };
1735 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001736 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001737 bias-disable;
1738 };
1739 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001740
1741 pinctrl_i2c: i2c {
1742 groups {
1743 groups = "I2C_UART";
1744 function = "I2C";
1745 };
1746
1747 pins {
1748 pins = "P0", "P1";
1749 drive-open-drain;
1750 };
1751 };
1752
1753 pinctrl_i2s: i2s {
1754 groups = "SPI_I2S";
1755 function = "I2S";
1756 };
1757
1758 pinctrl_spi: spi {
1759 groups = "SPI_I2S";
1760 function = "SPI";
1761
1762 cs {
1763 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1764 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1765 };
1766 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001767 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001768
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001769 pinctrl-single-no-width {
1770 compatible = "pinctrl-single";
1771 reg = <0x0000 0x238>;
1772 #pinctrl-cells = <1>;
1773 pinctrl-single,function-mask = <0x7f>;
1774 };
1775
1776 pinctrl-single-pins {
1777 compatible = "pinctrl-single";
1778 reg = <0x0000 0x238>;
1779 #pinctrl-cells = <1>;
1780 pinctrl-single,register-width = <32>;
1781 pinctrl-single,function-mask = <0x7f>;
1782
1783 pinmux_pwm_pins: pinmux_pwm_pins {
1784 pinctrl-single,pins = < 0x48 0x06 >;
1785 };
1786
1787 pinmux_spi0_pins: pinmux_spi0_pins {
1788 pinctrl-single,pins = <
1789 0x190 0x0c
1790 0x194 0x0c
1791 0x198 0x23
1792 0x19c 0x0c
1793 >;
1794 };
1795
1796 pinmux_uart0_pins: pinmux_uart0_pins {
1797 pinctrl-single,pins = <
1798 0x70 0x30
1799 0x74 0x00
1800 >;
1801 };
1802 };
1803
1804 pinctrl-single-bits {
1805 compatible = "pinctrl-single";
1806 reg = <0x0000 0x50>;
1807 #pinctrl-cells = <2>;
1808 pinctrl-single,bit-per-mux;
1809 pinctrl-single,register-width = <32>;
1810 pinctrl-single,function-mask = <0xf>;
1811
1812 pinmux_i2c0_pins: pinmux_i2c0_pins {
1813 pinctrl-single,bits = <
1814 0x10 0x00002200 0x0000ff00
1815 >;
1816 };
1817
1818 pinmux_lcd_pins: pinmux_lcd_pins {
1819 pinctrl-single,bits = <
1820 0x40 0x22222200 0xffffff00
1821 0x44 0x22222222 0xffffffff
1822 0x48 0x00000022 0x000000ff
1823 0x48 0x02000000 0x0f000000
1824 0x4c 0x02000022 0x0f0000ff
1825 >;
1826 };
1827 };
1828
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001829 hwspinlock@0 {
1830 compatible = "sandbox,hwspinlock";
1831 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001832
1833 dma: dma {
1834 compatible = "sandbox,dma";
1835 #dma-cells = <1>;
1836
1837 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1838 dma-names = "m2m", "tx0", "rx0";
1839 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001840
Alex Marginean0649be52019-07-12 10:13:53 +03001841 /*
1842 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1843 * end of the test. If parent mdio is removed first, clean-up of the
1844 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1845 * active at the end of the test. That it turn doesn't allow the mdio
1846 * class to be destroyed, triggering an error.
1847 */
1848 mdio-mux-test {
1849 compatible = "sandbox,mdio-mux";
1850 #address-cells = <1>;
1851 #size-cells = <0>;
1852 mdio-parent-bus = <&mdio>;
1853
1854 mdio-ch-test@0 {
1855 reg = <0>;
1856 };
1857 mdio-ch-test@1 {
1858 reg = <1>;
1859 };
1860 };
1861
1862 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001863 compatible = "sandbox,mdio";
Marek Behúnf4f1ddc2022-04-07 00:32:57 +02001864 #address-cells = <1>;
1865 #size-cells = <0>;
1866
1867 ethphy1: ethernet-phy@1 {
1868 reg = <1>;
1869 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001870 };
Sean Andersonb7860542020-06-24 06:41:12 -04001871
1872 pm-bus-test {
1873 compatible = "simple-pm-bus";
1874 clocks = <&clk_sandbox 4>;
1875 power-domains = <&pwrdom 1>;
1876 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001877
1878 resetc2: syscon-reset {
1879 compatible = "syscon-reset";
1880 #reset-cells = <1>;
1881 regmap = <&syscon0>;
1882 offset = <1>;
1883 mask = <0x27FFFFFF>;
1884 assert-high = <0>;
1885 };
1886
1887 syscon-reset-test {
1888 compatible = "sandbox,misc_sandbox";
1889 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1890 reset-names = "valid", "no_mask", "out_of_range";
1891 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301892
Simon Glass458b66a2020-11-05 06:32:05 -07001893 sysinfo {
1894 compatible = "sandbox,sysinfo-sandbox";
1895 };
1896
Sean Anderson1c830672021-04-20 10:50:58 -04001897 sysinfo-gpio {
1898 compatible = "gpio-sysinfo";
1899 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1900 revisions = <19>, <5>;
1901 names = "rev_a", "foo";
1902 };
1903
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301904 some_regmapped-bus {
1905 #address-cells = <0x1>;
1906 #size-cells = <0x1>;
1907
1908 ranges = <0x0 0x0 0x10>;
1909 compatible = "simple-bus";
1910
1911 regmap-test_0 {
1912 reg = <0 0x10>;
1913 compatible = "sandbox,regmap_test";
1914 };
1915 };
Robert Marko9cf87122022-09-06 13:30:35 +02001916
1917 thermal {
1918 compatible = "sandbox,thermal";
1919 };
Sughosh Ganu77079e72022-10-21 18:16:05 +05301920
1921 fwu-mdata {
1922 compatible = "u-boot,fwu-mdata-gpt";
1923 fwu-mdata-store = <&mmc0>;
1924 };
Abdellatif El Khlifi6b005872023-04-17 10:11:55 +01001925
1926 nvmxip-qspi1@08000000 {
1927 compatible = "nvmxip,qspi";
1928 reg = <0x08000000 0x00200000>;
1929 lba_shift = <9>;
1930 lba = <4096>;
1931 };
1932
1933 nvmxip-qspi2@08200000 {
1934 compatible = "nvmxip,qspi";
1935 reg = <0x08200000 0x00100000>;
1936 lba_shift = <9>;
1937 lba = <2048>;
1938 };
Svyatoslav Ryhel669f5c82023-04-25 10:57:21 +03001939
1940 extcon {
1941 compatible = "sandbox,extcon";
1942 };
Abdellatif El Khlifi4970d5b2023-08-04 14:33:41 +01001943
1944 arm-ffa-emul {
1945 compatible = "sandbox,arm-ffa-emul";
1946
1947 sandbox-arm-ffa {
1948 compatible = "sandbox,arm-ffa";
1949 };
1950 };
Sean Anderson326422b2023-11-04 16:37:52 -04001951
1952 nand-controller {
1953 #address-cells = <1>;
1954 #size-cells = <0>;
1955 compatible = "sandbox,nand";
1956
1957 nand@0 {
1958 reg = <0>;
1959 nand-ecc-mode = "soft";
1960 sandbox,id = [00 e3];
1961 sandbox,erasesize = <(8 * 1024)>;
1962 sandbox,oobsize = <16>;
1963 sandbox,pagesize = <512>;
1964 sandbox,pages = <0x2000>;
1965 sandbox,err-count = <1>;
1966 sandbox,err-step-size = <512>;
1967 };
1968
1969 /* MT29F64G08AKABA */
1970 nand@1 {
1971 reg = <1>;
1972 nand-ecc-mode = "soft_bch";
1973 sandbox,id = [2C 48 00 26 89 00 00 00];
1974 sandbox,onfi = [
1975 4f 4e 46 49 0e 00 5a 00
1976 ff 01 00 00 00 00 03 00
1977 00 00 00 00 00 00 00 00
1978 00 00 00 00 00 00 00 00
1979 4d 49 43 52 4f 4e 20 20
1980 20 20 20 20 4d 54 32 39
1981 46 36 34 47 30 38 41 4b
1982 41 42 41 43 35 20 20 20
1983 2c 00 00 00 00 00 00 00
1984 00 00 00 00 00 00 00 00
1985 00 10 00 00 e0 00 00 02
1986 00 00 1c 00 80 00 00 00
1987 00 10 00 00 02 23 01 50
1988 00 01 05 01 00 00 04 00
1989 04 01 1e 00 00 00 00 00
1990 00 00 00 00 00 00 00 00
1991 0e 1f 00 1f 00 f4 01 ac
1992 0d 19 00 c8 00 00 00 00
1993 00 00 00 00 00 00 0a 07
1994 19 00 00 00 00 00 00 00
1995 00 00 00 00 01 00 01 00
1996 00 00 04 10 01 81 04 02
1997 02 01 1e 90 00 00 00 00
1998 00 00 00 00 00 00 00 00
1999 00 00 00 00 00 00 00 00
2000 00 00 00 00 00 00 00 00
2001 00 00 00 00 00 00 00 00
2002 00 00 00 00 00 00 00 00
2003 00 00 00 00 00 00 00 00
2004 00 00 00 00 00 00 00 00
2005 00 00 00 00 00 00 00 00
2006 00 00 00 00 00 03 20 7d
2007 ];
2008 sandbox,erasesize = <(512 * 1024)>;
2009 sandbox,oobsize = <224>;
2010 sandbox,pagesize = <4096>;
2011 sandbox,pages = <0x200000>;
2012 sandbox,err-count = <3>;
2013 sandbox,err-step-size = <512>;
2014 };
2015 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07002016};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02002017
2018#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01002019#include "cros-ec-keyboard.dtsi"
Simon Glass5e135d32022-10-20 18:23:15 -06002020
2021#ifdef CONFIG_SANDBOX_VPL
2022#include "sandbox_vpl.dtsi"
2023#endif
Simon Glass61300722023-06-01 10:23:01 -06002024
Sughosh Ganu05137922024-03-27 16:19:00 +05302025#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
2026#include "sandbox_capsule.dtsi"
2027#endif
2028
Simon Glass61300722023-06-01 10:23:01 -06002029#include "cedit.dtsi"