blob: 5015f7d16d1ac37df7d558918126f3f45888f795 [file] [log] [blame]
Yann Gautier4b0c72a2018-07-16 10:54:09 +02001/*
Yann Gautierb76c61a2020-12-16 10:17:35 +01002 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
Yann Gautier4b0c72a2018-07-16 10:54:09 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Yann Gautier4b0c72a2018-07-16 10:54:09 +02007#include <assert.h>
Yann Gautier658775c2021-07-06 10:00:44 +02008#include <errno.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009#include <string.h>
10
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <arch_helpers.h>
12#include <common/bl_common.h>
13#include <common/debug.h>
14#include <common/desc_image_load.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <drivers/generic_delay_timer.h>
Yann Gautiera3bd8d12021-06-18 11:33:26 +020016#include <drivers/mmc.h>
Yann Gautier3edc7c32019-05-20 19:17:08 +020017#include <drivers/st/bsec.h>
Pascal Pailletfc7b8052021-01-29 14:48:49 +010018#include <drivers/st/regulator_fixed.h>
Yann Gautier091eab52019-06-04 18:06:34 +020019#include <drivers/st/stm32_iwdg.h>
Yann Gautier3d8497c2021-10-18 16:06:22 +020020#include <drivers/st/stm32_uart.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000021#include <drivers/st/stm32mp1_clk.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000022#include <drivers/st/stm32mp1_pwr.h>
23#include <drivers/st/stm32mp1_ram.h>
Yann Gautier0c810882021-12-17 09:53:04 +010024#include <drivers/st/stm32mp_pmic.h>
Yann Gautier658775c2021-07-06 10:00:44 +020025#include <lib/fconf/fconf.h>
26#include <lib/fconf/fconf_dyn_cfg_getter.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000027#include <lib/mmio.h>
Yann Gautierb3386f72019-04-19 09:41:01 +020028#include <lib/optee_utils.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000029#include <lib/xlat_tables/xlat_tables_v2.h>
30#include <plat/common/platform.h>
31
Yann Gautier0c810882021-12-17 09:53:04 +010032#include <platform_def.h>
Sughosh Ganu03e2f802021-12-01 15:56:27 +053033#include <stm32mp_common.h>
Yann Gautier091eab52019-06-04 18:06:34 +020034#include <stm32mp1_dbgmcu.h>
Yann Gautier4b0c72a2018-07-16 10:54:09 +020035
Lionel Debieve7192a002020-01-28 09:02:41 +010036#if DEBUG
37static const char debug_msg[] = {
38 "***************************************************\n"
39 "** DEBUG ACCESS PORT IS OPEN! **\n"
40 "** This boot image is only for debugging purpose **\n"
41 "** and is unsafe for production use. **\n"
42 "** **\n"
43 "** If you see this message and you are not **\n"
44 "** debugging report this immediately to your **\n"
45 "** vendor! **\n"
46 "***************************************************\n"
47};
48#endif
49
Yann Gautiercc5f89a2020-02-12 09:36:23 +010050#if STM32MP15
Lionel Debieve7bd96f42019-09-03 12:22:23 +020051static struct stm32mp_auth_ops stm32mp1_auth_ops;
Yann Gautiercc5f89a2020-02-12 09:36:23 +010052#endif
Yann Gautier8593e442018-11-14 18:46:15 +010053
Yann Gautierf9d40d52019-01-17 14:41:46 +010054static void print_reset_reason(void)
55{
Yann Gautier3d78a2e2019-02-14 11:01:20 +010056 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR);
Yann Gautierf9d40d52019-01-17 14:41:46 +010057
58 if (rstsr == 0U) {
59 WARN("Reset reason unknown\n");
60 return;
61 }
62
63 INFO("Reset reason (0x%x):\n", rstsr);
64
65 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) {
66 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) {
67 INFO("System exits from STANDBY\n");
68 return;
69 }
70
71 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) {
72 INFO("MPU exits from CSTANDBY\n");
73 return;
74 }
75 }
76
77 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) {
78 INFO(" Power-on Reset (rst_por)\n");
79 return;
80 }
81
82 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) {
83 INFO(" Brownout Reset (rst_bor)\n");
84 return;
85 }
86
Yann Gautiercc5f89a2020-02-12 09:36:23 +010087#if STM32MP15
Yann Gautierf9d40d52019-01-17 14:41:46 +010088 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) {
89 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
90 INFO(" System reset generated by MCU (MCSYSRST)\n");
91 } else {
92 INFO(" Local reset generated by MCU (MCSYSRST)\n");
93 }
94 return;
95 }
Yann Gautiercc5f89a2020-02-12 09:36:23 +010096#endif
Yann Gautierf9d40d52019-01-17 14:41:46 +010097
98 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) {
99 INFO(" System reset generated by MPU (MPSYSRST)\n");
100 return;
101 }
102
103 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) {
104 INFO(" Reset due to a clock failure on HSE\n");
105 return;
106 }
107
108 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) {
109 INFO(" IWDG1 Reset (rst_iwdg1)\n");
110 return;
111 }
112
113 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) {
114 INFO(" IWDG2 Reset (rst_iwdg2)\n");
115 return;
116 }
117
118 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) {
119 INFO(" MPU Processor 0 Reset\n");
120 return;
121 }
122
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100123#if STM32MP15
Yann Gautierf9d40d52019-01-17 14:41:46 +0100124 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) {
125 INFO(" MPU Processor 1 Reset\n");
126 return;
127 }
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100128#endif
Yann Gautierf9d40d52019-01-17 14:41:46 +0100129
130 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
131 INFO(" Pad Reset from NRST\n");
132 return;
133 }
134
135 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) {
136 INFO(" Reset due to a failure of VDD_CORE\n");
137 return;
138 }
139
140 ERROR(" Unidentified reset reason\n");
141}
142
143void bl2_el3_early_platform_setup(u_register_t arg0,
144 u_register_t arg1 __unused,
145 u_register_t arg2 __unused,
146 u_register_t arg3 __unused)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200147{
Yann Gautierd1435742021-10-18 10:55:23 +0200148 stm32mp_setup_early_console();
149
Yann Gautiera2e2a302019-02-14 11:13:39 +0100150 stm32mp_save_boot_ctx_address(arg0);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200151}
152
153void bl2_platform_setup(void)
154{
Yann Gautiercaf575b2018-07-24 17:18:19 +0200155 int ret;
156
Yann Gautiercaf575b2018-07-24 17:18:19 +0200157 ret = stm32mp1_ddr_probe();
158 if (ret < 0) {
159 ERROR("Invalid DDR init: error %d\n", ret);
160 panic();
161 }
162
Yann Gautierf3bd87e2020-09-04 15:55:53 +0200163 /* Map DDR for binary load, now with cacheable attribute */
Yann Gautiera55169b2020-01-10 18:18:59 +0100164 ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
Yann Gautierf3bd87e2020-09-04 15:55:53 +0200165 STM32MP_DDR_MAX_SIZE, MT_MEMORY | MT_RW | MT_SECURE);
166 if (ret < 0) {
167 ERROR("DDR mapping: error %d\n", ret);
168 panic();
169 }
Yann Gautiera55169b2020-01-10 18:18:59 +0100170
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200171#if STM32MP_USE_STM32IMAGE
Yann Gautierb3386f72019-04-19 09:41:01 +0200172#ifdef AARCH32_SP_OPTEE
173 INFO("BL2 runs OP-TEE setup\n");
Yann Gautierb3386f72019-04-19 09:41:01 +0200174#else
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200175 INFO("BL2 runs SP_MIN setup\n");
Yann Gautierb3386f72019-04-19 09:41:01 +0200176#endif
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200177#endif /* STM32MP_USE_STM32IMAGE */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200178}
179
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100180#if STM32MP15
Yann Gautier5c1dab32019-04-17 15:12:58 +0200181static void update_monotonic_counter(void)
182{
183 uint32_t version;
184 uint32_t otp;
185
186 CASSERT(STM32_TF_VERSION <= MAX_MONOTONIC_VALUE,
187 assert_stm32mp1_monotonic_counter_reach_max);
188
189 /* Check if monotonic counter needs to be incremented */
190 if (stm32_get_otp_index(MONOTONIC_OTP, &otp, NULL) != 0) {
191 panic();
192 }
193
194 if (stm32_get_otp_value_from_idx(otp, &version) != 0) {
195 panic();
196 }
197
198 if ((version + 1U) < BIT(STM32_TF_VERSION)) {
199 uint32_t result;
200
201 /* Need to increment the monotonic counter. */
202 version = BIT(STM32_TF_VERSION) - 1U;
203
204 result = bsec_program_otp(version, otp);
205 if (result != BSEC_OK) {
206 ERROR("BSEC: MONOTONIC_OTP program Error %u\n",
207 result);
208 panic();
209 }
210 INFO("Monotonic counter has been incremented (value 0x%x)\n",
211 version);
212 }
213}
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100214#endif
Yann Gautier5c1dab32019-04-17 15:12:58 +0200215
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200216void bl2_el3_plat_arch_setup(void)
217{
Yann Gautier69035a82018-07-05 16:48:16 +0200218 const char *board_model;
Yann Gautier41934662018-07-20 11:36:05 +0200219 boot_api_context_t *boot_context =
Yann Gautiera2e2a302019-02-14 11:13:39 +0100220 (boot_api_context_t *)stm32mp_get_boot_ctx_address();
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100221 uintptr_t pwr_base;
222 uintptr_t rcc_base;
Yann Gautier41934662018-07-20 11:36:05 +0200223
Nicolas Le Bayon97287cd2019-05-20 18:35:02 +0200224 if (bsec_probe() != 0U) {
225 panic();
226 }
227
Yann Gautierf9d40d52019-01-17 14:41:46 +0100228 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
229 BL_CODE_END - BL_CODE_BASE,
230 MT_CODE | MT_SECURE);
231
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200232#if STM32MP_USE_STM32IMAGE
Yann Gautierb3386f72019-04-19 09:41:01 +0200233#ifdef AARCH32_SP_OPTEE
Yann Gautierb3386f72019-04-19 09:41:01 +0200234 mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE,
235 STM32MP_OPTEE_SIZE,
236 MT_MEMORY | MT_RW | MT_SECURE);
Yann Gautier90f84d72021-07-13 14:44:09 +0200237#else
238 /* Prevent corruption of preloaded BL32 */
239 mmap_add_region(BL32_BASE, BL32_BASE,
240 BL32_LIMIT - BL32_BASE,
241 MT_RO_DATA | MT_SECURE);
Yann Gautierb3386f72019-04-19 09:41:01 +0200242#endif
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200243#endif /* STM32MP_USE_STM32IMAGE */
244
Yann Gautierf9d40d52019-01-17 14:41:46 +0100245 /* Prevent corruption of preloaded Device Tree */
246 mmap_add_region(DTB_BASE, DTB_BASE,
247 DTB_LIMIT - DTB_BASE,
Yann Gautier3d33df62019-12-17 17:11:10 +0100248 MT_RO_DATA | MT_SECURE);
Yann Gautierf9d40d52019-01-17 14:41:46 +0100249
250 configure_mmu();
251
Yann Gautier05773eb2020-08-24 11:51:50 +0200252 if (dt_open_and_check(STM32MP_DTB_BASE) < 0) {
Yann Gautierf9d40d52019-01-17 14:41:46 +0100253 panic();
254 }
255
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100256 pwr_base = stm32mp_pwr_base();
257 rcc_base = stm32mp_rcc_base();
258
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200259 /*
260 * Disable the backup domain write protection.
261 * The protection is enable at each reset by hardware
262 * and must be disabled by software.
263 */
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100264 mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200265
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100266 while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) {
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200267 ;
268 }
269
270 /* Reset backup domain on cold boot cases */
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100271 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) {
272 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200273
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100274 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) ==
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200275 0U) {
276 ;
277 }
278
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100279 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200280 }
281
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100282#if STM32MP15
Yann Gautiered342322019-02-15 17:33:27 +0100283 /* Disable MCKPROT */
284 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT);
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100285#endif
Yann Gautiered342322019-02-15 17:33:27 +0100286
Yann Gautierc0882f42021-04-27 18:19:13 +0200287 /*
288 * Set minimum reset pulse duration to 31ms for discrete power
289 * supplied boards.
290 */
291 if (dt_pmic_status() <= 0) {
292 mmio_clrsetbits_32(rcc_base + RCC_RDLSICR,
293 RCC_RDLSICR_MRD_MASK,
294 31U << RCC_RDLSICR_MRD_SHIFT);
295 }
296
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200297 generic_delay_timer_init();
298
Yann Gautier3d8497c2021-10-18 16:06:22 +0200299#if STM32MP_UART_PROGRAMMER
300 /* Disable programmer UART before changing clock tree */
301 if (boot_context->boot_interface_selected ==
302 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) {
303 uintptr_t uart_prog_addr =
304 get_uart_address(boot_context->boot_interface_instance);
305
306 stm32_uart_stop(uart_prog_addr);
307 }
308#endif
Yann Gautier9aea69e2018-07-24 17:13:36 +0200309 if (stm32mp1_clk_probe() < 0) {
310 panic();
311 }
312
313 if (stm32mp1_clk_init() < 0) {
314 panic();
315 }
316
Yann Gautier6eef5252021-12-10 17:04:40 +0100317 stm32_save_boot_interface(boot_context->boot_interface_selected,
318 boot_context->boot_interface_instance);
Igor Opaniukf07e8f32022-06-23 21:19:26 +0300319 stm32_save_boot_auth(boot_context->auth_status,
320 boot_context->boot_partition_used_toboot);
Yann Gautier6eef5252021-12-10 17:04:40 +0100321
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100322#if STM32MP_USB_PROGRAMMER && STM32MP15
Yann Gautiercd16df32021-06-04 14:04:05 +0200323 /* Deconfigure all UART RX pins configured by ROM code */
324 stm32mp1_deconfigure_uart_pins();
325#endif
326
Yann Gautier66baa962021-10-18 14:01:00 +0200327 if (stm32mp_uart_console_setup() != 0) {
Yann Gautier69035a82018-07-05 16:48:16 +0200328 goto skip_console_init;
329 }
330
Yann Gautierc7374052019-06-04 18:02:37 +0200331 stm32mp_print_cpuinfo();
332
Yann Gautier69035a82018-07-05 16:48:16 +0200333 board_model = dt_get_board_model();
334 if (board_model != NULL) {
Yann Gautierf9d40d52019-01-17 14:41:46 +0100335 NOTICE("Model: %s\n", board_model);
Yann Gautier69035a82018-07-05 16:48:16 +0200336 }
337
Yann Gautier35dc0772019-05-13 18:34:48 +0200338 stm32mp_print_boardinfo();
339
Lionel Debieve7bd96f42019-09-03 12:22:23 +0200340 if (boot_context->auth_status != BOOT_API_CTX_AUTH_NO) {
341 NOTICE("Bootrom authentication %s\n",
342 (boot_context->auth_status == BOOT_API_CTX_AUTH_FAILED) ?
343 "failed" : "succeeded");
344 }
345
Yann Gautier69035a82018-07-05 16:48:16 +0200346skip_console_init:
Pascal Pailletfc7b8052021-01-29 14:48:49 +0100347 if (fixed_regulator_register() != 0) {
348 panic();
349 }
350
Yann Gautier45c1e582020-09-17 11:54:52 +0200351 if (dt_pmic_status() > 0) {
352 initialize_pmic();
Yann Gautierb2ba78e2022-01-18 10:39:52 +0100353 if (pmic_voltages_init() != 0) {
354 ERROR("PMIC voltages init failed\n");
355 panic();
356 }
Nicolas Le Bayon0b10b652019-11-18 13:13:36 +0100357 print_pmic_info_and_debug();
Yann Gautier45c1e582020-09-17 11:54:52 +0200358 }
359
360 stm32mp1_syscfg_init();
361
Yann Gautier091eab52019-06-04 18:06:34 +0200362 if (stm32_iwdg_init() < 0) {
363 panic();
364 }
365
366 stm32_iwdg_refresh();
367
Lionel Debieve7192a002020-01-28 09:02:41 +0100368 if (bsec_read_debug_conf() != 0U) {
369 if (stm32mp_is_closed_device()) {
370#if DEBUG
371 WARN("\n%s", debug_msg);
372#else
373 ERROR("***Debug opened on closed chip***\n");
374#endif
375 }
376 }
377
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100378#if STM32MP15
Lionel Debieve06bc62d2019-12-06 12:42:20 +0100379 if (stm32mp_is_auth_supported()) {
380 stm32mp1_auth_ops.check_key =
381 boot_context->bootrom_ecdsa_check_key;
382 stm32mp1_auth_ops.verify_signature =
383 boot_context->bootrom_ecdsa_verify_signature;
Lionel Debieve7bd96f42019-09-03 12:22:23 +0200384
Lionel Debieve06bc62d2019-12-06 12:42:20 +0100385 stm32mp_init_auth(&stm32mp1_auth_ops);
386 }
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100387#endif
Lionel Debieve7bd96f42019-09-03 12:22:23 +0200388
Yann Gautiercaf575b2018-07-24 17:18:19 +0200389 stm32mp1_arch_security_setup();
390
Yann Gautierf9d40d52019-01-17 14:41:46 +0100391 print_reset_reason();
392
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100393#if STM32MP15
Yann Gautier5c1dab32019-04-17 15:12:58 +0200394 update_monotonic_counter();
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100395#endif
Yann Gautier5c1dab32019-04-17 15:12:58 +0200396
Yann Gautierb76c61a2020-12-16 10:17:35 +0100397 stm32mp1_syscfg_enable_io_compensation_finish();
398
Yann Gautier29f1f942021-07-13 18:07:41 +0200399#if !STM32MP_USE_STM32IMAGE
400 fconf_populate("TB_FW", STM32MP_DTB_BASE);
401#endif /* !STM32MP_USE_STM32IMAGE */
402
Yann Gautiera2e2a302019-02-14 11:13:39 +0100403 stm32mp_io_setup();
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200404}
Yann Gautierb3386f72019-04-19 09:41:01 +0200405
Yann Gautierb3386f72019-04-19 09:41:01 +0200406/*******************************************************************************
407 * This function can be used by the platforms to update/use image
408 * information for given `image_id`.
409 ******************************************************************************/
410int bl2_plat_handle_post_image_load(unsigned int image_id)
411{
412 int err = 0;
413 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
414 bl_mem_params_node_t *bl32_mem_params;
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200415 bl_mem_params_node_t *pager_mem_params __unused;
416 bl_mem_params_node_t *paged_mem_params __unused;
Yann Gautier658775c2021-07-06 10:00:44 +0200417#if !STM32MP_USE_STM32IMAGE
418 const struct dyn_cfg_dtb_info_t *config_info;
419 bl_mem_params_node_t *tos_fw_mem_params;
420 unsigned int i;
Yann Gautierfd648352021-12-13 15:24:41 +0100421 unsigned int idx;
Yann Gautier658775c2021-07-06 10:00:44 +0200422 unsigned long long ddr_top __unused;
423 const unsigned int image_ids[] = {
424 BL32_IMAGE_ID,
425 BL33_IMAGE_ID,
426 HW_CONFIG_ID,
427 TOS_FW_CONFIG_ID,
428 };
429#endif /* !STM32MP_USE_STM32IMAGE */
Yann Gautierb3386f72019-04-19 09:41:01 +0200430
431 assert(bl_mem_params != NULL);
432
433 switch (image_id) {
Yann Gautier658775c2021-07-06 10:00:44 +0200434#if !STM32MP_USE_STM32IMAGE
435 case FW_CONFIG_ID:
436 /* Set global DTB info for fixed fw_config information */
Manish V Badarkhefab76282022-03-16 13:51:26 +0000437 set_config_info(STM32MP_FW_CONFIG_BASE, ~0UL, STM32MP_FW_CONFIG_MAX_SIZE,
438 FW_CONFIG_ID);
Yann Gautier658775c2021-07-06 10:00:44 +0200439 fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE);
440
Yann Gautierfd648352021-12-13 15:24:41 +0100441 idx = dyn_cfg_dtb_info_get_index(TOS_FW_CONFIG_ID);
442
Yann Gautier658775c2021-07-06 10:00:44 +0200443 /* Iterate through all the fw config IDs */
444 for (i = 0U; i < ARRAY_SIZE(image_ids); i++) {
Yann Gautierfd648352021-12-13 15:24:41 +0100445 if ((image_ids[i] == TOS_FW_CONFIG_ID) && (idx == FCONF_INVALID_IDX)) {
446 continue;
447 }
448
Yann Gautier658775c2021-07-06 10:00:44 +0200449 bl_mem_params = get_bl_mem_params_node(image_ids[i]);
450 assert(bl_mem_params != NULL);
451
452 config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]);
453 if (config_info == NULL) {
454 continue;
455 }
456
457 bl_mem_params->image_info.image_base = config_info->config_addr;
458 bl_mem_params->image_info.image_max_size = config_info->config_max_size;
459
460 bl_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING;
461
462 switch (image_ids[i]) {
463 case BL32_IMAGE_ID:
464 bl_mem_params->ep_info.pc = config_info->config_addr;
465
466 /* In case of OPTEE, initialize address space with tos_fw addr */
467 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
Yann Gautierc6f77b02022-05-06 09:50:43 +0200468 assert(pager_mem_params != NULL);
Yann Gautier658775c2021-07-06 10:00:44 +0200469 pager_mem_params->image_info.image_base = config_info->config_addr;
470 pager_mem_params->image_info.image_max_size =
471 config_info->config_max_size;
472
473 /* Init base and size for pager if exist */
474 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
Yann Gautiere622a3d2022-06-20 11:43:17 +0200475 if (paged_mem_params != NULL) {
476 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE +
477 (dt_get_ddr_size() - STM32MP_DDR_S_SIZE -
478 STM32MP_DDR_SHMEM_SIZE);
479 paged_mem_params->image_info.image_max_size =
480 STM32MP_DDR_S_SIZE;
481 }
Yann Gautier658775c2021-07-06 10:00:44 +0200482 break;
483
484 case BL33_IMAGE_ID:
485 bl_mem_params->ep_info.pc = config_info->config_addr;
486 break;
487
488 case HW_CONFIG_ID:
489 case TOS_FW_CONFIG_ID:
490 break;
491
492 default:
493 return -EINVAL;
494 }
495 }
496 break;
497#endif /* !STM32MP_USE_STM32IMAGE */
498
Yann Gautierb3386f72019-04-19 09:41:01 +0200499 case BL32_IMAGE_ID:
Yann Gautier90f84d72021-07-13 14:44:09 +0200500 if (optee_header_is_valid(bl_mem_params->image_info.image_base)) {
Yann Gautiere622a3d2022-06-20 11:43:17 +0200501 image_info_t *paged_image_info = NULL;
502
Yann Gautier90f84d72021-07-13 14:44:09 +0200503 /* BL32 is OP-TEE header */
504 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base;
505 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
Yann Gautiere622a3d2022-06-20 11:43:17 +0200506 assert(pager_mem_params != NULL);
507
Yann Gautier90f84d72021-07-13 14:44:09 +0200508 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
Yann Gautiere622a3d2022-06-20 11:43:17 +0200509 if (paged_mem_params != NULL) {
510 paged_image_info = &paged_mem_params->image_info;
511 }
Yann Gautierb3386f72019-04-19 09:41:01 +0200512
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200513#if STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE)
Yann Gautier90f84d72021-07-13 14:44:09 +0200514 /* Set OP-TEE extra image load areas at run-time */
515 pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE;
516 pager_mem_params->image_info.image_max_size = STM32MP_OPTEE_SIZE;
Yann Gautierb3386f72019-04-19 09:41:01 +0200517
Yann Gautier90f84d72021-07-13 14:44:09 +0200518 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE +
519 dt_get_ddr_size() -
520 STM32MP_DDR_S_SIZE -
521 STM32MP_DDR_SHMEM_SIZE;
522 paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE;
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200523#endif /* STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) */
Yann Gautierb3386f72019-04-19 09:41:01 +0200524
Yann Gautier90f84d72021-07-13 14:44:09 +0200525 err = parse_optee_header(&bl_mem_params->ep_info,
526 &pager_mem_params->image_info,
Yann Gautiere622a3d2022-06-20 11:43:17 +0200527 paged_image_info);
528 if (err != 0) {
Yann Gautier90f84d72021-07-13 14:44:09 +0200529 ERROR("OPTEE header parse error.\n");
530 panic();
531 }
Yann Gautierb3386f72019-04-19 09:41:01 +0200532
Yann Gautier90f84d72021-07-13 14:44:09 +0200533 /* Set optee boot info from parsed header data */
Yann Gautiere622a3d2022-06-20 11:43:17 +0200534 if (paged_mem_params != NULL) {
535 bl_mem_params->ep_info.args.arg0 =
536 paged_mem_params->image_info.image_base;
537 } else {
538 bl_mem_params->ep_info.args.arg0 = 0U;
539 }
540
541 bl_mem_params->ep_info.args.arg1 = 0U; /* Unused */
542 bl_mem_params->ep_info.args.arg2 = 0U; /* No DT supported */
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200543 } else {
544#if !STM32MP_USE_STM32IMAGE
545 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base;
Yann Gautier658775c2021-07-06 10:00:44 +0200546 tos_fw_mem_params = get_bl_mem_params_node(TOS_FW_CONFIG_ID);
Yann Gautierc6f77b02022-05-06 09:50:43 +0200547 assert(tos_fw_mem_params != NULL);
Yann Gautier658775c2021-07-06 10:00:44 +0200548 bl_mem_params->image_info.image_max_size +=
549 tos_fw_mem_params->image_info.image_max_size;
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200550#endif /* !STM32MP_USE_STM32IMAGE */
551 bl_mem_params->ep_info.args.arg0 = 0;
Yann Gautier90f84d72021-07-13 14:44:09 +0200552 }
Yann Gautierb3386f72019-04-19 09:41:01 +0200553 break;
554
555 case BL33_IMAGE_ID:
556 bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
557 assert(bl32_mem_params != NULL);
558 bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
Sughosh Ganu03e2f802021-12-01 15:56:27 +0530559#if !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT
560 stm32mp1_fwu_set_boot_idx();
561#endif /* !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT */
Yann Gautierb3386f72019-04-19 09:41:01 +0200562 break;
563
564 default:
565 /* Do nothing in default case */
566 break;
567 }
568
Yann Gautiera3bd8d12021-06-18 11:33:26 +0200569#if STM32MP_SDMMC || STM32MP_EMMC
570 /*
571 * Invalidate remaining data read from MMC but not flushed by load_image_flush().
572 * We take the worst case which is 2 MMC blocks.
573 */
574 if ((image_id != FW_CONFIG_ID) &&
575 ((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) {
576 inv_dcache_range(bl_mem_params->image_info.image_base +
577 bl_mem_params->image_info.image_size,
578 2U * MMC_BLOCK_SIZE);
579 }
580#endif /* STM32MP_SDMMC || STM32MP_EMMC */
581
Yann Gautierb3386f72019-04-19 09:41:01 +0200582 return err;
583}
Yann Gautierd2d9b962021-08-16 11:58:01 +0200584
585void bl2_el3_plat_prepare_exit(void)
586{
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200587 uint16_t boot_itf = stm32mp_get_boot_itf_selected();
588
589 switch (boot_itf) {
Patrick Delaunaye50571b2021-10-28 13:48:52 +0200590#if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER
591 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART:
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200592 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB:
593 /* Invalidate the downloaded buffer used with io_memmap */
594 inv_dcache_range(DWL_BUFFER_BASE, DWL_BUFFER_SIZE);
595 break;
Patrick Delaunaye50571b2021-10-28 13:48:52 +0200596#endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */
Patrick Delaunay9c5ee782021-07-06 14:07:56 +0200597 default:
598 /* Do nothing in default case */
599 break;
600 }
601
Yann Gautierd2d9b962021-08-16 11:58:01 +0200602 stm32mp1_security_setup();
603}