blob: 24af13e76b3834e9b214ee51dfb1e283efca2185 [file] [log] [blame]
Paul Beesleyfc9ee362019-03-07 15:47:15 +00001Porting Guide
2=============
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
Douglas Raillardd7c21b72017-06-28 15:23:03 +01004Introduction
5------------
6
Dan Handley610e7e12018-03-01 18:44:00 +00007Porting Trusted Firmware-A (TF-A) to a new platform involves making some
Douglas Raillardd7c21b72017-06-28 15:23:03 +01008mandatory and optional modifications for both the cold and warm boot paths.
9Modifications consist of:
10
11- Implementing a platform-specific function or variable,
12- Setting up the execution context in a certain way, or
13- Defining certain constants (for example #defines).
14
15The platform-specific functions and variables are declared in
Paul Beesleyf8640672019-04-12 14:19:42 +010016``include/plat/common/platform.h``. The firmware provides a default
17implementation of variables and functions to fulfill the optional requirements.
18These implementations are all weakly defined; they are provided to ease the
19porting effort. Each platform port can override them with its own implementation
20if the default implementation is inadequate.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010021
Douglas Raillardd7c21b72017-06-28 15:23:03 +010022Some modifications are common to all Boot Loader (BL) stages. Section 2
23discusses these in detail. The subsequent sections discuss the remaining
24modifications for each BL stage in detail.
25
Paul Beesleyf8640672019-04-12 14:19:42 +010026Please refer to the :ref:`Platform Compatibility Policy` for the policy
27regarding compatibility and deprecation of these porting interfaces.
Soby Mathew02bdbb92018-09-26 11:17:23 +010028
Antonio Nino Diaz645feb42019-02-13 14:07:38 +000029Only Arm development platforms (such as FVP and Juno) may use the
30functions/definitions in ``include/plat/arm/common/`` and the corresponding
31source files in ``plat/arm/common/``. This is done so that there are no
32dependencies between platforms maintained by different people/companies. If you
33want to use any of the functionality present in ``plat/arm`` files, please
34create a pull request that moves the code to ``plat/common`` so that it can be
35discussed.
36
Douglas Raillardd7c21b72017-06-28 15:23:03 +010037Common modifications
38--------------------
39
40This section covers the modifications that should be made by the platform for
41each BL stage to correctly port the firmware stack. They are categorized as
42either mandatory or optional.
43
44Common mandatory modifications
45------------------------------
46
47A platform port must enable the Memory Management Unit (MMU) as well as the
48instruction and data caches for each BL stage. Setting up the translation
49tables is the responsibility of the platform port because memory maps differ
50across platforms. A memory translation library (see ``lib/xlat_tables/``) is
Sandrine Bailleux1861b7a2017-07-20 16:11:01 +010051provided to help in this setup.
52
53Note that although this library supports non-identity mappings, this is intended
54only for re-mapping peripheral physical addresses and allows platforms with high
55I/O addresses to reduce their virtual address space. All other addresses
56corresponding to code and data must currently use an identity mapping.
57
Dan Handley610e7e12018-03-01 18:44:00 +000058Also, the only translation granule size supported in TF-A is 4KB, as various
59parts of the code assume that is the case. It is not possible to switch to
6016 KB or 64 KB granule sizes at the moment.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010061
Dan Handley610e7e12018-03-01 18:44:00 +000062In Arm standard platforms, each BL stage configures the MMU in the
Douglas Raillardd7c21b72017-06-28 15:23:03 +010063platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses
64an identity mapping for all addresses.
65
66If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a
67block of identity mapped secure memory with Device-nGnRE attributes aligned to
68page boundary (4K) for each BL stage. All sections which allocate coherent
69memory are grouped under ``coherent_ram``. For ex: Bakery locks are placed in a
70section identified by name ``bakery_lock`` inside ``coherent_ram`` so that its
71possible for the firmware to place variables in it using the following C code
72directive:
73
74::
75
76 __section("bakery_lock")
77
78Or alternatively the following assembler code directive:
79
80::
81
82 .section bakery_lock
83
84The ``coherent_ram`` section is a sum of all sections like ``bakery_lock`` which are
85used to allocate any data structures that are accessed both when a CPU is
86executing with its MMU and caches enabled, and when it's running with its MMU
87and caches disabled. Examples are given below.
88
89The following variables, functions and constants must be defined by the platform
90for the firmware to work correctly.
91
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +010092File : platform_def.h [mandatory]
93~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +010094
95Each platform must ensure that a header file of this name is in the system
Antonio Nino Diaz50a4d1a2019-02-01 12:22:22 +000096include path with the following constants defined. This will require updating
97the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010098
Paul Beesleyf8640672019-04-12 14:19:42 +010099Platform ports may optionally use the file ``include/plat/common/common_def.h``,
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100100which provides typical values for some of the constants below. These values are
101likely to be suitable for all platform ports.
102
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100103- **#define : PLATFORM_LINKER_FORMAT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100104
105 Defines the linker format used by the platform, for example
106 ``elf64-littleaarch64``.
107
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100108- **#define : PLATFORM_LINKER_ARCH**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100109
110 Defines the processor architecture for the linker by the platform, for
111 example ``aarch64``.
112
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100113- **#define : PLATFORM_STACK_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100114
115 Defines the normal stack memory available to each CPU. This constant is used
Paul Beesleyf8640672019-04-12 14:19:42 +0100116 by ``plat/common/aarch64/platform_mp_stack.S`` and
117 ``plat/common/aarch64/platform_up_stack.S``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100118
David Horstmann051fd6d2020-11-12 15:19:04 +0000119- **#define : CACHE_WRITEBACK_GRANULE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100120
121 Defines the size in bits of the largest cache line across all the cache
122 levels in the platform.
123
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100124- **#define : FIRMWARE_WELCOME_STR**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100125
126 Defines the character string printed by BL1 upon entry into the ``bl1_main()``
127 function.
128
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100129- **#define : PLATFORM_CORE_COUNT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100130
131 Defines the total number of CPUs implemented by the platform across all
132 clusters in the system.
133
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100134- **#define : PLAT_NUM_PWR_DOMAINS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100135
136 Defines the total number of nodes in the power domain topology
137 tree at all the power domain levels used by the platform.
138 This macro is used by the PSCI implementation to allocate
139 data structures to represent power domain topology.
140
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100141- **#define : PLAT_MAX_PWR_LVL**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100142
143 Defines the maximum power domain level that the power management operations
144 should apply to. More often, but not always, the power domain level
145 corresponds to affinity level. This macro allows the PSCI implementation
146 to know the highest power domain level that it should consider for power
147 management operations in the system that the platform implements. For
148 example, the Base AEM FVP implements two clusters with a configurable
149 number of CPUs and it reports the maximum power domain level as 1.
150
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100151- **#define : PLAT_MAX_OFF_STATE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100152
153 Defines the local power state corresponding to the deepest power down
154 possible at every power domain level in the platform. The local power
155 states for each level may be sparsely allocated between 0 and this value
156 with 0 being reserved for the RUN state. The PSCI implementation uses this
157 value to initialize the local power states of the power domain nodes and
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100158 to specify the requested power state for a PSCI_CPU_OFF call.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100159
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100160- **#define : PLAT_MAX_RET_STATE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100161
162 Defines the local power state corresponding to the deepest retention state
163 possible at every power domain level in the platform. This macro should be
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100164 a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100165 PSCI implementation to distinguish between retention and power down local
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100166 power states within PSCI_CPU_SUSPEND call.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100167
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100168- **#define : PLAT_MAX_PWR_LVL_STATES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100169
170 Defines the maximum number of local power states per power domain level
171 that the platform supports. The default value of this macro is 2 since
172 most platforms just support a maximum of two local power states at each
173 power domain level (power-down and retention). If the platform needs to
174 account for more local power states, then it must redefine this macro.
175
176 Currently, this macro is used by the Generic PSCI implementation to size
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100177 the array used for PSCI_STAT_COUNT/RESIDENCY accounting.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100178
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100179- **#define : BL1_RO_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100180
181 Defines the base address in secure ROM where BL1 originally lives. Must be
182 aligned on a page-size boundary.
183
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100184- **#define : BL1_RO_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100185
186 Defines the maximum address in secure ROM that BL1's actual content (i.e.
187 excluding any data section allocated at runtime) can occupy.
188
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100189- **#define : BL1_RW_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100190
191 Defines the base address in secure RAM where BL1's read-write data will live
192 at runtime. Must be aligned on a page-size boundary.
193
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100194- **#define : BL1_RW_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100195
196 Defines the maximum address in secure RAM that BL1's read-write data can
197 occupy at runtime.
198
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100199- **#define : BL2_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100200
201 Defines the base address in secure RAM where BL1 loads the BL2 binary image.
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000202 Must be aligned on a page-size boundary. This constant is not applicable
203 when BL2_IN_XIP_MEM is set to '1'.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100204
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100205- **#define : BL2_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100206
207 Defines the maximum address in secure RAM that the BL2 image can occupy.
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000208 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'.
209
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100210- **#define : BL2_RO_BASE**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000211
212 Defines the base address in secure XIP memory where BL2 RO section originally
213 lives. Must be aligned on a page-size boundary. This constant is only needed
214 when BL2_IN_XIP_MEM is set to '1'.
215
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100216- **#define : BL2_RO_LIMIT**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000217
218 Defines the maximum address in secure XIP memory that BL2's actual content
219 (i.e. excluding any data section allocated at runtime) can occupy. This
220 constant is only needed when BL2_IN_XIP_MEM is set to '1'.
221
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100222- **#define : BL2_RW_BASE**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000223
224 Defines the base address in secure RAM where BL2's read-write data will live
225 at runtime. Must be aligned on a page-size boundary. This constant is only
226 needed when BL2_IN_XIP_MEM is set to '1'.
227
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100228- **#define : BL2_RW_LIMIT**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000229
230 Defines the maximum address in secure RAM that BL2's read-write data can
231 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set
232 to '1'.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100233
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100234- **#define : BL31_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100235
236 Defines the base address in secure RAM where BL2 loads the BL31 binary
237 image. Must be aligned on a page-size boundary.
238
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100239- **#define : BL31_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100240
241 Defines the maximum address in secure RAM that the BL31 image can occupy.
242
243For every image, the platform must define individual identifiers that will be
244used by BL1 or BL2 to load the corresponding image into memory from non-volatile
245storage. For the sake of performance, integer numbers will be used as
246identifiers. The platform will use those identifiers to return the relevant
247information about the image to be loaded (file handler, load address,
248authentication information, etc.). The following image identifiers are
249mandatory:
250
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100251- **#define : BL2_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100252
253 BL2 image identifier, used by BL1 to load BL2.
254
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100255- **#define : BL31_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100256
257 BL31 image identifier, used by BL2 to load BL31.
258
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100259- **#define : BL33_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100260
261 BL33 image identifier, used by BL2 to load BL33.
262
263If Trusted Board Boot is enabled, the following certificate identifiers must
264also be defined:
265
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100266- **#define : TRUSTED_BOOT_FW_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100267
268 BL2 content certificate identifier, used by BL1 to load the BL2 content
269 certificate.
270
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100271- **#define : TRUSTED_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100272
273 Trusted key certificate identifier, used by BL2 to load the trusted key
274 certificate.
275
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100276- **#define : SOC_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100277
278 BL31 key certificate identifier, used by BL2 to load the BL31 key
279 certificate.
280
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100281- **#define : SOC_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100282
283 BL31 content certificate identifier, used by BL2 to load the BL31 content
284 certificate.
285
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100286- **#define : NON_TRUSTED_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100287
288 BL33 key certificate identifier, used by BL2 to load the BL33 key
289 certificate.
290
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100291- **#define : NON_TRUSTED_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100292
293 BL33 content certificate identifier, used by BL2 to load the BL33 content
294 certificate.
295
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100296- **#define : FWU_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100297
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100298 Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100299 FWU content certificate.
300
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100301- **#define : PLAT_CRYPTOCELL_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100302
Dan Handley610e7e12018-03-01 18:44:00 +0000303 This defines the base address of Arm® TrustZone® CryptoCell and must be
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100304 defined if CryptoCell crypto driver is used for Trusted Board Boot. For
Dan Handley610e7e12018-03-01 18:44:00 +0000305 capable Arm platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100306 set.
307
308If the AP Firmware Updater Configuration image, BL2U is used, the following
309must also be defined:
310
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100311- **#define : BL2U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100312
313 Defines the base address in secure memory where BL1 copies the BL2U binary
314 image. Must be aligned on a page-size boundary.
315
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100316- **#define : BL2U_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100317
318 Defines the maximum address in secure memory that the BL2U image can occupy.
319
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100320- **#define : BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100321
322 BL2U image identifier, used by BL1 to fetch an image descriptor
323 corresponding to BL2U.
324
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100325If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100326must also be defined:
327
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100328- **#define : SCP_BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100329
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100330 SCP_BL2U image identifier, used by BL1 to fetch an image descriptor
331 corresponding to SCP_BL2U.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000332
333 .. note::
334 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100335
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100336If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100337also be defined:
338
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100339- **#define : NS_BL1U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100340
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100341 Defines the base address in non-secure ROM where NS_BL1U executes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100342 Must be aligned on a page-size boundary.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000343
344 .. note::
345 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100346
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100347- **#define : NS_BL1U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100348
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100349 NS_BL1U image identifier, used by BL1 to fetch an image descriptor
350 corresponding to NS_BL1U.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100351
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100352If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100353be defined:
354
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100355- **#define : NS_BL2U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100356
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100357 Defines the base address in non-secure memory where NS_BL2U executes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100358 Must be aligned on a page-size boundary.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000359
360 .. note::
361 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100362
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100363- **#define : NS_BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100364
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100365 NS_BL2U image identifier, used by BL1 to fetch an image descriptor
366 corresponding to NS_BL2U.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100367
368For the the Firmware update capability of TRUSTED BOARD BOOT, the following
369macros may also be defined:
370
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100371- **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100372
373 Total number of images that can be loaded simultaneously. If the platform
374 doesn't specify any value, it defaults to 10.
375
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100376If a SCP_BL2 image is supported by the platform, the following constants must
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100377also be defined:
378
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100379- **#define : SCP_BL2_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100380
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100381 SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000382 from platform storage before being transferred to the SCP.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100383
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100384- **#define : SCP_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100385
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100386 SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100387 certificate (mandatory when Trusted Board Boot is enabled).
388
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100389- **#define : SCP_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100390
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100391 SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100392 content certificate (mandatory when Trusted Board Boot is enabled).
393
394If a BL32 image is supported by the platform, the following constants must
395also be defined:
396
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100397- **#define : BL32_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100398
399 BL32 image identifier, used by BL2 to load BL32.
400
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100401- **#define : TRUSTED_OS_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100402
403 BL32 key certificate identifier, used by BL2 to load the BL32 key
404 certificate (mandatory when Trusted Board Boot is enabled).
405
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100406- **#define : TRUSTED_OS_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100407
408 BL32 content certificate identifier, used by BL2 to load the BL32 content
409 certificate (mandatory when Trusted Board Boot is enabled).
410
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100411- **#define : BL32_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100412
413 Defines the base address in secure memory where BL2 loads the BL32 binary
414 image. Must be aligned on a page-size boundary.
415
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100416- **#define : BL32_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100417
418 Defines the maximum address that the BL32 image can occupy.
419
420If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the
421platform, the following constants must also be defined:
422
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100423- **#define : TSP_SEC_MEM_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100424
425 Defines the base address of the secure memory used by the TSP image on the
426 platform. This must be at the same address or below ``BL32_BASE``.
427
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100428- **#define : TSP_SEC_MEM_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100429
430 Defines the size of the secure memory used by the BL32 image on the
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000431 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully
432 accommodate the memory required by the BL32 image, defined by ``BL32_BASE``
433 and ``BL32_LIMIT``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100434
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100435- **#define : TSP_IRQ_SEC_PHY_TIMER**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100436
437 Defines the ID of the secure physical generic timer interrupt used by the
438 TSP's interrupt handling code.
439
440If the platform port uses the translation table library code, the following
441constants must also be defined:
442
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100443- **#define : PLAT_XLAT_TABLES_DYNAMIC**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100444
445 Optional flag that can be set per-image to enable the dynamic allocation of
446 regions even when the MMU is enabled. If not defined, only static
447 functionality will be available, if defined and set to 1 it will also
448 include the dynamic functionality.
449
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100450- **#define : MAX_XLAT_TABLES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100451
452 Defines the maximum number of translation tables that are allocated by the
453 translation table library code. To minimize the amount of runtime memory
454 used, choose the smallest value needed to map the required virtual addresses
455 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL
456 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions
457 as well.
458
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100459- **#define : MAX_MMAP_REGIONS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100460
461 Defines the maximum number of regions that are allocated by the translation
462 table library code. A region consists of physical base address, virtual base
463 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as
464 defined in the ``mmap_region_t`` structure. The platform defines the regions
465 that should be mapped. Then, the translation table library will create the
466 corresponding tables and descriptors at runtime. To minimize the amount of
467 runtime memory used, choose the smallest value needed to register the
468 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is
469 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate
470 the dynamic regions as well.
471
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100472- **#define : PLAT_VIRT_ADDR_SPACE_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100473
474 Defines the total size of the virtual address space in bytes. For example,
David Cunadoc1503122018-02-16 21:12:58 +0000475 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100476
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100477- **#define : PLAT_PHY_ADDR_SPACE_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100478
479 Defines the total size of the physical address space in bytes. For example,
David Cunadoc1503122018-02-16 21:12:58 +0000480 for a 32 bit physical address space, this value should be ``(1ULL << 32)``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100481
482If the platform port uses the IO storage framework, the following constants
483must also be defined:
484
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100485- **#define : MAX_IO_DEVICES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100486
487 Defines the maximum number of registered IO devices. Attempting to register
488 more devices than this value using ``io_register_device()`` will fail with
489 -ENOMEM.
490
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100491- **#define : MAX_IO_HANDLES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100492
493 Defines the maximum number of open IO handles. Attempting to open more IO
494 entities than this value using ``io_open()`` will fail with -ENOMEM.
495
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100496- **#define : MAX_IO_BLOCK_DEVICES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100497
498 Defines the maximum number of registered IO block devices. Attempting to
499 register more devices this value using ``io_dev_open()`` will fail
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100500 with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100501 With this macro, multiple block devices could be supported at the same
502 time.
503
504If the platform needs to allocate data within the per-cpu data framework in
505BL31, it should define the following macro. Currently this is only required if
506the platform decides not to use the coherent memory section by undefining the
507``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the
508required memory within the the per-cpu data to minimize wastage.
509
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100510- **#define : PLAT_PCPU_DATA_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100511
512 Defines the memory (in bytes) to be reserved within the per-cpu data
513 structure for use by the platform layer.
514
515The following constants are optional. They should be defined when the platform
Dan Handley610e7e12018-03-01 18:44:00 +0000516memory layout implies some image overlaying like in Arm standard platforms.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100517
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100518- **#define : BL31_PROGBITS_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100519
520 Defines the maximum address in secure RAM that the BL31's progbits sections
521 can occupy.
522
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100523- **#define : TSP_PROGBITS_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100524
525 Defines the maximum address that the TSP's progbits sections can occupy.
526
527If the platform port uses the PL061 GPIO driver, the following constant may
528optionally be defined:
529
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100530- **PLAT_PL061_MAX_GPIOS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100531 Maximum number of GPIOs required by the platform. This allows control how
532 much memory is allocated for PL061 GPIO controllers. The default value is
533
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100534 #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS))
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100535
536If the platform port uses the partition driver, the following constant may
537optionally be defined:
538
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100539- **PLAT_PARTITION_MAX_ENTRIES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100540 Maximum number of partition entries required by the platform. This allows
541 control how much memory is allocated for partition entries. The default
542 value is 128.
Paul Beesleyf8640672019-04-12 14:19:42 +0100543 For example, define the build flag in ``platform.mk``:
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100544 PLAT_PARTITION_MAX_ENTRIES := 12
545 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100546
Haojian Zhuang42a746d2019-09-14 18:01:16 +0800547- **PLAT_PARTITION_BLOCK_SIZE**
548 The size of partition block. It could be either 512 bytes or 4096 bytes.
549 The default value is 512.
Paul Beesleyf2ec7142019-10-04 16:17:46 +0000550 For example, define the build flag in ``platform.mk``:
Haojian Zhuang42a746d2019-09-14 18:01:16 +0800551 PLAT_PARTITION_BLOCK_SIZE := 4096
552 $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE))
553
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100554The following constant is optional. It should be defined to override the default
555behaviour of the ``assert()`` function (for example, to save memory).
556
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100557- **PLAT_LOG_LEVEL_ASSERT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100558 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``,
559 ``assert()`` prints the name of the file, the line number and the asserted
560 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file
561 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it
562 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't
563 defined, it defaults to ``LOG_LEVEL``.
564
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100565File : plat_macros.S [mandatory]
566~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100567
568Each platform must ensure a file of this name is in the system include path with
Dan Handley610e7e12018-03-01 18:44:00 +0000569the following macro defined. In the Arm development platforms, this file is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100570found in ``plat/arm/board/<plat_name>/include/plat_macros.S``.
571
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100572- **Macro : plat_crash_print_regs**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100573
574 This macro allows the crash reporting routine to print relevant platform
575 registers in case of an unhandled exception in BL31. This aids in debugging
576 and this macro can be defined to be empty in case register reporting is not
577 desired.
578
579 For instance, GIC or interconnect registers may be helpful for
580 troubleshooting.
581
582Handling Reset
583--------------
584
585BL1 by default implements the reset vector where execution starts from a cold
586or warm boot. BL31 can be optionally set as a reset vector using the
587``RESET_TO_BL31`` make variable.
588
589For each CPU, the reset vector code is responsible for the following tasks:
590
591#. Distinguishing between a cold boot and a warm boot.
592
593#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that
594 the CPU is placed in a platform-specific state until the primary CPU
595 performs the necessary steps to remove it from this state.
596
597#. In the case of a warm boot, ensuring that the CPU jumps to a platform-
598 specific address in the BL31 image in the same processor mode as it was
599 when released from reset.
600
601The following functions need to be implemented by the platform port to enable
602reset vector code to perform the above tasks.
603
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100604Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0]
605~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100606
607::
608
609 Argument : void
610 Return : uintptr_t
611
612This function is called with the MMU and caches disabled
613(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for
614distinguishing between a warm and cold reset for the current CPU using
615platform-specific means. If it's a warm reset, then it returns the warm
616reset entrypoint point provided to ``plat_setup_psci_ops()`` during
617BL31 initialization. If it's a cold reset then this function must return zero.
618
619This function does not follow the Procedure Call Standard used by the
Dan Handley610e7e12018-03-01 18:44:00 +0000620Application Binary Interface for the Arm 64-bit architecture. The caller should
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100621not assume that callee saved registers are preserved across a call to this
622function.
623
624This function fulfills requirement 1 and 3 listed above.
625
626Note that for platforms that support programming the reset address, it is
627expected that a CPU will start executing code directly at the right address,
628both on a cold and warm reset. In this case, there is no need to identify the
629type of reset nor to query the warm reset entrypoint. Therefore, implementing
630this function is not required on such platforms.
631
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100632Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
633~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100634
635::
636
637 Argument : void
638
639This function is called with the MMU and data caches disabled. It is responsible
640for placing the executing secondary CPU in a platform-specific state until the
641primary CPU performs the necessary actions to bring it out of that state and
642allow entry into the OS. This function must not return.
643
Dan Handley610e7e12018-03-01 18:44:00 +0000644In the Arm FVP port, when using the normal boot flow, each secondary CPU powers
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100645itself off. The primary CPU is responsible for powering up the secondary CPUs
646when normal world software requires them. When booting an EL3 payload instead,
647they stay powered on and are put in a holding pen until their mailbox gets
648populated.
649
650This function fulfills requirement 2 above.
651
652Note that for platforms that can't release secondary CPUs out of reset, only the
653primary CPU will execute the cold boot code. Therefore, implementing this
654function is not required on such platforms.
655
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100656Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
657~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100658
659::
660
661 Argument : void
662 Return : unsigned int
663
664This function identifies whether the current CPU is the primary CPU or a
665secondary CPU. A return value of zero indicates that the CPU is not the
666primary CPU, while a non-zero return value indicates that the CPU is the
667primary CPU.
668
669Note that for platforms that can't release secondary CPUs out of reset, only the
670primary CPU will execute the cold boot code. Therefore, there is no need to
671distinguish between primary and secondary CPUs and implementing this function is
672not required.
673
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100674Function : platform_mem_init() [mandatory]
675~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100676
677::
678
679 Argument : void
680 Return : void
681
682This function is called before any access to data is made by the firmware, in
683order to carry out any essential memory initialization.
684
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100685Function: plat_get_rotpk_info()
686~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100687
688::
689
690 Argument : void *, void **, unsigned int *, unsigned int *
691 Return : int
692
693This function is mandatory when Trusted Board Boot is enabled. It returns a
694pointer to the ROTPK stored in the platform (or a hash of it) and its length.
695The ROTPK must be encoded in DER format according to the following ASN.1
696structure:
697
698::
699
700 AlgorithmIdentifier ::= SEQUENCE {
701 algorithm OBJECT IDENTIFIER,
702 parameters ANY DEFINED BY algorithm OPTIONAL
703 }
704
705 SubjectPublicKeyInfo ::= SEQUENCE {
706 algorithm AlgorithmIdentifier,
707 subjectPublicKey BIT STRING
708 }
709
710In case the function returns a hash of the key:
711
712::
713
714 DigestInfo ::= SEQUENCE {
715 digestAlgorithm AlgorithmIdentifier,
716 digest OCTET STRING
717 }
718
719The function returns 0 on success. Any other value is treated as error by the
720Trusted Board Boot. The function also reports extra information related
721to the ROTPK in the flags parameter:
722
723::
724
725 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a
726 hash.
727 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK
728 verification while the platform ROTPK is not deployed.
729 When this flag is set, the function does not need to
730 return a platform ROTPK, and the authentication
731 framework uses the ROTPK in the certificate without
732 verifying it against the platform value. This flag
733 must not be used in a deployed production environment.
734
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100735Function: plat_get_nv_ctr()
736~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100737
738::
739
740 Argument : void *, unsigned int *
741 Return : int
742
743This function is mandatory when Trusted Board Boot is enabled. It returns the
744non-volatile counter value stored in the platform in the second argument. The
745cookie in the first argument may be used to select the counter in case the
746platform provides more than one (for example, on platforms that use the default
747TBBR CoT, the cookie will correspond to the OID values defined in
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100748TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100749
750The function returns 0 on success. Any other value means the counter value could
751not be retrieved from the platform.
752
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100753Function: plat_set_nv_ctr()
754~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100755
756::
757
758 Argument : void *, unsigned int
759 Return : int
760
761This function is mandatory when Trusted Board Boot is enabled. It sets a new
762counter value in the platform. The cookie in the first argument may be used to
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100763select the counter (as explained in plat_get_nv_ctr()). The second argument is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100764the updated counter value to be written to the NV counter.
765
766The function returns 0 on success. Any other value means the counter value could
767not be updated.
768
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100769Function: plat_set_nv_ctr2()
770~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100771
772::
773
774 Argument : void *, const auth_img_desc_t *, unsigned int
775 Return : int
776
777This function is optional when Trusted Board Boot is enabled. If this
778interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The
779first argument passed is a cookie and is typically used to
780differentiate between a Non Trusted NV Counter and a Trusted NV
781Counter. The second argument is a pointer to an authentication image
782descriptor and may be used to decide if the counter is allowed to be
783updated or not. The third argument is the updated counter value to
784be written to the NV counter.
785
786The function returns 0 on success. Any other value means the counter value
787either could not be updated or the authentication image descriptor indicates
788that it is not allowed to be updated.
789
790Common mandatory function modifications
791---------------------------------------
792
793The following functions are mandatory functions which need to be implemented
794by the platform port.
795
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100796Function : plat_my_core_pos()
797~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100798
799::
800
801 Argument : void
802 Return : unsigned int
803
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000804This function returns the index of the calling CPU which is used as a
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100805CPU-specific linear index into blocks of memory (for example while allocating
806per-CPU stacks). This function will be invoked very early in the
807initialization sequence which mandates that this function should be
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000808implemented in assembly and should not rely on the availability of a C
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100809runtime environment. This function can clobber x0 - x8 and must preserve
810x9 - x29.
811
812This function plays a crucial role in the power domain topology framework in
Paul Beesleyf8640672019-04-12 14:19:42 +0100813PSCI and details of this can be found in
814:ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100815
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100816Function : plat_core_pos_by_mpidr()
817~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100818
819::
820
821 Argument : u_register_t
822 Return : int
823
824This function validates the ``MPIDR`` of a CPU and converts it to an index,
825which can be used as a CPU-specific linear index into blocks of memory. In
826case the ``MPIDR`` is invalid, this function returns -1. This function will only
827be invoked by BL31 after the power domain topology is initialized and can
Dan Handley610e7e12018-03-01 18:44:00 +0000828utilize the C runtime environment. For further details about how TF-A
829represents the power domain topology and how this relates to the linear CPU
Paul Beesleyf8640672019-04-12 14:19:42 +0100830index, please refer :ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100831
Ambroise Vincentd207f562019-04-10 12:50:27 +0100832Function : plat_get_mbedtls_heap() [when TRUSTED_BOARD_BOOT == 1]
833~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
834
835::
836
837 Arguments : void **heap_addr, size_t *heap_size
838 Return : int
839
840This function is invoked during Mbed TLS library initialisation to get a heap,
841by means of a starting address and a size. This heap will then be used
842internally by the Mbed TLS library. Hence, each BL stage that utilises Mbed TLS
843must be able to provide a heap to it.
844
845A helper function can be found in `drivers/auth/mbedtls/mbedtls_common.c` in
846which a heap is statically reserved during compile time inside every image
847(i.e. every BL stage) that utilises Mbed TLS. In this default implementation,
848the function simply returns the address and size of this "pre-allocated" heap.
849For a platform to use this default implementation, only a call to the helper
850from inside plat_get_mbedtls_heap() body is enough and nothing else is needed.
851
852However, by writting their own implementation, platforms have the potential to
853optimise memory usage. For example, on some Arm platforms, the Mbed TLS heap is
854shared between BL1 and BL2 stages and, thus, the necessary space is not reserved
855twice.
856
857On success the function should return 0 and a negative error code otherwise.
858
Sumit Gargc0c369c2019-11-15 18:47:53 +0530859Function : plat_get_enc_key_info() [when FW_ENC_STATUS == 0 or 1]
860~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
861
862::
863
864 Arguments : enum fw_enc_status_t fw_enc_status, uint8_t *key,
865 size_t *key_len, unsigned int *flags, const uint8_t *img_id,
866 size_t img_id_len
867 Return : int
868
869This function provides a symmetric key (either SSK or BSSK depending on
870fw_enc_status) which is invoked during runtime decryption of encrypted
871firmware images. `plat/common/plat_bl_common.c` provides a dummy weak
872implementation for testing purposes which must be overridden by the platform
873trying to implement a real world firmware encryption use-case.
874
875It also allows the platform to pass symmetric key identifier rather than
876actual symmetric key which is useful in cases where the crypto backend provides
877secure storage for the symmetric key. So in this case ``ENC_KEY_IS_IDENTIFIER``
878flag must be set in ``flags``.
879
880In addition to above a platform may also choose to provide an image specific
881symmetric key/identifier using img_id.
882
883On success the function should return 0 and a negative error code otherwise.
884
Manish Pandey34a305e2021-10-21 21:53:49 +0100885Note that this API depends on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530886
Manish V Badarkheda87af12021-06-20 21:14:46 +0100887Function : plat_fwu_set_images_source() [when PSA_FWU_SUPPORT == 1]
888~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
889
890::
891
892 Argument : struct fwu_metadata *metadata
893 Return : void
894
895This function is mandatory when PSA_FWU_SUPPORT is enabled.
896It provides a means to retrieve image specification (offset in
897non-volatile storage and length) of active/updated images using the passed
898FWU metadata, and update I/O policies of active/updated images using retrieved
899image specification information.
900Further I/O layer operations such as I/O open, I/O read, etc. on these
901images rely on this function call.
902
903In Arm platforms, this function is used to set an I/O policy of the FIP image,
904container of all active/updated secure and non-secure images.
905
906Function : plat_fwu_set_metadata_image_source() [when PSA_FWU_SUPPORT == 1]
907~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
908
909::
910
911 Argument : unsigned int image_id, uintptr_t *dev_handle,
912 uintptr_t *image_spec
913 Return : int
914
915This function is mandatory when PSA_FWU_SUPPORT is enabled. It is
916responsible for setting up the platform I/O policy of the requested metadata
917image (either FWU_METADATA_IMAGE_ID or BKUP_FWU_METADATA_IMAGE_ID) that will
918be used to load this image from the platform's non-volatile storage.
919
920FWU metadata can not be always stored as a raw image in non-volatile storage
921to define its image specification (offset in non-volatile storage and length)
922statically in I/O policy.
923For example, the FWU metadata image is stored as a partition inside the GUID
924partition table image. Its specification is defined in the partition table
925that needs to be parsed dynamically.
926This function provides a means to retrieve such dynamic information to set
927the I/O policy of the FWU metadata image.
928Further I/O layer operations such as I/O open, I/O read, etc. on FWU metadata
929image relies on this function call.
930
931It returns '0' on success, otherwise a negative error value on error.
932Alongside, returns device handle and image specification from the I/O policy
933of the requested FWU metadata image.
934
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100935Common optional modifications
936-----------------------------
937
938The following are helper functions implemented by the firmware that perform
939common platform-specific tasks. A platform may choose to override these
940definitions.
941
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100942Function : plat_set_my_stack()
943~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100944
945::
946
947 Argument : void
948 Return : void
949
950This function sets the current stack pointer to the normal memory stack that
951has been allocated for the current CPU. For BL images that only require a
952stack for the primary CPU, the UP version of the function is used. The size
953of the stack allocated to each CPU is specified by the platform defined
954constant ``PLATFORM_STACK_SIZE``.
955
956Common implementations of this function for the UP and MP BL images are
Paul Beesleyf8640672019-04-12 14:19:42 +0100957provided in ``plat/common/aarch64/platform_up_stack.S`` and
958``plat/common/aarch64/platform_mp_stack.S``
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100959
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100960Function : plat_get_my_stack()
961~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100962
963::
964
965 Argument : void
966 Return : uintptr_t
967
968This function returns the base address of the normal memory stack that
969has been allocated for the current CPU. For BL images that only require a
970stack for the primary CPU, the UP version of the function is used. The size
971of the stack allocated to each CPU is specified by the platform defined
972constant ``PLATFORM_STACK_SIZE``.
973
974Common implementations of this function for the UP and MP BL images are
Paul Beesleyf8640672019-04-12 14:19:42 +0100975provided in ``plat/common/aarch64/platform_up_stack.S`` and
976``plat/common/aarch64/platform_mp_stack.S``
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100977
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100978Function : plat_report_exception()
979~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100980
981::
982
983 Argument : unsigned int
984 Return : void
985
986A platform may need to report various information about its status when an
987exception is taken, for example the current exception level, the CPU security
988state (secure/non-secure), the exception type, and so on. This function is
989called in the following circumstances:
990
991- In BL1, whenever an exception is taken.
992- In BL2, whenever an exception is taken.
993
994The default implementation doesn't do anything, to avoid making assumptions
995about the way the platform displays its status information.
996
997For AArch64, this function receives the exception type as its argument.
998Possible values for exceptions types are listed in the
Paul Beesleyf8640672019-04-12 14:19:42 +0100999``include/common/bl_common.h`` header file. Note that these constants are not
Dan Handley610e7e12018-03-01 18:44:00 +00001000related to any architectural exception code; they are just a TF-A convention.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001001
1002For AArch32, this function receives the exception mode as its argument.
1003Possible values for exception modes are listed in the
Paul Beesleyf8640672019-04-12 14:19:42 +01001004``include/lib/aarch32/arch.h`` header file.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001005
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001006Function : plat_reset_handler()
1007~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001008
1009::
1010
1011 Argument : void
1012 Return : void
1013
1014A platform may need to do additional initialization after reset. This function
Paul Beesleyf2ec7142019-10-04 16:17:46 +00001015allows the platform to do the platform specific initializations. Platform
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001016specific errata workarounds could also be implemented here. The API should
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001017preserve the values of callee saved registers x19 to x29.
1018
1019The default implementation doesn't do anything. If a platform needs to override
Paul Beesleyf8640672019-04-12 14:19:42 +01001020the default implementation, refer to the :ref:`Firmware Design` for general
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001021guidelines.
1022
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001023Function : plat_disable_acp()
1024~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001025
1026::
1027
1028 Argument : void
1029 Return : void
1030
John Tsichritzis6dda9762018-07-23 09:18:04 +01001031This API allows a platform to disable the Accelerator Coherency Port (if
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001032present) during a cluster power down sequence. The default weak implementation
John Tsichritzis6dda9762018-07-23 09:18:04 +01001033doesn't do anything. Since this API is called during the power down sequence,
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001034it has restrictions for stack usage and it can use the registers x0 - x17 as
1035scratch registers. It should preserve the value in x18 register as it is used
1036by the caller to store the return address.
1037
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001038Function : plat_error_handler()
1039~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001040
1041::
1042
1043 Argument : int
1044 Return : void
1045
1046This API is called when the generic code encounters an error situation from
1047which it cannot continue. It allows the platform to perform error reporting or
1048recovery actions (for example, reset the system). This function must not return.
1049
1050The parameter indicates the type of error using standard codes from ``errno.h``.
1051Possible errors reported by the generic code are:
1052
1053- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted
1054 Board Boot is enabled)
1055- ``-ENOENT``: the requested image or certificate could not be found or an IO
1056 error was detected
Dan Handley610e7e12018-03-01 18:44:00 +00001057- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this
1058 error is usually an indication of an incorrect array size
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001059
1060The default implementation simply spins.
1061
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001062Function : plat_panic_handler()
1063~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001064
1065::
1066
1067 Argument : void
1068 Return : void
1069
1070This API is called when the generic code encounters an unexpected error
1071situation from which it cannot recover. This function must not return,
1072and must be implemented in assembly because it may be called before the C
1073environment is initialized.
1074
Paul Beesleyba3ed402019-03-13 16:20:44 +00001075.. note::
1076 The address from where it was called is stored in x30 (Link Register).
1077 The default implementation simply spins.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001078
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001079Function : plat_get_bl_image_load_info()
1080~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001081
1082::
1083
1084 Argument : void
1085 Return : bl_load_info_t *
1086
1087This function returns pointer to the list of images that the platform has
Soby Mathew97b1bff2018-09-27 16:46:41 +01001088populated to load. This function is invoked in BL2 to load the
1089BL3xx images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001090
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001091Function : plat_get_next_bl_params()
1092~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001093
1094::
1095
1096 Argument : void
1097 Return : bl_params_t *
1098
1099This function returns a pointer to the shared memory that the platform has
Dan Handley610e7e12018-03-01 18:44:00 +00001100kept aside to pass TF-A related information that next BL image needs. This
Soby Mathew97b1bff2018-09-27 16:46:41 +01001101function is invoked in BL2 to pass this information to the next BL
1102image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001103
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001104Function : plat_get_stack_protector_canary()
1105~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001106
1107::
1108
1109 Argument : void
1110 Return : u_register_t
1111
1112This function returns a random value that is used to initialize the canary used
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001113when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001114value will weaken the protection as the attacker could easily write the right
1115value as part of the attack most of the time. Therefore, it should return a
1116true random number.
1117
Paul Beesleyba3ed402019-03-13 16:20:44 +00001118.. warning::
1119 For the protection to be effective, the global data need to be placed at
1120 a lower address than the stack bases. Failure to do so would allow an
1121 attacker to overwrite the canary as part of the stack buffer overflow attack.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001122
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001123Function : plat_flush_next_bl_params()
1124~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001125
1126::
1127
1128 Argument : void
1129 Return : void
1130
1131This function flushes to main memory all the image params that are passed to
Soby Mathew97b1bff2018-09-27 16:46:41 +01001132next image. This function is invoked in BL2 to flush this information
1133to the next BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001134
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001135Function : plat_log_get_prefix()
1136~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Soby Mathewaaf15f52017-09-04 11:49:29 +01001137
1138::
1139
1140 Argument : unsigned int
1141 Return : const char *
1142
1143This function defines the prefix string corresponding to the `log_level` to be
Dan Handley610e7e12018-03-01 18:44:00 +00001144prepended to all the log output from TF-A. The `log_level` (argument) will
1145correspond to one of the standard log levels defined in debug.h. The platform
1146can override the common implementation to define a different prefix string for
John Tsichritzis30f89642018-06-07 16:31:34 +01001147the log output. The implementation should be robust to future changes that
Dan Handley610e7e12018-03-01 18:44:00 +00001148increase the number of log levels.
Soby Mathewaaf15f52017-09-04 11:49:29 +01001149
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001150Function : plat_get_soc_version()
Manish V Badarkhe904f93a2020-03-26 14:20:27 +00001151~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001152
1153::
1154
1155 Argument : void
1156 Return : int32_t
1157
1158This function returns soc version which mainly consist of below fields
1159
1160::
1161
1162 soc_version[30:24] = JEP-106 continuation code for the SiP
1163 soc_version[23:16] = JEP-106 identification code with parity bit for the SiP
Manish V Badarkhe80f13ee2020-07-23 20:23:01 +01001164 soc_version[15:0] = Implementation defined SoC ID
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001165
1166Function : plat_get_soc_revision()
Manish V Badarkhe904f93a2020-03-26 14:20:27 +00001167~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001168
1169::
1170
1171 Argument : void
1172 Return : int32_t
1173
1174This function returns soc revision in below format
1175
1176::
1177
1178 soc_revision[0:30] = SOC revision of specific SOC
1179
Manish V Badarkhe80f13ee2020-07-23 20:23:01 +01001180Function : plat_is_smccc_feature_available()
1181~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1182
1183::
1184
1185 Argument : u_register_t
1186 Return : int32_t
1187
1188This function returns SMC_ARCH_CALL_SUCCESS if the platform supports
1189the SMCCC function specified in the argument; otherwise returns
1190SMC_ARCH_CALL_NOT_SUPPORTED.
1191
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001192Function : plat_mboot_measure_image()
1193~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1194
1195::
1196
1197 Argument : unsigned int, image_info_t *
Manish V Badarkhe931c6ef2021-10-21 09:06:18 +01001198 Return : int
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001199
1200When the MEASURED_BOOT flag is enabled:
1201
1202- This function measures the given image and records its measurement using
1203 the measured boot backend driver.
1204- On the Arm FVP port, this function measures the given image using its
1205 passed id and information and then records that measurement in the
1206 Event Log buffer.
Manish V Badarkhe931c6ef2021-10-21 09:06:18 +01001207- This function must return 0 on success, a signed integer error code
1208 otherwise.
1209
1210When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1211
1212Function : plat_mboot_measure_critical_data()
1213~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1214
1215::
1216
1217 Argument : unsigned int, const void *, size_t
1218 Return : int
1219
1220When the MEASURED_BOOT flag is enabled:
1221
1222- This function measures the given critical data structure and records its
1223 measurement using the measured boot backend driver.
1224- This function must return 0 on success, a signed integer error code
1225 otherwise.
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001226
1227When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1228
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001229Modifications specific to a Boot Loader stage
1230---------------------------------------------
1231
1232Boot Loader Stage 1 (BL1)
1233-------------------------
1234
1235BL1 implements the reset vector where execution starts from after a cold or
1236warm boot. For each CPU, BL1 is responsible for the following tasks:
1237
1238#. Handling the reset as described in section 2.2
1239
1240#. In the case of a cold boot and the CPU being the primary CPU, ensuring that
1241 only this CPU executes the remaining BL1 code, including loading and passing
1242 control to the BL2 stage.
1243
1244#. Identifying and starting the Firmware Update process (if required).
1245
1246#. Loading the BL2 image from non-volatile storage into secure memory at the
1247 address specified by the platform defined constant ``BL2_BASE``.
1248
1249#. Populating a ``meminfo`` structure with the following information in memory,
1250 accessible by BL2 immediately upon entry.
1251
1252 ::
1253
1254 meminfo.total_base = Base address of secure RAM visible to BL2
1255 meminfo.total_size = Size of secure RAM visible to BL2
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001256
Soby Mathew97b1bff2018-09-27 16:46:41 +01001257 By default, BL1 places this ``meminfo`` structure at the end of secure
1258 memory visible to BL2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001259
Soby Mathewb1bf0442018-02-16 14:52:52 +00001260 It is possible for the platform to decide where it wants to place the
1261 ``meminfo`` structure for BL2 or restrict the amount of memory visible to
1262 BL2 by overriding the weak default implementation of
1263 ``bl1_plat_handle_post_image_load`` API.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001264
1265The following functions need to be implemented by the platform port to enable
1266BL1 to perform the above tasks.
1267
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001268Function : bl1_early_platform_setup() [mandatory]
1269~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001270
1271::
1272
1273 Argument : void
1274 Return : void
1275
1276This function executes with the MMU and data caches disabled. It is only called
1277by the primary CPU.
1278
Dan Handley610e7e12018-03-01 18:44:00 +00001279On Arm standard platforms, this function:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001280
1281- Enables a secure instance of SP805 to act as the Trusted Watchdog.
1282
1283- Initializes a UART (PL011 console), which enables access to the ``printf``
1284 family of functions in BL1.
1285
1286- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to
1287 the CCI slave interface corresponding to the cluster that includes the
1288 primary CPU.
1289
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001290Function : bl1_plat_arch_setup() [mandatory]
1291~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001292
1293::
1294
1295 Argument : void
1296 Return : void
1297
1298This function performs any platform-specific and architectural setup that the
1299platform requires. Platform-specific setup might include configuration of
1300memory controllers and the interconnect.
1301
Dan Handley610e7e12018-03-01 18:44:00 +00001302In Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001303
1304This function helps fulfill requirement 2 above.
1305
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001306Function : bl1_platform_setup() [mandatory]
1307~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001308
1309::
1310
1311 Argument : void
1312 Return : void
1313
1314This function executes with the MMU and data caches enabled. It is responsible
1315for performing any remaining platform-specific setup that can occur after the
1316MMU and data cache have been enabled.
1317
Roberto Vargas0cd866c2017-12-12 10:39:44 +00001318if support for multiple boot sources is required, it initializes the boot
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001319sequence used by plat_try_next_boot_source().
Roberto Vargas0cd866c2017-12-12 10:39:44 +00001320
Dan Handley610e7e12018-03-01 18:44:00 +00001321In Arm standard platforms, this function initializes the storage abstraction
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001322layer used to load the next bootloader image.
1323
1324This function helps fulfill requirement 4 above.
1325
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001326Function : bl1_plat_sec_mem_layout() [mandatory]
1327~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001328
1329::
1330
1331 Argument : void
1332 Return : meminfo *
1333
1334This function should only be called on the cold boot path. It executes with the
1335MMU and data caches enabled. The pointer returned by this function must point to
1336a ``meminfo`` structure containing the extents and availability of secure RAM for
1337the BL1 stage.
1338
1339::
1340
1341 meminfo.total_base = Base address of secure RAM visible to BL1
1342 meminfo.total_size = Size of secure RAM visible to BL1
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001343
1344This information is used by BL1 to load the BL2 image in secure RAM. BL1 also
1345populates a similar structure to tell BL2 the extents of memory available for
1346its own use.
1347
1348This function helps fulfill requirements 4 and 5 above.
1349
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001350Function : bl1_plat_prepare_exit() [optional]
1351~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001352
1353::
1354
1355 Argument : entry_point_info_t *
1356 Return : void
1357
1358This function is called prior to exiting BL1 in response to the
1359``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform
1360platform specific clean up or bookkeeping operations before transferring
1361control to the next image. It receives the address of the ``entry_point_info_t``
1362structure passed from BL2. This function runs with MMU disabled.
1363
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001364Function : bl1_plat_set_ep_info() [optional]
1365~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001366
1367::
1368
1369 Argument : unsigned int image_id, entry_point_info_t *ep_info
1370 Return : void
1371
1372This function allows platforms to override ``ep_info`` for the given ``image_id``.
1373
1374The default implementation just returns.
1375
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001376Function : bl1_plat_get_next_image_id() [optional]
1377~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001378
1379::
1380
1381 Argument : void
1382 Return : unsigned int
1383
1384This and the following function must be overridden to enable the FWU feature.
1385
1386BL1 calls this function after platform setup to identify the next image to be
1387loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds
1388with the normal boot sequence, which loads and executes BL2. If the platform
1389returns a different image id, BL1 assumes that Firmware Update is required.
1390
Dan Handley610e7e12018-03-01 18:44:00 +00001391The default implementation always returns ``BL2_IMAGE_ID``. The Arm development
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001392platforms override this function to detect if firmware update is required, and
1393if so, return the first image in the firmware update process.
1394
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001395Function : bl1_plat_get_image_desc() [optional]
1396~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001397
1398::
1399
1400 Argument : unsigned int image_id
1401 Return : image_desc_t *
1402
1403BL1 calls this function to get the image descriptor information ``image_desc_t``
1404for the provided ``image_id`` from the platform.
1405
Dan Handley610e7e12018-03-01 18:44:00 +00001406The default implementation always returns a common BL2 image descriptor. Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001407standard platforms return an image descriptor corresponding to BL2 or one of
1408the firmware update images defined in the Trusted Board Boot Requirements
1409specification.
1410
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001411Function : bl1_plat_handle_pre_image_load() [optional]
1412~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001413
1414::
1415
Soby Mathew2f38ce32018-02-08 17:45:12 +00001416 Argument : unsigned int image_id
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001417 Return : int
1418
1419This function can be used by the platforms to update/use image information
Soby Mathew2f38ce32018-02-08 17:45:12 +00001420corresponding to ``image_id``. This function is invoked in BL1, both in cold
1421boot and FWU code path, before loading the image.
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001422
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001423Function : bl1_plat_handle_post_image_load() [optional]
1424~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001425
1426::
1427
Soby Mathew2f38ce32018-02-08 17:45:12 +00001428 Argument : unsigned int image_id
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001429 Return : int
1430
1431This function can be used by the platforms to update/use image information
Soby Mathew2f38ce32018-02-08 17:45:12 +00001432corresponding to ``image_id``. This function is invoked in BL1, both in cold
1433boot and FWU code path, after loading and authenticating the image.
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001434
Soby Mathewb1bf0442018-02-16 14:52:52 +00001435The default weak implementation of this function calculates the amount of
1436Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t``
1437structure at the beginning of this free memory and populates it. The address
1438of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint
1439information to BL2.
1440
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001441Function : bl1_plat_fwu_done() [optional]
1442~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001443
1444::
1445
1446 Argument : unsigned int image_id, uintptr_t image_src,
1447 unsigned int image_size
1448 Return : void
1449
1450BL1 calls this function when the FWU process is complete. It must not return.
1451The platform may override this function to take platform specific action, for
1452example to initiate the normal boot flow.
1453
1454The default implementation spins forever.
1455
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001456Function : bl1_plat_mem_check() [mandatory]
1457~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001458
1459::
1460
1461 Argument : uintptr_t mem_base, unsigned int mem_size,
1462 unsigned int flags
1463 Return : int
1464
1465BL1 calls this function while handling FWU related SMCs, more specifically when
1466copying or authenticating an image. Its responsibility is to ensure that the
1467region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and
1468that this memory corresponds to either a secure or non-secure memory region as
1469indicated by the security state of the ``flags`` argument.
1470
1471This function can safely assume that the value resulting from the addition of
1472``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not
1473overflow.
1474
1475This function must return 0 on success, a non-null error code otherwise.
1476
1477The default implementation of this function asserts therefore platforms must
1478override it when using the FWU feature.
1479
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001480Function : bl1_plat_mboot_init() [optional]
1481~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1482
1483::
1484
1485 Argument : void
1486 Return : void
1487
1488When the MEASURED_BOOT flag is enabled:
1489
1490- This function is used to initialize the backend driver(s) of measured boot.
1491- On the Arm FVP port, this function is used to initialize the Event Log
1492 backend driver, and also to write header information in the Event Log buffer.
1493
1494When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1495
1496Function : bl1_plat_mboot_finish() [optional]
1497~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1498
1499::
1500
1501 Argument : void
1502 Return : void
1503
1504When the MEASURED_BOOT flag is enabled:
1505
1506- This function is used to finalize the measured boot backend driver(s),
1507 and also, set the information for the next bootloader component to
1508 extend the measurement if needed.
1509- On the Arm FVP port, this function is used to pass the base address of
1510 the Event Log buffer and its size to BL2 via tb_fw_config to extend the
1511 Event Log buffer with the measurement of various images loaded by BL2.
1512 It results in panic on error.
1513
1514When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1515
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001516Boot Loader Stage 2 (BL2)
1517-------------------------
1518
1519The BL2 stage is executed only by the primary CPU, which is determined in BL1
1520using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at
Soby Mathew97b1bff2018-09-27 16:46:41 +01001521``BL2_BASE``. BL2 executes in Secure EL1 and and invokes
1522``plat_get_bl_image_load_info()`` to retrieve the list of images to load from
1523non-volatile storage to secure/non-secure RAM. After all the images are loaded
1524then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable
1525images to be passed to the next BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001526
1527The following functions must be implemented by the platform port to enable BL2
1528to perform the above tasks.
1529
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001530Function : bl2_early_platform_setup2() [mandatory]
1531~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001532
1533::
1534
Soby Mathew97b1bff2018-09-27 16:46:41 +01001535 Argument : u_register_t, u_register_t, u_register_t, u_register_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001536 Return : void
1537
1538This function executes with the MMU and data caches disabled. It is only called
Soby Mathew97b1bff2018-09-27 16:46:41 +01001539by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments
1540are platform specific.
1541
1542On Arm standard platforms, the arguments received are :
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001543
Manish V Badarkhe81414512020-06-24 15:58:38 +01001544 arg0 - Points to load address of FW_CONFIG
Soby Mathew97b1bff2018-09-27 16:46:41 +01001545
1546 arg1 - ``meminfo`` structure populated by BL1. The platform copies
1547 the contents of ``meminfo`` as it may be subsequently overwritten by BL2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001548
Dan Handley610e7e12018-03-01 18:44:00 +00001549On Arm standard platforms, this function also:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001550
1551- Initializes a UART (PL011 console), which enables access to the ``printf``
1552 family of functions in BL2.
1553
1554- Initializes the storage abstraction layer used to load further bootloader
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001555 images. It is necessary to do this early on platforms with a SCP_BL2 image,
1556 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001557
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001558Function : bl2_plat_arch_setup() [mandatory]
1559~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001560
1561::
1562
1563 Argument : void
1564 Return : void
1565
1566This function executes with the MMU and data caches disabled. It is only called
1567by the primary CPU.
1568
1569The purpose of this function is to perform any architectural initialization
1570that varies across platforms.
1571
Dan Handley610e7e12018-03-01 18:44:00 +00001572On Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001573
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001574Function : bl2_platform_setup() [mandatory]
1575~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001576
1577::
1578
1579 Argument : void
1580 Return : void
1581
1582This function may execute with the MMU and data caches enabled if the platform
1583port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only
1584called by the primary CPU.
1585
1586The purpose of this function is to perform any platform initialization
1587specific to BL2.
1588
Dan Handley610e7e12018-03-01 18:44:00 +00001589In Arm standard platforms, this function performs security setup, including
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001590configuration of the TrustZone controller to allow non-secure masters access
1591to most of DRAM. Part of DRAM is reserved for secure world use.
1592
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001593Function : bl2_plat_handle_pre_image_load() [optional]
1594~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001595
1596::
1597
1598 Argument : unsigned int
1599 Return : int
1600
1601This function can be used by the platforms to update/use image information
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001602for given ``image_id``. This function is currently invoked in BL2 before
Soby Mathew97b1bff2018-09-27 16:46:41 +01001603loading each image.
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001604
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001605Function : bl2_plat_handle_post_image_load() [optional]
1606~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001607
1608::
1609
1610 Argument : unsigned int
1611 Return : int
1612
1613This function can be used by the platforms to update/use image information
1614for given ``image_id``. This function is currently invoked in BL2 after
Soby Mathew97b1bff2018-09-27 16:46:41 +01001615loading each image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001616
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001617Function : bl2_plat_preload_setup [optional]
1618~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001619
1620::
John Tsichritzisee10e792018-06-06 09:38:10 +01001621
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001622 Argument : void
1623 Return : void
1624
1625This optional function performs any BL2 platform initialization
1626required before image loading, that is not done later in
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001627bl2_platform_setup(). Specifically, if support for multiple
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001628boot sources is required, it initializes the boot sequence used by
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001629plat_try_next_boot_source().
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001630
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001631Function : plat_try_next_boot_source() [optional]
1632~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001633
1634::
John Tsichritzisee10e792018-06-06 09:38:10 +01001635
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001636 Argument : void
1637 Return : int
1638
1639This optional function passes to the next boot source in the redundancy
1640sequence.
1641
1642This function moves the current boot redundancy source to the next
1643element in the boot sequence. If there are no more boot sources then it
1644must return 0, otherwise it must return 1. The default implementation
1645of this always returns 0.
1646
Roberto Vargasb1584272017-11-20 13:36:10 +00001647Boot Loader Stage 2 (BL2) at EL3
1648--------------------------------
1649
Dan Handley610e7e12018-03-01 18:44:00 +00001650When the platform has a non-TF-A Boot ROM it is desirable to jump
1651directly to BL2 instead of TF-A BL1. In this case BL2 is expected to
Paul Beesleyf8640672019-04-12 14:19:42 +01001652execute at EL3 instead of executing at EL1. Refer to the :ref:`Firmware Design`
1653document for more information.
Roberto Vargasb1584272017-11-20 13:36:10 +00001654
1655All mandatory functions of BL2 must be implemented, except the functions
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001656bl2_early_platform_setup and bl2_el3_plat_arch_setup, because
1657their work is done now by bl2_el3_early_platform_setup and
1658bl2_el3_plat_arch_setup. These functions should generally implement
1659the bl1_plat_xxx() and bl2_plat_xxx() functionality combined.
Roberto Vargasb1584272017-11-20 13:36:10 +00001660
1661
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001662Function : bl2_el3_early_platform_setup() [mandatory]
1663~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00001664
1665::
John Tsichritzisee10e792018-06-06 09:38:10 +01001666
Roberto Vargasb1584272017-11-20 13:36:10 +00001667 Argument : u_register_t, u_register_t, u_register_t, u_register_t
1668 Return : void
1669
1670This function executes with the MMU and data caches disabled. It is only called
1671by the primary CPU. This function receives four parameters which can be used
1672by the platform to pass any needed information from the Boot ROM to BL2.
1673
Dan Handley610e7e12018-03-01 18:44:00 +00001674On Arm standard platforms, this function does the following:
Roberto Vargasb1584272017-11-20 13:36:10 +00001675
1676- Initializes a UART (PL011 console), which enables access to the ``printf``
1677 family of functions in BL2.
1678
1679- Initializes the storage abstraction layer used to load further bootloader
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001680 images. It is necessary to do this early on platforms with a SCP_BL2 image,
1681 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
Roberto Vargasb1584272017-11-20 13:36:10 +00001682
1683- Initializes the private variables that define the memory layout used.
1684
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001685Function : bl2_el3_plat_arch_setup() [mandatory]
1686~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00001687
1688::
John Tsichritzisee10e792018-06-06 09:38:10 +01001689
Roberto Vargasb1584272017-11-20 13:36:10 +00001690 Argument : void
1691 Return : void
1692
1693This function executes with the MMU and data caches disabled. It is only called
1694by the primary CPU.
1695
1696The purpose of this function is to perform any architectural initialization
1697that varies across platforms.
1698
Dan Handley610e7e12018-03-01 18:44:00 +00001699On Arm standard platforms, this function enables the MMU.
Roberto Vargasb1584272017-11-20 13:36:10 +00001700
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001701Function : bl2_el3_plat_prepare_exit() [optional]
1702~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00001703
1704::
John Tsichritzisee10e792018-06-06 09:38:10 +01001705
Roberto Vargasb1584272017-11-20 13:36:10 +00001706 Argument : void
1707 Return : void
1708
1709This function is called prior to exiting BL2 and run the next image.
1710It should be used to perform platform specific clean up or bookkeeping
1711operations before transferring control to the next image. This function
1712runs with MMU disabled.
1713
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001714FWU Boot Loader Stage 2 (BL2U)
1715------------------------------
1716
1717The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU
1718process and is executed only by the primary CPU. BL1 passes control to BL2U at
1719``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for:
1720
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001721#. (Optional) Transferring the optional SCP_BL2U binary image from AP secure
1722 memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1.
1723 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U
1724 should be copied from. Subsequent handling of the SCP_BL2U image is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001725 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function.
1726 If ``SCP_BL2U_BASE`` is not defined then this step is not performed.
1727
1728#. Any platform specific setup required to perform the FWU process. For
Dan Handley610e7e12018-03-01 18:44:00 +00001729 example, Arm standard platforms initialize the TZC controller so that the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001730 normal world can access DDR memory.
1731
1732The following functions must be implemented by the platform port to enable
1733BL2U to perform the tasks mentioned above.
1734
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001735Function : bl2u_early_platform_setup() [mandatory]
1736~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001737
1738::
1739
1740 Argument : meminfo *mem_info, void *plat_info
1741 Return : void
1742
1743This function executes with the MMU and data caches disabled. It is only
1744called by the primary CPU. The arguments to this function is the address
1745of the ``meminfo`` structure and platform specific info provided by BL1.
1746
1747The platform may copy the contents of the ``mem_info`` and ``plat_info`` into
1748private storage as the original memory may be subsequently overwritten by BL2U.
1749
Dan Handley610e7e12018-03-01 18:44:00 +00001750On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure,
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001751to extract SCP_BL2U image information, which is then copied into a private
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001752variable.
1753
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001754Function : bl2u_plat_arch_setup() [mandatory]
1755~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001756
1757::
1758
1759 Argument : void
1760 Return : void
1761
1762This function executes with the MMU and data caches disabled. It is only
1763called by the primary CPU.
1764
1765The purpose of this function is to perform any architectural initialization
1766that varies across platforms, for example enabling the MMU (since the memory
1767map differs across platforms).
1768
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001769Function : bl2u_platform_setup() [mandatory]
1770~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001771
1772::
1773
1774 Argument : void
1775 Return : void
1776
1777This function may execute with the MMU and data caches enabled if the platform
1778port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only
1779called by the primary CPU.
1780
1781The purpose of this function is to perform any platform initialization
1782specific to BL2U.
1783
Dan Handley610e7e12018-03-01 18:44:00 +00001784In Arm standard platforms, this function performs security setup, including
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001785configuration of the TrustZone controller to allow non-secure masters access
1786to most of DRAM. Part of DRAM is reserved for secure world use.
1787
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001788Function : bl2u_plat_handle_scp_bl2u() [optional]
1789~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001790
1791::
1792
1793 Argument : void
1794 Return : int
1795
1796This function is used to perform any platform-specific actions required to
1797handle the SCP firmware. Typically it transfers the image into SCP memory using
1798a platform-specific protocol and waits until SCP executes it and signals to the
1799Application Processor (AP) for BL2U execution to continue.
1800
1801This function returns 0 on success, a negative error code otherwise.
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001802This function is included if SCP_BL2U_BASE is defined.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001803
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001804Function : bl2_plat_mboot_init() [optional]
1805~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1806
1807::
1808
1809 Argument : void
1810 Return : void
1811
1812When the MEASURED_BOOT flag is enabled:
1813
1814- This function is used to initialize the backend driver(s) of measured boot.
1815- On the Arm FVP port, this function is used to initialize the Event Log
1816 backend driver with the Event Log buffer information (base address and
1817 size) received from BL1. It results in panic on error.
1818
1819When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1820
1821Function : bl2_plat_mboot_finish() [optional]
1822~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1823
1824::
1825
1826 Argument : void
1827 Return : void
1828
1829When the MEASURED_BOOT flag is enabled:
1830
1831- This function is used to finalize the measured boot backend driver(s),
1832 and also, set the information for the next bootloader component to extend
1833 the measurement if needed.
1834- On the Arm FVP port, this function is used to pass the Event Log buffer
1835 information (base address and size) to non-secure(BL33) and trusted OS(BL32)
1836 via nt_fw and tos_fw config respectively. It results in panic on error.
1837
1838When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1839
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001840Boot Loader Stage 3-1 (BL31)
1841----------------------------
1842
1843During cold boot, the BL31 stage is executed only by the primary CPU. This is
1844determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes
1845control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all
1846CPUs. BL31 executes at EL3 and is responsible for:
1847
1848#. Re-initializing all architectural and platform state. Although BL1 performs
1849 some of this initialization, BL31 remains resident in EL3 and must ensure
1850 that EL3 architectural and platform state is completely initialized. It
1851 should make no assumptions about the system state when it receives control.
1852
1853#. Passing control to a normal world BL image, pre-loaded at a platform-
Soby Mathew97b1bff2018-09-27 16:46:41 +01001854 specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list
1855 populated by BL2 in memory to do this.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001856
1857#. Providing runtime firmware services. Currently, BL31 only implements a
1858 subset of the Power State Coordination Interface (PSCI) API as a runtime
1859 service. See Section 3.3 below for details of porting the PSCI
1860 implementation.
1861
1862#. Optionally passing control to the BL32 image, pre-loaded at a platform-
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001863 specific address by BL2. BL31 exports a set of APIs that allow runtime
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001864 services to specify the security state in which the next image should be
Soby Mathew97b1bff2018-09-27 16:46:41 +01001865 executed and run the corresponding image. On ARM platforms, BL31 uses the
1866 ``bl_params`` list populated by BL2 in memory to do this.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001867
1868If BL31 is a reset vector, It also needs to handle the reset as specified in
1869section 2.2 before the tasks described above.
1870
1871The following functions must be implemented by the platform port to enable BL31
1872to perform the above tasks.
1873
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001874Function : bl31_early_platform_setup2() [mandatory]
1875~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001876
1877::
1878
Soby Mathew97b1bff2018-09-27 16:46:41 +01001879 Argument : u_register_t, u_register_t, u_register_t, u_register_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001880 Return : void
1881
1882This function executes with the MMU and data caches disabled. It is only called
Soby Mathew97b1bff2018-09-27 16:46:41 +01001883by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are
1884platform specific.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001885
Soby Mathew97b1bff2018-09-27 16:46:41 +01001886In Arm standard platforms, the arguments received are :
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001887
Soby Mathew97b1bff2018-09-27 16:46:41 +01001888 arg0 - The pointer to the head of `bl_params_t` list
1889 which is list of executable images following BL31,
1890
1891 arg1 - Points to load address of SOC_FW_CONFIG if present
Mikael Olsson0232da22021-02-12 17:30:16 +01001892 except in case of Arm FVP and Juno platform.
Manish V Badarkhe81414512020-06-24 15:58:38 +01001893
Mikael Olsson0232da22021-02-12 17:30:16 +01001894 In case of Arm FVP and Juno platform, points to load address
Manish V Badarkhe81414512020-06-24 15:58:38 +01001895 of FW_CONFIG.
Soby Mathew97b1bff2018-09-27 16:46:41 +01001896
1897 arg2 - Points to load address of HW_CONFIG if present
1898
1899 arg3 - A special value to verify platform parameters from BL2 to BL31. Not
1900 used in release builds.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001901
Soby Mathew97b1bff2018-09-27 16:46:41 +01001902The function runs through the `bl_param_t` list and extracts the entry point
1903information for BL32 and BL33. It also performs the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001904
1905- Initialize a UART (PL011 console), which enables access to the ``printf``
1906 family of functions in BL31.
1907
1908- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the
1909 CCI slave interface corresponding to the cluster that includes the primary
1910 CPU.
1911
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001912Function : bl31_plat_arch_setup() [mandatory]
1913~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001914
1915::
1916
1917 Argument : void
1918 Return : void
1919
1920This function executes with the MMU and data caches disabled. It is only called
1921by the primary CPU.
1922
1923The purpose of this function is to perform any architectural initialization
1924that varies across platforms.
1925
Dan Handley610e7e12018-03-01 18:44:00 +00001926On Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001927
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001928Function : bl31_platform_setup() [mandatory]
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001929~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1930
1931::
1932
1933 Argument : void
1934 Return : void
1935
1936This function may execute with the MMU and data caches enabled if the platform
1937port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only
1938called by the primary CPU.
1939
1940The purpose of this function is to complete platform initialization so that both
1941BL31 runtime services and normal world software can function correctly.
1942
Dan Handley610e7e12018-03-01 18:44:00 +00001943On Arm standard platforms, this function does the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001944
1945- Initialize the generic interrupt controller.
1946
1947 Depending on the GIC driver selected by the platform, the appropriate GICv2
1948 or GICv3 initialization will be done, which mainly consists of:
1949
1950 - Enable secure interrupts in the GIC CPU interface.
1951 - Disable the legacy interrupt bypass mechanism.
1952 - Configure the priority mask register to allow interrupts of all priorities
1953 to be signaled to the CPU interface.
1954 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure.
1955 - Target all secure SPIs to CPU0.
1956 - Enable these secure interrupts in the GIC distributor.
1957 - Configure all other interrupts as non-secure.
1958 - Enable signaling of secure interrupts in the GIC distributor.
1959
1960- Enable system-level implementation of the generic timer counter through the
1961 memory mapped interface.
1962
1963- Grant access to the system counter timer module
1964
1965- Initialize the power controller device.
1966
1967 In particular, initialise the locks that prevent concurrent accesses to the
1968 power controller device.
1969
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001970Function : bl31_plat_runtime_setup() [optional]
1971~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001972
1973::
1974
1975 Argument : void
1976 Return : void
1977
1978The purpose of this function is allow the platform to perform any BL31 runtime
1979setup just prior to BL31 exit during cold boot. The default weak
Julius Werneraae9bb12017-09-18 16:49:48 -07001980implementation of this function will invoke ``console_switch_state()`` to switch
1981console output to consoles marked for use in the ``runtime`` state.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001982
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001983Function : bl31_plat_get_next_image_ep_info() [mandatory]
1984~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001985
1986::
1987
Sandrine Bailleux842117d2018-05-14 14:25:47 +02001988 Argument : uint32_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001989 Return : entry_point_info *
1990
1991This function may execute with the MMU and data caches enabled if the platform
1992port does the necessary initializations in ``bl31_plat_arch_setup()``.
1993
1994This function is called by ``bl31_main()`` to retrieve information provided by
1995BL2 for the next image in the security state specified by the argument. BL31
1996uses this information to pass control to that image in the specified security
1997state. This function must return a pointer to the ``entry_point_info`` structure
1998(that was copied during ``bl31_early_platform_setup()``) if the image exists. It
1999should return NULL otherwise.
2000
Jeenu Viswambharane834ee12018-04-27 15:17:03 +01002001Function : bl31_plat_enable_mmu [optional]
2002~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2003
2004::
2005
2006 Argument : uint32_t
2007 Return : void
2008
2009This function enables the MMU. The boot code calls this function with MMU and
2010caches disabled. This function should program necessary registers to enable
2011translation, and upon return, the MMU on the calling PE must be enabled.
2012
2013The function must honor flags passed in the first argument. These flags are
2014defined by the translation library, and can be found in the file
2015``include/lib/xlat_tables/xlat_mmu_helpers.h``.
2016
2017On DynamIQ systems, this function must not use stack while enabling MMU, which
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002018is how the function in xlat table library version 2 is implemented.
Jeenu Viswambharane834ee12018-04-27 15:17:03 +01002019
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002020Function : plat_init_apkey [optional]
2021~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002022
2023::
2024
2025 Argument : void
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002026 Return : uint128_t
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002027
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002028This function returns the 128-bit value which can be used to program ARMv8.3
2029pointer authentication keys.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002030
2031The value should be obtained from a reliable source of randomness.
2032
2033This function is only needed if ARMv8.3 pointer authentication is used in the
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002034Trusted Firmware by building with ``BRANCH_PROTECTION`` option set to non-zero.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002035
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002036Function : plat_get_syscnt_freq2() [mandatory]
2037~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002038
2039::
2040
2041 Argument : void
2042 Return : unsigned int
2043
2044This function is used by the architecture setup code to retrieve the counter
2045frequency for the CPU's generic timer. This value will be programmed into the
Dan Handley610e7e12018-03-01 18:44:00 +00002046``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002047of the system counter, which is retrieved from the first entry in the frequency
2048modes table.
2049
johpow013e24c162020-04-22 14:05:13 -05002050Function : plat_arm_set_twedel_scr_el3() [optional]
2051~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2052
2053::
2054
2055 Argument : void
2056 Return : uint32_t
2057
2058This function is used in v8.6+ systems to set the WFE trap delay value in
2059SCR_EL3. If this function returns TWED_DISABLED or is left unimplemented, this
2060feature is not enabled. The only hook provided is to set the TWED fields in
2061SCR_EL3, there are similar fields in HCR_EL2, SCTLR_EL2, and SCTLR_EL1 to adjust
2062the WFE trap delays in lower ELs and these fields should be set by the
2063appropriate EL2 or EL1 code depending on the platform configuration.
2064
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002065#define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional]
2066~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002067
2068When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in
2069bytes) aligned to the cache line boundary that should be allocated per-cpu to
2070accommodate all the bakery locks.
2071
2072If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker
2073calculates the size of the ``bakery_lock`` input section, aligns it to the
2074nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT``
2075and stores the result in a linker symbol. This constant prevents a platform
2076from relying on the linker and provide a more efficient mechanism for
2077accessing per-cpu bakery lock information.
2078
2079If this constant is defined and its value is not equal to the value
2080calculated by the linker then a link time assertion is raised. A compile time
2081assertion is raised if the value of the constant is not aligned to the cache
2082line boundary.
2083
Paul Beesleyf8640672019-04-12 14:19:42 +01002084.. _porting_guide_sdei_requirements:
2085
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002086SDEI porting requirements
2087~~~~~~~~~~~~~~~~~~~~~~~~~
2088
Paul Beesley606d8072019-03-13 13:58:02 +00002089The |SDEI| dispatcher requires the platform to provide the following macros
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002090and functions, of which some are optional, and some others mandatory.
2091
2092Macros
2093......
2094
2095Macro: PLAT_SDEI_NORMAL_PRI [mandatory]
2096^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2097
2098This macro must be defined to the EL3 exception priority level associated with
Paul Beesley606d8072019-03-13 13:58:02 +00002099Normal |SDEI| events on the platform. This must have a higher value
2100(therefore of lower priority) than ``PLAT_SDEI_CRITICAL_PRI``.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002101
2102Macro: PLAT_SDEI_CRITICAL_PRI [mandatory]
2103^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2104
2105This macro must be defined to the EL3 exception priority level associated with
Paul Beesley606d8072019-03-13 13:58:02 +00002106Critical |SDEI| events on the platform. This must have a lower value
2107(therefore of higher priority) than ``PLAT_SDEI_NORMAL_PRI``.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002108
Paul Beesley606d8072019-03-13 13:58:02 +00002109**Note**: |SDEI| exception priorities must be the lowest among Secure
2110priorities. Among the |SDEI| exceptions, Critical |SDEI| priority must
2111be higher than Normal |SDEI| priority.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002112
2113Functions
2114.........
2115
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002116Function: int plat_sdei_validate_entry_point() [optional]
2117^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002118
2119::
2120
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002121 Argument: uintptr_t ep, unsigned int client_mode
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002122 Return: int
2123
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002124This function validates the entry point address of the event handler provided by
2125the client for both event registration and *Complete and Resume* |SDEI| calls.
2126The function ensures that the address is valid in the client translation regime.
2127
2128The second argument is the exception level that the client is executing in. It
2129can be Non-Secure EL1 or Non-Secure EL2.
2130
2131The function must return ``0`` for successful validation, or ``-1`` upon failure.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002132
Dan Handley610e7e12018-03-01 18:44:00 +00002133The default implementation always returns ``0``. On Arm platforms, this function
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002134translates the entry point address within the client translation regime and
2135further ensures that the resulting physical address is located in Non-secure
2136DRAM.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002137
2138Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional]
2139^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2140
2141::
2142
2143 Argument: uint64_t
2144 Argument: unsigned int
2145 Return: void
2146
Paul Beesley606d8072019-03-13 13:58:02 +00002147|SDEI| specification requires that a PE comes out of reset with the events
2148masked. The client therefore is expected to call ``PE_UNMASK`` to unmask
2149|SDEI| events on the PE. No |SDEI| events can be dispatched until such
2150time.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002151
Paul Beesley606d8072019-03-13 13:58:02 +00002152Should a PE receive an interrupt that was bound to an |SDEI| event while the
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002153events are masked on the PE, the dispatcher implementation invokes the function
2154``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the
2155interrupt and the interrupt ID are passed as parameters.
2156
2157The default implementation only prints out a warning message.
2158
Jimmy Brisson26c5b5c2020-06-22 14:18:42 -05002159.. _porting_guide_trng_requirements:
2160
2161TRNG porting requirements
2162~~~~~~~~~~~~~~~~~~~~~~~~~
2163
2164The |TRNG| backend requires the platform to provide the following values
2165and mandatory functions.
2166
2167Values
2168......
2169
2170value: uuid_t plat_trng_uuid [mandatory]
2171^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2172
2173This value must be defined to the UUID of the TRNG backend that is specific to
2174the hardware after ``plat_trng_setup`` function is called. This value must
2175conform to the SMCCC calling convention; The most significant 32 bits of the
2176UUID must not equal ``0xffffffff`` or the signed integer ``-1`` as this value in
2177w0 indicates failure to get a TRNG source.
2178
2179Functions
2180.........
2181
2182Function: void plat_entropy_setup(void) [mandatory]
2183^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2184
2185::
2186
2187 Argument: none
2188 Return: none
2189
2190This function is expected to do platform-specific initialization of any TRNG
2191hardware. This may include generating a UUID from a hardware-specific seed.
2192
2193Function: bool plat_get_entropy(uint64_t \*out) [mandatory]
2194^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2195
2196::
2197
2198 Argument: uint64_t *
2199 Return: bool
2200 Out : when the return value is true, the entropy has been written into the
2201 storage pointed to
2202
2203This function writes entropy into storage provided by the caller. If no entropy
2204is available, it must return false and the storage must not be written.
2205
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002206Power State Coordination Interface (in BL31)
2207--------------------------------------------
2208
Dan Handley610e7e12018-03-01 18:44:00 +00002209The TF-A implementation of the PSCI API is based around the concept of a
2210*power domain*. A *power domain* is a CPU or a logical group of CPUs which
2211share some state on which power management operations can be performed as
2212specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is
2213a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The
2214*power domains* are arranged in a hierarchical tree structure and each
2215*power domain* can be identified in a system by the cpu index of any CPU that
2216is part of that domain and a *power domain level*. A processing element (for
2217example, a CPU) is at level 0. If the *power domain* node above a CPU is a
2218logical grouping of CPUs that share some state, then level 1 is that group of
2219CPUs (for example, a cluster), and level 2 is a group of clusters (for
2220example, the system). More details on the power domain topology and its
Paul Beesleyf8640672019-04-12 14:19:42 +01002221organization can be found in :ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002222
2223BL31's platform initialization code exports a pointer to the platform-specific
2224power management operations required for the PSCI implementation to function
2225correctly. This information is populated in the ``plat_psci_ops`` structure. The
2226PSCI implementation calls members of the ``plat_psci_ops`` structure for performing
2227power management operations on the power domains. For example, the target
2228CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()``
2229handler (if present) is called for the CPU power domain.
2230
2231The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to
2232describe composite power states specific to a platform. The PSCI implementation
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +00002233defines a generic representation of the power-state parameter, which is an
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002234array of local power states where each index corresponds to a power domain
2235level. Each entry contains the local power state the power domain at that power
2236level could enter. It depends on the ``validate_power_state()`` handler to
2237convert the power-state parameter (possibly encoding a composite power state)
2238passed in a PSCI ``CPU_SUSPEND`` call to this representation.
2239
2240The following functions form part of platform port of PSCI functionality.
2241
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002242Function : plat_psci_stat_accounting_start() [optional]
2243~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002244
2245::
2246
2247 Argument : const psci_power_state_t *
2248 Return : void
2249
2250This is an optional hook that platforms can implement for residency statistics
2251accounting before entering a low power state. The ``pwr_domain_state`` field of
2252``state_info`` (first argument) can be inspected if stat accounting is done
2253differently at CPU level versus higher levels. As an example, if the element at
2254index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
2255state, special hardware logic may be programmed in order to keep track of the
2256residency statistics. For higher levels (array indices > 0), the residency
2257statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
2258default implementation will use PMF to capture timestamps.
2259
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002260Function : plat_psci_stat_accounting_stop() [optional]
2261~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002262
2263::
2264
2265 Argument : const psci_power_state_t *
2266 Return : void
2267
2268This is an optional hook that platforms can implement for residency statistics
2269accounting after exiting from a low power state. The ``pwr_domain_state`` field
2270of ``state_info`` (first argument) can be inspected if stat accounting is done
2271differently at CPU level versus higher levels. As an example, if the element at
2272index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
2273state, special hardware logic may be programmed in order to keep track of the
2274residency statistics. For higher levels (array indices > 0), the residency
2275statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
2276default implementation will use PMF to capture timestamps.
2277
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002278Function : plat_psci_stat_get_residency() [optional]
2279~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002280
2281::
2282
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -06002283 Argument : unsigned int, const psci_power_state_t *, unsigned int
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002284 Return : u_register_t
2285
2286This is an optional interface that is is invoked after resuming from a low power
2287state and provides the time spent resident in that low power state by the power
2288domain at a particular power domain level. When a CPU wakes up from suspend,
2289all its parent power domain levels are also woken up. The generic PSCI code
2290invokes this function for each parent power domain that is resumed and it
2291identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second
2292argument) describes the low power state that the power domain has resumed from.
2293The current CPU is the first CPU in the power domain to resume from the low
2294power state and the ``last_cpu_idx`` (third parameter) is the index of the last
2295CPU in the power domain to suspend and may be needed to calculate the residency
2296for that power domain.
2297
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002298Function : plat_get_target_pwr_state() [optional]
2299~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002300
2301::
2302
2303 Argument : unsigned int, const plat_local_state_t *, unsigned int
2304 Return : plat_local_state_t
2305
2306The PSCI generic code uses this function to let the platform participate in
2307state coordination during a power management operation. The function is passed
2308a pointer to an array of platform specific local power state ``states`` (second
2309argument) which contains the requested power state for each CPU at a particular
2310power domain level ``lvl`` (first argument) within the power domain. The function
2311is expected to traverse this array of upto ``ncpus`` (third argument) and return
2312a coordinated target power state by the comparing all the requested power
2313states. The target power state should not be deeper than any of the requested
2314power states.
2315
2316A weak definition of this API is provided by default wherein it assumes
2317that the platform assigns a local state value in order of increasing depth
2318of the power state i.e. for two power states X & Y, if X < Y
2319then X represents a shallower power state than Y. As a result, the
2320coordinated target local power state for a power domain will be the minimum
2321of the requested local power state values.
2322
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002323Function : plat_get_power_domain_tree_desc() [mandatory]
2324~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002325
2326::
2327
2328 Argument : void
2329 Return : const unsigned char *
2330
2331This function returns a pointer to the byte array containing the power domain
2332topology tree description. The format and method to construct this array are
Paul Beesleyf8640672019-04-12 14:19:42 +01002333described in :ref:`PSCI Power Domain Tree Structure`. The BL31 PSCI
2334initialization code requires this array to be described by the platform, either
2335statically or dynamically, to initialize the power domain topology tree. In case
2336the array is populated dynamically, then plat_core_pos_by_mpidr() and
2337plat_my_core_pos() should also be implemented suitably so that the topology tree
2338description matches the CPU indices returned by these APIs. These APIs together
2339form the platform interface for the PSCI topology framework.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002340
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002341Function : plat_setup_psci_ops() [mandatory]
2342~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002343
2344::
2345
2346 Argument : uintptr_t, const plat_psci_ops **
2347 Return : int
2348
2349This function may execute with the MMU and data caches enabled if the platform
2350port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only
2351called by the primary CPU.
2352
2353This function is called by PSCI initialization code. Its purpose is to let
2354the platform layer know about the warm boot entrypoint through the
2355``sec_entrypoint`` (first argument) and to export handler routines for
2356platform-specific psci power management actions by populating the passed
2357pointer with a pointer to BL31's private ``plat_psci_ops`` structure.
2358
2359A description of each member of this structure is given below. Please refer to
Dan Handley610e7e12018-03-01 18:44:00 +00002360the Arm FVP specific implementation of these handlers in
Paul Beesleyf8640672019-04-12 14:19:42 +01002361``plat/arm/board/fvp/fvp_pm.c`` as an example. For each PSCI function that the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002362platform wants to support, the associated operation or operations in this
2363structure must be provided and implemented (Refer section 4 of
Paul Beesleyf8640672019-04-12 14:19:42 +01002364:ref:`Firmware Design` for the PSCI API supported in TF-A). To disable a PSCI
Dan Handley610e7e12018-03-01 18:44:00 +00002365function in a platform port, the operation should be removed from this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002366structure instead of providing an empty implementation.
2367
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002368plat_psci_ops.cpu_standby()
2369...........................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002370
2371Perform the platform-specific actions to enter the standby state for a cpu
2372indicated by the passed argument. This provides a fast path for CPU standby
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002373wherein overheads of PSCI state management and lock acquisition is avoided.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002374For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation,
2375the suspend state type specified in the ``power-state`` parameter should be
2376STANDBY and the target power domain level specified should be the CPU. The
2377handler should put the CPU into a low power retention state (usually by
2378issuing a wfi instruction) and ensure that it can be woken up from that
2379state by a normal interrupt. The generic code expects the handler to succeed.
2380
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002381plat_psci_ops.pwr_domain_on()
2382.............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002383
2384Perform the platform specific actions to power on a CPU, specified
2385by the ``MPIDR`` (first argument). The generic code expects the platform to
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002386return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002387
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002388plat_psci_ops.pwr_domain_off()
2389..............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002390
2391Perform the platform specific actions to prepare to power off the calling CPU
2392and its higher parent power domain levels as indicated by the ``target_state``
2393(first argument). It is called by the PSCI ``CPU_OFF`` API implementation.
2394
2395The ``target_state`` encodes the platform coordinated target local power states
2396for the CPU power domain and its parent power domain levels. The handler
2397needs to perform power management operation corresponding to the local state
2398at each power level.
2399
2400For this handler, the local power state for the CPU power domain will be a
2401power down state where as it could be either power down, retention or run state
2402for the higher power domain levels depending on the result of state
2403coordination. The generic code expects the handler to succeed.
2404
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002405plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional]
2406...........................................................
Varun Wadekarae87f4b2017-07-10 16:02:05 -07002407
2408This optional function may be used as a performance optimization to replace
2409or complement pwr_domain_suspend() on some platforms. Its calling semantics
2410are identical to pwr_domain_suspend(), except the PSCI implementation only
2411calls this function when suspending to a power down state, and it guarantees
2412that data caches are enabled.
2413
2414When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches
2415before calling pwr_domain_suspend(). If the target_state corresponds to a
2416power down state and it is safe to perform some or all of the platform
2417specific actions in that function with data caches enabled, it may be more
2418efficient to move those actions to this function. When HW_ASSISTED_COHERENCY
2419= 1, data caches remain enabled throughout, and so there is no advantage to
2420moving platform specific actions to this function.
2421
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002422plat_psci_ops.pwr_domain_suspend()
2423..................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002424
2425Perform the platform specific actions to prepare to suspend the calling
2426CPU and its higher parent power domain levels as indicated by the
2427``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND``
2428API implementation.
2429
2430The ``target_state`` has a similar meaning as described in
2431the ``pwr_domain_off()`` operation. It encodes the platform coordinated
2432target local power states for the CPU power domain and its parent
2433power domain levels. The handler needs to perform power management operation
2434corresponding to the local state at each power level. The generic code
2435expects the handler to succeed.
2436
Douglas Raillarda84996b2017-08-02 16:57:32 +01002437The difference between turning a power domain off versus suspending it is that
2438in the former case, the power domain is expected to re-initialize its state
2439when it is next powered on (see ``pwr_domain_on_finish()``). In the latter
2440case, the power domain is expected to save enough state so that it can resume
2441execution by restoring this state when its powered on (see
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002442``pwr_domain_suspend_finish()``).
2443
Douglas Raillarda84996b2017-08-02 16:57:32 +01002444When suspending a core, the platform can also choose to power off the GICv3
2445Redistributor and ITS through an implementation-defined sequence. To achieve
2446this safely, the ITS context must be saved first. The architectural part is
2447implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed
2448sequence is implementation defined and it is therefore the responsibility of
2449the platform code to implement the necessary sequence. Then the GIC
2450Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper.
2451Powering off the Redistributor requires the implementation to support it and it
2452is the responsibility of the platform code to execute the right implementation
2453defined sequence.
2454
2455When a system suspend is requested, the platform can also make use of the
2456``gicv3_distif_save()`` helper to save the context of the GIC Distributor after
2457it has saved the context of the Redistributors and ITS of all the cores in the
2458system. The context of the Distributor can be large and may require it to be
2459allocated in a special area if it cannot fit in the platform's global static
2460data, for example in DRAM. The Distributor can then be powered down using an
2461implementation-defined sequence.
2462
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002463plat_psci_ops.pwr_domain_pwr_down_wfi()
2464.......................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002465
2466This is an optional function and, if implemented, is expected to perform
2467platform specific actions including the ``wfi`` invocation which allows the
2468CPU to powerdown. Since this function is invoked outside the PSCI locks,
2469the actions performed in this hook must be local to the CPU or the platform
2470must ensure that races between multiple CPUs cannot occur.
2471
2472The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()``
2473operation and it encodes the platform coordinated target local power states for
2474the CPU power domain and its parent power domain levels. This function must
2475not return back to the caller.
2476
2477If this function is not implemented by the platform, PSCI generic
2478implementation invokes ``psci_power_down_wfi()`` for power down.
2479
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002480plat_psci_ops.pwr_domain_on_finish()
2481....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002482
2483This function is called by the PSCI implementation after the calling CPU is
2484powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call.
2485It performs the platform-specific setup required to initialize enough state for
2486this CPU to enter the normal world and also provide secure runtime firmware
2487services.
2488
2489The ``target_state`` (first argument) is the prior state of the power domains
2490immediately before the CPU was turned on. It indicates which power domains
2491above the CPU might require initialization due to having previously been in
2492low power states. The generic code expects the handler to succeed.
2493
Madhukar Pappireddy33bd5142019-08-12 18:31:33 -05002494plat_psci_ops.pwr_domain_on_finish_late() [optional]
2495...........................................................
2496
2497This optional function is called by the PSCI implementation after the calling
2498CPU is fully powered on with respective data caches enabled. The calling CPU and
2499the associated cluster are guaranteed to be participating in coherency. This
2500function gives the flexibility to perform any platform-specific actions safely,
2501such as initialization or modification of shared data structures, without the
2502overhead of explicit cache maintainace operations.
2503
2504The ``target_state`` has a similar meaning as described in the ``pwr_domain_on_finish()``
2505operation. The generic code expects the handler to succeed.
2506
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002507plat_psci_ops.pwr_domain_suspend_finish()
2508.........................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002509
2510This function is called by the PSCI implementation after the calling CPU is
2511powered on and released from reset in response to an asynchronous wakeup
2512event, for example a timer interrupt that was programmed by the CPU during the
2513``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific
2514setup required to restore the saved state for this CPU to resume execution
2515in the normal world and also provide secure runtime firmware services.
2516
2517The ``target_state`` (first argument) has a similar meaning as described in
2518the ``pwr_domain_on_finish()`` operation. The generic code expects the platform
2519to succeed.
2520
Douglas Raillarda84996b2017-08-02 16:57:32 +01002521If the Distributor, Redistributors or ITS have been powered off as part of a
2522suspend, their context must be restored in this function in the reverse order
2523to how they were saved during suspend sequence.
2524
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002525plat_psci_ops.system_off()
2526..........................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002527
2528This function is called by PSCI implementation in response to a ``SYSTEM_OFF``
2529call. It performs the platform-specific system poweroff sequence after
2530notifying the Secure Payload Dispatcher.
2531
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002532plat_psci_ops.system_reset()
2533............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002534
2535This function is called by PSCI implementation in response to a ``SYSTEM_RESET``
2536call. It performs the platform-specific system reset sequence after
2537notifying the Secure Payload Dispatcher.
2538
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002539plat_psci_ops.validate_power_state()
2540....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002541
2542This function is called by the PSCI implementation during the ``CPU_SUSPEND``
2543call to validate the ``power_state`` parameter of the PSCI API and if valid,
2544populate it in ``req_state`` (second argument) array as power domain level
2545specific local states. If the ``power_state`` is invalid, the platform must
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002546return PSCI_E_INVALID_PARAMS as error, which is propagated back to the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002547normal world PSCI client.
2548
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002549plat_psci_ops.validate_ns_entrypoint()
2550......................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002551
2552This function is called by the PSCI implementation during the ``CPU_SUSPEND``,
2553``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point``
2554parameter passed by the normal world. If the ``entry_point`` is invalid,
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002555the platform must return PSCI_E_INVALID_ADDRESS as error, which is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002556propagated back to the normal world PSCI client.
2557
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002558plat_psci_ops.get_sys_suspend_power_state()
2559...........................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002560
2561This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND``
2562call to get the ``req_state`` parameter from platform which encodes the power
2563domain level specific local states to suspend to system affinity level. The
2564``req_state`` will be utilized to do the PSCI state coordination and
2565``pwr_domain_suspend()`` will be invoked with the coordinated target state to
2566enter system suspend.
2567
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002568plat_psci_ops.get_pwr_lvl_state_idx()
2569.....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002570
2571This is an optional function and, if implemented, is invoked by the PSCI
2572implementation to convert the ``local_state`` (first argument) at a specified
2573``pwr_lvl`` (second argument) to an index between 0 and
2574``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform
2575supports more than two local power states at each power domain level, that is
2576``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these
2577local power states.
2578
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002579plat_psci_ops.translate_power_state_by_mpidr()
2580..............................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002581
2582This is an optional function and, if implemented, verifies the ``power_state``
2583(second argument) parameter of the PSCI API corresponding to a target power
2584domain. The target power domain is identified by using both ``MPIDR`` (first
2585argument) and the power domain level encoded in ``power_state``. The power domain
2586level specific local states are to be extracted from ``power_state`` and be
2587populated in the ``output_state`` (third argument) array. The functionality
2588is similar to the ``validate_power_state`` function described above and is
2589envisaged to be used in case the validity of ``power_state`` depend on the
2590targeted power domain. If the ``power_state`` is invalid for the targeted power
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002591domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002592function is not implemented, then the generic implementation relies on
2593``validate_power_state`` function to translate the ``power_state``.
2594
2595This function can also be used in case the platform wants to support local
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002596power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002597APIs as described in Section 5.18 of `PSCI`_.
2598
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002599plat_psci_ops.get_node_hw_state()
2600.................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002601
2602This is an optional function. If implemented this function is intended to return
2603the power state of a node (identified by the first parameter, the ``MPIDR``) in
2604the power domain topology (identified by the second parameter, ``power_level``),
2605as retrieved from a power controller or equivalent component on the platform.
2606Upon successful completion, the implementation must map and return the final
2607status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it
2608must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as
2609appropriate.
2610
2611Implementations are not expected to handle ``power_levels`` greater than
2612``PLAT_MAX_PWR_LVL``.
2613
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002614plat_psci_ops.system_reset2()
2615.............................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002616
2617This is an optional function. If implemented this function is
2618called during the ``SYSTEM_RESET2`` call to perform a reset
2619based on the first parameter ``reset_type`` as specified in
2620`PSCI`_. The parameter ``cookie`` can be used to pass additional
2621reset information. If the ``reset_type`` is not supported, the
2622function must return ``PSCI_E_NOT_SUPPORTED``. For architectural
2623resets, all failures must return ``PSCI_E_INVALID_PARAMETERS``
2624and vendor reset can return other PSCI error codes as defined
2625in `PSCI`_. On success this function will not return.
2626
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002627plat_psci_ops.write_mem_protect()
2628.................................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002629
2630This is an optional function. If implemented it enables or disables the
2631``MEM_PROTECT`` functionality based on the value of ``val``.
2632A non-zero value enables ``MEM_PROTECT`` and a value of zero
2633disables it. Upon encountering failures it must return a negative value
2634and on success it must return 0.
2635
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002636plat_psci_ops.read_mem_protect()
2637................................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002638
2639This is an optional function. If implemented it returns the current
2640state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering
2641failures it must return a negative value and on success it must
2642return 0.
2643
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002644plat_psci_ops.mem_protect_chk()
2645...............................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002646
2647This is an optional function. If implemented it checks if a memory
2648region defined by a base address ``base`` and with a size of ``length``
2649bytes is protected by ``MEM_PROTECT``. If the region is protected
2650then it must return 0, otherwise it must return a negative number.
2651
Paul Beesleyf8640672019-04-12 14:19:42 +01002652.. _porting_guide_imf_in_bl31:
2653
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002654Interrupt Management framework (in BL31)
2655----------------------------------------
2656
2657BL31 implements an Interrupt Management Framework (IMF) to manage interrupts
2658generated in either security state and targeted to EL1 or EL2 in the non-secure
2659state or EL3/S-EL1 in the secure state. The design of this framework is
Paul Beesleyf8640672019-04-12 14:19:42 +01002660described in the :ref:`Interrupt Management Framework`
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002661
2662A platform should export the following APIs to support the IMF. The following
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002663text briefly describes each API and its implementation in Arm standard
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002664platforms. The API implementation depends upon the type of interrupt controller
Dan Handley610e7e12018-03-01 18:44:00 +00002665present in the platform. Arm standard platform layer supports both
2666`Arm Generic Interrupt Controller version 2.0 (GICv2)`_
2667and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the
2668FVP can be configured to use either GICv2 or GICv3 depending on the build flag
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01002669``FVP_USE_GIC_DRIVER`` (See :ref:`build_options_arm_fvp_platform` for more
2670details).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002671
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -05002672See also: :ref:`Interrupt Controller Abstraction APIs<Platform Interrupt Controller API>`.
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +01002673
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002674Function : plat_interrupt_type_to_line() [mandatory]
2675~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002676
2677::
2678
2679 Argument : uint32_t, uint32_t
2680 Return : uint32_t
2681
Dan Handley610e7e12018-03-01 18:44:00 +00002682The Arm processor signals an interrupt exception either through the IRQ or FIQ
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002683interrupt line. The specific line that is signaled depends on how the interrupt
2684controller (IC) reports different interrupt types from an execution context in
2685either security state. The IMF uses this API to determine which interrupt line
2686the platform IC uses to signal each type of interrupt supported by the framework
2687from a given security state. This API must be invoked at EL3.
2688
2689The first parameter will be one of the ``INTR_TYPE_*`` values (see
Paul Beesleyf8640672019-04-12 14:19:42 +01002690:ref:`Interrupt Management Framework`) indicating the target type of the
2691interrupt, the second parameter is the security state of the originating
2692execution context. The return result is the bit position in the ``SCR_EL3``
2693register of the respective interrupt trap: IRQ=1, FIQ=2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002694
Dan Handley610e7e12018-03-01 18:44:00 +00002695In the case of Arm standard platforms using GICv2, S-EL1 interrupts are
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002696configured as FIQs and Non-secure interrupts as IRQs from either security
2697state.
2698
Dan Handley610e7e12018-03-01 18:44:00 +00002699In the case of Arm standard platforms using GICv3, the interrupt line to be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002700configured depends on the security state of the execution context when the
2701interrupt is signalled and are as follows:
2702
2703- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in
2704 NS-EL0/1/2 context.
2705- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ
2706 in the NS-EL0/1/2 context.
2707- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2
2708 context.
2709
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002710Function : plat_ic_get_pending_interrupt_type() [mandatory]
2711~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002712
2713::
2714
2715 Argument : void
2716 Return : uint32_t
2717
2718This API returns the type of the highest priority pending interrupt at the
2719platform IC. The IMF uses the interrupt type to retrieve the corresponding
2720handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt
2721pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``,
2722``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3.
2723
Dan Handley610e7e12018-03-01 18:44:00 +00002724In the case of Arm standard platforms using GICv2, the *Highest Priority
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002725Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of
2726the pending interrupt. The type of interrupt depends upon the id value as
2727follows.
2728
2729#. id < 1022 is reported as a S-EL1 interrupt
2730#. id = 1022 is reported as a Non-secure interrupt.
2731#. id = 1023 is reported as an invalid interrupt type.
2732
Dan Handley610e7e12018-03-01 18:44:00 +00002733In the case of Arm standard platforms using GICv3, the system register
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002734``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*,
2735is read to determine the id of the pending interrupt. The type of interrupt
2736depends upon the id value as follows.
2737
2738#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt
2739#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt.
2740#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type.
2741#. All other interrupt id's are reported as EL3 interrupt.
2742
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002743Function : plat_ic_get_pending_interrupt_id() [mandatory]
2744~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002745
2746::
2747
2748 Argument : void
2749 Return : uint32_t
2750
2751This API returns the id of the highest priority pending interrupt at the
2752platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt
2753pending.
2754
Dan Handley610e7e12018-03-01 18:44:00 +00002755In the case of Arm standard platforms using GICv2, the *Highest Priority
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002756Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the
2757pending interrupt. The id that is returned by API depends upon the value of
2758the id read from the interrupt controller as follows.
2759
2760#. id < 1022. id is returned as is.
2761#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register*
2762 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt.
2763 This id is returned by the API.
2764#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned.
2765
Dan Handley610e7e12018-03-01 18:44:00 +00002766In the case of Arm standard platforms using GICv3, if the API is invoked from
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002767EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt
2768group 0 Register*, is read to determine the id of the pending interrupt. The id
2769that is returned by API depends upon the value of the id read from the
2770interrupt controller as follows.
2771
2772#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is.
2773#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system
2774 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1
2775 Register* is read to determine the id of the group 1 interrupt. This id
2776 is returned by the API as long as it is a valid interrupt id
2777#. If the id is any of the special interrupt identifiers,
2778 ``INTR_ID_UNAVAILABLE`` is returned.
2779
2780When the API invoked from S-EL1 for GICv3 systems, the id read from system
2781register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002782Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002783``INTR_ID_UNAVAILABLE`` is returned.
2784
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002785Function : plat_ic_acknowledge_interrupt() [mandatory]
2786~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002787
2788::
2789
2790 Argument : void
2791 Return : uint32_t
2792
2793This API is used by the CPU to indicate to the platform IC that processing of
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01002794the highest pending interrupt has begun. It should return the raw, unmodified
2795value obtained from the interrupt controller when acknowledging an interrupt.
2796The actual interrupt number shall be extracted from this raw value using the API
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -05002797`plat_ic_get_interrupt_id()<plat_ic_get_interrupt_id>`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002798
Dan Handley610e7e12018-03-01 18:44:00 +00002799This function in Arm standard platforms using GICv2, reads the *Interrupt
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002800Acknowledge Register* (``GICC_IAR``). This changes the state of the highest
2801priority pending interrupt from pending to active in the interrupt controller.
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01002802It returns the value read from the ``GICC_IAR``, unmodified.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002803
Dan Handley610e7e12018-03-01 18:44:00 +00002804In the case of Arm standard platforms using GICv3, if the API is invoked
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002805from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt
2806Acknowledge Register group 0*. If the API is invoked from S-EL1, the function
2807reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register
2808group 1*. The read changes the state of the highest pending interrupt from
2809pending to active in the interrupt controller. The value read is returned
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01002810unmodified.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002811
2812The TSP uses this API to start processing of the secure physical timer
2813interrupt.
2814
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002815Function : plat_ic_end_of_interrupt() [mandatory]
2816~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002817
2818::
2819
2820 Argument : uint32_t
2821 Return : void
2822
2823This API is used by the CPU to indicate to the platform IC that processing of
2824the interrupt corresponding to the id (passed as the parameter) has
2825finished. The id should be the same as the id returned by the
2826``plat_ic_acknowledge_interrupt()`` API.
2827
Dan Handley610e7e12018-03-01 18:44:00 +00002828Arm standard platforms write the id to the *End of Interrupt Register*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002829(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1``
2830system register in case of GICv3 depending on where the API is invoked from,
2831EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt
2832controller.
2833
2834The TSP uses this API to finish processing of the secure physical timer
2835interrupt.
2836
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002837Function : plat_ic_get_interrupt_type() [mandatory]
2838~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002839
2840::
2841
2842 Argument : uint32_t
2843 Return : uint32_t
2844
2845This API returns the type of the interrupt id passed as the parameter.
2846``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid
2847interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is
2848returned depending upon how the interrupt has been configured by the platform
2849IC. This API must be invoked at EL3.
2850
Dan Handley610e7e12018-03-01 18:44:00 +00002851Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002852and Non-secure interrupts as Group1 interrupts. It reads the group value
2853corresponding to the interrupt id from the relevant *Interrupt Group Register*
2854(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt.
2855
Dan Handley610e7e12018-03-01 18:44:00 +00002856In the case of Arm standard platforms using GICv3, both the *Interrupt Group
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002857Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register*
2858(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured
2859as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt.
2860
2861Crash Reporting mechanism (in BL31)
2862-----------------------------------
2863
2864BL31 implements a crash reporting mechanism which prints the various registers
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01002865of the CPU to enable quick crash analysis and debugging. This mechanism relies
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002866on the platform implementing ``plat_crash_console_init``,
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01002867``plat_crash_console_putc`` and ``plat_crash_console_flush``.
2868
2869The file ``plat/common/aarch64/crash_console_helpers.S`` contains sample
2870implementation of all of them. Platforms may include this file to their
2871makefiles in order to benefit from them. By default, they will cause the crash
Julius Werneraae9bb12017-09-18 16:49:48 -07002872output to be routed over the normal console infrastructure and get printed on
2873consoles configured to output in crash state. ``console_set_scope()`` can be
2874used to control whether a console is used for crash output.
Paul Beesleyba3ed402019-03-13 16:20:44 +00002875
2876.. note::
2877 Platforms are responsible for making sure that they only mark consoles for
2878 use in the crash scope that are able to support this, i.e. that are written
2879 in assembly and conform with the register clobber rules for putc()
2880 (x0-x2, x16-x17) and flush() (x0-x3, x16-x17) crash callbacks.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002881
Julius Werneraae9bb12017-09-18 16:49:48 -07002882In some cases (such as debugging very early crashes that happen before the
2883normal boot console can be set up), platforms may want to control crash output
Julius Werner1338c9c2018-11-19 14:25:55 -08002884more explicitly. These platforms may instead provide custom implementations for
2885these. They are executed outside of a C environment and without a stack. Many
2886console drivers provide functions named ``console_xxx_core_init/putc/flush``
2887that are designed to be used by these functions. See Arm platforms (like juno)
2888for an example of this.
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01002889
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002890Function : plat_crash_console_init [mandatory]
2891~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002892
2893::
2894
2895 Argument : void
2896 Return : int
2897
2898This API is used by the crash reporting mechanism to initialize the crash
Julius Werneraae9bb12017-09-18 16:49:48 -07002899console. It must only use the general purpose registers x0 through x7 to do the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002900initialization and returns 1 on success.
2901
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002902Function : plat_crash_console_putc [mandatory]
2903~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002904
2905::
2906
2907 Argument : int
2908 Return : int
2909
2910This API is used by the crash reporting mechanism to print a character on the
2911designated crash console. It must only use general purpose registers x1 and
2912x2 to do its work. The parameter and the return value are in general purpose
2913register x0.
2914
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002915Function : plat_crash_console_flush [mandatory]
2916~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002917
2918::
2919
2920 Argument : void
Jimmy Brisson39f9eee2020-08-05 13:44:05 -05002921 Return : void
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002922
2923This API is used by the crash reporting mechanism to force write of all buffered
2924data on the designated crash console. It should only use general purpose
Jimmy Brisson39f9eee2020-08-05 13:44:05 -05002925registers x0 through x5 to do its work.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002926
Manish Pandey9c9f38a2020-06-30 00:46:08 +01002927.. _External Abort handling and RAS Support:
2928
Jeenu Viswambharane34bf582018-10-12 08:48:36 +01002929External Abort handling and RAS Support
2930---------------------------------------
Jeenu Viswambharanbf235bc2018-07-12 10:00:01 +01002931
2932Function : plat_ea_handler
2933~~~~~~~~~~~~~~~~~~~~~~~~~~
2934
2935::
2936
2937 Argument : int
2938 Argument : uint64_t
2939 Argument : void *
2940 Argument : void *
2941 Argument : uint64_t
2942 Return : void
2943
2944This function is invoked by the RAS framework for the platform to handle an
2945External Abort received at EL3. The intention of the function is to attempt to
2946resolve the cause of External Abort and return; if that's not possible, to
2947initiate orderly shutdown of the system.
2948
2949The first parameter (``int ea_reason``) indicates the reason for External Abort.
2950Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``.
2951
2952The second parameter (``uint64_t syndrome``) is the respective syndrome
2953presented to EL3 after having received the External Abort. Depending on the
2954nature of the abort (as can be inferred from the ``ea_reason`` parameter), this
2955can be the content of either ``ESR_EL3`` or ``DISR_EL1``.
2956
2957The third parameter (``void *cookie``) is unused for now. The fourth parameter
2958(``void *handle``) is a pointer to the preempted context. The fifth parameter
2959(``uint64_t flags``) indicates the preempted security state. These parameters
2960are received from the top-level exception handler.
2961
2962If ``RAS_EXTENSION`` is set to ``1``, the default implementation of this
2963function iterates through RAS handlers registered by the platform. If any of the
2964RAS handlers resolve the External Abort, no further action is taken.
2965
2966If ``RAS_EXTENSION`` is set to ``0``, or if none of the platform RAS handlers
2967could resolve the External Abort, the default implementation prints an error
2968message, and panics.
2969
2970Function : plat_handle_uncontainable_ea
2971~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2972
2973::
2974
2975 Argument : int
2976 Argument : uint64_t
2977 Return : void
2978
2979This function is invoked by the RAS framework when an External Abort of
2980Uncontainable type is received at EL3. Due to the critical nature of
2981Uncontainable errors, the intention of this function is to initiate orderly
2982shutdown of the system, and is not expected to return.
2983
2984This function must be implemented in assembly.
2985
2986The first and second parameters are the same as that of ``plat_ea_handler``.
2987
2988The default implementation of this function calls
2989``report_unhandled_exception``.
2990
2991Function : plat_handle_double_fault
2992~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2993
2994::
2995
2996 Argument : int
2997 Argument : uint64_t
2998 Return : void
2999
3000This function is invoked by the RAS framework when another External Abort is
3001received at EL3 while one is already being handled. I.e., a call to
3002``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of
3003this function is to initiate orderly shutdown of the system, and is not expected
3004recover or return.
3005
3006This function must be implemented in assembly.
3007
3008The first and second parameters are the same as that of ``plat_ea_handler``.
3009
3010The default implementation of this function calls
3011``report_unhandled_exception``.
3012
3013Function : plat_handle_el3_ea
3014~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3015
3016::
3017
3018 Return : void
3019
3020This function is invoked when an External Abort is received while executing in
3021EL3. Due to its critical nature, the intention of this function is to initiate
3022orderly shutdown of the system, and is not expected recover or return.
3023
3024This function must be implemented in assembly.
3025
3026The default implementation of this function calls
3027``report_unhandled_exception``.
3028
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003029Build flags
3030-----------
3031
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003032There are some build flags which can be defined by the platform to control
3033inclusion or exclusion of certain BL stages from the FIP image. These flags
3034need to be defined in the platform makefile which will get included by the
3035build system.
3036
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003037- **NEED_BL33**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003038 By default, this flag is defined ``yes`` by the build system and ``BL33``
3039 build option should be supplied as a build option. The platform has the
3040 option of excluding the BL33 image in the ``fip`` image by defining this flag
3041 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE``
3042 are used, this flag will be set to ``no`` automatically.
3043
Paul Beesley07f0a312019-05-16 13:33:18 +01003044Platform include paths
3045----------------------
3046
3047Platforms are allowed to add more include paths to be passed to the compiler.
3048The ``PLAT_INCLUDES`` variable is used for this purpose. This is needed in
3049particular for the file ``platform_def.h``.
3050
3051Example:
3052
3053.. code:: c
3054
3055 PLAT_INCLUDES += -Iinclude/plat/myplat/include
3056
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003057C Library
3058---------
3059
3060To avoid subtle toolchain behavioral dependencies, the header files provided
3061by the compiler are not used. The software is built with the ``-nostdinc`` flag
3062to ensure no headers are included from the toolchain inadvertently. Instead the
Dan Handley610e7e12018-03-01 18:44:00 +00003063required headers are included in the TF-A source tree. The library only
3064contains those C library definitions required by the local implementation. If
3065more functionality is required, the needed library functions will need to be
3066added to the local implementation.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003067
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01003068Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have
Paul Beesleyf2ec7142019-10-04 16:17:46 +00003069been written specifically for TF-A. Some implementation files have been obtained
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01003070from `FreeBSD`_, others have been written specifically for TF-A as well. The
3071files can be found in ``include/lib/libc`` and ``lib/libc``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003072
Sandrine Bailleux6f0ecd72019-02-08 14:46:42 +01003073SCC can be found in http://www.simple-cc.org/. A copy of the `FreeBSD`_ sources
3074can be obtained from http://github.com/freebsd/freebsd.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003075
3076Storage abstraction layer
3077-------------------------
3078
Louis Mayencourtb5469002019-07-15 13:56:03 +01003079In order to improve platform independence and portability a storage abstraction
3080layer is used to load data from non-volatile platform storage. Currently
3081storage access is only required by BL1 and BL2 phases and performed inside the
3082``load_image()`` function in ``bl_common.c``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003083
Louis Mayencourtb5469002019-07-15 13:56:03 +01003084.. uml:: ../resources/diagrams/plantuml/io_framework_usage_overview.puml
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003085
Dan Handley610e7e12018-03-01 18:44:00 +00003086It is mandatory to implement at least one storage driver. For the Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003087development platforms the Firmware Image Package (FIP) driver is provided as
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01003088the default means to load data from storage (see :ref:`firmware_design_fip`).
3089The storage layer is described in the header file
3090``include/drivers/io/io_storage.h``. The implementation of the common library is
3091in ``drivers/io/io_storage.c`` and the driver files are located in
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003092``drivers/io/``.
3093
Louis Mayencourtb5469002019-07-15 13:56:03 +01003094.. uml:: ../resources/diagrams/plantuml/io_arm_class_diagram.puml
3095
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003096Each IO driver must provide ``io_dev_*`` structures, as described in
3097``drivers/io/io_driver.h``. These are returned via a mandatory registration
3098function that is called on platform initialization. The semi-hosting driver
3099implementation in ``io_semihosting.c`` can be used as an example.
3100
Louis Mayencourtb5469002019-07-15 13:56:03 +01003101Each platform should register devices and their drivers via the storage
3102abstraction layer. These drivers then need to be initialized by bootloader
3103phases as required in their respective ``blx_platform_setup()`` functions.
3104
3105.. uml:: ../resources/diagrams/plantuml/io_dev_registration.puml
3106
3107The storage abstraction layer provides mechanisms (``io_dev_init()``) to
3108initialize storage devices before IO operations are called.
3109
3110.. uml:: ../resources/diagrams/plantuml/io_dev_init_and_check.puml
3111
3112The basic operations supported by the layer
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003113include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``.
3114Drivers do not have to implement all operations, but each platform must
3115provide at least one driver for a device capable of supporting generic
3116operations such as loading a bootloader image.
3117
3118The current implementation only allows for known images to be loaded by the
3119firmware. These images are specified by using their identifiers, as defined in
Antonio Nino Diaz645feb42019-02-13 14:07:38 +00003120``include/plat/common/common_def.h`` (or a separate header file included from
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003121there). The platform layer (``plat_get_image_source()``) then returns a reference
3122to a device and a driver-specific ``spec`` which will be understood by the driver
3123to allow access to the image data.
3124
3125The layer is designed in such a way that is it possible to chain drivers with
3126other drivers. For example, file-system drivers may be implemented on top of
3127physical block devices, both represented by IO devices with corresponding
3128drivers. In such a case, the file-system "binding" with the block device may
3129be deferred until the file-system device is initialised.
3130
3131The abstraction currently depends on structures being statically allocated
3132by the drivers and callers, as the system does not yet provide a means of
3133dynamically allocating memory. This may also have the affect of limiting the
3134amount of open resources per driver.
3135
3136--------------
3137
Jimmy Brisson26c5b5c2020-06-22 14:18:42 -05003138*Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003139
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003140.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
Dan Handley610e7e12018-03-01 18:44:00 +00003141.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003142.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html
Paul Beesley2437ddc2019-02-08 16:43:05 +00003143.. _FreeBSD: https://www.freebsd.org
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01003144.. _SCC: http://www.simple-cc.org/