blob: dee280184b1bb8fc9010fa4c72aead6dbec8f1a5 [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Eddie James1a55a7a2023-10-24 10:43:51 -050012#include <config.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010013#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010015#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040016#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053017#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010018
Simon Glassb2c1cac2014-02-26 15:59:21 -070019/ {
20 model = "sandbox";
21 compatible = "sandbox";
22 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060023 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070024
Simon Glassfef72b72014-07-23 06:55:03 -060025 aliases {
26 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010027 ethernet0 = "/eth@10002000";
28 ethernet2 = &swp_0;
29 ethernet3 = &eth_3;
30 ethernet4 = &dsa_eth0;
31 ethernet5 = &eth_5;
Sean Anderson67d93a42022-05-05 13:11:30 -040032 ethernet6 = "/eth@10004000";
33 ethernet7 = &swp_1;
34 ethernet8 = &phy_eth0;
Simon Glass5620cf82018-10-01 12:22:40 -060035 gpio1 = &gpio_a;
36 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010037 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070038 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060039 mmc0 = "/mmc0";
40 mmc1 = "/mmc1";
Simon Glassf1eba352022-10-20 18:23:20 -060041 mmc2 = "/mmc2";
42 mmc3 = "/mmc3";
Simon Glassfff928c2023-08-24 13:55:41 -060043 mmc4 = "/mmc4";
44 mmc5 = "/mmc5";
Alexander Gendin038cb022023-10-09 01:24:36 +000045 mmc6 = "/mmc6";
Mattijs Korpershoekd77f8152024-07-10 10:40:06 +020046 mmc7 = "/mmc7";
Bin Meng408e5902018-08-03 01:14:41 -070047 pci0 = &pci0;
48 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070049 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020050 remoteproc0 = &rproc_1;
51 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060052 rtc0 = &rtc_0;
53 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060054 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020055 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070056 testbus3 = "/some-bus";
57 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070058 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070059 testfdt3 = "/b-test";
60 testfdt5 = "/some-bus/c-test@5";
61 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070062 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020063 fdt-dummy0 = "/translation-test@8000/dev@0,0";
64 fdt-dummy1 = "/translation-test@8000/dev@1,100";
65 fdt-dummy2 = "/translation-test@8000/dev@2,200";
66 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060067 usb0 = &usb_0;
68 usb1 = &usb_1;
69 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020070 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020071 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060072 };
73
Eddie James1a55a7a2023-10-24 10:43:51 -050074 reserved-memory {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 ranges;
78
79 event_log: tcg_event_log {
80 no-map;
Sughosh Ganu3f768682024-08-26 17:29:32 +053081 reg = <(CFG_SYS_SDRAM_BASE + 0x100000) 0x2000>;
Eddie James1a55a7a2023-10-24 10:43:51 -050082 };
83 };
84
Simon Glass5e135d32022-10-20 18:23:15 -060085 binman: binman {
Philippe Reynes462d1632022-03-28 22:56:53 +020086 };
87
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020088 config {
Simon Glass0034d962021-08-07 07:24:01 -060089 testing-bool;
90 testing-int = <123>;
91 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020092 environment {
93 from_fdt = "yes";
94 fdt_env_path = "";
95 };
96 };
97
Michal Simek43c42bd2023-08-31 08:59:05 +020098 options {
99 u-boot {
100 compatible = "u-boot,config";
101 bootscr-ram-offset = /bits/ 64 <0x12345678>;
Michal Simek6a7c1ce2023-08-31 09:04:27 +0200102 bootscr-flash-offset = /bits/ 64 <0>;
103 bootscr-flash-size = /bits/ 64 <0x2000>;
Christian Marangi719108e2024-10-01 14:24:43 +0200104 boot-led = "sandbox:green";
105 activity-led = "sandbox:red";
Christian Marangicdc38152024-10-01 14:24:44 +0200106 testing-bool;
107 testing-int = <123>;
108 testing-str = "testing";
Michal Simek43c42bd2023-08-31 08:59:05 +0200109 };
110 };
111
Simon Glassb255efc2022-04-24 23:31:24 -0600112 bootstd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700113 bootph-verify;
Simon Glassb255efc2022-04-24 23:31:24 -0600114 compatible = "u-boot,boot-std";
115
116 filename-prefixes = "/", "/boot/";
117 bootdev-order = "mmc2", "mmc1";
118
Simon Glassb71d7f72023-05-10 16:34:46 -0600119 extlinux {
120 compatible = "u-boot,extlinux";
Simon Glassb255efc2022-04-24 23:31:24 -0600121 };
122
123 efi {
124 compatible = "u-boot,distro-efi";
125 };
Simon Glassa9289612022-10-20 18:23:14 -0600126
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600127 theme {
128 font-size = <30>;
Simon Glass86f1ac52023-06-01 10:23:00 -0600129 menu-inset = <3>;
130 menuitem-gap-y = <1>;
Simon Glassd2bc33ed2023-01-06 08:52:41 -0600131 };
132
Simon Glass82adc292023-08-14 16:40:30 -0600133 cedit-theme {
134 font-size = <30>;
135 menu-inset = <3>;
136 menuitem-gap-y = <1>;
137 };
138
Simon Glassf1eba352022-10-20 18:23:20 -0600139 /*
140 * This is used for the VBE OS-request tests. A FAT filesystem
141 * created in a partition with the VBE information appearing
Michal Simek33224372023-09-07 14:55:48 +0200142 * before the partition starts
Simon Glassf1eba352022-10-20 18:23:20 -0600143 */
Simon Glassa9289612022-10-20 18:23:14 -0600144 firmware0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700145 bootph-verify;
Simon Glassa9289612022-10-20 18:23:14 -0600146 compatible = "fwupd,vbe-simple";
147 storage = "mmc1";
148 skip-offset = <0x200>;
149 area-start = <0x400>;
150 area-size = <0x1000>;
151 state-offset = <0x400>;
152 state-size = <0x40>;
153 version-offset = <0x800>;
154 version-size = <0x100>;
155 };
Simon Glassf1eba352022-10-20 18:23:20 -0600156
157 /*
158 * This is used for the VBE VPL tests. The MMC device holds the
159 * binman image.bin file. The test progresses through each phase
160 * of U-Boot, loading each in turn from MMC.
161 *
162 * Note that the test enables this node (and mmc3) before
163 * running U-Boot
164 */
165 firmware1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700166 bootph-verify;
Simon Glassf1eba352022-10-20 18:23:20 -0600167 status = "disabled";
168 compatible = "fwupd,vbe-simple";
169 storage = "mmc3";
Simon Glass9bb73e32023-04-02 14:01:24 +1200170 skip-offset = <0x800000>;
Simon Glassf1eba352022-10-20 18:23:20 -0600171 area-start = <0>;
172 area-size = <0xe00000>;
173 state-offset = <0xdffc00>;
174 state-size = <0x40>;
175 version-offset = <0xdffe00>;
176 version-size = <0x100>;
177 };
Simon Glassb255efc2022-04-24 23:31:24 -0600178 };
179
Simon Glass61300722023-06-01 10:23:01 -0600180 cedit: cedit {
181 };
182
Andrew Scull451b8b12022-05-30 10:00:12 +0000183 fuzzing-engine {
184 compatible = "sandbox,fuzzing-engine";
185 };
186
Nandor Han6521e5d2021-06-10 16:56:44 +0300187 reboot-mode0 {
188 compatible = "reboot-mode-gpio";
189 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
190 u-boot,env-variable = "bootstatus";
191 mode-test = <0x01>;
192 mode-download = <0x03>;
193 };
194
Nandor Han7e4067a2021-06-10 16:56:45 +0300195 reboot_mode1: reboot-mode@14 {
196 compatible = "reboot-mode-rtc";
197 rtc = <&rtc_0>;
198 reg = <0x30 4>;
199 u-boot,env-variable = "bootstatus";
200 big-endian;
201 mode-test = <0x21969147>;
202 mode-download = <0x51939147>;
203 };
204
Simon Glassed96cde2018-12-10 10:37:33 -0700205 audio: audio-codec {
206 compatible = "sandbox,audio-codec";
207 #sound-dai-cells = <1>;
208 };
209
Philippe Reynes1ee26482020-07-24 18:19:51 +0200210 buttons {
211 compatible = "gpio-keys";
212
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200213 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200214 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200215 label = "button1";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300216 linux,code = <BTN_1>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200217 };
218
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200219 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200220 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200221 label = "button2";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300222 linux,code = <BTN_2>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200223 };
224 };
225
Marek Szyprowskiad398592021-02-18 11:33:18 +0100226 buttons2 {
227 compatible = "adc-keys";
228 io-channels = <&adc 3>;
229 keyup-threshold-microvolt = <3000000>;
230
231 button-up {
232 label = "button3";
233 linux,code = <KEY_F3>;
234 press-threshold-microvolt = <1500000>;
235 };
236
237 button-down {
238 label = "button4";
239 linux,code = <KEY_F4>;
240 press-threshold-microvolt = <1000000>;
241 };
242
243 button-enter {
244 label = "button5";
245 linux,code = <KEY_F5>;
246 press-threshold-microvolt = <500000>;
247 };
248 };
249
Simon Glassc953aaf2018-12-10 10:37:34 -0700250 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600251 reg = <0 0>;
252 compatible = "google,cros-ec-sandbox";
253
254 /*
255 * This describes the flash memory within the EC. Note
256 * that the STM32L flash erases to 0, not 0xff.
257 */
258 flash {
259 image-pos = <0x08000000>;
260 size = <0x20000>;
261 erase-value = <0>;
262
263 /* Information for sandbox */
264 ro {
265 image-pos = <0>;
266 size = <0xf000>;
267 };
268 wp-ro {
269 image-pos = <0xf000>;
270 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700271 used = <0x884>;
272 compress = "lz4";
273 uncomp-size = <0xcf8>;
274 hash {
275 algo = "sha256";
276 value = [00 01 02 03 04 05 06 07
277 08 09 0a 0b 0c 0d 0e 0f
278 10 11 12 13 14 15 16 17
279 18 19 1a 1b 1c 1d 1e 1f];
280 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600281 };
282 rw {
283 image-pos = <0x10000>;
284 size = <0x10000>;
285 };
286 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300287
288 cros_ec_pwm: cros-ec-pwm {
289 compatible = "google,cros-ec-pwm";
290 #pwm-cells = <1>;
291 };
292
Simon Glass699c9ca2018-10-01 12:22:08 -0600293 };
294
Yannick Fertré9712c822019-10-07 15:29:05 +0200295 dsi_host: dsi_host {
296 compatible = "sandbox,dsi-host";
297 };
298
Simon Glassb2c1cac2014-02-26 15:59:21 -0700299 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600300 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700301 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600302 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700303 ping-add = <0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700304 bootph-all;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100305 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
306 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700307 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100308 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
309 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
310 <&gpio_b 7 GPIO_IN 3 2 1>,
311 <&gpio_b 8 GPIO_OUT 3 2 1>,
312 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100313 test3-gpios =
314 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
315 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
316 <&gpio_c 2 GPIO_OUT>,
317 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
318 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200319 <&gpio_c 5 GPIO_IN>,
320 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
321 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530322 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
323 test5-gpios = <&gpio_a 19>;
324
Simon Glass73025392021-10-23 17:26:04 -0600325 bool-value;
Stefan Herbrechtsmeier1b090e62022-06-14 15:21:30 +0200326 int8-value = /bits/ 8 <0x12>;
327 int16-value = /bits/ 16 <0x1234>;
Simon Glass6df01f92018-12-10 10:37:37 -0700328 int-value = <1234>;
329 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200330 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200331 int-array = <5678 9123 4567>;
Michal Simek08a194e2023-08-25 11:37:46 +0200332 int64-array = /bits/ 64 <0x1111222233334444 0x4444333322221111>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600333 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700334 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600335 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200336 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530337
338 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
339 <&muxcontroller0 2>, <&muxcontroller0 3>,
340 <&muxcontroller1>;
341 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
342 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100343 display-timings {
344 timing0: 240x320 {
345 clock-frequency = <6500000>;
346 hactive = <240>;
347 vactive = <320>;
348 hfront-porch = <6>;
349 hback-porch = <7>;
350 hsync-len = <1>;
351 vback-porch = <5>;
352 vfront-porch = <8>;
353 vsync-len = <2>;
354 hsync-active = <1>;
355 vsync-active = <0>;
356 de-active = <1>;
357 pixelclk-active = <1>;
358 interlaced;
359 doublescan;
360 doubleclk;
361 };
362 timing1: 480x800 {
363 clock-frequency = <9000000>;
364 hactive = <480>;
365 vactive = <800>;
366 hfront-porch = <10>;
367 hback-porch = <59>;
368 hsync-len = <12>;
369 vback-porch = <15>;
370 vfront-porch = <17>;
371 vsync-len = <16>;
372 hsync-active = <0>;
373 vsync-active = <1>;
374 de-active = <0>;
375 pixelclk-active = <0>;
376 };
377 timing2: 800x480 {
378 clock-frequency = <33500000>;
379 hactive = <800>;
380 vactive = <480>;
381 hback-porch = <89>;
382 hfront-porch = <164>;
383 vback-porch = <23>;
384 vfront-porch = <10>;
385 hsync-len = <11>;
386 vsync-len = <13>;
387 };
388 };
Raphael Gallais-Poua853b922023-05-11 16:36:52 +0200389 panel-timing {
Nikhil M Jainbb9d1312023-01-31 15:35:15 +0530390 clock-frequency = <6500000>;
391 hactive = <240>;
392 vactive = <320>;
393 hfront-porch = <6>;
394 hback-porch = <7>;
395 hsync-len = <1>;
396 vback-porch = <5>;
397 vfront-porch = <8>;
398 vsync-len = <2>;
399 hsync-active = <1>;
400 vsync-active = <0>;
401 de-active = <1>;
402 pixelclk-active = <1>;
403 interlaced;
404 doublescan;
405 doubleclk;
406 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700407 };
408
409 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600410 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700411 compatible = "not,compatible";
412 };
413
414 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600415 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700416 };
417
Simon Glass5620cf82018-10-01 12:22:40 -0600418 backlight: backlight {
419 compatible = "pwm-backlight";
420 enable-gpios = <&gpio_a 1>;
421 power-supply = <&ldo_1>;
422 pwms = <&pwm 0 1000>;
423 default-brightness-level = <5>;
424 brightness-levels = <0 16 32 64 128 170 202 234 255>;
425 };
426
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200427 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200428 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200429 bind-test-child1 {
430 compatible = "sandbox,phy";
431 #phy-cells = <1>;
432 };
433
434 bind-test-child2 {
435 compatible = "simple-bus";
436 };
437 };
438
Simon Glassb2c1cac2014-02-26 15:59:21 -0700439 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600440 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700441 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600442 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700443 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530444
445 mux-controls = <&muxcontroller0 0>;
446 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700447 };
448
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200449 phy_provider0: gen_phy@0 {
450 compatible = "sandbox,phy";
451 #phy-cells = <1>;
452 };
453
454 phy_provider1: gen_phy@1 {
455 compatible = "sandbox,phy";
456 #phy-cells = <0>;
457 broken;
458 };
459
developer71092972020-05-02 11:35:12 +0200460 phy_provider2: gen_phy@2 {
461 compatible = "sandbox,phy";
462 #phy-cells = <0>;
463 };
464
Jonas Karlman9f89e682023-08-31 22:16:35 +0000465 phy_provider3: gen_phy@3 {
466 compatible = "sandbox,phy";
467 #phy-cells = <2>;
468 };
469
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200470 gen_phy_user: gen_phy_user {
471 compatible = "simple-bus";
472 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
473 phy-names = "phy1", "phy2", "phy3";
474 };
475
developer71092972020-05-02 11:35:12 +0200476 gen_phy_user1: gen_phy_user1 {
477 compatible = "simple-bus";
478 phys = <&phy_provider0 0>, <&phy_provider2>;
479 phy-names = "phy1", "phy2";
480 };
481
Jonas Karlman9f89e682023-08-31 22:16:35 +0000482 gen_phy_user2: gen_phy_user2 {
483 compatible = "simple-bus";
484 phys = <&phy_provider3 0 0>;
485 phy-names = "phy1";
486 };
487
Simon Glassb2c1cac2014-02-26 15:59:21 -0700488 some-bus {
489 #address-cells = <1>;
490 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600491 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600492 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600493 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700494 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600495 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700496 compatible = "denx,u-boot-fdt-test";
497 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600498 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700499 ping-add = <5>;
500 };
Simon Glass40717422014-07-23 06:55:18 -0600501 c-test@0 {
502 compatible = "denx,u-boot-fdt-test";
503 reg = <0>;
504 ping-expect = <6>;
505 ping-add = <6>;
506 };
507 c-test@1 {
508 compatible = "denx,u-boot-fdt-test";
509 reg = <1>;
510 ping-expect = <7>;
511 ping-add = <7>;
512 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700513 };
514
515 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600516 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600517 ping-expect = <6>;
518 ping-add = <6>;
519 compatible = "google,another-fdt-test";
520 };
521
522 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600523 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600524 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700525 ping-add = <6>;
526 compatible = "google,another-fdt-test";
527 };
528
Simon Glass0ccb0972015-01-25 08:27:05 -0700529 f-test {
Patrick Rudolph0fe88cc2024-10-23 15:20:05 +0200530 #interrupt-cells = <2>;
531 interrupt-parent = <&irq>;
532 interrupts = <4 0>;
Simon Glass0ccb0972015-01-25 08:27:05 -0700533 compatible = "denx,u-boot-fdt-test";
534 };
535
536 g-test {
537 compatible = "denx,u-boot-fdt-test";
538 };
539
Bin Mengd9d24782018-10-10 22:07:01 -0700540 h-test {
541 compatible = "denx,u-boot-fdt-test1";
542 };
543
developercf8bc132020-05-02 11:35:10 +0200544 i-test {
545 compatible = "mediatek,u-boot-fdt-test";
546 #address-cells = <1>;
547 #size-cells = <0>;
548
549 subnode@0 {
550 reg = <0>;
551 };
552
553 subnode@1 {
554 reg = <1>;
555 };
556
557 subnode@2 {
558 reg = <2>;
559 };
560 };
561
Simon Glass204675c2019-12-29 21:19:25 -0700562 devres-test {
563 compatible = "denx,u-boot-devres-test";
564 };
565
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530566 another-test {
567 reg = <0 2>;
568 compatible = "denx,u-boot-fdt-test";
569 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
570 test5-gpios = <&gpio_a 19>;
571 };
572
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100573 mmio-bus@0 {
574 #address-cells = <1>;
575 #size-cells = <1>;
576 compatible = "denx,u-boot-test-bus";
577 dma-ranges = <0x10000000 0x00000000 0x00040000>;
578
579 subnode@0 {
580 compatible = "denx,u-boot-fdt-test";
581 };
582 };
583
584 mmio-bus@1 {
585 #address-cells = <1>;
586 #size-cells = <1>;
587 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100588
589 subnode@0 {
590 compatible = "denx,u-boot-fdt-test";
591 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100592 };
593
Simon Glass3c601b12020-07-07 13:12:06 -0600594 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600595 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600596 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600597 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600598 child {
599 compatible = "denx,u-boot-acpi-test";
600 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600601 };
602
Simon Glass3c601b12020-07-07 13:12:06 -0600603 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600604 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600605 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600606 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600607 };
608
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200609 clocks {
610 clk_fixed: clk-fixed {
611 compatible = "fixed-clock";
612 #clock-cells = <0>;
613 clock-frequency = <1234>;
614 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000615
616 clk_fixed_factor: clk-fixed-factor {
617 compatible = "fixed-factor-clock";
618 #clock-cells = <0>;
619 clock-div = <3>;
620 clock-mult = <2>;
621 clocks = <&clk_fixed>;
622 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200623
624 osc {
625 compatible = "fixed-clock";
626 #clock-cells = <0>;
627 clock-frequency = <20000000>;
628 };
Stephen Warrena9622432016-06-17 09:44:00 -0600629 };
630
631 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600632 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600633 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200634 assigned-clocks = <&clk_sandbox 3>;
635 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600636 };
637
638 clk-test {
639 compatible = "sandbox,clk-test";
640 clocks = <&clk_fixed>,
641 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200642 <&clk_sandbox 0>,
Yang Xiwene89289c2023-12-16 02:28:52 +0800643 <&ccf 11>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200644 <&clk_sandbox 3>,
645 <&clk_sandbox 2>;
Yang Xiwene89289c2023-12-16 02:28:52 +0800646 clock-names = "fixed", "i2c", "spi", "i2c_root", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600647 };
648
Ashok Reddy Soma8f03cef2023-08-30 10:31:42 +0200649 clk-test2 {
650 compatible = "sandbox,clk-test";
651 assigned-clock-rates = <321>;
652 };
653
654 clk-test3 {
655 compatible = "sandbox,clk-test";
656 assigned-clocks = <&clk_sandbox 1>;
657 };
658
659 clk-test4 {
660 compatible = "sandbox,clk-test";
661 assigned-clock-rates = <654>, <321>;
662 assigned-clocks = <&clk_sandbox 1>;
663 };
664
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200665 ccf: clk-ccf {
666 compatible = "sandbox,clk-ccf";
Yang Xiwene89289c2023-12-16 02:28:52 +0800667 #clock-cells = <1>;
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200668 };
669
Simon Glass507ab962021-12-04 08:56:31 -0700670 efi-media {
671 compatible = "sandbox,efi-media";
672 };
673
Simon Glass5b968632015-05-22 15:42:15 -0600674 eth@10002000 {
675 compatible = "sandbox,eth";
676 reg = <0x10002000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600677 };
678
679 eth_5: eth@10003000 {
680 compatible = "sandbox,eth";
681 reg = <0x10003000 0x1000>;
Sean Anderson13652b82022-05-05 13:11:44 -0400682 nvmem-cells = <&eth5_addr>;
683 nvmem-cell-names = "mac-address";
Simon Glass5b968632015-05-22 15:42:15 -0600684 };
685
Bin Meng04a11cb2015-08-27 22:25:53 -0700686 eth_3: sbe5 {
687 compatible = "sandbox,eth";
688 reg = <0x10005000 0x1000>;
Sean Andersone2dc0e62022-05-05 13:11:42 -0400689 nvmem-cells = <&eth3_addr>;
690 nvmem-cell-names = "mac-address";
Bin Meng04a11cb2015-08-27 22:25:53 -0700691 };
692
Simon Glass5b968632015-05-22 15:42:15 -0600693 eth@10004000 {
694 compatible = "sandbox,eth";
695 reg = <0x10004000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600696 };
697
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200698 phy_eth0: phy-test-eth {
699 compatible = "sandbox,eth";
700 reg = <0x10007000 0x1000>;
Sean Anderson24b1b8d2022-05-05 13:11:35 -0400701 mac-address = [ 02 00 11 22 33 49 ];
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200702 phy-handle = <&ethphy1>;
Marek Behúnbc194772022-04-07 00:33:01 +0200703 phy-mode = "2500base-x";
Marek Behúnf4f1ddc2022-04-07 00:32:57 +0200704 };
705
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800706 dsa_eth0: dsa-test-eth {
707 compatible = "sandbox,eth";
708 reg = <0x10006000 0x1000>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400709 nvmem-cells = <&eth4_addr>;
710 nvmem-cell-names = "mac-address";
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800711 };
712
713 dsa-test {
714 compatible = "sandbox,dsa";
715
716 ports {
717 #address-cells = <1>;
718 #size-cells = <0>;
719 swp_0: port@0 {
720 reg = <0>;
721 label = "lan0";
722 phy-mode = "rgmii-rxid";
723
724 fixed-link {
725 speed = <100>;
726 full-duplex;
727 };
728 };
729
730 swp_1: port@1 {
731 reg = <1>;
732 label = "lan1";
733 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800734 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800735 };
736
737 port@2 {
738 reg = <2>;
739 ethernet = <&dsa_eth0>;
740
741 fixed-link {
742 speed = <1000>;
743 full-duplex;
744 };
745 };
746 };
747 };
748
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700749 firmware {
750 sandbox_firmware: sandbox-firmware {
751 compatible = "sandbox,firmware";
752 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200753
Etienne Carriere09665cb2022-02-21 09:22:39 +0100754 scmi {
Etienne Carriere02fd1262020-09-09 18:44:00 +0200755 compatible = "sandbox,scmi-agent";
756 #address-cells = <1>;
757 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200758
AKASHI Takahiro535a7bd2023-10-16 14:39:45 +0900759 pwrdom_scmi: protocol@11 {
760 reg = <0x11>;
761 #power-domain-cells = <1>;
762 };
763
Etienne Carriere09665cb2022-02-21 09:22:39 +0100764 clk_scmi: protocol@14 {
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200765 reg = <0x14>;
766 #clock-cells = <1>;
AKASHI Takahirocc4ecda2023-10-11 19:06:59 +0900767 linaro,sandbox-channel-id = <0x14>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200768 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200769
Etienne Carriere09665cb2022-02-21 09:22:39 +0100770 reset_scmi: protocol@16 {
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200771 reg = <0x16>;
772 #reset-cells = <1>;
773 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100774
775 protocol@17 {
776 reg = <0x17>;
777
778 regulators {
779 #address-cells = <1>;
780 #size-cells = <0>;
781
Etienne Carriere09665cb2022-02-21 09:22:39 +0100782 regul0_scmi: reg@0 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100783 reg = <0>;
784 regulator-name = "sandbox-voltd0";
785 regulator-min-microvolt = <1100000>;
786 regulator-max-microvolt = <3300000>;
787 };
Etienne Carriere09665cb2022-02-21 09:22:39 +0100788 regul1_scmi: reg@1 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100789 reg = <0x1>;
790 regulator-name = "sandbox-voltd1";
791 regulator-min-microvolt = <1800000>;
792 };
793 };
794 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200795 };
Alexey Romanov9dc617d2023-09-21 11:13:36 +0300796
797 sm: secure-monitor {
798 compatible = "sandbox,sm";
799 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700800 };
801
Alexander Dahl6ac319d2022-09-30 14:04:30 +0200802 fpga {
803 compatible = "sandbox,fpga";
804 };
805
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100806 pinctrl-gpio {
807 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700808
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100809 gpio_a: base-gpios {
810 compatible = "sandbox,gpio";
811 gpio-controller;
812 #gpio-cells = <1>;
813 gpio-bank-name = "a";
814 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200815 hog_input_active_low {
816 gpio-hog;
817 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200818 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200819 };
820 hog_input_active_high {
821 gpio-hog;
822 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200823 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200824 };
825 hog_output_low {
826 gpio-hog;
827 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200828 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200829 };
830 hog_output_high {
831 gpio-hog;
832 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200833 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200834 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100835 };
836
837 gpio_b: extra-gpios {
838 compatible = "sandbox,gpio";
839 gpio-controller;
840 #gpio-cells = <5>;
841 gpio-bank-name = "b";
842 sandbox,gpio-count = <10>;
843 };
Simon Glass25348a42014-10-13 23:42:11 -0600844
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100845 gpio_c: pinmux-gpios {
846 compatible = "sandbox,gpio";
847 gpio-controller;
848 #gpio-cells = <2>;
849 gpio-bank-name = "c";
850 sandbox,gpio-count = <10>;
851 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100852 };
853
Simon Glass7df766e2014-12-10 08:55:55 -0700854 i2c@0 {
855 #address-cells = <1>;
856 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600857 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700858 compatible = "sandbox,i2c";
859 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200860 pinctrl-names = "default";
861 pinctrl-0 = <&pinmux_i2c0_pins>;
862
Simon Glass7df766e2014-12-10 08:55:55 -0700863 eeprom@2c {
Sean Andersone2dc0e62022-05-05 13:11:42 -0400864 #address-cells = <1>;
865 #size-cells = <1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700866 reg = <0x2c>;
867 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700868 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200869 partitions {
870 compatible = "fixed-partitions";
871 #address-cells = <1>;
872 #size-cells = <1>;
873 bootcount_i2c: bootcount@10 {
874 reg = <10 2>;
875 };
876 };
Sean Andersone2dc0e62022-05-05 13:11:42 -0400877
878 eth3_addr: mac-address@24 {
879 reg = <24 6>;
880 };
Simon Glass7df766e2014-12-10 08:55:55 -0700881 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200882
Simon Glass336b2952015-05-22 15:42:17 -0600883 rtc_0: rtc@43 {
Sean Anderson5768e8b2022-05-05 13:11:43 -0400884 #address-cells = <1>;
885 #size-cells = <1>;
Simon Glass336b2952015-05-22 15:42:17 -0600886 reg = <0x43>;
887 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700888 sandbox,emul = <&emul0>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400889
890 eth4_addr: mac-address@40 {
891 reg = <0x40 6>;
892 };
Simon Glass336b2952015-05-22 15:42:17 -0600893 };
894
895 rtc_1: rtc@61 {
896 reg = <0x61>;
897 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700898 sandbox,emul = <&emul1>;
899 };
900
901 i2c_emul: emul {
902 reg = <0xff>;
903 compatible = "sandbox,i2c-emul-parent";
904 emul_eeprom: emul-eeprom {
905 compatible = "sandbox,i2c-eeprom";
906 sandbox,filename = "i2c.bin";
907 sandbox,size = <256>;
908 };
909 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700910 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700911 };
912 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700913 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600914 };
915 };
916
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200917 sandbox_pmic: sandbox_pmic {
918 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700919 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200920 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200921
922 mc34708: pmic@41 {
923 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700924 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200925 };
Simon Glass7df766e2014-12-10 08:55:55 -0700926 };
927
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100928 bootcount@0 {
929 compatible = "u-boot,bootcount-rtc";
930 rtc = <&rtc_1>;
931 offset = <0x13>;
932 };
933
Michal Simek4f18f922020-05-28 11:48:55 +0200934 bootcount {
935 compatible = "u-boot,bootcount-i2c-eeprom";
936 i2c-eeprom = <&bootcount_i2c>;
937 };
938
Nandor Han88895812021-06-10 15:40:38 +0300939 bootcount_4@0 {
940 compatible = "u-boot,bootcount-syscon";
941 syscon = <&syscon0>;
942 reg = <0x0 0x04>, <0x0 0x04>;
943 reg-names = "syscon_reg", "offset";
944 };
945
946 bootcount_2@0 {
947 compatible = "u-boot,bootcount-syscon";
948 syscon = <&syscon0>;
949 reg = <0x0 0x04>, <0x0 0x02> ;
950 reg-names = "syscon_reg", "offset";
951 };
952
Marek Szyprowskiad398592021-02-18 11:33:18 +0100953 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100954 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100955 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100956 vdd-supply = <&buck2>;
957 vss-microvolts = <0>;
958 };
959
Mark Kettenis67748ee2021-10-23 16:58:02 +0200960 iommu: iommu@0 {
961 compatible = "sandbox,iommu";
962 #iommu-cells = <0>;
963 };
964
Simon Glass515dcff2020-02-06 09:55:00 -0700965 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700966 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700967 interrupt-controller;
968 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700969 };
970
Simon Glass90b6fef2016-01-18 19:52:26 -0700971 lcd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700972 bootph-all;
Simon Glass90b6fef2016-01-18 19:52:26 -0700973 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200974 pinctrl-names = "default";
975 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700976 xres = <1366>;
977 yres = <768>;
978 };
979
Simon Glassd783eb32015-07-06 12:54:34 -0600980 leds {
981 compatible = "gpio-leds";
982
983 iracibble {
984 gpios = <&gpio_a 1 0>;
985 label = "sandbox:red";
986 };
987
988 martinet {
989 gpios = <&gpio_a 2 0>;
990 label = "sandbox:green";
991 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200992
993 default_on {
994 gpios = <&gpio_a 5 0>;
995 label = "sandbox:default_on";
996 default-state = "on";
997 };
998
999 default_off {
1000 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -04001001 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +02001002 default-state = "off";
1003 };
Simon Glassd783eb32015-07-06 12:54:34 -06001004 };
1005
Paul Doelle709f0372022-07-04 09:00:25 +00001006 wdt-gpio-toggle {
Simon Glasse0f8cd22023-08-10 09:53:13 -06001007 gpios = <&gpio_a 8 0>;
Rasmus Villemoes2b673872021-08-19 11:57:05 +02001008 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001009 hw_margin_ms = <100>;
Paul Doelle709f0372022-07-04 09:00:25 +00001010 hw_algo = "toggle";
1011 always-running;
1012 };
1013
1014 wdt-gpio-level {
1015 gpios = <&gpio_a 7 0>;
1016 compatible = "linux,wdt-gpio";
1017 hw_margin_ms = <100>;
1018 hw_algo = "level";
Rasmus Villemoes2b673872021-08-19 11:57:05 +02001019 always-running;
1020 };
1021
Stephen Warren62f2c902016-05-16 17:41:37 -06001022 mbox: mbox {
1023 compatible = "sandbox,mbox";
1024 #mbox-cells = <1>;
1025 };
1026
1027 mbox-test {
1028 compatible = "sandbox,mbox-test";
1029 mboxes = <&mbox 100>, <&mbox 1>;
1030 mbox-names = "other", "test";
1031 };
1032
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001033 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001034 #address-cells = <1>;
1035 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -04001036 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001037 cpu1: cpu@1 {
1038 device_type = "cpu";
1039 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -04001040 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001041 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001042 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001043 };
Mario Sixdea5df72018-08-06 10:23:44 +02001044
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001045 cpu2: cpu@2 {
1046 device_type = "cpu";
1047 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001048 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001049 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001050 };
Mario Sixdea5df72018-08-06 10:23:44 +02001051
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +02001052 cpu3: cpu@3 {
1053 device_type = "cpu";
1054 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001055 compatible = "sandbox,cpu_sandbox";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001056 bootph-all;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +09001057 };
Mario Sixdea5df72018-08-06 10:23:44 +02001058 };
1059
Dave Gerlach75dbdfc2020-07-15 23:39:58 -05001060 chipid: chipid {
1061 compatible = "sandbox,soc";
1062 };
1063
Simon Glassc953aaf2018-12-10 10:37:34 -07001064 i2s: i2s {
1065 compatible = "sandbox,i2s";
1066 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -07001067 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -07001068 };
1069
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +02001070 nop-test_0 {
1071 compatible = "sandbox,nop_sandbox1";
1072 nop-test_1 {
1073 compatible = "sandbox,nop_sandbox2";
1074 bind = "True";
1075 };
1076 nop-test_2 {
1077 compatible = "sandbox,nop_sandbox2";
1078 bind = "False";
1079 };
1080 };
1081
Roger Quadrosb0679a72022-10-20 16:30:46 +03001082 memory-controller {
1083 compatible = "sandbox,memory";
1084 };
1085
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001086 misc-test {
Sean Anderson13652b82022-05-05 13:11:44 -04001087 #address-cells = <1>;
1088 #size-cells = <1>;
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001089 compatible = "sandbox,misc_sandbox";
Sean Anderson13652b82022-05-05 13:11:44 -04001090
1091 eth5_addr: mac-address@10 {
1092 reg = <0x10 6>;
1093 };
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001094 };
1095
Simon Glasse4fef742017-04-23 20:02:07 -06001096 mmc2 {
1097 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -06001098 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -06001099 };
1100
Simon Glassb255efc2022-04-24 23:31:24 -06001101 /* This is used for the bootdev tests */
Simon Glasse4fef742017-04-23 20:02:07 -06001102 mmc1 {
1103 compatible = "sandbox,mmc";
Simon Glassb255efc2022-04-24 23:31:24 -06001104 filename = "mmc1.img";
Simon Glasse4fef742017-04-23 20:02:07 -06001105 };
1106
Simon Glassb255efc2022-04-24 23:31:24 -06001107 /* This is used for the fastboot tests */
Sughosh Ganu77079e72022-10-21 18:16:05 +05301108 mmc0: mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -06001109 compatible = "sandbox,mmc";
1110 };
1111
Simon Glassf1eba352022-10-20 18:23:20 -06001112 /* This is used for VBE VPL tests */
1113 mmc3 {
1114 status = "disabled";
1115 compatible = "sandbox,mmc";
1116 filename = "image.bin";
1117 non-removable;
1118 };
1119
Simon Glassd2bc33ed2023-01-06 08:52:41 -06001120 /* This is used for bootstd bootmenu tests */
1121 mmc4 {
1122 status = "disabled";
1123 compatible = "sandbox,mmc";
1124 filename = "mmc4.img";
1125 };
1126
Simon Glassfff928c2023-08-24 13:55:41 -06001127 /* This is used for ChromiumOS tests */
1128 mmc5 {
1129 status = "disabled";
1130 compatible = "sandbox,mmc";
1131 filename = "mmc5.img";
1132 };
1133
Alexander Gendin038cb022023-10-09 01:24:36 +00001134 /* This is used for mbr tests */
1135 mmc6 {
1136 status = "disabled";
1137 compatible = "sandbox,mmc";
1138 filename = "mmc6.img";
1139 };
1140
Mattijs Korpershoekd77f8152024-07-10 10:40:06 +02001141 /* This is used for Android tests */
1142 mmc7 {
1143 status = "disabled";
1144 compatible = "sandbox,mmc";
1145 filename = "mmc7.img";
1146 };
1147
Simon Glass53a68b32019-02-16 20:24:50 -07001148 pch {
1149 compatible = "sandbox,pch";
1150 };
1151
Tom Rini4a3ca482020-02-11 12:41:23 -05001152 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -07001153 compatible = "sandbox,pci";
1154 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001155 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001156 #address-cells = <3>;
1157 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -06001158 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -07001159 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Mark Kettenis5dfd4ec2023-01-21 20:27:57 +01001160 iommu-map = <0x0010 &iommu 0 1>;
1161 iommu-map-mask = <0xfffffff8>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001162 pci@0,0 {
1163 compatible = "pci-generic";
1164 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001165 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001166 };
Alex Margineanf1274432019-06-07 11:24:24 +03001167 pci@1,0 {
1168 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001169 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
Simon Glass4289c262023-09-26 08:14:58 -06001170 reg = <0x02000814 0 0 0x80 0
1171 0x01000810 0 0 0xc0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001172 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +03001173 };
Simon Glass937bb472019-12-06 21:41:57 -07001174 p2sb-pci@2,0 {
1175 compatible = "sandbox,p2sb";
1176 reg = <0x02001010 0 0 0 0>;
1177 sandbox,emul = <&p2sb_emul>;
1178
1179 adder {
1180 intel,p2sb-port-id = <3>;
1181 compatible = "sandbox,adder";
1182 };
1183 };
Simon Glass8c501022019-12-06 21:41:54 -07001184 pci@1e,0 {
1185 compatible = "sandbox,pmc";
1186 reg = <0xf000 0 0 0 0>;
1187 sandbox,emul = <&pmc_emul1e>;
1188 acpi-base = <0x400>;
1189 gpe0-dwx-mask = <0xf>;
1190 gpe0-dwx-shift-base = <4>;
1191 gpe0-dw = <6 7 9>;
1192 gpe0-sts = <0x20>;
1193 gpe0-en = <0x30>;
1194 };
Simon Glass3a6eae62015-03-05 12:25:34 -07001195 pci@1f,0 {
1196 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001197 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
Simon Glass4289c262023-09-26 08:14:58 -06001198 reg = <0x0100f810 0 0 0x100 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001199 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001200 };
1201 };
1202
Simon Glassb98ba4c2019-09-25 08:56:10 -06001203 pci-emul0 {
1204 compatible = "sandbox,pci-emul-parent";
1205 swap_case_emul0_0: emul0@0,0 {
1206 compatible = "sandbox,swap-case";
1207 };
1208 swap_case_emul0_1: emul0@1,0 {
1209 compatible = "sandbox,swap-case";
1210 use-ea;
1211 };
1212 swap_case_emul0_1f: emul0@1f,0 {
1213 compatible = "sandbox,swap-case";
1214 };
Simon Glass937bb472019-12-06 21:41:57 -07001215 p2sb_emul: emul@2,0 {
1216 compatible = "sandbox,p2sb-emul";
1217 };
Simon Glass8c501022019-12-06 21:41:54 -07001218 pmc_emul1e: emul@1e,0 {
1219 compatible = "sandbox,pmc-emul";
1220 };
Simon Glassb98ba4c2019-09-25 08:56:10 -06001221 };
1222
Tom Rini4a3ca482020-02-11 12:41:23 -05001223 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -07001224 compatible = "sandbox,pci";
1225 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001226 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -07001227 #address-cells = <3>;
1228 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001229 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scullc7456a42022-04-21 16:11:09 +00001230 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001231 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -07001232 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +02001233 0x0c 0x00 0x1234 0x5678
1234 0x10 0x00 0x1234 0x5678>;
1235 pci@10,0 {
1236 reg = <0x8000 0 0 0 0>;
1237 };
Bin Meng408e5902018-08-03 01:14:41 -07001238 };
1239
Tom Rini4a3ca482020-02-11 12:41:23 -05001240 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -07001241 compatible = "sandbox,pci";
1242 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001243 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -07001244 #address-cells = <3>;
1245 #size-cells = <2>;
1246 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1247 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1248 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1249 pci@1f,0 {
1250 compatible = "pci-generic";
1251 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001252 sandbox,emul = <&swap_case_emul2_1f>;
1253 };
1254 };
1255
1256 pci-emul2 {
1257 compatible = "sandbox,pci-emul-parent";
1258 swap_case_emul2_1f: emul2@1f,0 {
1259 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001260 };
1261 };
1262
Ramon Friedc64f19b2019-04-27 11:15:23 +03001263 pci_ep: pci_ep {
1264 compatible = "sandbox,pci_ep";
1265 };
1266
Simon Glass9c433fe2017-04-23 20:10:44 -06001267 probing {
1268 compatible = "simple-bus";
1269 test1 {
1270 compatible = "denx,u-boot-probe-test";
1271 };
1272
1273 test2 {
1274 compatible = "denx,u-boot-probe-test";
1275 };
1276
1277 test3 {
1278 compatible = "denx,u-boot-probe-test";
1279 };
1280
1281 test4 {
1282 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001283 first-syscon = <&syscon0>;
1284 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001285 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001286 };
1287 };
1288
Stephen Warren92c67fa2016-07-13 13:45:31 -06001289 pwrdom: power-domain {
1290 compatible = "sandbox,power-domain";
1291 #power-domain-cells = <1>;
1292 };
1293
1294 power-domain-test {
1295 compatible = "sandbox,power-domain-test";
1296 power-domains = <&pwrdom 2>;
1297 };
1298
Simon Glass5620cf82018-10-01 12:22:40 -06001299 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001300 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001301 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001302 pinctrl-names = "default";
1303 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001304 };
1305
1306 pwm2 {
1307 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001308 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001309 };
1310
Simon Glass3d355e62015-07-06 12:54:31 -06001311 ram {
1312 compatible = "sandbox,ram";
1313 };
1314
Simon Glassd860f222015-07-06 12:54:29 -06001315 reset@0 {
1316 compatible = "sandbox,warm-reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001317 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001318 };
1319
1320 reset@1 {
1321 compatible = "sandbox,reset";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001322 bootph-some-ram;
Simon Glassd860f222015-07-06 12:54:29 -06001323 };
1324
Stephen Warren6488e642016-06-17 09:43:59 -06001325 resetc: reset-ctl {
1326 compatible = "sandbox,reset-ctl";
1327 #reset-cells = <1>;
1328 };
1329
1330 reset-ctl-test {
1331 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001332 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1333 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001334 };
1335
Sughosh Ganu23e37512019-12-28 23:58:31 +05301336 rng {
1337 compatible = "sandbox,sandbox-rng";
1338 };
1339
Nishanth Menonedf85812015-09-17 15:42:41 -05001340 rproc_1: rproc@1 {
1341 compatible = "sandbox,test-processor";
1342 remoteproc-name = "remoteproc-test-dev1";
1343 };
1344
1345 rproc_2: rproc@2 {
1346 compatible = "sandbox,test-processor";
1347 internal-memory-mapped;
1348 remoteproc-name = "remoteproc-test-dev2";
1349 };
1350
Simon Glass5620cf82018-10-01 12:22:40 -06001351 panel {
1352 compatible = "simple-panel";
1353 backlight = <&backlight 0 100>;
1354 };
1355
Simon Glass509f32e2022-09-21 16:21:47 +02001356 scsi {
1357 compatible = "sandbox,scsi";
1358 sandbox,filepath = "scsi.img";
1359 };
1360
Ramon Fried26ed32e2018-07-02 02:57:59 +03001361 smem@0 {
1362 compatible = "sandbox,smem";
1363 };
1364
Simon Glass76072ac2018-12-10 10:37:36 -07001365 sound {
1366 compatible = "sandbox,sound";
1367 cpu {
1368 sound-dai = <&i2s 0>;
1369 };
1370
1371 codec {
1372 sound-dai = <&audio 0>;
1373 };
1374 };
1375
Simon Glass25348a42014-10-13 23:42:11 -06001376 spi@0 {
1377 #address-cells = <1>;
1378 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001379 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001380 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001381 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001382 pinctrl-names = "default";
1383 pinctrl-0 = <&pinmux_spi0_pins>;
1384
Simon Glass25348a42014-10-13 23:42:11 -06001385 spi.bin@0 {
1386 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001387 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001388 spi-max-frequency = <40000000>;
1389 sandbox,filename = "spi.bin";
1390 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001391 spi.bin@1 {
1392 reg = <1>;
1393 compatible = "spansion,m25p16", "jedec,spi-nor";
1394 spi-max-frequency = <50000000>;
1395 sandbox,filename = "spi.bin";
1396 spi-cpol;
1397 spi-cpha;
1398 };
Simon Glass25348a42014-10-13 23:42:11 -06001399 };
1400
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001401 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001402 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001403 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001404 };
1405
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001406 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001407 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001408 reg = <0x20 5
1409 0x28 6
1410 0x30 7
1411 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001412 };
1413
Patrick Delaunayee010432019-03-07 09:57:13 +01001414 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001415 compatible = "simple-mfd", "syscon";
1416 reg = <0x40 5
1417 0x48 6
1418 0x50 7
1419 0x58 8>;
1420 };
1421
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301422 syscon3: syscon@3 {
1423 compatible = "simple-mfd", "syscon";
1424 reg = <0x000100 0x10>;
1425
1426 muxcontroller0: a-mux-controller {
1427 compatible = "mmio-mux";
1428 #mux-control-cells = <1>;
1429
1430 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1431 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1432 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1433 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1434 u-boot,mux-autoprobe;
1435 };
1436 };
1437
1438 muxcontroller1: emul-mux-controller {
1439 compatible = "mux-emul";
1440 #mux-control-cells = <0>;
1441 u-boot,mux-autoprobe;
1442 idle-state = <0xabcd>;
1443 };
1444
Simon Glass791a17f2020-12-16 21:20:27 -07001445 testfdtm0 {
1446 compatible = "denx,u-boot-fdtm-test";
1447 };
1448
1449 testfdtm1: testfdtm1 {
1450 compatible = "denx,u-boot-fdtm-test";
1451 };
1452
1453 testfdtm2 {
1454 compatible = "denx,u-boot-fdtm-test";
1455 };
1456
Sean Anderson79d3bba2020-09-28 10:52:23 -04001457 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001458 compatible = "sandbox,timer";
1459 clock-frequency = <1000000>;
1460 };
1461
Sean Anderson79d3bba2020-09-28 10:52:23 -04001462 timer@1 {
1463 compatible = "sandbox,timer";
1464 sandbox,timebase-frequency-fallback;
1465 };
1466
Miquel Raynal80938c12018-05-15 11:57:27 +02001467 tpm2 {
1468 compatible = "sandbox,tpm2";
Eddie James1a55a7a2023-10-24 10:43:51 -05001469 memory-region = <&event_log>;
Miquel Raynal80938c12018-05-15 11:57:27 +02001470 };
1471
Simon Glasseef107e2023-02-21 06:24:51 -07001472 tpm {
1473 compatible = "google,sandbox-tpm";
1474 };
1475
Simon Glass5b968632015-05-22 15:42:15 -06001476 uart0: serial {
1477 compatible = "sandbox,serial";
Simon Glassd3a98cb2023-02-13 08:56:33 -07001478 bootph-all;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001479 pinctrl-names = "default";
1480 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001481 };
1482
Simon Glass31680482015-03-25 12:23:05 -06001483 usb_0: usb@0 {
1484 compatible = "sandbox,usb";
1485 status = "disabled";
1486 hub {
1487 compatible = "sandbox,usb-hub";
1488 #address-cells = <1>;
1489 #size-cells = <0>;
1490 flash-stick {
1491 reg = <0>;
1492 compatible = "sandbox,usb-flash";
1493 };
1494 };
1495 };
1496
1497 usb_1: usb@1 {
1498 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001499 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001500 hub {
1501 compatible = "usb-hub";
1502 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001503 #address-cells = <1>;
1504 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001505 hub-emul {
1506 compatible = "sandbox,usb-hub";
1507 #address-cells = <1>;
1508 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001509 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001510 reg = <0>;
1511 compatible = "sandbox,usb-flash";
1512 sandbox,filepath = "testflash.bin";
1513 };
1514
Simon Glass4700fe52015-11-08 23:48:01 -07001515 flash-stick@1 {
1516 reg = <1>;
1517 compatible = "sandbox,usb-flash";
Simon Glass64c63252024-11-07 14:31:49 -07001518 sandbox,filepath = "flash1.img";
Simon Glass4700fe52015-11-08 23:48:01 -07001519 };
1520
1521 flash-stick@2 {
1522 reg = <2>;
1523 compatible = "sandbox,usb-flash";
1524 sandbox,filepath = "testflash2.bin";
1525 };
1526
Simon Glassc0ccc722015-11-08 23:48:08 -07001527 keyb@3 {
1528 reg = <3>;
1529 compatible = "sandbox,usb-keyb";
1530 };
1531
Simon Glass31680482015-03-25 12:23:05 -06001532 };
Michael Walle7c961322020-06-02 01:47:07 +02001533
1534 usbstor@1 {
1535 reg = <1>;
1536 };
1537 usbstor@3 {
1538 reg = <3>;
1539 };
Simon Glass31680482015-03-25 12:23:05 -06001540 };
1541 };
1542
1543 usb_2: usb@2 {
1544 compatible = "sandbox,usb";
1545 status = "disabled";
1546 };
1547
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001548 spmi: spmi@0 {
1549 compatible = "sandbox,spmi";
1550 #address-cells = <0x1>;
1551 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001552 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001553 pm8916@0 {
1554 compatible = "qcom,spmi-pmic";
1555 reg = <0x0 0x1>;
1556 #address-cells = <0x1>;
1557 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001558 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001559
1560 spmi_gpios: gpios@c000 {
1561 compatible = "qcom,pm8916-gpio";
1562 reg = <0xc000 0x400>;
Caleb Connolly1edc45f2024-01-08 15:30:51 +00001563 gpio-ranges = <&spmi_gpios 0 0 4>;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001564 gpio-controller;
1565 gpio-count = <4>;
1566 #gpio-cells = <2>;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001567 };
1568 };
1569 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001570
1571 wdt0: wdt@0 {
1572 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001573 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001574 };
Rob Clarka471b672018-01-10 11:33:30 +01001575
Mario Six95922152018-08-09 14:51:19 +02001576 axi: axi@0 {
1577 compatible = "sandbox,axi";
1578 #address-cells = <0x1>;
1579 #size-cells = <0x1>;
1580 store@0 {
1581 compatible = "sandbox,sandbox_store";
1582 reg = <0x0 0x400>;
1583 };
1584 };
1585
Rob Clarka471b672018-01-10 11:33:30 +01001586 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001587 #address-cells = <1>;
1588 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001589 setting = "sunrise ohoka";
1590 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001591 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001592 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Algapally Santosh Sagardf178992023-09-21 16:50:43 +05301593 stdout-path = "serial0:115200n8";
Rob Clarka471b672018-01-10 11:33:30 +01001594 chosen-test {
1595 compatible = "denx,u-boot-fdt-test";
1596 reg = <9 1>;
1597 };
1598 };
Mario Six35616ef2018-03-12 14:53:33 +01001599
1600 translation-test@8000 {
1601 compatible = "simple-bus";
1602 reg = <0x8000 0x4000>;
1603
1604 #address-cells = <0x2>;
1605 #size-cells = <0x1>;
1606
1607 ranges = <0 0x0 0x8000 0x1000
1608 1 0x100 0x9000 0x1000
1609 2 0x200 0xA000 0x1000
1610 3 0x300 0xB000 0x1000
1611 >;
1612
Fabien Dessenne22236e02019-05-31 15:11:30 +02001613 dma-ranges = <0 0x000 0x10000000 0x1000
1614 1 0x100 0x20000000 0x1000
1615 >;
1616
Mario Six35616ef2018-03-12 14:53:33 +01001617 dev@0,0 {
1618 compatible = "denx,u-boot-fdt-dummy";
1619 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +01001620 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001621 };
1622
1623 dev@1,100 {
1624 compatible = "denx,u-boot-fdt-dummy";
1625 reg = <1 0x100 0x1000>;
1626
1627 };
1628
1629 dev@2,200 {
1630 compatible = "denx,u-boot-fdt-dummy";
1631 reg = <2 0x200 0x1000>;
1632 };
1633
1634
1635 noxlatebus@3,300 {
1636 compatible = "simple-bus";
1637 reg = <3 0x300 0x1000>;
1638
1639 #address-cells = <0x1>;
1640 #size-cells = <0x0>;
1641
1642 dev@42 {
1643 compatible = "denx,u-boot-fdt-dummy";
1644 reg = <0x42>;
1645 };
1646 };
1647 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001648
Dzmitry Sankouski54f4c832023-01-22 18:21:23 +03001649 ofnode-foreach {
1650 compatible = "foreach";
1651
1652 first {
1653 prop1 = <1>;
1654 prop2 = <2>;
1655 };
1656
1657 second {
1658 prop1 = <1>;
1659 prop2 = <2>;
1660 };
1661 };
1662
Mario Six02ad6fb2018-09-27 09:19:31 +02001663 osd {
1664 compatible = "sandbox,sandbox_osd";
1665 };
Tom Rinib93eea72018-09-30 18:16:51 -04001666
Jens Wiklander86afaa62018-09-25 16:40:16 +02001667 sandbox_tee {
1668 compatible = "sandbox,tee";
1669 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001670
1671 sandbox_virtio1 {
1672 compatible = "sandbox,virtio1";
Simon Glass8de5a542023-01-17 10:47:51 -07001673 virtio-type = <4>; /* rng */
Bin Meng1bb290d2018-10-15 02:21:26 -07001674 };
1675
1676 sandbox_virtio2 {
1677 compatible = "sandbox,virtio2";
1678 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001679
Simon Glass8de5a542023-01-17 10:47:51 -07001680 sandbox-virtio-blk {
1681 compatible = "sandbox,virtio1";
1682 virtio-type = <2>; /* block */
1683 };
1684
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001685 sandbox_scmi {
1686 compatible = "sandbox,scmi-devices";
AKASHI Takahiro535a7bd2023-10-16 14:39:45 +09001687 power-domains = <&pwrdom_scmi 2>;
Etienne Carrierebf1f1322022-02-21 09:22:41 +01001688 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere09665cb2022-02-21 09:22:39 +01001689 resets = <&reset_scmi 3>;
1690 regul0-supply = <&regul0_scmi>;
1691 regul1-supply = <&regul1_scmi>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001692 };
1693
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001694 pinctrl {
1695 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001696
Sean Anderson3438e3b2020-09-14 11:01:57 -04001697 pinctrl-names = "default", "alternate";
1698 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1699 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001700
Sean Anderson3438e3b2020-09-14 11:01:57 -04001701 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001702 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001703 pins = "P5";
1704 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001705 bias-pull-up;
1706 input-disable;
1707 };
1708 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001709 pins = "P6";
1710 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001711 output-high;
1712 drive-open-drain;
1713 };
1714 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001715 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001716 bias-pull-down;
1717 input-enable;
1718 };
1719 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001720 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001721 bias-disable;
1722 };
1723 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001724
1725 pinctrl_i2c: i2c {
1726 groups {
1727 groups = "I2C_UART";
1728 function = "I2C";
1729 };
1730
1731 pins {
1732 pins = "P0", "P1";
1733 drive-open-drain;
1734 };
1735 };
1736
1737 pinctrl_i2s: i2s {
1738 groups = "SPI_I2S";
1739 function = "I2S";
1740 };
1741
1742 pinctrl_spi: spi {
1743 groups = "SPI_I2S";
1744 function = "SPI";
1745
1746 cs {
1747 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1748 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1749 };
1750 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001751 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001752
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001753 pinctrl-single-no-width {
1754 compatible = "pinctrl-single";
1755 reg = <0x0000 0x238>;
1756 #pinctrl-cells = <1>;
1757 pinctrl-single,function-mask = <0x7f>;
1758 };
1759
1760 pinctrl-single-pins {
1761 compatible = "pinctrl-single";
1762 reg = <0x0000 0x238>;
1763 #pinctrl-cells = <1>;
1764 pinctrl-single,register-width = <32>;
1765 pinctrl-single,function-mask = <0x7f>;
1766
1767 pinmux_pwm_pins: pinmux_pwm_pins {
1768 pinctrl-single,pins = < 0x48 0x06 >;
1769 };
1770
1771 pinmux_spi0_pins: pinmux_spi0_pins {
1772 pinctrl-single,pins = <
1773 0x190 0x0c
1774 0x194 0x0c
1775 0x198 0x23
1776 0x19c 0x0c
1777 >;
1778 };
1779
1780 pinmux_uart0_pins: pinmux_uart0_pins {
1781 pinctrl-single,pins = <
1782 0x70 0x30
1783 0x74 0x00
1784 >;
1785 };
1786 };
1787
1788 pinctrl-single-bits {
1789 compatible = "pinctrl-single";
1790 reg = <0x0000 0x50>;
1791 #pinctrl-cells = <2>;
1792 pinctrl-single,bit-per-mux;
1793 pinctrl-single,register-width = <32>;
1794 pinctrl-single,function-mask = <0xf>;
1795
1796 pinmux_i2c0_pins: pinmux_i2c0_pins {
1797 pinctrl-single,bits = <
1798 0x10 0x00002200 0x0000ff00
1799 >;
1800 };
1801
1802 pinmux_lcd_pins: pinmux_lcd_pins {
1803 pinctrl-single,bits = <
1804 0x40 0x22222200 0xffffff00
1805 0x44 0x22222222 0xffffffff
1806 0x48 0x00000022 0x000000ff
1807 0x48 0x02000000 0x0f000000
1808 0x4c 0x02000022 0x0f0000ff
1809 >;
1810 };
1811 };
1812
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001813 hwspinlock@0 {
1814 compatible = "sandbox,hwspinlock";
1815 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001816
1817 dma: dma {
1818 compatible = "sandbox,dma";
1819 #dma-cells = <1>;
1820
1821 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1822 dma-names = "m2m", "tx0", "rx0";
1823 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001824
Alex Marginean0649be52019-07-12 10:13:53 +03001825 /*
1826 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1827 * end of the test. If parent mdio is removed first, clean-up of the
1828 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1829 * active at the end of the test. That it turn doesn't allow the mdio
1830 * class to be destroyed, triggering an error.
1831 */
1832 mdio-mux-test {
1833 compatible = "sandbox,mdio-mux";
1834 #address-cells = <1>;
1835 #size-cells = <0>;
1836 mdio-parent-bus = <&mdio>;
1837
1838 mdio-ch-test@0 {
1839 reg = <0>;
1840 };
1841 mdio-ch-test@1 {
1842 reg = <1>;
1843 };
1844 };
1845
1846 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001847 compatible = "sandbox,mdio";
Marek Behúnf4f1ddc2022-04-07 00:32:57 +02001848 #address-cells = <1>;
1849 #size-cells = <0>;
1850
1851 ethphy1: ethernet-phy@1 {
1852 reg = <1>;
1853 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001854 };
Sean Andersonb7860542020-06-24 06:41:12 -04001855
1856 pm-bus-test {
1857 compatible = "simple-pm-bus";
1858 clocks = <&clk_sandbox 4>;
1859 power-domains = <&pwrdom 1>;
1860 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001861
1862 resetc2: syscon-reset {
1863 compatible = "syscon-reset";
1864 #reset-cells = <1>;
1865 regmap = <&syscon0>;
1866 offset = <1>;
1867 mask = <0x27FFFFFF>;
1868 assert-high = <0>;
1869 };
1870
1871 syscon-reset-test {
1872 compatible = "sandbox,misc_sandbox";
1873 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1874 reset-names = "valid", "no_mask", "out_of_range";
1875 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301876
Simon Glass458b66a2020-11-05 06:32:05 -07001877 sysinfo {
1878 compatible = "sandbox,sysinfo-sandbox";
1879 };
1880
Sean Anderson1c830672021-04-20 10:50:58 -04001881 sysinfo-gpio {
1882 compatible = "gpio-sysinfo";
1883 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1884 revisions = <19>, <5>;
1885 names = "rev_a", "foo";
1886 };
1887
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301888 some_regmapped-bus {
1889 #address-cells = <0x1>;
1890 #size-cells = <0x1>;
1891
1892 ranges = <0x0 0x0 0x10>;
1893 compatible = "simple-bus";
1894
1895 regmap-test_0 {
1896 reg = <0 0x10>;
1897 compatible = "sandbox,regmap_test";
1898 };
1899 };
Robert Marko9cf87122022-09-06 13:30:35 +02001900
1901 thermal {
1902 compatible = "sandbox,thermal";
1903 };
Sughosh Ganu77079e72022-10-21 18:16:05 +05301904
1905 fwu-mdata {
1906 compatible = "u-boot,fwu-mdata-gpt";
1907 fwu-mdata-store = <&mmc0>;
1908 };
Abdellatif El Khlifi6b005872023-04-17 10:11:55 +01001909
1910 nvmxip-qspi1@08000000 {
1911 compatible = "nvmxip,qspi";
1912 reg = <0x08000000 0x00200000>;
1913 lba_shift = <9>;
1914 lba = <4096>;
1915 };
1916
1917 nvmxip-qspi2@08200000 {
1918 compatible = "nvmxip,qspi";
1919 reg = <0x08200000 0x00100000>;
1920 lba_shift = <9>;
1921 lba = <2048>;
1922 };
Svyatoslav Ryhel669f5c82023-04-25 10:57:21 +03001923
1924 extcon {
1925 compatible = "sandbox,extcon";
1926 };
Abdellatif El Khlifi4970d5b2023-08-04 14:33:41 +01001927
1928 arm-ffa-emul {
1929 compatible = "sandbox,arm-ffa-emul";
1930
1931 sandbox-arm-ffa {
1932 compatible = "sandbox,arm-ffa";
1933 };
1934 };
Sean Anderson326422b2023-11-04 16:37:52 -04001935
1936 nand-controller {
1937 #address-cells = <1>;
1938 #size-cells = <0>;
1939 compatible = "sandbox,nand";
1940
1941 nand@0 {
1942 reg = <0>;
1943 nand-ecc-mode = "soft";
1944 sandbox,id = [00 e3];
1945 sandbox,erasesize = <(8 * 1024)>;
1946 sandbox,oobsize = <16>;
1947 sandbox,pagesize = <512>;
1948 sandbox,pages = <0x2000>;
1949 sandbox,err-count = <1>;
1950 sandbox,err-step-size = <512>;
1951 };
1952
1953 /* MT29F64G08AKABA */
1954 nand@1 {
1955 reg = <1>;
1956 nand-ecc-mode = "soft_bch";
1957 sandbox,id = [2C 48 00 26 89 00 00 00];
1958 sandbox,onfi = [
1959 4f 4e 46 49 0e 00 5a 00
1960 ff 01 00 00 00 00 03 00
1961 00 00 00 00 00 00 00 00
1962 00 00 00 00 00 00 00 00
1963 4d 49 43 52 4f 4e 20 20
1964 20 20 20 20 4d 54 32 39
1965 46 36 34 47 30 38 41 4b
1966 41 42 41 43 35 20 20 20
1967 2c 00 00 00 00 00 00 00
1968 00 00 00 00 00 00 00 00
1969 00 10 00 00 e0 00 00 02
1970 00 00 1c 00 80 00 00 00
1971 00 10 00 00 02 23 01 50
1972 00 01 05 01 00 00 04 00
1973 04 01 1e 00 00 00 00 00
1974 00 00 00 00 00 00 00 00
1975 0e 1f 00 1f 00 f4 01 ac
1976 0d 19 00 c8 00 00 00 00
1977 00 00 00 00 00 00 0a 07
1978 19 00 00 00 00 00 00 00
1979 00 00 00 00 01 00 01 00
1980 00 00 04 10 01 81 04 02
1981 02 01 1e 90 00 00 00 00
1982 00 00 00 00 00 00 00 00
1983 00 00 00 00 00 00 00 00
1984 00 00 00 00 00 00 00 00
1985 00 00 00 00 00 00 00 00
1986 00 00 00 00 00 00 00 00
1987 00 00 00 00 00 00 00 00
1988 00 00 00 00 00 00 00 00
1989 00 00 00 00 00 00 00 00
1990 00 00 00 00 00 03 20 7d
1991 ];
1992 sandbox,erasesize = <(512 * 1024)>;
1993 sandbox,oobsize = <224>;
1994 sandbox,pagesize = <4096>;
1995 sandbox,pages = <0x200000>;
1996 sandbox,err-count = <3>;
1997 sandbox,err-step-size = <512>;
1998 };
1999 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07002000};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02002001
2002#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01002003#include "cros-ec-keyboard.dtsi"
Simon Glass5e135d32022-10-20 18:23:15 -06002004
2005#ifdef CONFIG_SANDBOX_VPL
2006#include "sandbox_vpl.dtsi"
2007#endif
Simon Glass61300722023-06-01 10:23:01 -06002008
Sughosh Ganu05137922024-03-27 16:19:00 +05302009#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
2010#include "sandbox_capsule.dtsi"
2011#endif
2012
Simon Glass61300722023-06-01 10:23:01 -06002013#include "cedit.dtsi"