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Achin Gupta7aea9082014-02-01 07:51:28 +00001/*
Govindraj Raja24d3a4e2023-12-21 13:57:49 -06002 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
Varun Wadekarcc238bb2022-09-13 12:38:47 +01003 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved.
Achin Gupta7aea9082014-02-01 07:51:28 +00004 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta7aea9082014-02-01 07:51:28 +00006 */
7
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <assert.h>
9#include <stdbool.h>
10#include <string.h>
11
12#include <platform_def.h>
13
Achin Gupta27b895e2014-05-04 18:38:28 +010014#include <arch.h>
Achin Gupta7aea9082014-02-01 07:51:28 +000015#include <arch_helpers.h>
Soby Mathew830f0ad2019-07-12 09:23:38 +010016#include <arch_features.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <bl31/interrupt_mgmt.h>
18#include <common/bl_common.h>
Claus Pedersen785e66c2022-09-12 22:42:58 +000019#include <common/debug.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010020#include <context.h>
Zelalem Awekef92c0cb2022-01-31 16:59:42 -060021#include <drivers/arm/gicv3.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000022#include <lib/el3_runtime/context_mgmt.h>
Elizabeth Ho4fc00d22023-07-18 14:10:25 +010023#include <lib/el3_runtime/cpu_data.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000024#include <lib/el3_runtime/pubsub_events.h>
25#include <lib/extensions/amu.h>
johpow0181865962022-01-28 17:06:20 -060026#include <lib/extensions/brbe.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000027#include <lib/extensions/mpam.h>
Boyan Karatotev05504ba2023-02-15 13:21:50 +000028#include <lib/extensions/pmuv3.h>
johpow019baade32021-07-08 14:14:00 -050029#include <lib/extensions/sme.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000030#include <lib/extensions/spe.h>
31#include <lib/extensions/sve.h>
Manish V Badarkhef356f7e2021-06-29 11:44:20 +010032#include <lib/extensions/sys_reg_trace.h>
Manish V Badarkhe20df29c2021-07-02 09:10:56 +010033#include <lib/extensions/trbe.h>
Manish V Badarkhe51a97112021-07-08 09:33:18 +010034#include <lib/extensions/trf.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000035#include <lib/utils.h>
Achin Gupta7aea9082014-02-01 07:51:28 +000036
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +010037#if ENABLE_FEAT_TWED
38/* Make sure delay value fits within the range(0-15) */
39CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check);
40#endif /* ENABLE_FEAT_TWED */
Achin Gupta7aea9082014-02-01 07:51:28 +000041
Elizabeth Ho4fc00d22023-07-18 14:10:25 +010042per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM];
43static bool has_secure_perworld_init;
44
Boyan Karatotev36cebf92023-03-08 11:56:49 +000045static void manage_extensions_nonsecure(cpu_context_t *ctx);
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +010046static void manage_extensions_secure(cpu_context_t *ctx);
Elizabeth Ho4fc00d22023-07-18 14:10:25 +010047static void manage_extensions_secure_per_world(void);
Zelalem Aweke20126002022-04-08 16:48:05 -050048
49static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep)
50{
51 u_register_t sctlr_elx, actlr_elx;
52
53 /*
54 * Initialise SCTLR_EL1 to the reset value corresponding to the target
55 * execution state setting all fields rather than relying on the hw.
56 * Some fields have architecturally UNKNOWN reset values and these are
57 * set to zero.
58 *
59 * SCTLR.EE: Endianness is taken from the entrypoint attributes.
60 *
61 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as
62 * required by PSCI specification)
63 */
64 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL;
65 if (GET_RW(ep->spsr) == MODE_RW_64) {
66 sctlr_elx |= SCTLR_EL1_RES1;
67 } else {
68 /*
69 * If the target execution state is AArch32 then the following
70 * fields need to be set.
71 *
72 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE
73 * instructions are not trapped to EL1.
74 *
75 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI
76 * instructions are not trapped to EL1.
77 *
78 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the
79 * CP15DMB, CP15DSB, and CP15ISB instructions.
80 */
81 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT
82 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT;
83 }
84
85#if ERRATA_A75_764081
86 /*
87 * If workaround of errata 764081 for Cortex-A75 is used then set
88 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier.
89 */
90 sctlr_elx |= SCTLR_IESB_BIT;
91#endif
92 /* Store the initialised SCTLR_EL1 value in the cpu_context */
93 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx);
94
95 /*
96 * Base the context ACTLR_EL1 on the current value, as it is
97 * implementation defined. The context restore process will write
98 * the value from the context to the actual register and can cause
99 * problems for processor cores that don't expect certain bits to
100 * be zero.
101 */
102 actlr_elx = read_actlr_el1();
103 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx));
104}
105
Zelalem Aweke42401112022-01-05 17:12:24 -0600106/******************************************************************************
107 * This function performs initializations that are specific to SECURE state
108 * and updates the cpu context specified by 'ctx'.
109 *****************************************************************************/
110static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep)
Achin Gupta7aea9082014-02-01 07:51:28 +0000111{
Zelalem Aweke42401112022-01-05 17:12:24 -0600112 u_register_t scr_el3;
113 el3_state_t *state;
114
115 state = get_el3state_ctx(ctx);
116 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
117
118#if defined(IMAGE_BL31) && !defined(SPD_spmd)
Achin Gupta7aea9082014-02-01 07:51:28 +0000119 /*
Zelalem Aweke42401112022-01-05 17:12:24 -0600120 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
121 * indicated by the interrupt routing model for BL31.
122 */
123 scr_el3 |= get_scr_el3_from_routing_model(SECURE);
124#endif
125
Govindraj Raja73e1d802024-02-28 14:37:09 -0600126 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */
127 if (is_feat_mte2_supported()) {
Zelalem Aweke42401112022-01-05 17:12:24 -0600128 scr_el3 |= SCR_ATA_BIT;
129 }
Zelalem Aweke42401112022-01-05 17:12:24 -0600130
Zelalem Aweke42401112022-01-05 17:12:24 -0600131 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
132
Zelalem Aweke20126002022-04-08 16:48:05 -0500133 /*
134 * Initialize EL1 context registers unless SPMC is running
135 * at S-EL2.
136 */
137#if !SPMD_SPM_AT_SEL2
138 setup_el1_context(ctx, ep);
139#endif
140
Zelalem Aweke42401112022-01-05 17:12:24 -0600141 manage_extensions_secure(ctx);
Elizabeth Ho4fc00d22023-07-18 14:10:25 +0100142
143 /**
144 * manage_extensions_secure_per_world api has to be executed once,
145 * as the registers getting initialised, maintain constant value across
146 * all the cpus for the secure world.
147 * Henceforth, this check ensures that the registers are initialised once
148 * and avoids re-initialization from multiple cores.
149 */
150 if (!has_secure_perworld_init) {
151 manage_extensions_secure_per_world();
152 }
153
Achin Gupta7aea9082014-02-01 07:51:28 +0000154}
155
Zelalem Aweke42401112022-01-05 17:12:24 -0600156#if ENABLE_RME
157/******************************************************************************
158 * This function performs initializations that are specific to REALM state
159 * and updates the cpu context specified by 'ctx'.
160 *****************************************************************************/
161static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep)
162{
163 u_register_t scr_el3;
164 el3_state_t *state;
165
166 state = get_el3state_ctx(ctx);
167 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
168
Maksims Svecovs1e25c5b2023-02-02 16:10:22 +0000169 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT;
170
Sona Mathew3b84c962023-10-25 16:48:19 -0500171 /* CSV2 version 2 and above */
Andre Przywara902c9022022-11-17 17:30:43 +0000172 if (is_feat_csv2_2_supported()) {
173 /* Enable access to the SCXTNUM_ELx registers. */
174 scr_el3 |= SCR_EnSCXT_BIT;
175 }
Zelalem Aweke42401112022-01-05 17:12:24 -0600176
177 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
178}
179#endif /* ENABLE_RME */
180
181/******************************************************************************
182 * This function performs initializations that are specific to NON-SECURE state
183 * and updates the cpu context specified by 'ctx'.
184 *****************************************************************************/
185static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep)
186{
187 u_register_t scr_el3;
188 el3_state_t *state;
189
190 state = get_el3state_ctx(ctx);
191 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
192
193 /* SCR_NS: Set the NS bit */
194 scr_el3 |= SCR_NS_BIT;
195
Govindraj Raja73e1d802024-02-28 14:37:09 -0600196 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */
197 if (is_feat_mte2_supported()) {
198 scr_el3 |= SCR_ATA_BIT;
199 }
Boyan Karatotev8ae58f02023-04-20 11:00:50 +0100200
Zelalem Aweke42401112022-01-05 17:12:24 -0600201#if !CTX_INCLUDE_PAUTH_REGS
202 /*
Boyan Karatotev8ae58f02023-04-20 11:00:50 +0100203 * Pointer Authentication feature, if present, is always enabled by default
204 * for Non secure lower exception levels. We do not have an explicit
205 * flag to set it.
206 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower
207 * exception levels of secure and realm worlds.
Zelalem Aweke42401112022-01-05 17:12:24 -0600208 *
Boyan Karatotev8ae58f02023-04-20 11:00:50 +0100209 * To prevent the leakage between the worlds during world switch,
210 * we enable it only for the non-secure world.
211 *
212 * If the Secure/realm world wants to use pointer authentication,
213 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case
214 * it will be enabled globally for all the contexts.
215 *
216 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs
217 * other than EL3
218 *
219 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other
220 * than EL3
Zelalem Aweke42401112022-01-05 17:12:24 -0600221 */
222 scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
Zelalem Aweke42401112022-01-05 17:12:24 -0600223
Boyan Karatotev8ae58f02023-04-20 11:00:50 +0100224#endif /* CTX_INCLUDE_PAUTH_REGS */
Zelalem Aweke42401112022-01-05 17:12:24 -0600225
Manish Pandey0e3379d2022-10-10 11:43:08 +0100226#if HANDLE_EA_EL3_FIRST_NS
227 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */
228 scr_el3 |= SCR_EA_BIT;
229#endif
230
Manish Pandey7c6fcb42022-09-27 14:30:34 +0100231#if RAS_TRAP_NS_ERR_REC_ACCESS
232 /*
233 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR
234 * and RAS ERX registers from EL1 and EL2(from any security state)
235 * are trapped to EL3.
236 * Set here to trap only for NS EL1/EL2
237 *
238 */
239 scr_el3 |= SCR_TERR_BIT;
240#endif
241
Sona Mathew3b84c962023-10-25 16:48:19 -0500242 /* CSV2 version 2 and above */
Andre Przywara902c9022022-11-17 17:30:43 +0000243 if (is_feat_csv2_2_supported()) {
244 /* Enable access to the SCXTNUM_ELx registers. */
245 scr_el3 |= SCR_EnSCXT_BIT;
246 }
Maksims Svecovs1e25c5b2023-02-02 16:10:22 +0000247
Zelalem Aweke42401112022-01-05 17:12:24 -0600248#ifdef IMAGE_BL31
249 /*
250 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
251 * indicated by the interrupt routing model for BL31.
252 */
253 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE);
254#endif
255 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
Zelalem Awekef92c0cb2022-01-31 16:59:42 -0600256
Zelalem Aweke20126002022-04-08 16:48:05 -0500257 /* Initialize EL1 context registers */
258 setup_el1_context(ctx, ep);
259
Zelalem Awekef92c0cb2022-01-31 16:59:42 -0600260 /* Initialize EL2 context registers */
261#if CTX_INCLUDE_EL2_REGS
262
263 /*
264 * Initialize SCTLR_EL2 context register using Endianness value
265 * taken from the entrypoint attribute.
266 */
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +0000267 u_register_t sctlr_el2_val = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL;
268 sctlr_el2_val |= SCTLR_EL2_RES1;
269 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, sctlr_el2_val);
270
Zelalem Awekef92c0cb2022-01-31 16:59:42 -0600271
Juan Pablo Conde72e0da12023-02-22 10:09:52 -0600272 if (is_feat_hcx_supported()) {
273 /*
274 * Initialize register HCRX_EL2 with its init value.
275 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a
276 * chance that this can lead to unexpected behavior in lower
277 * ELs that have not been updated since the introduction of
278 * this feature if not properly initialized, especially when
279 * it comes to those bits that enable/disable traps.
280 */
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +0000281 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2,
Juan Pablo Conde72e0da12023-02-22 10:09:52 -0600282 HCRX_EL2_INIT_VAL);
283 }
Juan Pablo Condef7252982023-07-10 16:00:41 -0500284
285 if (is_feat_fgt_supported()) {
286 /*
287 * Initialize HFG*_EL2 registers with a default value so legacy
288 * systems unaware of FEAT_FGT do not get trapped due to their lack
289 * of initialization for this feature.
290 */
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +0000291 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2,
Juan Pablo Condef7252982023-07-10 16:00:41 -0500292 HFGITR_EL2_INIT_VAL);
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +0000293 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2,
Juan Pablo Condef7252982023-07-10 16:00:41 -0500294 HFGRTR_EL2_INIT_VAL);
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +0000295 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2,
Juan Pablo Condef7252982023-07-10 16:00:41 -0500296 HFGWTR_EL2_INIT_VAL);
297 }
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +0000298
Zelalem Awekef92c0cb2022-01-31 16:59:42 -0600299#endif /* CTX_INCLUDE_EL2_REGS */
Boyan Karatotev36cebf92023-03-08 11:56:49 +0000300
301 manage_extensions_nonsecure(ctx);
Zelalem Aweke42401112022-01-05 17:12:24 -0600302}
303
Achin Gupta7aea9082014-02-01 07:51:28 +0000304/*******************************************************************************
Zelalem Aweke42401112022-01-05 17:12:24 -0600305 * The following function performs initialization of the cpu_context 'ctx'
306 * for first use that is common to all security states, and sets the
307 * initial entrypoint state as specified by the entry_point_info structure.
Andrew Thoelke4e126072014-06-04 21:10:52 +0100308 *
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000309 * The EE and ST attributes are used to configure the endianness and secure
Soby Mathewb0082d22015-04-09 13:40:55 +0100310 * timer availability for the new execution context.
Andrew Thoelke4e126072014-06-04 21:10:52 +0100311 ******************************************************************************/
Zelalem Aweke42401112022-01-05 17:12:24 -0600312static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep)
Andrew Thoelke4e126072014-06-04 21:10:52 +0100313{
Louis Mayencourt1c819c32020-01-24 13:30:28 +0000314 u_register_t scr_el3;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100315 el3_state_t *state;
316 gp_regs_t *gp_regs;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100317
Boyan Karatotev8ae58f02023-04-20 11:00:50 +0100318 state = get_el3state_ctx(ctx);
319
Andrew Thoelke4e126072014-06-04 21:10:52 +0100320 /* Clear any residual register values from the context */
Douglas Raillarda8954fc2017-01-26 15:54:44 +0000321 zeromem(ctx, sizeof(*ctx));
Andrew Thoelke4e126072014-06-04 21:10:52 +0100322
323 /*
Boyan Karatotevef25db32023-05-23 12:04:00 +0100324 * The lower-EL context is zeroed so that no stale values leak to a world.
325 * It is assumed that an all-zero lower-EL context is good enough for it
326 * to boot correctly. However, there are very few registers where this
327 * is not true and some values need to be recreated.
328 */
329#if CTX_INCLUDE_EL2_REGS
330 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx);
331
332 /*
333 * These bits are set in the gicv3 driver. Losing them (especially the
334 * SRE bit) is problematic for all worlds. Henceforth recreate them.
335 */
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +0000336 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT |
Boyan Karatotevef25db32023-05-23 12:04:00 +0100337 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT;
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +0000338 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val);
Boyan Karatotevef25db32023-05-23 12:04:00 +0100339#endif /* CTX_INCLUDE_EL2_REGS */
340
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +0100341 /* Start with a clean SCR_EL3 copy as all relevant values are set */
342 scr_el3 = SCR_RESET_VAL;
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500343
David Cunadofee86532017-04-13 22:38:29 +0100344 /*
Boyan Karatotev8ae58f02023-04-20 11:00:50 +0100345 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at
346 * EL2, EL1 and EL0 are not trapped to EL3.
347 *
348 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at
349 * EL2, EL1 and EL0 are not trapped to EL3.
350 *
351 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from
352 * both Security states and both Execution states.
353 *
354 * SCR_EL3.SIF: Set to one to disable secure instruction execution from
355 * Non-secure memory.
356 */
357 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT);
358
359 scr_el3 |= SCR_SIF_BIT;
360
361 /*
David Cunadofee86532017-04-13 22:38:29 +0100362 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next
363 * Exception level as specified by SPSR.
364 */
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500365 if (GET_RW(ep->spsr) == MODE_RW_64) {
Andrew Thoelke4e126072014-06-04 21:10:52 +0100366 scr_el3 |= SCR_RW_BIT;
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500367 }
Zelalem Aweke42401112022-01-05 17:12:24 -0600368
David Cunadofee86532017-04-13 22:38:29 +0100369 /*
370 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical
Zelalem Aweke20126002022-04-08 16:48:05 -0500371 * Secure timer registers to EL3, from AArch64 state only, if specified
372 * by the entrypoint attributes. If SEL2 is present and enabled, the ST
373 * bit always behaves as 1 (i.e. secure physical timer register access
374 * is not trapped)
David Cunadofee86532017-04-13 22:38:29 +0100375 */
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500376 if (EP_GET_ST(ep->h.attr) != 0U) {
Andrew Thoelke4e126072014-06-04 21:10:52 +0100377 scr_el3 |= SCR_ST_BIT;
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500378 }
Andrew Thoelke4e126072014-06-04 21:10:52 +0100379
johpow01f91e59f2021-08-04 19:38:18 -0500380 /*
381 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting
382 * SCR_EL3.HXEn.
383 */
Andre Przywara1d8795e2022-11-15 11:45:19 +0000384 if (is_feat_hcx_supported()) {
385 scr_el3 |= SCR_HXEn_BIT;
386 }
johpow01f91e59f2021-08-04 19:38:18 -0500387
Juan Pablo Conde42305f22022-07-12 16:40:29 -0400388 /*
389 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS
390 * registers are trapped to EL3.
391 */
392#if ENABLE_FEAT_RNG_TRAP
393 scr_el3 |= SCR_TRNDR_BIT;
394#endif
395
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000396#if FAULT_INJECTION_SUPPORT
397 /* Enable fault injection from lower ELs */
398 scr_el3 |= SCR_FIEN_BIT;
399#endif
400
Boyan Karatotev8ae58f02023-04-20 11:00:50 +0100401#if CTX_INCLUDE_PAUTH_REGS
402 /*
403 * Enable Pointer Authentication globally for all the worlds.
404 *
405 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs
406 * other than EL3
407 *
408 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other
409 * than EL3
410 */
411 scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
412#endif /* CTX_INCLUDE_PAUTH_REGS */
413
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000414 /*
Mark Brownc37eee72023-03-14 20:13:03 +0000415 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present.
416 */
417 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) {
418 scr_el3 |= SCR_TCR2EN_BIT;
419 }
420
421 /*
Mark Brown293a6612023-03-14 20:48:43 +0000422 * SCR_EL3.PIEN: Enable permission indirection and overlay
423 * registers for AArch64 if present.
424 */
425 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) {
426 scr_el3 |= SCR_PIEN_BIT;
427 }
428
429 /*
Mark Brown326f2952023-03-14 21:33:04 +0000430 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present.
431 */
432 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) {
433 scr_el3 |= SCR_GCSEn_BIT;
434 }
435
436 /*
David Cunadofee86532017-04-13 22:38:29 +0100437 * SCR_EL3.HCE: Enable HVC instructions if next execution state is
438 * AArch64 and next EL is EL2, or if next execution state is AArch32 and
439 * next mode is Hyp.
Jimmy Brissonecc3c672020-04-16 10:47:56 -0500440 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the
441 * same conditions as HVC instructions and when the processor supports
442 * ARMv8.6-FGT.
Jimmy Brisson83573892020-04-16 10:48:02 -0500443 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV)
444 * CNTPOFF_EL2 register under the same conditions as HVC instructions
445 * and when the processor supports ECV.
David Cunadofee86532017-04-13 22:38:29 +0100446 */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000447 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2))
448 || ((GET_RW(ep->spsr) != MODE_RW_64)
449 && (GET_M32(ep->spsr) == MODE32_hyp))) {
David Cunadofee86532017-04-13 22:38:29 +0100450 scr_el3 |= SCR_HCE_BIT;
Jimmy Brissonecc3c672020-04-16 10:47:56 -0500451
Andre Przywarae8920f62022-11-10 14:28:01 +0000452 if (is_feat_fgt_supported()) {
Jimmy Brissonecc3c672020-04-16 10:47:56 -0500453 scr_el3 |= SCR_FGTEN_BIT;
454 }
Jimmy Brisson83573892020-04-16 10:48:02 -0500455
Andre Przywarac3464182022-11-17 17:30:43 +0000456 if (is_feat_ecv_supported()) {
Jimmy Brisson83573892020-04-16 10:48:02 -0500457 scr_el3 |= SCR_ECVEN_BIT;
458 }
David Cunadofee86532017-04-13 22:38:29 +0100459 }
460
johpow013e24c162020-04-22 14:05:13 -0500461 /* Enable WFE trap delay in SCR_EL3 if supported and configured */
Andre Przywara0cf77402023-01-27 12:25:49 +0000462 if (is_feat_twed_supported()) {
463 /* Set delay in SCR_EL3 */
464 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT);
465 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK)
466 << SCR_TWEDEL_SHIFT);
johpow013e24c162020-04-22 14:05:13 -0500467
Andre Przywara0cf77402023-01-27 12:25:49 +0000468 /* Enable WFE delay */
469 scr_el3 |= SCR_TWEDEn_BIT;
470 }
Jayanth Dodderi Chidanandf870cf62023-09-22 15:30:13 +0100471
472#if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2
473 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */
474 if (is_feat_sel2_supported()) {
475 scr_el3 |= SCR_EEL2_BIT;
476 }
477#endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */
johpow013e24c162020-04-22 14:05:13 -0500478
David Cunadofee86532017-04-13 22:38:29 +0100479 /*
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100480 * Populate EL3 state so that we've the right context
481 * before doing ERET
482 */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100483 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
484 write_ctx_reg(state, CTX_ELR_EL3, ep->pc);
485 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr);
486
487 /*
488 * Store the X0-X7 value from the entrypoint into the context
489 * Use memcpy as we are in control of the layout of the structures
490 */
491 gp_regs = get_gpregs_ctx(ctx);
492 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t));
493}
494
495/*******************************************************************************
Zelalem Aweke42401112022-01-05 17:12:24 -0600496 * Context management library initialization routine. This library is used by
497 * runtime services to share pointers to 'cpu_context' structures for secure
498 * non-secure and realm states. Management of the structures and their associated
499 * memory is not done by the context management library e.g. the PSCI service
500 * manages the cpu context used for entry from and exit to the non-secure state.
501 * The Secure payload dispatcher service manages the context(s) corresponding to
502 * the secure state. It also uses this library to get access to the non-secure
503 * state cpu context pointers.
504 * Lastly, this library provides the API to make SP_EL3 point to the cpu context
505 * which will be used for programming an entry into a lower EL. The same context
506 * will be used to save state upon exception entry from that EL.
507 ******************************************************************************/
508void __init cm_init(void)
509{
510 /*
Elyes Haouas2be03c02023-02-13 09:14:48 +0100511 * The context management library has only global data to initialize, but
Zelalem Aweke42401112022-01-05 17:12:24 -0600512 * that will be done when the BSS is zeroed out.
513 */
514}
515
516/*******************************************************************************
517 * This is the high-level function used to initialize the cpu_context 'ctx' for
518 * first use. It performs initializations that are common to all security states
519 * and initializations specific to the security state specified in 'ep'
520 ******************************************************************************/
521void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
522{
523 unsigned int security_state;
524
525 assert(ctx != NULL);
526
527 /*
528 * Perform initializations that are common
529 * to all security states
530 */
531 setup_context_common(ctx, ep);
532
533 security_state = GET_SECURITY_STATE(ep->h.attr);
534
535 /* Perform security state specific initializations */
536 switch (security_state) {
537 case SECURE:
538 setup_secure_context(ctx, ep);
539 break;
540#if ENABLE_RME
541 case REALM:
542 setup_realm_context(ctx, ep);
543 break;
544#endif
545 case NON_SECURE:
546 setup_ns_context(ctx, ep);
547 break;
548 default:
549 ERROR("Invalid security state\n");
550 panic();
551 break;
552 }
553}
554
555/*******************************************************************************
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000556 * Enable architecture extensions for EL3 execution. This function only updates
557 * registers in-place which are expected to either never change or be
558 * overwritten by el3_exit.
559 ******************************************************************************/
560#if IMAGE_BL31
561void cm_manage_extensions_el3(void)
562{
563 if (is_feat_spe_supported()) {
564 spe_init_el3();
Boyan Karatotev7f5dcc72023-03-08 16:29:26 +0000565 }
566
Boyan Karatotev1e966f32023-03-27 17:02:43 +0100567 if (is_feat_amu_supported()) {
568 amu_init_el3();
569 }
570
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +0000571 if (is_feat_sme_supported()) {
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000572 sme_init_el3();
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +0000573 }
Arunachalam Ganapathycac7d162021-07-08 09:35:57 +0100574
Andre Przywara191eff62022-11-17 16:42:09 +0000575 if (is_feat_trbe_supported()) {
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000576 trbe_init_el3();
Andre Przywara191eff62022-11-17 16:42:09 +0000577 }
Manish V Badarkhe20df29c2021-07-02 09:10:56 +0100578
Andre Przywarac97c5512022-11-17 16:42:09 +0000579 if (is_feat_brbe_supported()) {
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000580 brbe_init_el3();
Andre Przywarac97c5512022-11-17 16:42:09 +0000581 }
johpow0181865962022-01-28 17:06:20 -0600582
Andre Przywara06ea44e2022-11-17 17:30:43 +0000583 if (is_feat_trf_supported()) {
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000584 trf_init_el3();
Andre Przywara06ea44e2022-11-17 17:30:43 +0000585 }
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000586
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000587 pmuv3_init_el3();
Boyan Karatotev36cebf92023-03-08 11:56:49 +0000588}
589#endif /* IMAGE_BL31 */
590
Jayanth Dodderi Chidanand56aa3822023-12-11 11:22:02 +0000591/******************************************************************************
592 * Function to initialise the registers with the RESET values in the context
593 * memory, which are maintained per world.
594 ******************************************************************************/
595#if IMAGE_BL31
596void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx)
597{
598 /*
599 * Initialise CPTR_EL3, setting all fields rather than relying on hw.
600 *
601 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers
602 * by Advanced SIMD, floating-point or SVE instructions (if
603 * implemented) do not trap to EL3.
604 *
605 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1,
606 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3.
607 */
608 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT);
Arvind Ram Prakashb5d95592023-11-08 12:28:30 -0600609
Jayanth Dodderi Chidanand56aa3822023-12-11 11:22:02 +0000610 per_world_ctx->ctx_cptr_el3 = cptr_el3;
Arvind Ram Prakashb5d95592023-11-08 12:28:30 -0600611
612 /*
613 * Initialize MPAM3_EL3 to its default reset value
614 *
615 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces
616 * all lower ELn MPAM3_EL3 register access to, trap to EL3
617 */
618
619 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL;
Jayanth Dodderi Chidanand56aa3822023-12-11 11:22:02 +0000620}
621#endif /* IMAGE_BL31 */
622
Boyan Karatotev36cebf92023-03-08 11:56:49 +0000623/*******************************************************************************
Elizabeth Ho4fc00d22023-07-18 14:10:25 +0100624 * Initialise per_world_context for Non-Secure world.
625 * This function enables the architecture extensions, which have same value
626 * across the cores for the non-secure world.
Boyan Karatotev36cebf92023-03-08 11:56:49 +0000627 ******************************************************************************/
Boyan Karatotev36cebf92023-03-08 11:56:49 +0000628#if IMAGE_BL31
Elizabeth Ho4fc00d22023-07-18 14:10:25 +0100629void manage_extensions_nonsecure_per_world(void)
630{
Jayanth Dodderi Chidanand56aa3822023-12-11 11:22:02 +0000631 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]);
632
Elizabeth Ho4fc00d22023-07-18 14:10:25 +0100633 if (is_feat_sme_supported()) {
634 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
Boyan Karatotev1e966f32023-03-27 17:02:43 +0100635 }
636
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000637 if (is_feat_sve_supported()) {
Elizabeth Ho4fc00d22023-07-18 14:10:25 +0100638 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
639 }
640
641 if (is_feat_amu_supported()) {
642 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
643 }
644
645 if (is_feat_sys_reg_trace_supported()) {
646 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000647 }
Arvind Ram Prakashb5d95592023-11-08 12:28:30 -0600648
649 if (is_feat_mpam_supported()) {
650 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
651 }
Elizabeth Ho4fc00d22023-07-18 14:10:25 +0100652}
653#endif /* IMAGE_BL31 */
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000654
Elizabeth Ho4fc00d22023-07-18 14:10:25 +0100655/*******************************************************************************
656 * Initialise per_world_context for Secure world.
657 * This function enables the architecture extensions, which have same value
658 * across the cores for the secure world.
659 ******************************************************************************/
Elizabeth Ho4fc00d22023-07-18 14:10:25 +0100660static void manage_extensions_secure_per_world(void)
661{
662#if IMAGE_BL31
Jayanth Dodderi Chidanand56aa3822023-12-11 11:22:02 +0000663 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
664
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000665 if (is_feat_sme_supported()) {
Elizabeth Ho4fc00d22023-07-18 14:10:25 +0100666
667 if (ENABLE_SME_FOR_SWD) {
668 /*
669 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure
670 * SME, SVE, and FPU/SIMD context properly managed.
671 */
672 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
673 } else {
674 /*
675 * Disable SME, SVE, FPU/SIMD in secure context so non-secure
676 * world can safely use the associated registers.
677 */
678 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
679 }
680 }
681 if (is_feat_sve_supported()) {
682 if (ENABLE_SVE_FOR_SWD) {
683 /*
684 * Enable SVE and FPU in secure context, SPM must ensure
685 * that the SVE and FPU register contexts are properly managed.
686 */
687 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
688 } else {
689 /*
690 * Disable SVE and FPU in secure context so non-secure world
691 * can safely use them.
692 */
693 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
694 }
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000695 }
696
Elizabeth Ho4fc00d22023-07-18 14:10:25 +0100697 /* NS can access this but Secure shouldn't */
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000698 if (is_feat_sys_reg_trace_supported()) {
Elizabeth Ho4fc00d22023-07-18 14:10:25 +0100699 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000700 }
701
Elizabeth Ho4fc00d22023-07-18 14:10:25 +0100702 has_secure_perworld_init = true;
703#endif /* IMAGE_BL31 */
704}
705
706/*******************************************************************************
707 * Enable architecture extensions on first entry to Non-secure world.
708 ******************************************************************************/
709static void manage_extensions_nonsecure(cpu_context_t *ctx)
710{
711#if IMAGE_BL31
712 if (is_feat_amu_supported()) {
713 amu_enable(ctx);
714 }
715
716 if (is_feat_sme_supported()) {
717 sme_enable(ctx);
718 }
719
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000720 pmuv3_enable(ctx);
Boyan Karatotev36cebf92023-03-08 11:56:49 +0000721#endif /* IMAGE_BL31 */
722}
723
Boyan Karatotevfe1cd942023-03-08 17:04:00 +0000724/* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */
725static __unused void enable_pauth_el2(void)
726{
727 u_register_t hcr_el2 = read_hcr_el2();
728 /*
729 * For Armv8.3 pointer authentication feature, disable traps to EL2 when
730 * accessing key registers or using pointer authentication instructions
731 * from lower ELs.
732 */
733 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT);
734
735 write_hcr_el2(hcr_el2);
736}
737
Arvind Ram Prakash8bd27c92023-08-15 16:28:06 -0500738#if INIT_UNUSED_NS_EL2
Boyan Karatotev36cebf92023-03-08 11:56:49 +0000739/*******************************************************************************
740 * Enable architecture extensions in-place at EL2 on first entry to Non-secure
741 * world when EL2 is empty and unused.
742 ******************************************************************************/
743static void manage_extensions_nonsecure_el2_unused(void)
744{
745#if IMAGE_BL31
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000746 if (is_feat_spe_supported()) {
747 spe_init_el2_unused();
748 }
749
Boyan Karatotev1e966f32023-03-27 17:02:43 +0100750 if (is_feat_amu_supported()) {
751 amu_init_el2_unused();
752 }
753
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000754 if (is_feat_mpam_supported()) {
755 mpam_init_el2_unused();
756 }
757
758 if (is_feat_trbe_supported()) {
759 trbe_init_el2_unused();
760 }
761
762 if (is_feat_sys_reg_trace_supported()) {
763 sys_reg_trace_init_el2_unused();
764 }
765
766 if (is_feat_trf_supported()) {
767 trf_init_el2_unused();
768 }
769
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000770 pmuv3_init_el2_unused();
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000771
772 if (is_feat_sve_supported()) {
773 sve_init_el2_unused();
774 }
775
776 if (is_feat_sme_supported()) {
777 sme_init_el2_unused();
778 }
Boyan Karatotevfe1cd942023-03-08 17:04:00 +0000779
780#if ENABLE_PAUTH
781 enable_pauth_el2();
782#endif /* ENABLE_PAUTH */
Boyan Karatotev36cebf92023-03-08 11:56:49 +0000783#endif /* IMAGE_BL31 */
784}
Arvind Ram Prakash8bd27c92023-08-15 16:28:06 -0500785#endif /* INIT_UNUSED_NS_EL2 */
Boyan Karatotev36cebf92023-03-08 11:56:49 +0000786
787/*******************************************************************************
Arunachalam Ganapathycac7d162021-07-08 09:35:57 +0100788 * Enable architecture extensions on first entry to Secure world.
789 ******************************************************************************/
johpow019baade32021-07-08 14:14:00 -0500790static void manage_extensions_secure(cpu_context_t *ctx)
Arunachalam Ganapathycac7d162021-07-08 09:35:57 +0100791{
792#if IMAGE_BL31
Boyan Karatotev7f5dcc72023-03-08 16:29:26 +0000793 if (is_feat_sme_supported()) {
794 if (ENABLE_SME_FOR_SWD) {
795 /*
796 * Enable SME, SVE, FPU/SIMD in secure context, secure manager
797 * must ensure SME, SVE, and FPU/SIMD context properly managed.
798 */
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000799 sme_init_el3();
Boyan Karatotev7f5dcc72023-03-08 16:29:26 +0000800 sme_enable(ctx);
801 } else {
802 /*
803 * Disable SME, SVE, FPU/SIMD in secure context so non-secure
804 * world can safely use the associated registers.
805 */
806 sme_disable(ctx);
807 }
808 }
johpow019baade32021-07-08 14:14:00 -0500809#endif /* IMAGE_BL31 */
Arunachalam Ganapathycac7d162021-07-08 09:35:57 +0100810}
811
812/*******************************************************************************
Soby Mathewb0082d22015-04-09 13:40:55 +0100813 * The following function initializes the cpu_context for a CPU specified by
814 * its `cpu_idx` for first use, and sets the initial entrypoint state as
815 * specified by the entry_point_info structure.
816 ******************************************************************************/
817void cm_init_context_by_index(unsigned int cpu_idx,
818 const entry_point_info_t *ep)
819{
820 cpu_context_t *ctx;
821 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr));
Antonio Nino Diaz28dce9e2018-05-22 10:09:10 +0100822 cm_setup_context(ctx, ep);
Soby Mathewb0082d22015-04-09 13:40:55 +0100823}
824
825/*******************************************************************************
826 * The following function initializes the cpu_context for the current CPU
827 * for first use, and sets the initial entrypoint state as specified by the
828 * entry_point_info structure.
829 ******************************************************************************/
830void cm_init_my_context(const entry_point_info_t *ep)
831{
832 cpu_context_t *ctx;
833 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr));
Antonio Nino Diaz28dce9e2018-05-22 10:09:10 +0100834 cm_setup_context(ctx, ep);
Soby Mathewb0082d22015-04-09 13:40:55 +0100835}
836
Boyan Karatotevfe1cd942023-03-08 17:04:00 +0000837/* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */
Arvind Ram Prakash8bd27c92023-08-15 16:28:06 -0500838static void init_nonsecure_el2_unused(cpu_context_t *ctx)
Boyan Karatotevfe1cd942023-03-08 17:04:00 +0000839{
Arvind Ram Prakash8bd27c92023-08-15 16:28:06 -0500840#if INIT_UNUSED_NS_EL2
Boyan Karatotevfe1cd942023-03-08 17:04:00 +0000841 u_register_t hcr_el2 = HCR_RESET_VAL;
842 u_register_t mdcr_el2;
843 u_register_t scr_el3;
844
845 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3);
846
847 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */
848 if ((scr_el3 & SCR_RW_BIT) != 0U) {
849 hcr_el2 |= HCR_RW_BIT;
850 }
851
852 write_hcr_el2(hcr_el2);
853
854 /*
855 * Initialise CPTR_EL2 setting all fields rather than relying on the hw.
856 * All fields have architecturally UNKNOWN reset values.
857 */
858 write_cptr_el2(CPTR_EL2_RESET_VAL);
859
860 /*
861 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on
862 * reset and are set to zero except for field(s) listed below.
863 *
864 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of
865 * Non-secure EL0 and EL1 accesses to the physical timer registers.
866 *
867 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of
868 * Non-secure EL0 and EL1 accesses to the physical counter registers.
869 */
870 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT);
871
872 /*
873 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally
874 * UNKNOWN value.
875 */
876 write_cntvoff_el2(0);
877
878 /*
879 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1
880 * respectively.
881 */
882 write_vpidr_el2(read_midr_el1());
883 write_vmpidr_el2(read_mpidr_el1());
884
885 /*
886 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset.
887 *
888 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address
889 * translation is disabled, cache maintenance operations depend on the
890 * VMID.
891 *
892 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is
893 * disabled.
894 */
895 write_vttbr_el2(VTTBR_RESET_VAL &
896 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) |
897 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT)));
898
899 /*
900 * Initialise MDCR_EL2, setting all fields rather than relying on hw.
901 * Some fields are architecturally UNKNOWN on reset.
902 *
903 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System
904 * register accesses to the Debug ROM registers are not trapped to EL2.
905 *
906 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register
907 * accesses to the powerdown debug registers are not trapped to EL2.
908 *
909 * MDCR_EL2.TDA: Set to zero so that System register accesses to the
910 * debug registers do not trap to EL2.
911 *
912 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to
913 * EL2.
914 */
915 mdcr_el2 = MDCR_EL2_RESET_VAL &
916 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT |
917 MDCR_EL2_TDE_BIT);
918
919 write_mdcr_el2(mdcr_el2);
920
921 /*
922 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset.
923 *
924 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or
925 * EL1 accesses to System registers do not trap to EL2.
926 */
927 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK));
928
929 /*
930 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on
931 * reset.
932 *
933 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer
934 * and prevent timer interrupts.
935 */
936 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT));
937
938 manage_extensions_nonsecure_el2_unused();
Arvind Ram Prakash8bd27c92023-08-15 16:28:06 -0500939#endif /* INIT_UNUSED_NS_EL2 */
Boyan Karatotevfe1cd942023-03-08 17:04:00 +0000940}
941
Soby Mathewb0082d22015-04-09 13:40:55 +0100942/*******************************************************************************
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500943 * Prepare the CPU system registers for first entry into realm, secure, or
944 * normal world.
Andrew Thoelke4e126072014-06-04 21:10:52 +0100945 *
946 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized
947 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports
948 * EL2 then EL2 is disabled by configuring all necessary EL2 registers.
949 * For all entries, the EL1 registers are initialized from the cpu_context
950 ******************************************************************************/
951void cm_prepare_el3_exit(uint32_t security_state)
952{
Boyan Karatotevfe1cd942023-03-08 17:04:00 +0000953 u_register_t sctlr_elx, scr_el3;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100954 cpu_context_t *ctx = cm_get_context(security_state);
955
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000956 assert(ctx != NULL);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100957
958 if (security_state == NON_SECURE) {
Juan Pablo Conde72e0da12023-02-22 10:09:52 -0600959 uint64_t el2_implemented = el_implemented(2);
960
Louis Mayencourt1c819c32020-01-24 13:30:28 +0000961 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx),
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000962 CTX_SCR_EL3);
Juan Pablo Conde72e0da12023-02-22 10:09:52 -0600963
Jayanth Dodderi Chidanand6cab6c02024-03-06 13:31:35 +0000964 if (el2_implemented != EL_IMPL_NONE) {
965
Juan Pablo Conde72e0da12023-02-22 10:09:52 -0600966 /*
967 * If context is not being used for EL2, initialize
968 * HCRX_EL2 with its init value here.
969 */
970 if (is_feat_hcx_supported()) {
971 write_hcrx_el2(HCRX_EL2_INIT_VAL);
972 }
Juan Pablo Condef7252982023-07-10 16:00:41 -0500973
974 /*
975 * Initialize Fine-grained trap registers introduced
976 * by FEAT_FGT so all traps are initially disabled when
977 * switching to EL2 or a lower EL, preventing undesired
978 * behavior.
979 */
980 if (is_feat_fgt_supported()) {
981 /*
982 * Initialize HFG*_EL2 registers with a default
983 * value so legacy systems unaware of FEAT_FGT
984 * do not get trapped due to their lack of
985 * initialization for this feature.
986 */
987 write_hfgitr_el2(HFGITR_EL2_INIT_VAL);
988 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL);
989 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL);
990 }
Juan Pablo Conde72e0da12023-02-22 10:09:52 -0600991
Jayanth Dodderi Chidanand6cab6c02024-03-06 13:31:35 +0000992 /* Condition to ensure EL2 is being used. */
993 if ((scr_el3 & SCR_HCE_BIT) != 0U) {
994 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
995 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx),
996 CTX_SCTLR_EL1);
997 sctlr_elx &= SCTLR_EE_BIT;
998 sctlr_elx |= SCTLR_EL2_RES1;
Louis Mayencourt78a0aed2019-02-20 12:11:41 +0000999#if ERRATA_A75_764081
Jayanth Dodderi Chidanand6cab6c02024-03-06 13:31:35 +00001000 /*
1001 * If workaround of errata 764081 for Cortex-A75
1002 * is used then set SCTLR_EL2.IESB to enable
1003 * Implicit Error Synchronization Barrier.
1004 */
1005 sctlr_elx |= SCTLR_IESB_BIT;
1006#endif /* ERRATA_A75_764081 */
1007 write_sctlr_el2(sctlr_elx);
1008 } else {
1009 /*
1010 * (scr_el3 & SCR_HCE_BIT==0)
1011 * EL2 implemented but unused.
1012 */
1013 init_nonsecure_el2_unused(ctx);
1014 }
Andrew Thoelke4e126072014-06-04 21:10:52 +01001015 }
1016 }
Dimitris Papastamosa7921b92017-10-13 15:27:58 +01001017 cm_el1_sysregs_context_restore(security_state);
1018 cm_set_next_eret_context(security_state);
Andrew Thoelke4e126072014-06-04 21:10:52 +01001019}
1020
Max Shvetsovbdf502d2020-02-25 13:56:19 +00001021#if CTX_INCLUDE_EL2_REGS
Andre Przywara5d6d2ab2022-11-10 14:40:37 +00001022
1023static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx)
1024{
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001025 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2());
Andre Przywara8258f142023-02-15 15:56:15 +00001026 if (is_feat_amu_supported()) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001027 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2());
Andre Przywara5d6d2ab2022-11-10 14:40:37 +00001028 }
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001029 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2());
1030 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2());
1031 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2());
1032 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2());
Andre Przywara5d6d2ab2022-11-10 14:40:37 +00001033}
1034
1035static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx)
1036{
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001037 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2));
Andre Przywara8258f142023-02-15 15:56:15 +00001038 if (is_feat_amu_supported()) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001039 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2));
Andre Przywara5d6d2ab2022-11-10 14:40:37 +00001040 }
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001041 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2));
1042 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2));
1043 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2));
1044 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2));
Andre Przywara5d6d2ab2022-11-10 14:40:37 +00001045}
1046
Arvind Ram Prakash4851b492023-10-06 14:35:21 -05001047#if CTX_INCLUDE_MPAM_REGS
1048
1049static void el2_sysregs_context_save_mpam(mpam_t *ctx)
Andre Przywara84b86532022-11-17 16:42:09 +00001050{
1051 u_register_t mpam_idr = read_mpamidr_el1();
1052
1053 write_ctx_reg(ctx, CTX_MPAM2_EL2, read_mpam2_el2());
1054
1055 /*
1056 * The context registers that we intend to save would be part of the
1057 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1.
1058 */
1059 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) {
1060 return;
1061 }
1062
1063 /*
1064 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if
1065 * MPAMIDR_HAS_HCR_BIT == 1.
1066 */
1067 write_ctx_reg(ctx, CTX_MPAMHCR_EL2, read_mpamhcr_el2());
1068 write_ctx_reg(ctx, CTX_MPAMVPM0_EL2, read_mpamvpm0_el2());
1069 write_ctx_reg(ctx, CTX_MPAMVPMV_EL2, read_mpamvpmv_el2());
1070
1071 /*
1072 * The number of MPAMVPM registers is implementation defined, their
1073 * number is stored in the MPAMIDR_EL1 register.
1074 */
1075 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) {
1076 case 7:
1077 write_ctx_reg(ctx, CTX_MPAMVPM7_EL2, read_mpamvpm7_el2());
1078 __fallthrough;
1079 case 6:
1080 write_ctx_reg(ctx, CTX_MPAMVPM6_EL2, read_mpamvpm6_el2());
1081 __fallthrough;
1082 case 5:
1083 write_ctx_reg(ctx, CTX_MPAMVPM5_EL2, read_mpamvpm5_el2());
1084 __fallthrough;
1085 case 4:
1086 write_ctx_reg(ctx, CTX_MPAMVPM4_EL2, read_mpamvpm4_el2());
1087 __fallthrough;
1088 case 3:
1089 write_ctx_reg(ctx, CTX_MPAMVPM3_EL2, read_mpamvpm3_el2());
1090 __fallthrough;
1091 case 2:
1092 write_ctx_reg(ctx, CTX_MPAMVPM2_EL2, read_mpamvpm2_el2());
1093 __fallthrough;
1094 case 1:
1095 write_ctx_reg(ctx, CTX_MPAMVPM1_EL2, read_mpamvpm1_el2());
1096 break;
1097 }
1098}
1099
Arvind Ram Prakash4851b492023-10-06 14:35:21 -05001100#endif /* CTX_INCLUDE_MPAM_REGS */
1101
1102#if CTX_INCLUDE_MPAM_REGS
1103static void el2_sysregs_context_restore_mpam(mpam_t *ctx)
Andre Przywara84b86532022-11-17 16:42:09 +00001104{
1105 u_register_t mpam_idr = read_mpamidr_el1();
1106
1107 write_mpam2_el2(read_ctx_reg(ctx, CTX_MPAM2_EL2));
1108
1109 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) {
1110 return;
1111 }
1112
1113 write_mpamhcr_el2(read_ctx_reg(ctx, CTX_MPAMHCR_EL2));
1114 write_mpamvpm0_el2(read_ctx_reg(ctx, CTX_MPAMVPM0_EL2));
1115 write_mpamvpmv_el2(read_ctx_reg(ctx, CTX_MPAMVPMV_EL2));
1116
1117 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) {
1118 case 7:
1119 write_mpamvpm7_el2(read_ctx_reg(ctx, CTX_MPAMVPM7_EL2));
1120 __fallthrough;
1121 case 6:
1122 write_mpamvpm6_el2(read_ctx_reg(ctx, CTX_MPAMVPM6_EL2));
1123 __fallthrough;
1124 case 5:
1125 write_mpamvpm5_el2(read_ctx_reg(ctx, CTX_MPAMVPM5_EL2));
1126 __fallthrough;
1127 case 4:
1128 write_mpamvpm4_el2(read_ctx_reg(ctx, CTX_MPAMVPM4_EL2));
1129 __fallthrough;
1130 case 3:
1131 write_mpamvpm3_el2(read_ctx_reg(ctx, CTX_MPAMVPM3_EL2));
1132 __fallthrough;
1133 case 2:
1134 write_mpamvpm2_el2(read_ctx_reg(ctx, CTX_MPAMVPM2_EL2));
1135 __fallthrough;
1136 case 1:
1137 write_mpamvpm1_el2(read_ctx_reg(ctx, CTX_MPAMVPM1_EL2));
1138 break;
1139 }
1140}
Arvind Ram Prakash4851b492023-10-06 14:35:21 -05001141#endif /* CTX_INCLUDE_MPAM_REGS */
Andre Przywara84b86532022-11-17 16:42:09 +00001142
Manish Pandey238262f2024-02-05 21:40:21 +00001143/* ---------------------------------------------------------------------------
Boyan Karatoteva6989892023-05-15 15:09:16 +01001144 * The following registers are not added:
Boyan Karatoteva6989892023-05-15 15:09:16 +01001145 * ICH_AP0R<n>_EL2
1146 * ICH_AP1R<n>_EL2
1147 * ICH_LR<n>_EL2
Manish Pandey238262f2024-02-05 21:40:21 +00001148 *
1149 * NOTE: For a system with S-EL2 present but not enabled, accessing
1150 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the
1151 * SCR_EL3.NS = 1 before accessing this register.
1152 * ---------------------------------------------------------------------------
1153 */
1154static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx)
1155{
1156#if defined(SPD_spmd) && SPMD_SPM_AT_SEL2
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001157 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2());
Manish Pandey238262f2024-02-05 21:40:21 +00001158#else
1159 u_register_t scr_el3 = read_scr_el3();
1160 write_scr_el3(scr_el3 | SCR_NS_BIT);
1161 isb();
1162
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001163 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2());
Manish Pandey238262f2024-02-05 21:40:21 +00001164
1165 write_scr_el3(scr_el3);
1166 isb();
Manish Pandey238262f2024-02-05 21:40:21 +00001167#endif
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001168 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2());
1169 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2());
Manish Pandey238262f2024-02-05 21:40:21 +00001170}
1171
1172static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx)
1173{
1174#if defined(SPD_spmd) && SPMD_SPM_AT_SEL2
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001175 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2));
Manish Pandey238262f2024-02-05 21:40:21 +00001176#else
1177 u_register_t scr_el3 = read_scr_el3();
1178 write_scr_el3(scr_el3 | SCR_NS_BIT);
1179 isb();
1180
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001181 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2));
Manish Pandey238262f2024-02-05 21:40:21 +00001182
1183 write_scr_el3(scr_el3);
1184 isb();
1185#endif
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001186 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2));
1187 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2));
Manish Pandey238262f2024-02-05 21:40:21 +00001188}
1189
1190/* -----------------------------------------------------
1191 * The following registers are not added:
1192 * AMEVCNTVOFF0<n>_EL2
1193 * AMEVCNTVOFF1<n>_EL2
Boyan Karatoteva6989892023-05-15 15:09:16 +01001194 * -----------------------------------------------------
1195 */
1196static void el2_sysregs_context_save_common(el2_sysregs_t *ctx)
1197{
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001198 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2());
1199 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2());
1200 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2());
1201 write_el2_ctx_common(ctx, amair_el2, read_amair_el2());
1202 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2());
1203 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2());
1204 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2());
Boyan Karatoteva6989892023-05-15 15:09:16 +01001205 if (CTX_INCLUDE_AARCH32_REGS) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001206 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2());
Boyan Karatoteva6989892023-05-15 15:09:16 +01001207 }
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001208 write_el2_ctx_common(ctx, elr_el2, read_elr_el2());
1209 write_el2_ctx_common(ctx, esr_el2, read_esr_el2());
1210 write_el2_ctx_common(ctx, far_el2, read_far_el2());
1211 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2());
1212 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2());
1213 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2());
1214 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2());
1215 write_el2_ctx_common(ctx, mair_el2, read_mair_el2());
1216 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2());
1217 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2());
1218 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2());
1219 write_el2_ctx_common(ctx, sp_el2, read_sp_el2());
1220 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2());
1221 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2());
1222 write_el2_ctx_common(ctx, ttbr0_el2, read_ttbr0_el2());
1223 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2());
1224 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2());
1225 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2());
1226 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2());
1227 write_el2_ctx_common(ctx, vttbr_el2, read_vttbr_el2());
Boyan Karatoteva6989892023-05-15 15:09:16 +01001228}
1229
1230static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx)
1231{
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001232 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2));
1233 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2));
1234 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2));
1235 write_amair_el2(read_el2_ctx_common(ctx, amair_el2));
1236 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2));
1237 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2));
1238 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2));
Boyan Karatoteva6989892023-05-15 15:09:16 +01001239 if (CTX_INCLUDE_AARCH32_REGS) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001240 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2));
Boyan Karatoteva6989892023-05-15 15:09:16 +01001241 }
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001242 write_elr_el2(read_el2_ctx_common(ctx, elr_el2));
1243 write_esr_el2(read_el2_ctx_common(ctx, esr_el2));
1244 write_far_el2(read_el2_ctx_common(ctx, far_el2));
1245 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2));
1246 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2));
1247 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2));
1248 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2));
1249 write_mair_el2(read_el2_ctx_common(ctx, mair_el2));
1250 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2));
1251 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2));
1252 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2));
1253 write_sp_el2(read_el2_ctx_common(ctx, sp_el2));
1254 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2));
1255 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2));
1256 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2));
1257 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2));
1258 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2));
1259 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2));
1260 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2));
1261 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2));
Boyan Karatoteva6989892023-05-15 15:09:16 +01001262}
1263
Max Shvetsovbdf502d2020-02-25 13:56:19 +00001264/*******************************************************************************
1265 * Save EL2 sysreg context
1266 ******************************************************************************/
1267void cm_el2_sysregs_context_save(uint32_t security_state)
1268{
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001269 cpu_context_t *ctx;
1270 el2_sysregs_t *el2_sysregs_ctx;
Max Shvetsovbdf502d2020-02-25 13:56:19 +00001271
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001272 ctx = cm_get_context(security_state);
1273 assert(ctx != NULL);
Max Shvetsovbdf502d2020-02-25 13:56:19 +00001274
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001275 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx);
Zelalem Aweke5362beb2022-04-04 17:42:48 -05001276
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001277 el2_sysregs_context_save_common(el2_sysregs_ctx);
Manish Pandey238262f2024-02-05 21:40:21 +00001278 el2_sysregs_context_save_gic(el2_sysregs_ctx);
Govindraj Raja24d3a4e2023-12-21 13:57:49 -06001279
Govindraj Rajac1be66f2024-03-07 14:42:20 -06001280 if (is_feat_mte2_supported()) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001281 write_el2_ctx_mte(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2());
Govindraj Raja24d3a4e2023-12-21 13:57:49 -06001282 }
Arvind Ram Prakash4851b492023-10-06 14:35:21 -05001283
1284#if CTX_INCLUDE_MPAM_REGS
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001285 if (is_feat_mpam_supported()) {
Arvind Ram Prakash4851b492023-10-06 14:35:21 -05001286 mpam_t *mpam_ctx = get_mpam_ctx(ctx);
1287 el2_sysregs_context_save_mpam(mpam_ctx);
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001288 }
Arvind Ram Prakash4851b492023-10-06 14:35:21 -05001289#endif
Andre Przywara5d6d2ab2022-11-10 14:40:37 +00001290
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001291 if (is_feat_fgt_supported()) {
1292 el2_sysregs_context_save_fgt(el2_sysregs_ctx);
1293 }
Andre Przywara5d6d2ab2022-11-10 14:40:37 +00001294
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001295 if (is_feat_ecv_v2_supported()) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001296 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2());
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001297 }
Andre Przywarac3464182022-11-17 17:30:43 +00001298
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001299 if (is_feat_vhe_supported()) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001300 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2,
1301 read_contextidr_el2());
1302 write_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2());
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001303 }
Andre Przywara870627e2023-01-27 12:25:49 +00001304
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001305 if (is_feat_ras_supported()) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001306 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2());
1307 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2());
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001308 }
Andre Przywaraedc449d2023-01-27 14:09:20 +00001309
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001310 if (is_feat_nv2_supported()) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001311 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2());
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001312 }
Andre Przywaraedc449d2023-01-27 14:09:20 +00001313
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001314 if (is_feat_trf_supported()) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001315 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2());
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001316 }
Andre Przywara902c9022022-11-17 17:30:43 +00001317
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001318 if (is_feat_csv2_2_supported()) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001319 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2,
1320 read_scxtnum_el2());
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001321 }
Andre Przywara902c9022022-11-17 17:30:43 +00001322
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001323 if (is_feat_hcx_supported()) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001324 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2());
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001325 }
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001326
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001327 if (is_feat_tcr2_supported()) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001328 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2());
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001329 }
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001330
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001331 if (is_feat_sxpie_supported()) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001332 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2());
1333 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2());
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001334 }
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001335
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001336 if (is_feat_sxpoe_supported()) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001337 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2());
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001338 }
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001339
1340 if (is_feat_s2pie_supported()) {
1341 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2());
1342 }
1343
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001344 if (is_feat_gcs_supported()) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001345 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcspr_el2());
1346 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcscr_el2());
Max Shvetsovbdf502d2020-02-25 13:56:19 +00001347 }
1348}
1349
1350/*******************************************************************************
1351 * Restore EL2 sysreg context
1352 ******************************************************************************/
1353void cm_el2_sysregs_context_restore(uint32_t security_state)
1354{
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001355 cpu_context_t *ctx;
1356 el2_sysregs_t *el2_sysregs_ctx;
Max Shvetsovbdf502d2020-02-25 13:56:19 +00001357
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001358 ctx = cm_get_context(security_state);
1359 assert(ctx != NULL);
Max Shvetsovbdf502d2020-02-25 13:56:19 +00001360
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001361 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx);
Zelalem Aweke5362beb2022-04-04 17:42:48 -05001362
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001363 el2_sysregs_context_restore_common(el2_sysregs_ctx);
Manish Pandey238262f2024-02-05 21:40:21 +00001364 el2_sysregs_context_restore_gic(el2_sysregs_ctx);
Govindraj Raja77922ca2024-01-25 08:09:39 -06001365
Govindraj Rajac1be66f2024-03-07 14:42:20 -06001366 if (is_feat_mte2_supported()) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001367 write_tfsr_el2(read_el2_ctx_mte(el2_sysregs_ctx, tfsr_el2));
Govindraj Raja77922ca2024-01-25 08:09:39 -06001368 }
Arvind Ram Prakash4851b492023-10-06 14:35:21 -05001369
1370#if CTX_INCLUDE_MPAM_REGS
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001371 if (is_feat_mpam_supported()) {
Arvind Ram Prakash4851b492023-10-06 14:35:21 -05001372 mpam_t *mpam_ctx = get_mpam_ctx(ctx);
1373 el2_sysregs_context_restore_mpam(mpam_ctx);
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001374 }
Arvind Ram Prakash4851b492023-10-06 14:35:21 -05001375#endif
Andre Przywara5d6d2ab2022-11-10 14:40:37 +00001376
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001377 if (is_feat_fgt_supported()) {
1378 el2_sysregs_context_restore_fgt(el2_sysregs_ctx);
1379 }
Andre Przywara5d6d2ab2022-11-10 14:40:37 +00001380
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001381 if (is_feat_ecv_v2_supported()) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001382 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2));
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001383 }
Andre Przywarac3464182022-11-17 17:30:43 +00001384
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001385 if (is_feat_vhe_supported()) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001386 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx,
1387 contextidr_el2));
1388 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2));
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001389 }
Andre Przywara870627e2023-01-27 12:25:49 +00001390
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001391 if (is_feat_ras_supported()) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001392 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2));
1393 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2));
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001394 }
Andre Przywaraedc449d2023-01-27 14:09:20 +00001395
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001396 if (is_feat_nv2_supported()) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001397 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2));
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001398 }
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001399
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001400 if (is_feat_trf_supported()) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001401 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2));
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001402 }
Andre Przywara902c9022022-11-17 17:30:43 +00001403
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001404 if (is_feat_csv2_2_supported()) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001405 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx,
1406 scxtnum_el2));
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001407 }
Andre Przywara902c9022022-11-17 17:30:43 +00001408
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001409 if (is_feat_hcx_supported()) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001410 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2));
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001411 }
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001412
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001413 if (is_feat_tcr2_supported()) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001414 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2));
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001415 }
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001416
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001417 if (is_feat_sxpie_supported()) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001418 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2));
1419 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2));
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001420 }
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001421
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001422 if (is_feat_sxpoe_supported()) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001423 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2));
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001424 }
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001425
1426 if (is_feat_s2pie_supported()) {
1427 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2));
1428 }
1429
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001430 if (is_feat_gcs_supported()) {
Jayanth Dodderi Chidanandfbbee6b2024-01-24 20:05:07 +00001431 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2));
1432 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2));
Max Shvetsovbdf502d2020-02-25 13:56:19 +00001433 }
1434}
1435#endif /* CTX_INCLUDE_EL2_REGS */
1436
Andrew Thoelke4e126072014-06-04 21:10:52 +01001437/*******************************************************************************
Zelalem Awekef92c0cb2022-01-31 16:59:42 -06001438 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS
1439 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly
1440 * updating EL1 and EL2 registers. Otherwise, it calls the generic
1441 * cm_prepare_el3_exit function.
1442 ******************************************************************************/
1443void cm_prepare_el3_exit_ns(void)
1444{
1445#if CTX_INCLUDE_EL2_REGS
Boyan Karatotev1e966f32023-03-27 17:02:43 +01001446#if ENABLE_ASSERTIONS
Zelalem Awekef92c0cb2022-01-31 16:59:42 -06001447 cpu_context_t *ctx = cm_get_context(NON_SECURE);
1448 assert(ctx != NULL);
1449
Zelalem Aweke20126002022-04-08 16:48:05 -05001450 /* Assert that EL2 is used. */
Boyan Karatotev1e966f32023-03-27 17:02:43 +01001451 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3);
Zelalem Aweke20126002022-04-08 16:48:05 -05001452 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) &&
1453 (el_implemented(2U) != EL_IMPL_NONE));
Boyan Karatotev1e966f32023-03-27 17:02:43 +01001454#endif /* ENABLE_ASSERTIONS */
Zelalem Awekef92c0cb2022-01-31 16:59:42 -06001455
Zelalem Awekef92c0cb2022-01-31 16:59:42 -06001456 /* Restore EL2 and EL1 sysreg contexts */
1457 cm_el2_sysregs_context_restore(NON_SECURE);
1458 cm_el1_sysregs_context_restore(NON_SECURE);
1459 cm_set_next_eret_context(NON_SECURE);
1460#else
1461 cm_prepare_el3_exit(NON_SECURE);
1462#endif /* CTX_INCLUDE_EL2_REGS */
1463}
1464
Jayanth Dodderi Chidanand1facfb12024-01-08 13:14:27 +00001465static void el1_sysregs_context_save(el1_sysregs_t *ctx)
1466{
1467 write_ctx_reg(ctx, CTX_SPSR_EL1, read_spsr_el1());
1468 write_ctx_reg(ctx, CTX_ELR_EL1, read_elr_el1());
1469
1470#if !ERRATA_SPECULATIVE_AT
1471 write_ctx_reg(ctx, CTX_SCTLR_EL1, read_sctlr_el1());
1472 write_ctx_reg(ctx, CTX_TCR_EL1, read_tcr_el1());
1473#endif /* (!ERRATA_SPECULATIVE_AT) */
1474
1475 write_ctx_reg(ctx, CTX_CPACR_EL1, read_cpacr_el1());
1476 write_ctx_reg(ctx, CTX_CSSELR_EL1, read_csselr_el1());
1477 write_ctx_reg(ctx, CTX_SP_EL1, read_sp_el1());
1478 write_ctx_reg(ctx, CTX_ESR_EL1, read_esr_el1());
1479 write_ctx_reg(ctx, CTX_TTBR0_EL1, read_ttbr0_el1());
1480 write_ctx_reg(ctx, CTX_TTBR1_EL1, read_ttbr1_el1());
1481 write_ctx_reg(ctx, CTX_MAIR_EL1, read_mair_el1());
1482 write_ctx_reg(ctx, CTX_AMAIR_EL1, read_amair_el1());
1483 write_ctx_reg(ctx, CTX_ACTLR_EL1, read_actlr_el1());
1484 write_ctx_reg(ctx, CTX_TPIDR_EL1, read_tpidr_el1());
1485 write_ctx_reg(ctx, CTX_TPIDR_EL0, read_tpidr_el0());
1486 write_ctx_reg(ctx, CTX_TPIDRRO_EL0, read_tpidrro_el0());
1487 write_ctx_reg(ctx, CTX_PAR_EL1, read_par_el1());
1488 write_ctx_reg(ctx, CTX_FAR_EL1, read_far_el1());
1489 write_ctx_reg(ctx, CTX_AFSR0_EL1, read_afsr0_el1());
1490 write_ctx_reg(ctx, CTX_AFSR1_EL1, read_afsr1_el1());
1491 write_ctx_reg(ctx, CTX_CONTEXTIDR_EL1, read_contextidr_el1());
1492 write_ctx_reg(ctx, CTX_VBAR_EL1, read_vbar_el1());
1493
1494#if CTX_INCLUDE_AARCH32_REGS
1495 write_ctx_reg(ctx, CTX_SPSR_ABT, read_spsr_abt());
1496 write_ctx_reg(ctx, CTX_SPSR_UND, read_spsr_und());
1497 write_ctx_reg(ctx, CTX_SPSR_IRQ, read_spsr_irq());
1498 write_ctx_reg(ctx, CTX_SPSR_FIQ, read_spsr_fiq());
1499 write_ctx_reg(ctx, CTX_DACR32_EL2, read_dacr32_el2());
1500 write_ctx_reg(ctx, CTX_IFSR32_EL2, read_ifsr32_el2());
1501#endif /* CTX_INCLUDE_AARCH32_REGS */
1502
1503#if NS_TIMER_SWITCH
1504 write_ctx_reg(ctx, CTX_CNTP_CTL_EL0, read_cntp_ctl_el0());
1505 write_ctx_reg(ctx, CTX_CNTP_CVAL_EL0, read_cntp_cval_el0());
1506 write_ctx_reg(ctx, CTX_CNTV_CTL_EL0, read_cntv_ctl_el0());
1507 write_ctx_reg(ctx, CTX_CNTV_CVAL_EL0, read_cntv_cval_el0());
1508 write_ctx_reg(ctx, CTX_CNTKCTL_EL1, read_cntkctl_el1());
1509#endif /* NS_TIMER_SWITCH */
1510
Govindraj Rajac1be66f2024-03-07 14:42:20 -06001511#if ENABLE_FEAT_MTE2
Jayanth Dodderi Chidanand1facfb12024-01-08 13:14:27 +00001512 write_ctx_reg(ctx, CTX_TFSRE0_EL1, read_tfsre0_el1());
1513 write_ctx_reg(ctx, CTX_TFSR_EL1, read_tfsr_el1());
1514 write_ctx_reg(ctx, CTX_RGSR_EL1, read_rgsr_el1());
1515 write_ctx_reg(ctx, CTX_GCR_EL1, read_gcr_el1());
Govindraj Rajac1be66f2024-03-07 14:42:20 -06001516#endif /* ENABLE_FEAT_MTE2 */
Jayanth Dodderi Chidanand1facfb12024-01-08 13:14:27 +00001517
1518}
1519
1520static void el1_sysregs_context_restore(el1_sysregs_t *ctx)
1521{
1522 write_spsr_el1(read_ctx_reg(ctx, CTX_SPSR_EL1));
1523 write_elr_el1(read_ctx_reg(ctx, CTX_ELR_EL1));
1524
1525#if !ERRATA_SPECULATIVE_AT
1526 write_sctlr_el1(read_ctx_reg(ctx, CTX_SCTLR_EL1));
1527 write_tcr_el1(read_ctx_reg(ctx, CTX_TCR_EL1));
1528#endif /* (!ERRATA_SPECULATIVE_AT) */
1529
1530 write_cpacr_el1(read_ctx_reg(ctx, CTX_CPACR_EL1));
1531 write_csselr_el1(read_ctx_reg(ctx, CTX_CSSELR_EL1));
1532 write_sp_el1(read_ctx_reg(ctx, CTX_SP_EL1));
1533 write_esr_el1(read_ctx_reg(ctx, CTX_ESR_EL1));
1534 write_ttbr0_el1(read_ctx_reg(ctx, CTX_TTBR0_EL1));
1535 write_ttbr1_el1(read_ctx_reg(ctx, CTX_TTBR1_EL1));
1536 write_mair_el1(read_ctx_reg(ctx, CTX_MAIR_EL1));
1537 write_amair_el1(read_ctx_reg(ctx, CTX_AMAIR_EL1));
1538 write_actlr_el1(read_ctx_reg(ctx, CTX_ACTLR_EL1));
1539 write_tpidr_el1(read_ctx_reg(ctx, CTX_TPIDR_EL1));
1540 write_tpidr_el0(read_ctx_reg(ctx, CTX_TPIDR_EL0));
1541 write_tpidrro_el0(read_ctx_reg(ctx, CTX_TPIDRRO_EL0));
1542 write_par_el1(read_ctx_reg(ctx, CTX_PAR_EL1));
1543 write_far_el1(read_ctx_reg(ctx, CTX_FAR_EL1));
1544 write_afsr0_el1(read_ctx_reg(ctx, CTX_AFSR0_EL1));
1545 write_afsr1_el1(read_ctx_reg(ctx, CTX_AFSR1_EL1));
1546 write_contextidr_el1(read_ctx_reg(ctx, CTX_CONTEXTIDR_EL1));
1547 write_vbar_el1(read_ctx_reg(ctx, CTX_VBAR_EL1));
1548
1549#if CTX_INCLUDE_AARCH32_REGS
1550 write_spsr_abt(read_ctx_reg(ctx, CTX_SPSR_ABT));
1551 write_spsr_und(read_ctx_reg(ctx, CTX_SPSR_UND));
1552 write_spsr_irq(read_ctx_reg(ctx, CTX_SPSR_IRQ));
1553 write_spsr_fiq(read_ctx_reg(ctx, CTX_SPSR_FIQ));
1554 write_dacr32_el2(read_ctx_reg(ctx, CTX_DACR32_EL2));
1555 write_ifsr32_el2(read_ctx_reg(ctx, CTX_IFSR32_EL2));
1556#endif /* CTX_INCLUDE_AARCH32_REGS */
1557
1558#if NS_TIMER_SWITCH
1559 write_cntp_ctl_el0(read_ctx_reg(ctx, CTX_CNTP_CTL_EL0));
1560 write_cntp_cval_el0(read_ctx_reg(ctx, CTX_CNTP_CVAL_EL0));
1561 write_cntv_ctl_el0(read_ctx_reg(ctx, CTX_CNTV_CTL_EL0));
1562 write_cntv_cval_el0(read_ctx_reg(ctx, CTX_CNTV_CVAL_EL0));
1563 write_cntkctl_el1(read_ctx_reg(ctx, CTX_CNTKCTL_EL1));
1564#endif /* NS_TIMER_SWITCH */
1565
Govindraj Rajac1be66f2024-03-07 14:42:20 -06001566#if ENABLE_FEAT_MTE2
Jayanth Dodderi Chidanand1facfb12024-01-08 13:14:27 +00001567 write_tfsre0_el1(read_ctx_reg(ctx, CTX_TFSRE0_EL1));
1568 write_tfsr_el1(read_ctx_reg(ctx, CTX_TFSR_EL1));
1569 write_rgsr_el1(read_ctx_reg(ctx, CTX_RGSR_EL1));
1570 write_gcr_el1(read_ctx_reg(ctx, CTX_GCR_EL1));
Govindraj Rajac1be66f2024-03-07 14:42:20 -06001571#endif /* ENABLE_FEAT_MTE2 */
Jayanth Dodderi Chidanand1facfb12024-01-08 13:14:27 +00001572
1573}
1574
Zelalem Awekef92c0cb2022-01-31 16:59:42 -06001575/*******************************************************************************
Soby Mathew2ed46e92014-07-04 16:02:26 +01001576 * The next four functions are used by runtime services to save and restore
1577 * EL1 context on the 'cpu_context' structure for the specified security
Achin Gupta7aea9082014-02-01 07:51:28 +00001578 * state.
1579 ******************************************************************************/
Achin Gupta7aea9082014-02-01 07:51:28 +00001580void cm_el1_sysregs_context_save(uint32_t security_state)
1581{
Dan Handleye2712bc2014-04-10 15:37:22 +01001582 cpu_context_t *ctx;
Achin Gupta7aea9082014-02-01 07:51:28 +00001583
Andrew Thoelkea2f65532014-05-14 17:09:32 +01001584 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00001585 assert(ctx != NULL);
Achin Gupta7aea9082014-02-01 07:51:28 +00001586
Max Shvetsovc9e2c922020-02-17 16:15:47 +00001587 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx));
Dimitris Papastamosa7921b92017-10-13 15:27:58 +01001588
1589#if IMAGE_BL31
1590 if (security_state == SECURE)
1591 PUBLISH_EVENT(cm_exited_secure_world);
1592 else
1593 PUBLISH_EVENT(cm_exited_normal_world);
1594#endif
Achin Gupta7aea9082014-02-01 07:51:28 +00001595}
1596
1597void cm_el1_sysregs_context_restore(uint32_t security_state)
1598{
Dan Handleye2712bc2014-04-10 15:37:22 +01001599 cpu_context_t *ctx;
Achin Gupta7aea9082014-02-01 07:51:28 +00001600
Andrew Thoelkea2f65532014-05-14 17:09:32 +01001601 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00001602 assert(ctx != NULL);
Achin Gupta7aea9082014-02-01 07:51:28 +00001603
Max Shvetsovc9e2c922020-02-17 16:15:47 +00001604 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx));
Dimitris Papastamosa7921b92017-10-13 15:27:58 +01001605
1606#if IMAGE_BL31
1607 if (security_state == SECURE)
1608 PUBLISH_EVENT(cm_entering_secure_world);
1609 else
1610 PUBLISH_EVENT(cm_entering_normal_world);
1611#endif
Achin Gupta7aea9082014-02-01 07:51:28 +00001612}
1613
1614/*******************************************************************************
Andrew Thoelke4e126072014-06-04 21:10:52 +01001615 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the
1616 * given security state with the given entrypoint
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001617 ******************************************************************************/
Soby Mathewa0fedc42016-06-16 14:52:04 +01001618void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint)
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001619{
Dan Handleye2712bc2014-04-10 15:37:22 +01001620 cpu_context_t *ctx;
1621 el3_state_t *state;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001622
Andrew Thoelkea2f65532014-05-14 17:09:32 +01001623 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00001624 assert(ctx != NULL);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001625
Andrew Thoelke4e126072014-06-04 21:10:52 +01001626 /* Populate EL3 state so that ERET jumps to the correct entry */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001627 state = get_el3state_ctx(ctx);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001628 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001629}
1630
1631/*******************************************************************************
Andrew Thoelke4e126072014-06-04 21:10:52 +01001632 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context'
1633 * pertaining to the given security state
Achin Gupta607084e2014-02-09 18:24:19 +00001634 ******************************************************************************/
Andrew Thoelke4e126072014-06-04 21:10:52 +01001635void cm_set_elr_spsr_el3(uint32_t security_state,
Soby Mathewa0fedc42016-06-16 14:52:04 +01001636 uintptr_t entrypoint, uint32_t spsr)
Achin Gupta607084e2014-02-09 18:24:19 +00001637{
Dan Handleye2712bc2014-04-10 15:37:22 +01001638 cpu_context_t *ctx;
1639 el3_state_t *state;
Achin Gupta607084e2014-02-09 18:24:19 +00001640
Andrew Thoelkea2f65532014-05-14 17:09:32 +01001641 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00001642 assert(ctx != NULL);
Achin Gupta607084e2014-02-09 18:24:19 +00001643
1644 /* Populate EL3 state so that ERET jumps to the correct entry */
1645 state = get_el3state_ctx(ctx);
1646 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
Andrew Thoelke4e126072014-06-04 21:10:52 +01001647 write_ctx_reg(state, CTX_SPSR_EL3, spsr);
Achin Gupta607084e2014-02-09 18:24:19 +00001648}
1649
1650/*******************************************************************************
Achin Gupta27b895e2014-05-04 18:38:28 +01001651 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context'
1652 * pertaining to the given security state using the value and bit position
1653 * specified in the parameters. It preserves all other bits.
1654 ******************************************************************************/
1655void cm_write_scr_el3_bit(uint32_t security_state,
1656 uint32_t bit_pos,
1657 uint32_t value)
1658{
1659 cpu_context_t *ctx;
1660 el3_state_t *state;
Louis Mayencourt1c819c32020-01-24 13:30:28 +00001661 u_register_t scr_el3;
Achin Gupta27b895e2014-05-04 18:38:28 +01001662
Andrew Thoelkea2f65532014-05-14 17:09:32 +01001663 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00001664 assert(ctx != NULL);
Achin Gupta27b895e2014-05-04 18:38:28 +01001665
1666 /* Ensure that the bit position is a valid one */
Jimmy Brissoned202072020-08-04 16:18:52 -05001667 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U);
Achin Gupta27b895e2014-05-04 18:38:28 +01001668
1669 /* Ensure that the 'value' is only a bit wide */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00001670 assert(value <= 1U);
Achin Gupta27b895e2014-05-04 18:38:28 +01001671
1672 /*
1673 * Get the SCR_EL3 value from the cpu context, clear the desired bit
1674 * and set it to its new value.
1675 */
1676 state = get_el3state_ctx(ctx);
Louis Mayencourt1c819c32020-01-24 13:30:28 +00001677 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
Jimmy Brissoned202072020-08-04 16:18:52 -05001678 scr_el3 &= ~(1UL << bit_pos);
Louis Mayencourt1c819c32020-01-24 13:30:28 +00001679 scr_el3 |= (u_register_t)value << bit_pos;
Achin Gupta27b895e2014-05-04 18:38:28 +01001680 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
1681}
1682
1683/*******************************************************************************
1684 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the
1685 * given security state.
1686 ******************************************************************************/
Louis Mayencourt1c819c32020-01-24 13:30:28 +00001687u_register_t cm_get_scr_el3(uint32_t security_state)
Achin Gupta27b895e2014-05-04 18:38:28 +01001688{
1689 cpu_context_t *ctx;
1690 el3_state_t *state;
1691
Andrew Thoelkea2f65532014-05-14 17:09:32 +01001692 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00001693 assert(ctx != NULL);
Achin Gupta27b895e2014-05-04 18:38:28 +01001694
1695 /* Populate EL3 state so that ERET jumps to the correct entry */
1696 state = get_el3state_ctx(ctx);
Louis Mayencourt1c819c32020-01-24 13:30:28 +00001697 return read_ctx_reg(state, CTX_SCR_EL3);
Achin Gupta27b895e2014-05-04 18:38:28 +01001698}
1699
1700/*******************************************************************************
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001701 * This function is used to program the context that's used for exception
1702 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for
1703 * the required security state
Achin Gupta7aea9082014-02-01 07:51:28 +00001704 ******************************************************************************/
1705void cm_set_next_eret_context(uint32_t security_state)
1706{
Dan Handleye2712bc2014-04-10 15:37:22 +01001707 cpu_context_t *ctx;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001708
Andrew Thoelkea2f65532014-05-14 17:09:32 +01001709 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00001710 assert(ctx != NULL);
Achin Gupta7aea9082014-02-01 07:51:28 +00001711
Andrew Thoelke4e126072014-06-04 21:10:52 +01001712 cm_set_next_context(ctx);
Achin Gupta7aea9082014-02-01 07:51:28 +00001713}