Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 1 | /* |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 2 | * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 7 | #include <assert.h> |
| 8 | #include <stdbool.h> |
| 9 | #include <string.h> |
| 10 | |
| 11 | #include <platform_def.h> |
| 12 | |
Achin Gupta | 27b895e | 2014-05-04 18:38:28 +0100 | [diff] [blame] | 13 | #include <arch.h> |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 14 | #include <arch_helpers.h> |
Soby Mathew | 830f0ad | 2019-07-12 09:23:38 +0100 | [diff] [blame] | 15 | #include <arch_features.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 16 | #include <bl31/interrupt_mgmt.h> |
| 17 | #include <common/bl_common.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 18 | #include <context.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 19 | #include <lib/el3_runtime/context_mgmt.h> |
| 20 | #include <lib/el3_runtime/pubsub_events.h> |
| 21 | #include <lib/extensions/amu.h> |
| 22 | #include <lib/extensions/mpam.h> |
| 23 | #include <lib/extensions/spe.h> |
| 24 | #include <lib/extensions/sve.h> |
Manish V Badarkhe | f356f7e | 2021-06-29 11:44:20 +0100 | [diff] [blame^] | 25 | #include <lib/extensions/sys_reg_trace.h> |
Manish V Badarkhe | 20df29c | 2021-07-02 09:10:56 +0100 | [diff] [blame] | 26 | #include <lib/extensions/trbe.h> |
johpow01 | 3e24c16 | 2020-04-22 14:05:13 -0500 | [diff] [blame] | 27 | #include <lib/extensions/twed.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 28 | #include <lib/utils.h> |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 29 | |
Arunachalam Ganapathy | cac7d16 | 2021-07-08 09:35:57 +0100 | [diff] [blame] | 30 | static void enable_extensions_secure(cpu_context_t *ctx); |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 31 | |
| 32 | /******************************************************************************* |
| 33 | * Context management library initialisation routine. This library is used by |
| 34 | * runtime services to share pointers to 'cpu_context' structures for the secure |
| 35 | * and non-secure states. Management of the structures and their associated |
| 36 | * memory is not done by the context management library e.g. the PSCI service |
| 37 | * manages the cpu context used for entry from and exit to the non-secure state. |
| 38 | * The Secure payload dispatcher service manages the context(s) corresponding to |
| 39 | * the secure state. It also uses this library to get access to the non-secure |
| 40 | * state cpu context pointers. |
| 41 | * Lastly, this library provides the api to make SP_EL3 point to the cpu context |
| 42 | * which will used for programming an entry into a lower EL. The same context |
| 43 | * will used to save state upon exception entry from that EL. |
| 44 | ******************************************************************************/ |
Daniel Boulby | 5753e49 | 2018-09-20 14:12:46 +0100 | [diff] [blame] | 45 | void __init cm_init(void) |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 46 | { |
| 47 | /* |
| 48 | * The context management library has only global data to intialize, but |
| 49 | * that will be done when the BSS is zeroed out |
| 50 | */ |
| 51 | } |
| 52 | |
| 53 | /******************************************************************************* |
Soby Mathew | b0082d2 | 2015-04-09 13:40:55 +0100 | [diff] [blame] | 54 | * The following function initializes the cpu_context 'ctx' for |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 55 | * first use, and sets the initial entrypoint state as specified by the |
| 56 | * entry_point_info structure. |
| 57 | * |
| 58 | * The security state to initialize is determined by the SECURE attribute |
Antonio Nino Diaz | 28dce9e | 2018-05-22 10:09:10 +0100 | [diff] [blame] | 59 | * of the entry_point_info. |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 60 | * |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 61 | * The EE and ST attributes are used to configure the endianness and secure |
Soby Mathew | b0082d2 | 2015-04-09 13:40:55 +0100 | [diff] [blame] | 62 | * timer availability for the new execution context. |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 63 | * |
| 64 | * To prepare the register state for entry call cm_prepare_el3_exit() and |
| 65 | * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to |
Olivier Deprez | 7d0299f | 2021-05-25 12:06:03 +0200 | [diff] [blame] | 66 | * cm_el1_sysregs_context_restore(). |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 67 | ******************************************************************************/ |
Antonio Nino Diaz | 28dce9e | 2018-05-22 10:09:10 +0100 | [diff] [blame] | 68 | void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 69 | { |
Soby Mathew | b0082d2 | 2015-04-09 13:40:55 +0100 | [diff] [blame] | 70 | unsigned int security_state; |
Louis Mayencourt | 1c819c3 | 2020-01-24 13:30:28 +0000 | [diff] [blame] | 71 | u_register_t scr_el3; |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 72 | el3_state_t *state; |
| 73 | gp_regs_t *gp_regs; |
Deepika Bhavnani | b0f2602 | 2019-09-03 21:08:51 +0300 | [diff] [blame] | 74 | u_register_t sctlr_elx, actlr_elx; |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 75 | |
Antonio Nino Diaz | 864ca6f | 2018-10-31 15:25:35 +0000 | [diff] [blame] | 76 | assert(ctx != NULL); |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 77 | |
Soby Mathew | b0082d2 | 2015-04-09 13:40:55 +0100 | [diff] [blame] | 78 | security_state = GET_SECURITY_STATE(ep->h.attr); |
| 79 | |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 80 | /* Clear any residual register values from the context */ |
Douglas Raillard | a8954fc | 2017-01-26 15:54:44 +0000 | [diff] [blame] | 81 | zeromem(ctx, sizeof(*ctx)); |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 82 | |
| 83 | /* |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 84 | * SCR_EL3 was initialised during reset sequence in macro |
| 85 | * el3_arch_init_common. This code modifies the SCR_EL3 fields that |
| 86 | * affect the next EL. |
| 87 | * |
| 88 | * The following fields are initially set to zero and then updated to |
| 89 | * the required value depending on the state of the SPSR_EL3 and the |
| 90 | * Security state and entrypoint attributes of the next EL. |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 91 | */ |
Louis Mayencourt | 1c819c3 | 2020-01-24 13:30:28 +0000 | [diff] [blame] | 92 | scr_el3 = read_scr(); |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 93 | scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | |
| 94 | SCR_ST_BIT | SCR_HCE_BIT); |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 95 | /* |
| 96 | * SCR_NS: Set the security state of the next EL. |
| 97 | */ |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 98 | if (security_state != SECURE) |
| 99 | scr_el3 |= SCR_NS_BIT; |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 100 | /* |
| 101 | * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next |
| 102 | * Exception level as specified by SPSR. |
| 103 | */ |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 104 | if (GET_RW(ep->spsr) == MODE_RW_64) |
| 105 | scr_el3 |= SCR_RW_BIT; |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 106 | /* |
| 107 | * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical |
| 108 | * Secure timer registers to EL3, from AArch64 state only, if specified |
| 109 | * by the entrypoint attributes. |
| 110 | */ |
Antonio Nino Diaz | 864ca6f | 2018-10-31 15:25:35 +0000 | [diff] [blame] | 111 | if (EP_GET_ST(ep->h.attr) != 0U) |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 112 | scr_el3 |= SCR_ST_BIT; |
| 113 | |
Varun Wadekar | 9223485 | 2020-06-12 10:11:28 -0700 | [diff] [blame] | 114 | #if RAS_TRAP_LOWER_EL_ERR_ACCESS |
| 115 | /* |
| 116 | * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR |
| 117 | * and RAS ERX registers from EL1 and EL2 are trapped to EL3. |
| 118 | */ |
| 119 | scr_el3 |= SCR_TERR_BIT; |
| 120 | #endif |
| 121 | |
Julius Werner | c51a2ec | 2018-08-28 14:45:43 -0700 | [diff] [blame] | 122 | #if !HANDLE_EA_EL3_FIRST |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 123 | /* |
| 124 | * SCR_EL3.EA: Do not route External Abort and SError Interrupt External |
| 125 | * to EL3 when executing at a lower EL. When executing at EL3, External |
| 126 | * Aborts are taken to EL3. |
| 127 | */ |
Gerald Lejeune | 632d6df | 2016-03-22 09:29:23 +0100 | [diff] [blame] | 128 | scr_el3 &= ~SCR_EA_BIT; |
| 129 | #endif |
| 130 | |
Jeenu Viswambharan | f00da74 | 2017-12-08 12:13:51 +0000 | [diff] [blame] | 131 | #if FAULT_INJECTION_SUPPORT |
| 132 | /* Enable fault injection from lower ELs */ |
| 133 | scr_el3 |= SCR_FIEN_BIT; |
| 134 | #endif |
| 135 | |
Antonio Nino Diaz | 594811b | 2019-01-31 11:58:00 +0000 | [diff] [blame] | 136 | #if !CTX_INCLUDE_PAUTH_REGS |
| 137 | /* |
| 138 | * If the pointer authentication registers aren't saved during world |
| 139 | * switches the value of the registers can be leaked from the Secure to |
| 140 | * the Non-secure world. To prevent this, rather than enabling pointer |
| 141 | * authentication everywhere, we only enable it in the Non-secure world. |
| 142 | * |
| 143 | * If the Secure world wants to use pointer authentication, |
| 144 | * CTX_INCLUDE_PAUTH_REGS must be set to 1. |
| 145 | */ |
| 146 | if (security_state == NON_SECURE) |
| 147 | scr_el3 |= SCR_API_BIT | SCR_APK_BIT; |
| 148 | #endif /* !CTX_INCLUDE_PAUTH_REGS */ |
| 149 | |
Alexei Fedorov | af54f6e | 2020-12-01 13:22:25 +0000 | [diff] [blame] | 150 | #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS |
| 151 | /* Get Memory Tagging Extension support level */ |
| 152 | unsigned int mte = get_armv8_5_mte_support(); |
| 153 | #endif |
Soby Mathew | 830f0ad | 2019-07-12 09:23:38 +0100 | [diff] [blame] | 154 | /* |
Justin Chadwell | 1c7c13a | 2019-07-18 14:25:33 +0100 | [diff] [blame] | 155 | * Enable MTE support. Support is enabled unilaterally for the normal |
| 156 | * world, and only for the secure world when CTX_INCLUDE_MTE_REGS is |
| 157 | * set. |
Soby Mathew | 830f0ad | 2019-07-12 09:23:38 +0100 | [diff] [blame] | 158 | */ |
Justin Chadwell | 1c7c13a | 2019-07-18 14:25:33 +0100 | [diff] [blame] | 159 | #if CTX_INCLUDE_MTE_REGS |
Alexei Fedorov | af54f6e | 2020-12-01 13:22:25 +0000 | [diff] [blame] | 160 | assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); |
Justin Chadwell | 1c7c13a | 2019-07-18 14:25:33 +0100 | [diff] [blame] | 161 | scr_el3 |= SCR_ATA_BIT; |
| 162 | #else |
Alexei Fedorov | af54f6e | 2020-12-01 13:22:25 +0000 | [diff] [blame] | 163 | /* |
| 164 | * When MTE is only implemented at EL0, it can be enabled |
| 165 | * across both worlds as no MTE registers are used. |
| 166 | */ |
| 167 | if ((mte == MTE_IMPLEMENTED_EL0) || |
| 168 | /* |
| 169 | * When MTE is implemented at all ELs, it can be only enabled |
| 170 | * in Non-Secure world without register saving. |
| 171 | */ |
| 172 | (((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)) && |
| 173 | (security_state == NON_SECURE))) { |
Justin Chadwell | 1c7c13a | 2019-07-18 14:25:33 +0100 | [diff] [blame] | 174 | scr_el3 |= SCR_ATA_BIT; |
Soby Mathew | 830f0ad | 2019-07-12 09:23:38 +0100 | [diff] [blame] | 175 | } |
Alexei Fedorov | af54f6e | 2020-12-01 13:22:25 +0000 | [diff] [blame] | 176 | #endif /* CTX_INCLUDE_MTE_REGS */ |
Soby Mathew | 830f0ad | 2019-07-12 09:23:38 +0100 | [diff] [blame] | 177 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 178 | #ifdef IMAGE_BL31 |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 179 | /* |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 180 | * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 181 | * indicated by the interrupt routing model for BL31. |
Yatharth Kochar | 6c0566c | 2015-10-02 17:56:48 +0100 | [diff] [blame] | 182 | */ |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 183 | scr_el3 |= get_scr_el3_from_routing_model(security_state); |
Max Shvetsov | c450277 | 2021-03-22 11:59:37 +0000 | [diff] [blame] | 184 | #endif |
Arunachalam Ganapathy | cac7d16 | 2021-07-08 09:35:57 +0100 | [diff] [blame] | 185 | |
| 186 | /* Save the initialized value of CPTR_EL3 register */ |
| 187 | write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); |
Max Shvetsov | c450277 | 2021-03-22 11:59:37 +0000 | [diff] [blame] | 188 | if (security_state == SECURE) { |
Arunachalam Ganapathy | cac7d16 | 2021-07-08 09:35:57 +0100 | [diff] [blame] | 189 | enable_extensions_secure(ctx); |
Max Shvetsov | c450277 | 2021-03-22 11:59:37 +0000 | [diff] [blame] | 190 | } |
Max Shvetsov | c450277 | 2021-03-22 11:59:37 +0000 | [diff] [blame] | 191 | |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 192 | /* |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 193 | * SCR_EL3.HCE: Enable HVC instructions if next execution state is |
| 194 | * AArch64 and next EL is EL2, or if next execution state is AArch32 and |
| 195 | * next mode is Hyp. |
Jimmy Brisson | ecc3c67 | 2020-04-16 10:47:56 -0500 | [diff] [blame] | 196 | * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the |
| 197 | * same conditions as HVC instructions and when the processor supports |
| 198 | * ARMv8.6-FGT. |
Jimmy Brisson | 8357389 | 2020-04-16 10:48:02 -0500 | [diff] [blame] | 199 | * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) |
| 200 | * CNTPOFF_EL2 register under the same conditions as HVC instructions |
| 201 | * and when the processor supports ECV. |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 202 | */ |
Antonio Nino Diaz | 864ca6f | 2018-10-31 15:25:35 +0000 | [diff] [blame] | 203 | if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) |
| 204 | || ((GET_RW(ep->spsr) != MODE_RW_64) |
| 205 | && (GET_M32(ep->spsr) == MODE32_hyp))) { |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 206 | scr_el3 |= SCR_HCE_BIT; |
Jimmy Brisson | ecc3c67 | 2020-04-16 10:47:56 -0500 | [diff] [blame] | 207 | |
| 208 | if (is_armv8_6_fgt_present()) { |
| 209 | scr_el3 |= SCR_FGTEN_BIT; |
| 210 | } |
Jimmy Brisson | 8357389 | 2020-04-16 10:48:02 -0500 | [diff] [blame] | 211 | |
| 212 | if (get_armv8_6_ecv_support() |
| 213 | == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) { |
| 214 | scr_el3 |= SCR_ECVEN_BIT; |
| 215 | } |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 216 | } |
| 217 | |
Achin Gupta | 023c155 | 2019-10-11 14:44:05 +0100 | [diff] [blame] | 218 | /* Enable S-EL2 if the next EL is EL2 and security state is secure */ |
Artsem Artsemenka | a533447 | 2019-11-26 16:40:31 +0000 | [diff] [blame] | 219 | if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) { |
| 220 | if (GET_RW(ep->spsr) != MODE_RW_64) { |
| 221 | ERROR("S-EL2 can not be used in AArch32."); |
| 222 | panic(); |
| 223 | } |
| 224 | |
Achin Gupta | 023c155 | 2019-10-11 14:44:05 +0100 | [diff] [blame] | 225 | scr_el3 |= SCR_EEL2_BIT; |
Artsem Artsemenka | a533447 | 2019-11-26 16:40:31 +0000 | [diff] [blame] | 226 | } |
Achin Gupta | 023c155 | 2019-10-11 14:44:05 +0100 | [diff] [blame] | 227 | |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 228 | /* |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 229 | * FEAT_AMUv1p1 virtual offset registers are only accessible from EL3 |
| 230 | * and EL2, when clear, this bit traps accesses from EL2 so we set it |
| 231 | * to 1 when EL2 is present. |
| 232 | */ |
| 233 | if (is_armv8_6_feat_amuv1p1_present() && |
| 234 | (el_implemented(2) != EL_IMPL_NONE)) { |
| 235 | scr_el3 |= SCR_AMVOFFEN_BIT; |
| 236 | } |
| 237 | |
| 238 | /* |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 239 | * Initialise SCTLR_EL1 to the reset value corresponding to the target |
| 240 | * execution state setting all fields rather than relying of the hw. |
| 241 | * Some fields have architecturally UNKNOWN reset values and these are |
| 242 | * set to zero. |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 243 | * |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 244 | * SCTLR.EE: Endianness is taken from the entrypoint attributes. |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 245 | * |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 246 | * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as |
| 247 | * required by PSCI specification) |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 248 | */ |
Antonio Nino Diaz | 864ca6f | 2018-10-31 15:25:35 +0000 | [diff] [blame] | 249 | sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U; |
Jens Wiklander | c93c9df | 2014-09-04 10:23:27 +0200 | [diff] [blame] | 250 | if (GET_RW(ep->spsr) == MODE_RW_64) |
| 251 | sctlr_elx |= SCTLR_EL1_RES1; |
Soby Mathew | a993c42 | 2016-09-29 14:15:57 +0100 | [diff] [blame] | 252 | else { |
Soby Mathew | a993c42 | 2016-09-29 14:15:57 +0100 | [diff] [blame] | 253 | /* |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 254 | * If the target execution state is AArch32 then the following |
| 255 | * fields need to be set. |
| 256 | * |
| 257 | * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE |
| 258 | * instructions are not trapped to EL1. |
| 259 | * |
| 260 | * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI |
| 261 | * instructions are not trapped to EL1. |
| 262 | * |
| 263 | * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the |
| 264 | * CP15DMB, CP15DSB, and CP15ISB instructions. |
Soby Mathew | a993c42 | 2016-09-29 14:15:57 +0100 | [diff] [blame] | 265 | */ |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 266 | sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT |
| 267 | | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; |
Soby Mathew | a993c42 | 2016-09-29 14:15:57 +0100 | [diff] [blame] | 268 | } |
| 269 | |
Louis Mayencourt | 78a0aed | 2019-02-20 12:11:41 +0000 | [diff] [blame] | 270 | #if ERRATA_A75_764081 |
| 271 | /* |
| 272 | * If workaround of errata 764081 for Cortex-A75 is used then set |
| 273 | * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. |
| 274 | */ |
| 275 | sctlr_elx |= SCTLR_IESB_BIT; |
| 276 | #endif |
| 277 | |
johpow01 | 3e24c16 | 2020-04-22 14:05:13 -0500 | [diff] [blame] | 278 | /* Enable WFE trap delay in SCR_EL3 if supported and configured */ |
| 279 | if (is_armv8_6_twed_present()) { |
| 280 | uint32_t delay = plat_arm_set_twedel_scr_el3(); |
| 281 | |
| 282 | if (delay != TWED_DISABLED) { |
| 283 | /* Make sure delay value fits */ |
| 284 | assert((delay & ~SCR_TWEDEL_MASK) == 0U); |
| 285 | |
| 286 | /* Set delay in SCR_EL3 */ |
| 287 | scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); |
| 288 | scr_el3 |= ((delay & SCR_TWEDEL_MASK) |
| 289 | << SCR_TWEDEL_SHIFT); |
| 290 | |
| 291 | /* Enable WFE delay */ |
| 292 | scr_el3 |= SCR_TWEDEn_BIT; |
| 293 | } |
| 294 | } |
| 295 | |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 296 | /* |
| 297 | * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 |
Olivier Deprez | 7d0299f | 2021-05-25 12:06:03 +0200 | [diff] [blame] | 298 | * and other EL2 registers are set up by cm_prepare_el3_exit() as they |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 299 | * are not part of the stored cpu_context. |
| 300 | */ |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 301 | write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 302 | |
Varun Wadekar | b6dd0b3 | 2018-05-08 10:52:36 -0700 | [diff] [blame] | 303 | /* |
| 304 | * Base the context ACTLR_EL1 on the current value, as it is |
| 305 | * implementation defined. The context restore process will write |
| 306 | * the value from the context to the actual register and can cause |
| 307 | * problems for processor cores that don't expect certain bits to |
| 308 | * be zero. |
| 309 | */ |
| 310 | actlr_elx = read_actlr_el1(); |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 311 | write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); |
Varun Wadekar | b6dd0b3 | 2018-05-08 10:52:36 -0700 | [diff] [blame] | 312 | |
Alexei Fedorov | 503bbf3 | 2019-08-13 15:17:53 +0100 | [diff] [blame] | 313 | /* |
| 314 | * Populate EL3 state so that we've the right context |
| 315 | * before doing ERET |
| 316 | */ |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 317 | state = get_el3state_ctx(ctx); |
| 318 | write_ctx_reg(state, CTX_SCR_EL3, scr_el3); |
| 319 | write_ctx_reg(state, CTX_ELR_EL3, ep->pc); |
| 320 | write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); |
| 321 | |
| 322 | /* |
| 323 | * Store the X0-X7 value from the entrypoint into the context |
| 324 | * Use memcpy as we are in control of the layout of the structures |
| 325 | */ |
| 326 | gp_regs = get_gpregs_ctx(ctx); |
| 327 | memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); |
| 328 | } |
| 329 | |
| 330 | /******************************************************************************* |
Dimitris Papastamos | 1e6f93e | 2017-11-07 09:55:29 +0000 | [diff] [blame] | 331 | * Enable architecture extensions on first entry to Non-secure world. |
| 332 | * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise |
| 333 | * it is zero. |
| 334 | ******************************************************************************/ |
Arunachalam Ganapathy | cac7d16 | 2021-07-08 09:35:57 +0100 | [diff] [blame] | 335 | static void enable_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) |
Dimitris Papastamos | 1e6f93e | 2017-11-07 09:55:29 +0000 | [diff] [blame] | 336 | { |
| 337 | #if IMAGE_BL31 |
Dimitris Papastamos | 5bdbb47 | 2017-10-13 12:06:06 +0100 | [diff] [blame] | 338 | #if ENABLE_SPE_FOR_LOWER_ELS |
| 339 | spe_enable(el2_unused); |
| 340 | #endif |
Dimitris Papastamos | e08005a | 2017-10-12 13:02:29 +0100 | [diff] [blame] | 341 | |
| 342 | #if ENABLE_AMU |
Arunachalam Ganapathy | cac7d16 | 2021-07-08 09:35:57 +0100 | [diff] [blame] | 343 | amu_enable(el2_unused, ctx); |
Dimitris Papastamos | e08005a | 2017-10-12 13:02:29 +0100 | [diff] [blame] | 344 | #endif |
David Cunado | ce88eee | 2017-10-20 11:30:57 +0100 | [diff] [blame] | 345 | |
Arunachalam Ganapathy | cac7d16 | 2021-07-08 09:35:57 +0100 | [diff] [blame] | 346 | #if ENABLE_SVE_FOR_NS |
| 347 | sve_enable(ctx); |
| 348 | #endif |
| 349 | |
Jeenu Viswambharan | 2da918c | 2018-07-31 16:13:33 +0100 | [diff] [blame] | 350 | #if ENABLE_MPAM_FOR_LOWER_ELS |
| 351 | mpam_enable(el2_unused); |
| 352 | #endif |
Manish V Badarkhe | 20df29c | 2021-07-02 09:10:56 +0100 | [diff] [blame] | 353 | |
| 354 | #if ENABLE_TRBE_FOR_NS |
| 355 | trbe_enable(); |
| 356 | #endif /* ENABLE_TRBE_FOR_NS */ |
| 357 | |
Manish V Badarkhe | f356f7e | 2021-06-29 11:44:20 +0100 | [diff] [blame^] | 358 | #if ENABLE_SYS_REG_TRACE_FOR_NS |
| 359 | sys_reg_trace_enable(ctx); |
| 360 | #endif /* ENABLE_SYS_REG_TRACE_FOR_NS */ |
| 361 | |
Dimitris Papastamos | 1e6f93e | 2017-11-07 09:55:29 +0000 | [diff] [blame] | 362 | #endif |
| 363 | } |
| 364 | |
| 365 | /******************************************************************************* |
Arunachalam Ganapathy | cac7d16 | 2021-07-08 09:35:57 +0100 | [diff] [blame] | 366 | * Enable architecture extensions on first entry to Secure world. |
| 367 | ******************************************************************************/ |
| 368 | static void enable_extensions_secure(cpu_context_t *ctx) |
| 369 | { |
| 370 | #if IMAGE_BL31 |
| 371 | #if ENABLE_SVE_FOR_SWD |
| 372 | sve_enable(ctx); |
| 373 | #endif |
| 374 | #endif |
| 375 | } |
| 376 | |
| 377 | /******************************************************************************* |
Soby Mathew | b0082d2 | 2015-04-09 13:40:55 +0100 | [diff] [blame] | 378 | * The following function initializes the cpu_context for a CPU specified by |
| 379 | * its `cpu_idx` for first use, and sets the initial entrypoint state as |
| 380 | * specified by the entry_point_info structure. |
| 381 | ******************************************************************************/ |
| 382 | void cm_init_context_by_index(unsigned int cpu_idx, |
| 383 | const entry_point_info_t *ep) |
| 384 | { |
| 385 | cpu_context_t *ctx; |
| 386 | ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); |
Antonio Nino Diaz | 28dce9e | 2018-05-22 10:09:10 +0100 | [diff] [blame] | 387 | cm_setup_context(ctx, ep); |
Soby Mathew | b0082d2 | 2015-04-09 13:40:55 +0100 | [diff] [blame] | 388 | } |
| 389 | |
| 390 | /******************************************************************************* |
| 391 | * The following function initializes the cpu_context for the current CPU |
| 392 | * for first use, and sets the initial entrypoint state as specified by the |
| 393 | * entry_point_info structure. |
| 394 | ******************************************************************************/ |
| 395 | void cm_init_my_context(const entry_point_info_t *ep) |
| 396 | { |
| 397 | cpu_context_t *ctx; |
| 398 | ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); |
Antonio Nino Diaz | 28dce9e | 2018-05-22 10:09:10 +0100 | [diff] [blame] | 399 | cm_setup_context(ctx, ep); |
Soby Mathew | b0082d2 | 2015-04-09 13:40:55 +0100 | [diff] [blame] | 400 | } |
| 401 | |
| 402 | /******************************************************************************* |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 403 | * Prepare the CPU system registers for first entry into secure or normal world |
| 404 | * |
| 405 | * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized |
| 406 | * If execution is requested to non-secure EL1 or svc mode, and the CPU supports |
| 407 | * EL2 then EL2 is disabled by configuring all necessary EL2 registers. |
| 408 | * For all entries, the EL1 registers are initialized from the cpu_context |
| 409 | ******************************************************************************/ |
| 410 | void cm_prepare_el3_exit(uint32_t security_state) |
| 411 | { |
Louis Mayencourt | 1c819c3 | 2020-01-24 13:30:28 +0000 | [diff] [blame] | 412 | u_register_t sctlr_elx, scr_el3, mdcr_el2; |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 413 | cpu_context_t *ctx = cm_get_context(security_state); |
Antonio Nino Diaz | 033b4bb | 2018-10-25 16:52:26 +0100 | [diff] [blame] | 414 | bool el2_unused = false; |
Antonio Nino Diaz | 864ca6f | 2018-10-31 15:25:35 +0000 | [diff] [blame] | 415 | uint64_t hcr_el2 = 0U; |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 416 | |
Antonio Nino Diaz | 864ca6f | 2018-10-31 15:25:35 +0000 | [diff] [blame] | 417 | assert(ctx != NULL); |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 418 | |
| 419 | if (security_state == NON_SECURE) { |
Louis Mayencourt | 1c819c3 | 2020-01-24 13:30:28 +0000 | [diff] [blame] | 420 | scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), |
Antonio Nino Diaz | 864ca6f | 2018-10-31 15:25:35 +0000 | [diff] [blame] | 421 | CTX_SCR_EL3); |
| 422 | if ((scr_el3 & SCR_HCE_BIT) != 0U) { |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 423 | /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 424 | sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), |
Antonio Nino Diaz | 864ca6f | 2018-10-31 15:25:35 +0000 | [diff] [blame] | 425 | CTX_SCTLR_EL1); |
Ken Kuang | 00eac15 | 2017-08-23 16:03:29 +0800 | [diff] [blame] | 426 | sctlr_elx &= SCTLR_EE_BIT; |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 427 | sctlr_elx |= SCTLR_EL2_RES1; |
Louis Mayencourt | 78a0aed | 2019-02-20 12:11:41 +0000 | [diff] [blame] | 428 | #if ERRATA_A75_764081 |
| 429 | /* |
| 430 | * If workaround of errata 764081 for Cortex-A75 is used |
| 431 | * then set SCTLR_EL2.IESB to enable Implicit Error |
| 432 | * Synchronization Barrier. |
| 433 | */ |
| 434 | sctlr_elx |= SCTLR_IESB_BIT; |
| 435 | #endif |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 436 | write_sctlr_el2(sctlr_elx); |
Antonio Nino Diaz | 864ca6f | 2018-10-31 15:25:35 +0000 | [diff] [blame] | 437 | } else if (el_implemented(2) != EL_IMPL_NONE) { |
Antonio Nino Diaz | 033b4bb | 2018-10-25 16:52:26 +0100 | [diff] [blame] | 438 | el2_unused = true; |
Dimitris Papastamos | 1e6f93e | 2017-11-07 09:55:29 +0000 | [diff] [blame] | 439 | |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 440 | /* |
| 441 | * EL2 present but unused, need to disable safely. |
| 442 | * SCTLR_EL2 can be ignored in this case. |
| 443 | * |
Jeenu Viswambharan | cbad661 | 2018-08-15 14:29:29 +0100 | [diff] [blame] | 444 | * Set EL2 register width appropriately: Set HCR_EL2 |
| 445 | * field to match SCR_EL3.RW. |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 446 | */ |
Antonio Nino Diaz | 864ca6f | 2018-10-31 15:25:35 +0000 | [diff] [blame] | 447 | if ((scr_el3 & SCR_RW_BIT) != 0U) |
Jeenu Viswambharan | cbad661 | 2018-08-15 14:29:29 +0100 | [diff] [blame] | 448 | hcr_el2 |= HCR_RW_BIT; |
| 449 | |
| 450 | /* |
| 451 | * For Armv8.3 pointer authentication feature, disable |
| 452 | * traps to EL2 when accessing key registers or using |
| 453 | * pointer authentication instructions from lower ELs. |
| 454 | */ |
| 455 | hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); |
| 456 | |
| 457 | write_hcr_el2(hcr_el2); |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 458 | |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 459 | /* |
| 460 | * Initialise CPTR_EL2 setting all fields rather than |
| 461 | * relying on the hw. All fields have architecturally |
| 462 | * UNKNOWN reset values. |
| 463 | * |
| 464 | * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 |
| 465 | * accesses to the CPACR_EL1 or CPACR from both |
| 466 | * Execution states do not trap to EL2. |
| 467 | * |
| 468 | * CPTR_EL2.TTA: Set to zero so that Non-secure System |
| 469 | * register accesses to the trace registers from both |
| 470 | * Execution states do not trap to EL2. |
Manish V Badarkhe | f356f7e | 2021-06-29 11:44:20 +0100 | [diff] [blame^] | 471 | * If PE trace unit System registers are not implemented |
| 472 | * then this bit is reserved, and must be set to zero. |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 473 | * |
| 474 | * CPTR_EL2.TFP: Set to zero so that Non-secure accesses |
| 475 | * to SIMD and floating-point functionality from both |
| 476 | * Execution states do not trap to EL2. |
| 477 | */ |
| 478 | write_cptr_el2(CPTR_EL2_RESET_VAL & |
| 479 | ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT |
| 480 | | CPTR_EL2_TFP_BIT)); |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 481 | |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 482 | /* |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 483 | * Initialise CNTHCTL_EL2. All fields are |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 484 | * architecturally UNKNOWN on reset and are set to zero |
| 485 | * except for field(s) listed below. |
| 486 | * |
| 487 | * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to |
| 488 | * Hyp mode of Non-secure EL0 and EL1 accesses to the |
| 489 | * physical timer registers. |
| 490 | * |
| 491 | * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to |
| 492 | * Hyp mode of Non-secure EL0 and EL1 accesses to the |
| 493 | * physical counter registers. |
| 494 | */ |
| 495 | write_cnthctl_el2(CNTHCTL_RESET_VAL | |
| 496 | EL1PCEN_BIT | EL1PCTEN_BIT); |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 497 | |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 498 | /* |
| 499 | * Initialise CNTVOFF_EL2 to zero as it resets to an |
| 500 | * architecturally UNKNOWN value. |
| 501 | */ |
Soby Mathew | feddfcf | 2014-08-29 14:41:58 +0100 | [diff] [blame] | 502 | write_cntvoff_el2(0); |
| 503 | |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 504 | /* |
| 505 | * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and |
| 506 | * MPIDR_EL1 respectively. |
| 507 | */ |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 508 | write_vpidr_el2(read_midr_el1()); |
| 509 | write_vmpidr_el2(read_mpidr_el1()); |
Sandrine Bailleux | 8b0eafe | 2015-11-25 17:00:44 +0000 | [diff] [blame] | 510 | |
| 511 | /* |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 512 | * Initialise VTTBR_EL2. All fields are architecturally |
| 513 | * UNKNOWN on reset. |
| 514 | * |
| 515 | * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage |
| 516 | * 2 address translation is disabled, cache maintenance |
| 517 | * operations depend on the VMID. |
| 518 | * |
| 519 | * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address |
| 520 | * translation is disabled. |
Sandrine Bailleux | 8b0eafe | 2015-11-25 17:00:44 +0000 | [diff] [blame] | 521 | */ |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 522 | write_vttbr_el2(VTTBR_RESET_VAL & |
| 523 | ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) |
| 524 | | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); |
| 525 | |
David Cunado | 5f55e28 | 2016-10-31 17:37:34 +0000 | [diff] [blame] | 526 | /* |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 527 | * Initialise MDCR_EL2, setting all fields rather than |
| 528 | * relying on hw. Some fields are architecturally |
| 529 | * UNKNOWN on reset. |
| 530 | * |
Alexei Fedorov | 503bbf3 | 2019-08-13 15:17:53 +0100 | [diff] [blame] | 531 | * MDCR_EL2.HLP: Set to one so that event counter |
| 532 | * overflow, that is recorded in PMOVSCLR_EL0[0-30], |
| 533 | * occurs on the increment that changes |
| 534 | * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is |
| 535 | * implemented. This bit is RES0 in versions of the |
| 536 | * architecture earlier than ARMv8.5, setting it to 1 |
| 537 | * doesn't have any effect on them. |
| 538 | * |
| 539 | * MDCR_EL2.TTRF: Set to zero so that access to Trace |
| 540 | * Filter Control register TRFCR_EL1 at EL1 is not |
| 541 | * trapped to EL2. This bit is RES0 in versions of |
| 542 | * the architecture earlier than ARMv8.4. |
| 543 | * |
| 544 | * MDCR_EL2.HPMD: Set to one so that event counting is |
| 545 | * prohibited at EL2. This bit is RES0 in versions of |
| 546 | * the architecture earlier than ARMv8.1, setting it |
| 547 | * to 1 doesn't have any effect on them. |
| 548 | * |
| 549 | * MDCR_EL2.TPMS: Set to zero so that accesses to |
| 550 | * Statistical Profiling control registers from EL1 |
| 551 | * do not trap to EL2. This bit is RES0 when SPE is |
| 552 | * not implemented. |
| 553 | * |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 554 | * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and |
| 555 | * EL1 System register accesses to the Debug ROM |
| 556 | * registers are not trapped to EL2. |
| 557 | * |
| 558 | * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 |
| 559 | * System register accesses to the powerdown debug |
| 560 | * registers are not trapped to EL2. |
| 561 | * |
| 562 | * MDCR_EL2.TDA: Set to zero so that System register |
| 563 | * accesses to the debug registers do not trap to EL2. |
| 564 | * |
| 565 | * MDCR_EL2.TDE: Set to zero so that debug exceptions |
| 566 | * are not routed to EL2. |
| 567 | * |
| 568 | * MDCR_EL2.HPME: Set to zero to disable EL2 Performance |
| 569 | * Monitors. |
| 570 | * |
| 571 | * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and |
| 572 | * EL1 accesses to all Performance Monitors registers |
| 573 | * are not trapped to EL2. |
| 574 | * |
| 575 | * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 |
| 576 | * and EL1 accesses to the PMCR_EL0 or PMCR are not |
| 577 | * trapped to EL2. |
| 578 | * |
| 579 | * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the |
| 580 | * architecturally-defined reset value. |
Manish V Badarkhe | e1cccb4 | 2021-06-23 20:02:39 +0100 | [diff] [blame] | 581 | * |
| 582 | * MDCR_EL2.E2TB: Set to zero so that the trace Buffer |
| 583 | * owning exception level is NS-EL1 and, tracing is |
| 584 | * prohibited at NS-EL2. These bits are RES0 when |
| 585 | * FEAT_TRBE is not implemented. |
David Cunado | 5f55e28 | 2016-10-31 17:37:34 +0000 | [diff] [blame] | 586 | */ |
Alexei Fedorov | 503bbf3 | 2019-08-13 15:17:53 +0100 | [diff] [blame] | 587 | mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | |
| 588 | MDCR_EL2_HPMD) | |
| 589 | ((read_pmcr_el0() & PMCR_EL0_N_BITS) |
| 590 | >> PMCR_EL0_N_SHIFT)) & |
| 591 | ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | |
| 592 | MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | |
| 593 | MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | |
| 594 | MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | |
Manish V Badarkhe | e1cccb4 | 2021-06-23 20:02:39 +0100 | [diff] [blame] | 595 | MDCR_EL2_TPMCR_BIT | |
| 596 | MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)); |
dp-arm | ee3457b | 2017-05-23 09:32:49 +0100 | [diff] [blame] | 597 | |
dp-arm | ee3457b | 2017-05-23 09:32:49 +0100 | [diff] [blame] | 598 | write_mdcr_el2(mdcr_el2); |
| 599 | |
David Cunado | c14b08e | 2016-11-25 00:21:59 +0000 | [diff] [blame] | 600 | /* |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 601 | * Initialise HSTR_EL2. All fields are architecturally |
| 602 | * UNKNOWN on reset. |
| 603 | * |
| 604 | * HSTR_EL2.T<n>: Set all these fields to zero so that |
| 605 | * Non-secure EL0 or EL1 accesses to System registers |
| 606 | * do not trap to EL2. |
David Cunado | c14b08e | 2016-11-25 00:21:59 +0000 | [diff] [blame] | 607 | */ |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 608 | write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); |
David Cunado | c14b08e | 2016-11-25 00:21:59 +0000 | [diff] [blame] | 609 | /* |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 610 | * Initialise CNTHP_CTL_EL2. All fields are |
| 611 | * architecturally UNKNOWN on reset. |
| 612 | * |
| 613 | * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 |
| 614 | * physical timer and prevent timer interrupts. |
David Cunado | c14b08e | 2016-11-25 00:21:59 +0000 | [diff] [blame] | 615 | */ |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 616 | write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & |
| 617 | ~(CNTHP_CTL_ENABLE_BIT)); |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 618 | } |
Arunachalam Ganapathy | cac7d16 | 2021-07-08 09:35:57 +0100 | [diff] [blame] | 619 | enable_extensions_nonsecure(el2_unused, ctx); |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 620 | } |
| 621 | |
Dimitris Papastamos | a7921b9 | 2017-10-13 15:27:58 +0100 | [diff] [blame] | 622 | cm_el1_sysregs_context_restore(security_state); |
| 623 | cm_set_next_eret_context(security_state); |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 624 | } |
| 625 | |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 626 | #if CTX_INCLUDE_EL2_REGS |
| 627 | /******************************************************************************* |
| 628 | * Save EL2 sysreg context |
| 629 | ******************************************************************************/ |
| 630 | void cm_el2_sysregs_context_save(uint32_t security_state) |
| 631 | { |
| 632 | u_register_t scr_el3 = read_scr(); |
| 633 | |
| 634 | /* |
| 635 | * Always save the non-secure EL2 context, only save the |
| 636 | * S-EL2 context if S-EL2 is enabled. |
| 637 | */ |
| 638 | if ((security_state == NON_SECURE) || |
Ruari Phipps | 4283ed1 | 2020-07-28 11:26:29 +0100 | [diff] [blame] | 639 | ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 640 | cpu_context_t *ctx; |
| 641 | |
| 642 | ctx = cm_get_context(security_state); |
| 643 | assert(ctx != NULL); |
| 644 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 645 | el2_sysregs_context_save(get_el2_sysregs_ctx(ctx)); |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 646 | } |
| 647 | } |
| 648 | |
| 649 | /******************************************************************************* |
| 650 | * Restore EL2 sysreg context |
| 651 | ******************************************************************************/ |
| 652 | void cm_el2_sysregs_context_restore(uint32_t security_state) |
| 653 | { |
| 654 | u_register_t scr_el3 = read_scr(); |
| 655 | |
| 656 | /* |
| 657 | * Always restore the non-secure EL2 context, only restore the |
| 658 | * S-EL2 context if S-EL2 is enabled. |
| 659 | */ |
| 660 | if ((security_state == NON_SECURE) || |
Ruari Phipps | 4283ed1 | 2020-07-28 11:26:29 +0100 | [diff] [blame] | 661 | ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 662 | cpu_context_t *ctx; |
| 663 | |
| 664 | ctx = cm_get_context(security_state); |
| 665 | assert(ctx != NULL); |
| 666 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 667 | el2_sysregs_context_restore(get_el2_sysregs_ctx(ctx)); |
Max Shvetsov | bdf502d | 2020-02-25 13:56:19 +0000 | [diff] [blame] | 668 | } |
| 669 | } |
| 670 | #endif /* CTX_INCLUDE_EL2_REGS */ |
| 671 | |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 672 | /******************************************************************************* |
Soby Mathew | 2ed46e9 | 2014-07-04 16:02:26 +0100 | [diff] [blame] | 673 | * The next four functions are used by runtime services to save and restore |
| 674 | * EL1 context on the 'cpu_context' structure for the specified security |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 675 | * state. |
| 676 | ******************************************************************************/ |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 677 | void cm_el1_sysregs_context_save(uint32_t security_state) |
| 678 | { |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 679 | cpu_context_t *ctx; |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 680 | |
Andrew Thoelke | a2f6553 | 2014-05-14 17:09:32 +0100 | [diff] [blame] | 681 | ctx = cm_get_context(security_state); |
Antonio Nino Diaz | 864ca6f | 2018-10-31 15:25:35 +0000 | [diff] [blame] | 682 | assert(ctx != NULL); |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 683 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 684 | el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); |
Dimitris Papastamos | a7921b9 | 2017-10-13 15:27:58 +0100 | [diff] [blame] | 685 | |
| 686 | #if IMAGE_BL31 |
| 687 | if (security_state == SECURE) |
| 688 | PUBLISH_EVENT(cm_exited_secure_world); |
| 689 | else |
| 690 | PUBLISH_EVENT(cm_exited_normal_world); |
| 691 | #endif |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 692 | } |
| 693 | |
| 694 | void cm_el1_sysregs_context_restore(uint32_t security_state) |
| 695 | { |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 696 | cpu_context_t *ctx; |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 697 | |
Andrew Thoelke | a2f6553 | 2014-05-14 17:09:32 +0100 | [diff] [blame] | 698 | ctx = cm_get_context(security_state); |
Antonio Nino Diaz | 864ca6f | 2018-10-31 15:25:35 +0000 | [diff] [blame] | 699 | assert(ctx != NULL); |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 700 | |
Max Shvetsov | c9e2c92 | 2020-02-17 16:15:47 +0000 | [diff] [blame] | 701 | el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); |
Dimitris Papastamos | a7921b9 | 2017-10-13 15:27:58 +0100 | [diff] [blame] | 702 | |
| 703 | #if IMAGE_BL31 |
| 704 | if (security_state == SECURE) |
| 705 | PUBLISH_EVENT(cm_entering_secure_world); |
| 706 | else |
| 707 | PUBLISH_EVENT(cm_entering_normal_world); |
| 708 | #endif |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 709 | } |
| 710 | |
| 711 | /******************************************************************************* |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 712 | * This function populates ELR_EL3 member of 'cpu_context' pertaining to the |
| 713 | * given security state with the given entrypoint |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 714 | ******************************************************************************/ |
Soby Mathew | a0fedc4 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 715 | void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 716 | { |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 717 | cpu_context_t *ctx; |
| 718 | el3_state_t *state; |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 719 | |
Andrew Thoelke | a2f6553 | 2014-05-14 17:09:32 +0100 | [diff] [blame] | 720 | ctx = cm_get_context(security_state); |
Antonio Nino Diaz | 864ca6f | 2018-10-31 15:25:35 +0000 | [diff] [blame] | 721 | assert(ctx != NULL); |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 722 | |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 723 | /* Populate EL3 state so that ERET jumps to the correct entry */ |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 724 | state = get_el3state_ctx(ctx); |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 725 | write_ctx_reg(state, CTX_ELR_EL3, entrypoint); |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 726 | } |
| 727 | |
| 728 | /******************************************************************************* |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 729 | * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' |
| 730 | * pertaining to the given security state |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 731 | ******************************************************************************/ |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 732 | void cm_set_elr_spsr_el3(uint32_t security_state, |
Soby Mathew | a0fedc4 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 733 | uintptr_t entrypoint, uint32_t spsr) |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 734 | { |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 735 | cpu_context_t *ctx; |
| 736 | el3_state_t *state; |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 737 | |
Andrew Thoelke | a2f6553 | 2014-05-14 17:09:32 +0100 | [diff] [blame] | 738 | ctx = cm_get_context(security_state); |
Antonio Nino Diaz | 864ca6f | 2018-10-31 15:25:35 +0000 | [diff] [blame] | 739 | assert(ctx != NULL); |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 740 | |
| 741 | /* Populate EL3 state so that ERET jumps to the correct entry */ |
| 742 | state = get_el3state_ctx(ctx); |
| 743 | write_ctx_reg(state, CTX_ELR_EL3, entrypoint); |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 744 | write_ctx_reg(state, CTX_SPSR_EL3, spsr); |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 745 | } |
| 746 | |
| 747 | /******************************************************************************* |
Achin Gupta | 27b895e | 2014-05-04 18:38:28 +0100 | [diff] [blame] | 748 | * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' |
| 749 | * pertaining to the given security state using the value and bit position |
| 750 | * specified in the parameters. It preserves all other bits. |
| 751 | ******************************************************************************/ |
| 752 | void cm_write_scr_el3_bit(uint32_t security_state, |
| 753 | uint32_t bit_pos, |
| 754 | uint32_t value) |
| 755 | { |
| 756 | cpu_context_t *ctx; |
| 757 | el3_state_t *state; |
Louis Mayencourt | 1c819c3 | 2020-01-24 13:30:28 +0000 | [diff] [blame] | 758 | u_register_t scr_el3; |
Achin Gupta | 27b895e | 2014-05-04 18:38:28 +0100 | [diff] [blame] | 759 | |
Andrew Thoelke | a2f6553 | 2014-05-14 17:09:32 +0100 | [diff] [blame] | 760 | ctx = cm_get_context(security_state); |
Antonio Nino Diaz | 864ca6f | 2018-10-31 15:25:35 +0000 | [diff] [blame] | 761 | assert(ctx != NULL); |
Achin Gupta | 27b895e | 2014-05-04 18:38:28 +0100 | [diff] [blame] | 762 | |
| 763 | /* Ensure that the bit position is a valid one */ |
Jimmy Brisson | ed20207 | 2020-08-04 16:18:52 -0500 | [diff] [blame] | 764 | assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); |
Achin Gupta | 27b895e | 2014-05-04 18:38:28 +0100 | [diff] [blame] | 765 | |
| 766 | /* Ensure that the 'value' is only a bit wide */ |
Antonio Nino Diaz | 864ca6f | 2018-10-31 15:25:35 +0000 | [diff] [blame] | 767 | assert(value <= 1U); |
Achin Gupta | 27b895e | 2014-05-04 18:38:28 +0100 | [diff] [blame] | 768 | |
| 769 | /* |
| 770 | * Get the SCR_EL3 value from the cpu context, clear the desired bit |
| 771 | * and set it to its new value. |
| 772 | */ |
| 773 | state = get_el3state_ctx(ctx); |
Louis Mayencourt | 1c819c3 | 2020-01-24 13:30:28 +0000 | [diff] [blame] | 774 | scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); |
Jimmy Brisson | ed20207 | 2020-08-04 16:18:52 -0500 | [diff] [blame] | 775 | scr_el3 &= ~(1UL << bit_pos); |
Louis Mayencourt | 1c819c3 | 2020-01-24 13:30:28 +0000 | [diff] [blame] | 776 | scr_el3 |= (u_register_t)value << bit_pos; |
Achin Gupta | 27b895e | 2014-05-04 18:38:28 +0100 | [diff] [blame] | 777 | write_ctx_reg(state, CTX_SCR_EL3, scr_el3); |
| 778 | } |
| 779 | |
| 780 | /******************************************************************************* |
| 781 | * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the |
| 782 | * given security state. |
| 783 | ******************************************************************************/ |
Louis Mayencourt | 1c819c3 | 2020-01-24 13:30:28 +0000 | [diff] [blame] | 784 | u_register_t cm_get_scr_el3(uint32_t security_state) |
Achin Gupta | 27b895e | 2014-05-04 18:38:28 +0100 | [diff] [blame] | 785 | { |
| 786 | cpu_context_t *ctx; |
| 787 | el3_state_t *state; |
| 788 | |
Andrew Thoelke | a2f6553 | 2014-05-14 17:09:32 +0100 | [diff] [blame] | 789 | ctx = cm_get_context(security_state); |
Antonio Nino Diaz | 864ca6f | 2018-10-31 15:25:35 +0000 | [diff] [blame] | 790 | assert(ctx != NULL); |
Achin Gupta | 27b895e | 2014-05-04 18:38:28 +0100 | [diff] [blame] | 791 | |
| 792 | /* Populate EL3 state so that ERET jumps to the correct entry */ |
| 793 | state = get_el3state_ctx(ctx); |
Louis Mayencourt | 1c819c3 | 2020-01-24 13:30:28 +0000 | [diff] [blame] | 794 | return read_ctx_reg(state, CTX_SCR_EL3); |
Achin Gupta | 27b895e | 2014-05-04 18:38:28 +0100 | [diff] [blame] | 795 | } |
| 796 | |
| 797 | /******************************************************************************* |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 798 | * This function is used to program the context that's used for exception |
| 799 | * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for |
| 800 | * the required security state |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 801 | ******************************************************************************/ |
| 802 | void cm_set_next_eret_context(uint32_t security_state) |
| 803 | { |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 804 | cpu_context_t *ctx; |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 805 | |
Andrew Thoelke | a2f6553 | 2014-05-14 17:09:32 +0100 | [diff] [blame] | 806 | ctx = cm_get_context(security_state); |
Antonio Nino Diaz | 864ca6f | 2018-10-31 15:25:35 +0000 | [diff] [blame] | 807 | assert(ctx != NULL); |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 808 | |
Andrew Thoelke | 4e12607 | 2014-06-04 21:10:52 +0100 | [diff] [blame] | 809 | cm_set_next_context(ctx); |
Achin Gupta | 7aea908 | 2014-02-01 07:51:28 +0000 | [diff] [blame] | 810 | } |