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Usama Arifbec5afd2020-04-17 16:13:39 +01001/*
annsai017c607f22023-02-20 13:34:57 +00002 * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
Usama Arifbec5afd2020-04-17 16:13:39 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/dts-v1/;
8
Kshitij Sisodiab32a8f42023-08-16 09:46:05 +01009#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/interrupt-controller/irq.h>
Boyan Karatotev192ad5d2023-12-12 15:59:01 +000011#include "platform_def.h"
Boyan Karatotev6ed3bf62023-07-07 13:33:19 +000012#include "tc_vers.dtsi"
Boyan Karatotev9ac73a42023-11-14 09:38:08 +000013#if TARGET_FLAVOUR_FVP
14#include "tc_fvp.dtsi"
15#endif /* TARGET_FLAVOUR_FVP */
Kshitij Sisodiab32a8f42023-08-16 09:46:05 +010016
Usama Arifbec5afd2020-04-17 16:13:39 +010017/ {
Usama Ariff1513622021-04-09 17:07:41 +010018 compatible = "arm,tc";
Usama Arifbec5afd2020-04-17 16:13:39 +010019 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
22
23 aliases {
Boyan Karatotev13b8e742023-11-14 13:57:56 +000024 serial0 = &os_uart;
Usama Arifbec5afd2020-04-17 16:13:39 +010025 };
26
27 chosen {
Boyan Karatotev95562762023-11-15 11:54:33 +000028 stdout-path = STDOUT_PATH;
Ben Horgan7160e0d2023-12-11 16:01:10 +000029 /*
30 * Add some dummy entropy for Linux so it
31 * doesn't delay the boot waiting for it.
32 */
33 rng-seed = <0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
34 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
35 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
36 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
37 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
38 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
39 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
40 0x01 0x02 0x04 0x05 0x06 0x07 0x08 >;
Usama Arifbec5afd2020-04-17 16:13:39 +010041 };
42
43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46
47 cpu-map {
48 cluster0 {
49 core0 {
50 cpu = <&CPU0>;
51 };
52 core1 {
53 cpu = <&CPU1>;
54 };
55 core2 {
56 cpu = <&CPU2>;
57 };
58 core3 {
59 cpu = <&CPU3>;
60 };
Avinash Mehtaf68a0842020-10-28 16:43:28 +000061 core4 {
62 cpu = <&CPU4>;
63 };
64 core5 {
65 cpu = <&CPU5>;
66 };
67 core6 {
68 cpu = <&CPU6>;
69 };
70 core7 {
71 cpu = <&CPU7>;
72 };
Boyan Karatotev192ad5d2023-12-12 15:59:01 +000073#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
74 core8 {
75 cpu = <&CPU8>;
76 };
77 core9 {
78 cpu = <&CPU9>;
79 };
80 core10 {
81 cpu = <&CPU10>;
82 };
83 core11 {
84 cpu = <&CPU11>;
85 };
86 core12 {
87 cpu = <&CPU12>;
88 };
89 core13 {
90 cpu = <&CPU13>;
91 };
92#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
Usama Arifbec5afd2020-04-17 16:13:39 +010093 };
94 };
95
Usama Arif57900782020-08-12 17:14:37 +010096 /*
97 * The timings below are just to demonstrate working cpuidle.
98 * These values may be inaccurate.
99 */
100 idle-states {
Boyan Karatotev13b8e742023-11-14 13:57:56 +0000101 entry-method = "psci";
Usama Arif57900782020-08-12 17:14:37 +0100102
103 CPU_SLEEP_0: cpu-sleep-0 {
104 compatible = "arm,idle-state";
105 arm,psci-suspend-param = <0x0010000>;
106 local-timer-stop;
107 entry-latency-us = <300>;
108 exit-latency-us = <1200>;
109 min-residency-us = <2000>;
110 };
111 CLUSTER_SLEEP_0: cluster-sleep-0 {
112 compatible = "arm,idle-state";
113 arm,psci-suspend-param = <0x1010000>;
114 local-timer-stop;
115 entry-latency-us = <400>;
116 exit-latency-us = <1200>;
117 min-residency-us = <2500>;
118 };
119 };
120
Chris Kayc2d29ba2021-05-18 18:49:51 +0100121 amus {
122 amu: amu-0 {
123 #address-cells = <1>;
124 #size-cells = <0>;
125
126 mpmm_gear0: counter@0 {
127 reg = <0>;
Chris Kayc2d29ba2021-05-18 18:49:51 +0100128 enable-at-el3;
129 };
130
131 mpmm_gear1: counter@1 {
132 reg = <1>;
Chris Kayc2d29ba2021-05-18 18:49:51 +0100133 enable-at-el3;
134 };
135
136 mpmm_gear2: counter@2 {
137 reg = <2>;
Chris Kayc2d29ba2021-05-18 18:49:51 +0100138 enable-at-el3;
139 };
140 };
141 };
142
Usama Arifbec5afd2020-04-17 16:13:39 +0100143 CPU0:cpu@0 {
144 device_type = "cpu";
145 compatible = "arm,armv8";
146 reg = <0x0>;
147 enable-method = "psci";
148 clocks = <&scmi_dvfs 0>;
Usama Arif57900782020-08-12 17:14:37 +0100149 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Boyan Karatotev192ad5d2023-12-12 15:59:01 +0000150 capacity-dmips-mhz = <LIT_CAPACITY>;
Chris Kayc2d29ba2021-05-18 18:49:51 +0100151 amu = <&amu>;
152 supports-mpmm;
Usama Arifbec5afd2020-04-17 16:13:39 +0100153 };
154
155 CPU1:cpu@100 {
156 device_type = "cpu";
157 compatible = "arm,armv8";
158 reg = <0x100>;
159 enable-method = "psci";
160 clocks = <&scmi_dvfs 0>;
Usama Arif57900782020-08-12 17:14:37 +0100161 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Boyan Karatotev192ad5d2023-12-12 15:59:01 +0000162 capacity-dmips-mhz = <LIT_CAPACITY>;
Chris Kayc2d29ba2021-05-18 18:49:51 +0100163 amu = <&amu>;
164 supports-mpmm;
Usama Arifbec5afd2020-04-17 16:13:39 +0100165 };
166
167 CPU2:cpu@200 {
168 device_type = "cpu";
169 compatible = "arm,armv8";
170 reg = <0x200>;
171 enable-method = "psci";
Usama Arif57900782020-08-12 17:14:37 +0100172 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Boyan Karatotev192ad5d2023-12-12 15:59:01 +0000173#if TARGET_PLATFORM <= 2
174 clocks = <&scmi_dvfs 0>;
175 capacity-dmips-mhz = <LIT_CAPACITY>;
176#elif TARGET_PLATFORM == 3
177 clocks = <&scmi_dvfs 1>;
178 capacity-dmips-mhz = <MID_CAPACITY>;
179#endif /* TARGET_PLATFORM == 3 */
Chris Kayc2d29ba2021-05-18 18:49:51 +0100180 amu = <&amu>;
181 supports-mpmm;
Usama Arifbec5afd2020-04-17 16:13:39 +0100182 };
183
184 CPU3:cpu@300 {
185 device_type = "cpu";
186 compatible = "arm,armv8";
187 reg = <0x300>;
188 enable-method = "psci";
Usama Arif57900782020-08-12 17:14:37 +0100189 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Boyan Karatotev192ad5d2023-12-12 15:59:01 +0000190#if TARGET_PLATFORM <= 2
191 clocks = <&scmi_dvfs 0>;
192 capacity-dmips-mhz = <LIT_CAPACITY>;
193#elif TARGET_PLATFORM == 3
194 clocks = <&scmi_dvfs 1>;
195 capacity-dmips-mhz = <MID_CAPACITY>;
196#endif /* TARGET_PLATFORM == 3 */
Chris Kayc2d29ba2021-05-18 18:49:51 +0100197 amu = <&amu>;
198 supports-mpmm;
Usama Arifbec5afd2020-04-17 16:13:39 +0100199 };
200
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000201 CPU4:cpu@400 {
202 device_type = "cpu";
203 compatible = "arm,armv8";
204 reg = <0x400>;
205 enable-method = "psci";
Usama Arif75edb752021-02-03 15:40:46 +0000206 clocks = <&scmi_dvfs 1>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000207 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Boyan Karatotev192ad5d2023-12-12 15:59:01 +0000208 capacity-dmips-mhz = <MID_CAPACITY>;
Chris Kayc2d29ba2021-05-18 18:49:51 +0100209 amu = <&amu>;
210 supports-mpmm;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000211 };
212
213 CPU5:cpu@500 {
214 device_type = "cpu";
215 compatible = "arm,armv8";
216 reg = <0x500>;
217 enable-method = "psci";
Usama Arif75edb752021-02-03 15:40:46 +0000218 clocks = <&scmi_dvfs 1>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000219 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Boyan Karatotev192ad5d2023-12-12 15:59:01 +0000220 capacity-dmips-mhz = <MID_CAPACITY>;
Chris Kayc2d29ba2021-05-18 18:49:51 +0100221 amu = <&amu>;
222 supports-mpmm;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000223 };
224
225 CPU6:cpu@600 {
226 device_type = "cpu";
227 compatible = "arm,armv8";
228 reg = <0x600>;
229 enable-method = "psci";
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000230 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Boyan Karatotev192ad5d2023-12-12 15:59:01 +0000231#if TARGET_PLATFORM <= 2
232 clocks = <&scmi_dvfs 1>;
233 capacity-dmips-mhz = <MID_CAPACITY>;
234#elif TARGET_PLATFORM == 3
235 clocks = <&scmi_dvfs 2>;
236 capacity-dmips-mhz = <BIG_CAPACITY>;
237#endif /* TARGET_PLATFORM == 3 */
Chris Kayc2d29ba2021-05-18 18:49:51 +0100238 amu = <&amu>;
239 supports-mpmm;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000240 };
241
242 CPU7:cpu@700 {
243 device_type = "cpu";
244 compatible = "arm,armv8";
245 reg = <0x700>;
246 enable-method = "psci";
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000247 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Boyan Karatotev192ad5d2023-12-12 15:59:01 +0000248#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
249 clocks = <&scmi_dvfs 1>;
250 capacity-dmips-mhz = <MID_CAPACITY>;
251#else
252 clocks = <&scmi_dvfs 2>;
253 capacity-dmips-mhz = <BIG_CAPACITY>;
254#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
255 amu = <&amu>;
256 supports-mpmm;
257 };
258
259#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
260 CPU8:cpu@800 {
261 device_type = "cpu";
262 compatible = "arm,armv8";
263 reg = <0x800>;
264 enable-method = "psci";
265 clocks = <&scmi_dvfs 1>;
266 capacity-dmips-mhz = <MID_CAPACITY>;
267 amu = <&amu>;
268 supports-mpmm;
269 };
270
271 CPU9:cpu@900 {
272 device_type = "cpu";
273 compatible = "arm,armv8";
274 reg = <0x900>;
275 enable-method = "psci";
276 clocks = <&scmi_dvfs 2>;
277 capacity-dmips-mhz = <BIG2_CAPACITY>;
278 amu = <&amu>;
279 supports-mpmm;
280 };
281
282 CPU10:cpu@A00 {
283 device_type = "cpu";
284 compatible = "arm,armv8";
285 reg = <0xA00>;
286 enable-method = "psci";
287 clocks = <&scmi_dvfs 2>;
288 capacity-dmips-mhz = <BIG2_CAPACITY>;
289 amu = <&amu>;
290 supports-mpmm;
291 };
292
293 CPU11:cpu@B00 {
294 device_type = "cpu";
295 compatible = "arm,armv8";
296 reg = <0xB00>;
297 enable-method = "psci";
298 clocks = <&scmi_dvfs 2>;
299 capacity-dmips-mhz = <BIG2_CAPACITY>;
Chris Kayc2d29ba2021-05-18 18:49:51 +0100300 amu = <&amu>;
301 supports-mpmm;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000302 };
303
Boyan Karatotev192ad5d2023-12-12 15:59:01 +0000304 CPU12:cpu@C00 {
305 device_type = "cpu";
306 compatible = "arm,armv8";
307 reg = <0xC00>;
308 enable-method = "psci";
309 clocks = <&scmi_dvfs 3>;
310 capacity-dmips-mhz = <BIG_CAPACITY>;
311 amu = <&amu>;
312 supports-mpmm;
313 };
314
315 CPU13:cpu@D00 {
316 device_type = "cpu";
317 compatible = "arm,armv8";
318 reg = <0xD00>;
319 enable-method = "psci";
320 clocks = <&scmi_dvfs 3>;
321 capacity-dmips-mhz = <BIG_CAPACITY>;
322 amu = <&amu>;
323 supports-mpmm;
324 };
325#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
Usama Arifbec5afd2020-04-17 16:13:39 +0100326 };
327
Arunachalam Ganapathy948bb442020-12-14 12:31:32 +0000328 reserved-memory {
329 #address-cells = <2>;
330 #size-cells = <2>;
331 ranges;
332
Anders Delliena6c9b722021-12-08 21:57:21 +0000333 linux,cma {
334 compatible = "shared-dma-pool";
335 reusable;
336 size = <0x0 0x8000000>;
337 linux,cma-default;
338 };
339
Boyan Karatotev13b8e742023-11-14 13:57:56 +0000340 optee@f8e00000 {
Davidson K4662a882022-12-14 17:38:14 +0530341 compatible = "restricted-dma-pool";
Arunachalam Ganapathyac9e1202022-04-11 17:38:17 +0100342 reg = <0x00000000 0xf8e00000 0 0x00200000>;
Arunachalam Ganapathy948bb442020-12-14 12:31:32 +0000343 };
Tudor Cretu77b301a2021-09-24 12:09:53 +0000344
Boyan Karatotev13b8e742023-11-14 13:57:56 +0000345 fwu_mm@fca00000 {
Tudor Cretu77b301a2021-09-24 12:09:53 +0000346 reg = <0x00000000 0xfca00000 0 0x00400000>;
347 no-map;
348 };
Arunachalam Ganapathy948bb442020-12-14 12:31:32 +0000349 };
350
Usama Arifbec5afd2020-04-17 16:13:39 +0100351 psci {
Usama Arif7a64bfa2021-05-27 20:09:17 +0100352 compatible = "arm,psci-1.0", "arm,psci-0.2";
Usama Arifbec5afd2020-04-17 16:13:39 +0100353 method = "smc";
354 };
355
Boyan Karatotev4fef47c2023-11-15 11:29:59 +0000356 cpu-pmu {
357 compatible = "arm,armv8-pmuv3";
358 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
359 interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
360 <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>
Boyan Karatotev192ad5d2023-12-12 15:59:01 +0000361#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
362 ,<&CPU8>, <&CPU9>, <&CPU10>, <&CPU11>,
363 <&CPU12>, <&CPU13>
364#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
Boyan Karatotev4fef47c2023-11-15 11:29:59 +0000365 ;
366 };
367
Usama Arifbec5afd2020-04-17 16:13:39 +0100368 sram: sram@6000000 {
369 compatible = "mmio-sram";
370 reg = <0x0 0x06000000 0x0 0x8000>;
371
372 #address-cells = <1>;
373 #size-cells = <1>;
374 ranges = <0 0x0 0x06000000 0x8000>;
375
376 cpu_scp_scmi_mem: scp-shmem@0 {
377 compatible = "arm,scmi-shmem";
378 reg = <0x0 0x80>;
379 };
380 };
381
Boyan Karatotev6ed3bf62023-07-07 13:33:19 +0000382 mbox_db_rx: mhu@MHU_RX_ADDR() {
Usama Arifb315c702021-05-27 20:01:39 +0100383 compatible = "arm,mhuv2-rx","arm,primecell";
Boyan Karatotev6ed3bf62023-07-07 13:33:19 +0000384 reg = <0x0 MHU_RX_ADDR(0x) 0x0 0x1000>;
Boyan Karatotev13b8e742023-11-14 13:57:56 +0000385 clocks = <&soc_refclk>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100386 clock-names = "apb_pclk";
Usama Arifb315c702021-05-27 20:01:39 +0100387 #mbox-cells = <2>;
Boyan Karatotev6ed3bf62023-07-07 13:33:19 +0000388 interrupts = <GIC_SPI INT_MBOX_RX IRQ_TYPE_LEVEL_HIGH>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100389 interrupt-names = "mhu_rx";
390 mhu-protocol = "doorbell";
Usama Arifb315c702021-05-27 20:01:39 +0100391 arm,mhuv2-protocols = <0 1>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100392 };
393
Boyan Karatotev6ed3bf62023-07-07 13:33:19 +0000394 mbox_db_tx: mhu@MHU_TX_ADDR() {
Usama Arifb315c702021-05-27 20:01:39 +0100395 compatible = "arm,mhuv2-tx","arm,primecell";
Boyan Karatotev6ed3bf62023-07-07 13:33:19 +0000396 reg = <0x0 MHU_TX_ADDR(0x) 0x0 0x1000>;
Boyan Karatotev13b8e742023-11-14 13:57:56 +0000397 clocks = <&soc_refclk>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100398 clock-names = "apb_pclk";
Usama Arifb315c702021-05-27 20:01:39 +0100399 #mbox-cells = <2>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100400 interrupt-names = "mhu_tx";
401 mhu-protocol = "doorbell";
Usama Arifb315c702021-05-27 20:01:39 +0100402 arm,mhuv2-protocols = <0 1>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100403 };
404
405 scmi {
406 compatible = "arm,scmi";
Usama Arifbec5afd2020-04-17 16:13:39 +0100407 mbox-names = "tx", "rx";
Usama Arifb315c702021-05-27 20:01:39 +0100408 mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >;
Usama Arifbec5afd2020-04-17 16:13:39 +0100409 shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>;
410 #address-cells = <1>;
411 #size-cells = <0>;
412
Kshitij Sisodia090a6aa2023-11-22 17:03:45 +0000413#if TC_SCMI_PD_CTRL_EN
Ben Horgan80781a52023-07-26 20:45:27 +0100414 scmi_devpd: protocol@11 {
415 reg = <0x11>;
416 #power-domain-cells = <1>;
417 };
Kshitij Sisodia090a6aa2023-11-22 17:03:45 +0000418#endif /* TC_SCMI_PD_CTRL_EN */
Ben Horgan80781a52023-07-26 20:45:27 +0100419
Usama Arifbec5afd2020-04-17 16:13:39 +0100420 scmi_dvfs: protocol@13 {
421 reg = <0x13>;
422 #clock-cells = <1>;
423 };
424
425 scmi_clk: protocol@14 {
426 reg = <0x14>;
427 #clock-cells = <1>;
428 };
429 };
430
Boyan Karatotev95562762023-11-15 11:54:33 +0000431 gic: interrupt-controller@GIC_CTRL_ADDR {
Boyan Karatotev13b8e742023-11-14 13:57:56 +0000432 compatible = "arm,gic-v3";
Usama Arifbec5afd2020-04-17 16:13:39 +0100433 #address-cells = <2>;
434 #interrupt-cells = <3>;
435 #size-cells = <2>;
436 ranges;
437 interrupt-controller;
438 reg = <0x0 0x30000000 0 0x10000>, /* GICD */
Boyan Karatotev95562762023-11-15 11:54:33 +0000439 <0x0 0x30080000 0 GIC_GICR_OFFSET>; /* GICR */
Boyan Karatotev25c4fb72023-08-08 15:37:52 +0100440 interrupts = <GIC_PPI 0x9 IRQ_TYPE_LEVEL_LOW>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100441 };
442
443 timer {
444 compatible = "arm,armv8-timer";
Boyan Karatotev25c4fb72023-08-08 15:37:52 +0100445 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
446 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
447 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
448 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100449 };
450
Boyan Karatotev13b8e742023-11-14 13:57:56 +0000451 soc_refclk: refclk {
Usama Arifbec5afd2020-04-17 16:13:39 +0100452 compatible = "fixed-clock";
453 #clock-cells = <0>;
Boyan Karatotev95562762023-11-15 11:54:33 +0000454 clock-frequency = <1000000000>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100455 clock-output-names = "apb_pclk";
456 };
457
458 soc_refclk60mhz: refclk60mhz {
459 compatible = "fixed-clock";
460 #clock-cells = <0>;
461 clock-frequency = <60000000>;
462 clock-output-names = "iofpga_clk";
463 };
464
Boyan Karatotev13b8e742023-11-14 13:57:56 +0000465 soc_uartclk: uartclk {
Usama Arifbec5afd2020-04-17 16:13:39 +0100466 compatible = "fixed-clock";
467 #clock-cells = <0>;
Boyan Karatotev6ed3bf62023-07-07 13:33:19 +0000468 clock-frequency = <UARTCLK_FREQ>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100469 clock-output-names = "uartclk";
470 };
471
Boyan Karatotev95562762023-11-15 11:54:33 +0000472 /* soc_uart0 on FPGA, ap_ns_uart on FVP */
Boyan Karatotev13b8e742023-11-14 13:57:56 +0000473 os_uart: serial@2a400000 {
Usama Arifbec5afd2020-04-17 16:13:39 +0100474 compatible = "arm,pl011", "arm,primecell";
Boyan Karatotev95562762023-11-15 11:54:33 +0000475 reg = <0x0 0x2A400000 0x0 UART_OFFSET>;
Boyan Karatotev25c4fb72023-08-08 15:37:52 +0100476 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
Boyan Karatotev13b8e742023-11-14 13:57:56 +0000477 clocks = <&soc_uartclk>, <&soc_refclk>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100478 clock-names = "uartclk", "apb_pclk";
479 status = "okay";
480 };
481
482 vencoder {
483 compatible = "drm,virtual-encoder";
Usama Arifbec5afd2020-04-17 16:13:39 +0100484 port {
485 vencoder_in: endpoint {
Avinash Mehtadf71a602020-07-22 16:40:07 +0100486 remote-endpoint = <&dp_pl0_out0>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100487 };
488 };
489
490 display-timings {
Boyan Karatotev13b8e742023-11-14 13:57:56 +0000491 timing-panel {
Boyan Karatotev95562762023-11-15 11:54:33 +0000492 VENCODER_TIMING;
Usama Arifbec5afd2020-04-17 16:13:39 +0100493 };
494 };
495
496 };
497
Usama Arifbec5afd2020-04-17 16:13:39 +0100498 ethernet@18000000 {
Boyan Karatotev95562762023-11-15 11:54:33 +0000499 compatible = ETH_COMPATIBLE;
Usama Arifbec5afd2020-04-17 16:13:39 +0100500 reg = <0x0 0x18000000 0x0 0x10000>;
Boyan Karatotev25c4fb72023-08-08 15:37:52 +0100501 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
Boyan Karatotev95562762023-11-15 11:54:33 +0000502
503 /* FPGA only but will work on FVP. Keep for simplicity */
504 phy-mode = "mii";
505 reg-io-width = <2>;
506 smsc,irq-push-pull;
Usama Arifbec5afd2020-04-17 16:13:39 +0100507 };
508
Usama Arifbec5afd2020-04-17 16:13:39 +0100509 bp_clock24mhz: clock24mhz {
510 compatible = "fixed-clock";
511 #clock-cells = <0>;
512 clock-frequency = <24000000>;
513 clock-output-names = "bp:clock24mhz";
514 };
515
Usama Arifbec5afd2020-04-17 16:13:39 +0100516
Usama Arif1cd56dc2020-06-10 16:27:53 +0100517 sysreg: sysreg@1c010000 {
518 compatible = "arm,vexpress-sysreg";
519 reg = <0x0 0x001c010000 0x0 0x1000>;
520 gpio-controller;
521 #gpio-cells = <2>;
522 };
523
524 fixed_3v3: v2m-3v3 {
525 compatible = "regulator-fixed";
526 regulator-name = "3V3";
527 regulator-min-microvolt = <3300000>;
528 regulator-max-microvolt = <3300000>;
529 regulator-always-on;
530 };
531
532 mmci@1c050000 {
533 compatible = "arm,pl180", "arm,primecell";
534 reg = <0x0 0x001c050000 0x0 0x1000>;
Boyan Karatotev25c4fb72023-08-08 15:37:52 +0100535 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
Boyan Karatotev95562762023-11-15 11:54:33 +0000537 MMC_REMOVABLE;
Usama Arif1cd56dc2020-06-10 16:27:53 +0100538 wp-gpios = <&sysreg 1 0>;
Boyan Karatotev95562762023-11-15 11:54:33 +0000539 bus-width = <4>;
540 max-frequency = <25000000>;
Usama Arif1cd56dc2020-06-10 16:27:53 +0100541 vmmc-supply = <&fixed_3v3>;
542 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
543 clock-names = "mclk", "apb_pclk";
544 };
545
Rupinderjit Singhb2a75b82023-02-03 09:29:57 +0000546 gpu_clk: gpu_clk {
547 compatible = "fixed-clock";
548 #clock-cells = <0>;
549 clock-frequency = <1000000000>;
550 };
551
552 gpu_core_clk: gpu_core_clk {
553 compatible = "fixed-clock";
554 #clock-cells = <0>;
555 clock-frequency = <1000000000>;
556 };
557
Anders Dellien7a849802022-01-01 21:51:21 +0000558 gpu: gpu@2d000000 {
559 compatible = "arm,mali-midgard";
560 reg = <0x0 0x2d000000 0x0 0x200000>;
Boyan Karatotev25c4fb72023-08-08 15:37:52 +0100561 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
Anders Dellien7a849802022-01-01 21:51:21 +0000564 interrupt-names = "JOB", "MMU", "GPU";
Ben Horgan80781a52023-07-26 20:45:27 +0100565 clocks = <&gpu_core_clk>;
566 clock-names = "shadercores";
Kshitij Sisodia090a6aa2023-11-22 17:03:45 +0000567#if TC_SCMI_PD_CTRL_EN
Boyan Karatotev192ad5d2023-12-12 15:59:01 +0000568 power-domains = <&scmi_devpd GPU_SCMI_PD_IDX>;
Ben Horgan80781a52023-07-26 20:45:27 +0100569 scmi-perf-domain = <3>;
Kshitij Sisodia090a6aa2023-11-22 17:03:45 +0000570#endif /* TC_SCMI_PD_CTRL_EN */
571
572#if TC_IOMMU_EN
Davidson Kce633122022-11-21 17:49:51 +0530573 iommus = <&smmu_700 0x200>;
Kshitij Sisodia090a6aa2023-11-22 17:03:45 +0000574#endif /* TC_IOMMU_EN */
Anders Dellien7a849802022-01-01 21:51:21 +0000575 };
576
Boyan Karatotev13b8e742023-11-14 13:57:56 +0000577 power_model_simple {
Rupinderjit Singhb2a75b82023-02-03 09:29:57 +0000578 /*
579 * Numbers used are irrelevant to Titan,
580 * it helps suppressing the kernel warnings.
581 */
582 compatible = "arm,mali-simple-power-model";
583 static-coefficient = <2427750>;
584 dynamic-coefficient = <4687>;
585 ts = <20000 2000 (-20) 2>;
586 thermal-zone = "";
587 };
588
Kshitij Sisodia090a6aa2023-11-22 17:03:45 +0000589#if TC_IOMMU_EN
Boyan Karatotev13b8e742023-11-14 13:57:56 +0000590 smmu_700: iommu@3f000000 {
Anders Delliena1914132022-01-01 21:56:25 +0000591 #iommu-cells = <1>;
592 compatible = "arm,smmu-v3";
Davidson Kce633122022-11-21 17:49:51 +0530593 reg = <0x0 0x3f000000 0x0 0x5000000>;
Kshitij Sisodiab32a8f42023-08-16 09:46:05 +0100594 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
595 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
596 <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>;
597 interrupt-names = "eventq", "cmdq-sync", "gerror";
Davidson Kce633122022-11-21 17:49:51 +0530598 dma-coherent;
Anders Delliena1914132022-01-01 21:56:25 +0000599 };
Kshitij Sisodia090a6aa2023-11-22 17:03:45 +0000600#endif /* TC_IOMMU_EN */
Anders Delliena1914132022-01-01 21:56:25 +0000601
Davidson K938124e2023-12-14 12:03:23 +0530602 dp0: display@DPU_ADDR() {
Usama Arifbec5afd2020-04-17 16:13:39 +0100603 #address-cells = <1>;
604 #size-cells = <0>;
605 compatible = "arm,mali-d71";
Davidson K938124e2023-12-14 12:03:23 +0530606 reg = <HI(DPU_ADDR(0x)) LO(DPU_ADDR(0x)) 0 0x20000>;
607 interrupts = <GIC_SPI DPU_IRQ IRQ_TYPE_LEVEL_HIGH>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100608 interrupt-names = "DPU";
Boyan Karatotev95562762023-11-15 11:54:33 +0000609 DPU_CLK_ATTR1;
Kshitij Sisodia090a6aa2023-11-22 17:03:45 +0000610#if TC_IOMMU_EN
Davidson Kce633122022-11-21 17:49:51 +0530611 iommus = <&smmu_700 0x100>;
Kshitij Sisodia090a6aa2023-11-22 17:03:45 +0000612#endif /* TC_IOMMU_EN */
613#if TC_SCMI_PD_CTRL_EN && (TARGET_PLATFORM != 3)
Boyan Karatotev192ad5d2023-12-12 15:59:01 +0000614 power-domains = <&scmi_devpd DPU_SCMI_PD_IDX>;
Kshitij Sisodia090a6aa2023-11-22 17:03:45 +0000615#endif /* TC_SCMI_PD_CTRL_EN && (TARGET_PLATFORM != 3) */
616
Usama Arifbec5afd2020-04-17 16:13:39 +0100617 pl0: pipeline@0 {
618 reg = <0>;
Boyan Karatotev95562762023-11-15 11:54:33 +0000619 DPU_CLK_ATTR2;
Usama Arifbec5afd2020-04-17 16:13:39 +0100620 pl_id = <0>;
621 ports {
622 #address-cells = <1>;
623 #size-cells = <0>;
624 port@0 {
625 reg = <0>;
626 dp_pl0_out0: endpoint {
627 remote-endpoint = <&vencoder_in>;
628 };
629 };
630 };
631 };
632
633 pl1: pipeline@1 {
634 reg = <1>;
Boyan Karatotev95562762023-11-15 11:54:33 +0000635 DPU_CLK_ATTR3;
Usama Arifbec5afd2020-04-17 16:13:39 +0100636 pl_id = <1>;
637 ports {
638 #address-cells = <1>;
639 #size-cells = <0>;
640 port@0 {
641 reg = <0>;
642 };
643 };
644 };
645 };
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000646
Davidson K1ad2c412023-01-13 14:02:13 +0530647 /*
648 * L3 cache in the DSU is the Memory System Component (MSC)
649 * The MPAM registers are accessed through utility bus in the DSU
650 */
651 msc0 {
652 compatible = "arm,mpam-msc";
Boyan Karatotev6ed3bf62023-07-07 13:33:19 +0000653 reg = <MPAM_ADDR 0x0 0x2000>;
Davidson K1ad2c412023-01-13 14:02:13 +0530654 };
655
Davidson K65361052021-10-13 18:49:41 +0530656 ete0 {
657 compatible = "arm,embedded-trace-extension";
658 cpu = <&CPU0>;
659 };
660
661 ete1 {
662 compatible = "arm,embedded-trace-extension";
663 cpu = <&CPU1>;
664 };
665
666 ete2 {
667 compatible = "arm,embedded-trace-extension";
668 cpu = <&CPU2>;
669 };
670
671 ete3 {
672 compatible = "arm,embedded-trace-extension";
673 cpu = <&CPU3>;
674 };
675
676 ete4 {
677 compatible = "arm,embedded-trace-extension";
678 cpu = <&CPU4>;
679 };
680
681 ete5 {
682 compatible = "arm,embedded-trace-extension";
683 cpu = <&CPU5>;
684 };
685
686 ete6 {
687 compatible = "arm,embedded-trace-extension";
688 cpu = <&CPU6>;
689 };
690
691 ete7 {
692 compatible = "arm,embedded-trace-extension";
693 cpu = <&CPU7>;
694 };
Boyan Karatotev192ad5d2023-12-12 15:59:01 +0000695
696#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
697 ete8 {
698 compatible = "arm,embedded-trace-extension";
699 cpu = <&CPU8>;
700 };
701
702 ete9 {
703 compatible = "arm,embedded-trace-extension";
704 cpu = <&CPU9>;
705 };
706
707 ete10 {
708 compatible = "arm,embedded-trace-extension";
709 cpu = <&CPU10>;
710 };
711
712 ete11 {
713 compatible = "arm,embedded-trace-extension";
714 cpu = <&CPU11>;
715 };
716
717 ete12 {
718 compatible = "arm,embedded-trace-extension";
719 cpu = <&CPU12>;
720 };
721
722 ete13 {
723 compatible = "arm,embedded-trace-extension";
724 cpu = <&CPU13>;
725 };
726#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
Davidson K65361052021-10-13 18:49:41 +0530727
Boyan Karatotev13b8e742023-11-14 13:57:56 +0000728 trbe {
Davidson K65361052021-10-13 18:49:41 +0530729 compatible = "arm,trace-buffer-extension";
Boyan Karatotev25c4fb72023-08-08 15:37:52 +0100730 interrupts = <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>;
Davidson K65361052021-10-13 18:49:41 +0530731 };
Arunachalam Ganapathy63128dc2022-04-11 14:43:15 +0100732
733 trusty {
734 #size-cells = <0x02>;
735 #address-cells = <0x02>;
736 ranges = <0x00>;
737 compatible = "android,trusty-v1";
738
739 virtio {
740 compatible = "android,trusty-virtio-v1";
741 };
742
743 test {
744 compatible = "android,trusty-test-v1";
745 };
746
747 log {
748 compatible = "android,trusty-log-v1";
749 };
750
751 irq {
752 ipi-range = <0x08 0x0f 0x08>;
753 interrupt-ranges = <0x00 0x0f 0x00 0x10 0x1f 0x01 0x20 0x3f 0x02>;
754 interrupt-templates = <0x01 0x00 0x8001 0x01 0x01 0x04 0x8001 0x01 0x00 0x04>;
755 compatible = "android,trusty-irq-v1";
756 };
757 };
Boyan Karatotevd2ca2872023-11-28 16:08:52 +0000758
759 /* used in U-boot, Linux doesn't care */
760 arm_ffa {
761 compatible = "arm,ffa";
762 method = "smc";
763 };
Usama Arifbec5afd2020-04-17 16:13:39 +0100764};