Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 1 | /* |
annsai01 | 7c607f2 | 2023-02-20 13:34:57 +0000 | [diff] [blame] | 2 | * Copyright (c) 2020-2024, Arm Limited. All rights reserved. |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | |
Kshitij Sisodia | b32a8f4 | 2023-08-16 09:46:05 +0100 | [diff] [blame] | 9 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 10 | #include <dt-bindings/interrupt-controller/irq.h> |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 11 | #include "platform_def.h" |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame] | 12 | #include "tc_vers.dtsi" |
Boyan Karatotev | 9ac73a4 | 2023-11-14 09:38:08 +0000 | [diff] [blame] | 13 | #if TARGET_FLAVOUR_FVP |
| 14 | #include "tc_fvp.dtsi" |
| 15 | #endif /* TARGET_FLAVOUR_FVP */ |
Kshitij Sisodia | b32a8f4 | 2023-08-16 09:46:05 +0100 | [diff] [blame] | 16 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 17 | / { |
Usama Arif | f151362 | 2021-04-09 17:07:41 +0100 | [diff] [blame] | 18 | compatible = "arm,tc"; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 19 | interrupt-parent = <&gic>; |
| 20 | #address-cells = <2>; |
| 21 | #size-cells = <2>; |
| 22 | |
| 23 | aliases { |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 24 | serial0 = &os_uart; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 25 | }; |
| 26 | |
| 27 | chosen { |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame] | 28 | stdout-path = STDOUT_PATH; |
Ben Horgan | 7160e0d | 2023-12-11 16:01:10 +0000 | [diff] [blame] | 29 | /* |
| 30 | * Add some dummy entropy for Linux so it |
| 31 | * doesn't delay the boot waiting for it. |
| 32 | */ |
| 33 | rng-seed = <0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ |
| 34 | 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ |
| 35 | 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ |
| 36 | 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ |
| 37 | 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ |
| 38 | 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ |
| 39 | 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ |
| 40 | 0x01 0x02 0x04 0x05 0x06 0x07 0x08 >; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 41 | }; |
| 42 | |
| 43 | cpus { |
| 44 | #address-cells = <1>; |
| 45 | #size-cells = <0>; |
| 46 | |
| 47 | cpu-map { |
| 48 | cluster0 { |
| 49 | core0 { |
| 50 | cpu = <&CPU0>; |
| 51 | }; |
| 52 | core1 { |
| 53 | cpu = <&CPU1>; |
| 54 | }; |
| 55 | core2 { |
| 56 | cpu = <&CPU2>; |
| 57 | }; |
| 58 | core3 { |
| 59 | cpu = <&CPU3>; |
| 60 | }; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 61 | core4 { |
| 62 | cpu = <&CPU4>; |
| 63 | }; |
| 64 | core5 { |
| 65 | cpu = <&CPU5>; |
| 66 | }; |
| 67 | core6 { |
| 68 | cpu = <&CPU6>; |
| 69 | }; |
| 70 | core7 { |
| 71 | cpu = <&CPU7>; |
| 72 | }; |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 73 | #if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 |
| 74 | core8 { |
| 75 | cpu = <&CPU8>; |
| 76 | }; |
| 77 | core9 { |
| 78 | cpu = <&CPU9>; |
| 79 | }; |
| 80 | core10 { |
| 81 | cpu = <&CPU10>; |
| 82 | }; |
| 83 | core11 { |
| 84 | cpu = <&CPU11>; |
| 85 | }; |
| 86 | core12 { |
| 87 | cpu = <&CPU12>; |
| 88 | }; |
| 89 | core13 { |
| 90 | cpu = <&CPU13>; |
| 91 | }; |
| 92 | #endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */ |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 93 | }; |
| 94 | }; |
| 95 | |
Usama Arif | 5790078 | 2020-08-12 17:14:37 +0100 | [diff] [blame] | 96 | /* |
| 97 | * The timings below are just to demonstrate working cpuidle. |
| 98 | * These values may be inaccurate. |
| 99 | */ |
| 100 | idle-states { |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 101 | entry-method = "psci"; |
Usama Arif | 5790078 | 2020-08-12 17:14:37 +0100 | [diff] [blame] | 102 | |
| 103 | CPU_SLEEP_0: cpu-sleep-0 { |
| 104 | compatible = "arm,idle-state"; |
| 105 | arm,psci-suspend-param = <0x0010000>; |
| 106 | local-timer-stop; |
| 107 | entry-latency-us = <300>; |
| 108 | exit-latency-us = <1200>; |
| 109 | min-residency-us = <2000>; |
| 110 | }; |
| 111 | CLUSTER_SLEEP_0: cluster-sleep-0 { |
| 112 | compatible = "arm,idle-state"; |
| 113 | arm,psci-suspend-param = <0x1010000>; |
| 114 | local-timer-stop; |
| 115 | entry-latency-us = <400>; |
| 116 | exit-latency-us = <1200>; |
| 117 | min-residency-us = <2500>; |
| 118 | }; |
| 119 | }; |
| 120 | |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 121 | amus { |
| 122 | amu: amu-0 { |
| 123 | #address-cells = <1>; |
| 124 | #size-cells = <0>; |
| 125 | |
| 126 | mpmm_gear0: counter@0 { |
| 127 | reg = <0>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 128 | enable-at-el3; |
| 129 | }; |
| 130 | |
| 131 | mpmm_gear1: counter@1 { |
| 132 | reg = <1>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 133 | enable-at-el3; |
| 134 | }; |
| 135 | |
| 136 | mpmm_gear2: counter@2 { |
| 137 | reg = <2>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 138 | enable-at-el3; |
| 139 | }; |
| 140 | }; |
| 141 | }; |
| 142 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 143 | CPU0:cpu@0 { |
| 144 | device_type = "cpu"; |
| 145 | compatible = "arm,armv8"; |
| 146 | reg = <0x0>; |
| 147 | enable-method = "psci"; |
| 148 | clocks = <&scmi_dvfs 0>; |
Usama Arif | 5790078 | 2020-08-12 17:14:37 +0100 | [diff] [blame] | 149 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 150 | capacity-dmips-mhz = <LIT_CAPACITY>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 151 | amu = <&amu>; |
| 152 | supports-mpmm; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 153 | }; |
| 154 | |
| 155 | CPU1:cpu@100 { |
| 156 | device_type = "cpu"; |
| 157 | compatible = "arm,armv8"; |
| 158 | reg = <0x100>; |
| 159 | enable-method = "psci"; |
| 160 | clocks = <&scmi_dvfs 0>; |
Usama Arif | 5790078 | 2020-08-12 17:14:37 +0100 | [diff] [blame] | 161 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 162 | capacity-dmips-mhz = <LIT_CAPACITY>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 163 | amu = <&amu>; |
| 164 | supports-mpmm; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 165 | }; |
| 166 | |
| 167 | CPU2:cpu@200 { |
| 168 | device_type = "cpu"; |
| 169 | compatible = "arm,armv8"; |
| 170 | reg = <0x200>; |
| 171 | enable-method = "psci"; |
Usama Arif | 5790078 | 2020-08-12 17:14:37 +0100 | [diff] [blame] | 172 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 173 | #if TARGET_PLATFORM <= 2 |
| 174 | clocks = <&scmi_dvfs 0>; |
| 175 | capacity-dmips-mhz = <LIT_CAPACITY>; |
| 176 | #elif TARGET_PLATFORM == 3 |
| 177 | clocks = <&scmi_dvfs 1>; |
| 178 | capacity-dmips-mhz = <MID_CAPACITY>; |
| 179 | #endif /* TARGET_PLATFORM == 3 */ |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 180 | amu = <&amu>; |
| 181 | supports-mpmm; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 182 | }; |
| 183 | |
| 184 | CPU3:cpu@300 { |
| 185 | device_type = "cpu"; |
| 186 | compatible = "arm,armv8"; |
| 187 | reg = <0x300>; |
| 188 | enable-method = "psci"; |
Usama Arif | 5790078 | 2020-08-12 17:14:37 +0100 | [diff] [blame] | 189 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 190 | #if TARGET_PLATFORM <= 2 |
| 191 | clocks = <&scmi_dvfs 0>; |
| 192 | capacity-dmips-mhz = <LIT_CAPACITY>; |
| 193 | #elif TARGET_PLATFORM == 3 |
| 194 | clocks = <&scmi_dvfs 1>; |
| 195 | capacity-dmips-mhz = <MID_CAPACITY>; |
| 196 | #endif /* TARGET_PLATFORM == 3 */ |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 197 | amu = <&amu>; |
| 198 | supports-mpmm; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 199 | }; |
| 200 | |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 201 | CPU4:cpu@400 { |
| 202 | device_type = "cpu"; |
| 203 | compatible = "arm,armv8"; |
| 204 | reg = <0x400>; |
| 205 | enable-method = "psci"; |
Usama Arif | 75edb75 | 2021-02-03 15:40:46 +0000 | [diff] [blame] | 206 | clocks = <&scmi_dvfs 1>; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 207 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 208 | capacity-dmips-mhz = <MID_CAPACITY>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 209 | amu = <&amu>; |
| 210 | supports-mpmm; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 211 | }; |
| 212 | |
| 213 | CPU5:cpu@500 { |
| 214 | device_type = "cpu"; |
| 215 | compatible = "arm,armv8"; |
| 216 | reg = <0x500>; |
| 217 | enable-method = "psci"; |
Usama Arif | 75edb75 | 2021-02-03 15:40:46 +0000 | [diff] [blame] | 218 | clocks = <&scmi_dvfs 1>; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 219 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 220 | capacity-dmips-mhz = <MID_CAPACITY>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 221 | amu = <&amu>; |
| 222 | supports-mpmm; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 223 | }; |
| 224 | |
| 225 | CPU6:cpu@600 { |
| 226 | device_type = "cpu"; |
| 227 | compatible = "arm,armv8"; |
| 228 | reg = <0x600>; |
| 229 | enable-method = "psci"; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 230 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 231 | #if TARGET_PLATFORM <= 2 |
| 232 | clocks = <&scmi_dvfs 1>; |
| 233 | capacity-dmips-mhz = <MID_CAPACITY>; |
| 234 | #elif TARGET_PLATFORM == 3 |
| 235 | clocks = <&scmi_dvfs 2>; |
| 236 | capacity-dmips-mhz = <BIG_CAPACITY>; |
| 237 | #endif /* TARGET_PLATFORM == 3 */ |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 238 | amu = <&amu>; |
| 239 | supports-mpmm; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 240 | }; |
| 241 | |
| 242 | CPU7:cpu@700 { |
| 243 | device_type = "cpu"; |
| 244 | compatible = "arm,armv8"; |
| 245 | reg = <0x700>; |
| 246 | enable-method = "psci"; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 247 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 248 | #if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 |
| 249 | clocks = <&scmi_dvfs 1>; |
| 250 | capacity-dmips-mhz = <MID_CAPACITY>; |
| 251 | #else |
| 252 | clocks = <&scmi_dvfs 2>; |
| 253 | capacity-dmips-mhz = <BIG_CAPACITY>; |
| 254 | #endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */ |
| 255 | amu = <&amu>; |
| 256 | supports-mpmm; |
| 257 | }; |
| 258 | |
| 259 | #if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 |
| 260 | CPU8:cpu@800 { |
| 261 | device_type = "cpu"; |
| 262 | compatible = "arm,armv8"; |
| 263 | reg = <0x800>; |
| 264 | enable-method = "psci"; |
| 265 | clocks = <&scmi_dvfs 1>; |
| 266 | capacity-dmips-mhz = <MID_CAPACITY>; |
| 267 | amu = <&amu>; |
| 268 | supports-mpmm; |
| 269 | }; |
| 270 | |
| 271 | CPU9:cpu@900 { |
| 272 | device_type = "cpu"; |
| 273 | compatible = "arm,armv8"; |
| 274 | reg = <0x900>; |
| 275 | enable-method = "psci"; |
| 276 | clocks = <&scmi_dvfs 2>; |
| 277 | capacity-dmips-mhz = <BIG2_CAPACITY>; |
| 278 | amu = <&amu>; |
| 279 | supports-mpmm; |
| 280 | }; |
| 281 | |
| 282 | CPU10:cpu@A00 { |
| 283 | device_type = "cpu"; |
| 284 | compatible = "arm,armv8"; |
| 285 | reg = <0xA00>; |
| 286 | enable-method = "psci"; |
| 287 | clocks = <&scmi_dvfs 2>; |
| 288 | capacity-dmips-mhz = <BIG2_CAPACITY>; |
| 289 | amu = <&amu>; |
| 290 | supports-mpmm; |
| 291 | }; |
| 292 | |
| 293 | CPU11:cpu@B00 { |
| 294 | device_type = "cpu"; |
| 295 | compatible = "arm,armv8"; |
| 296 | reg = <0xB00>; |
| 297 | enable-method = "psci"; |
| 298 | clocks = <&scmi_dvfs 2>; |
| 299 | capacity-dmips-mhz = <BIG2_CAPACITY>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 300 | amu = <&amu>; |
| 301 | supports-mpmm; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 302 | }; |
| 303 | |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 304 | CPU12:cpu@C00 { |
| 305 | device_type = "cpu"; |
| 306 | compatible = "arm,armv8"; |
| 307 | reg = <0xC00>; |
| 308 | enable-method = "psci"; |
| 309 | clocks = <&scmi_dvfs 3>; |
| 310 | capacity-dmips-mhz = <BIG_CAPACITY>; |
| 311 | amu = <&amu>; |
| 312 | supports-mpmm; |
| 313 | }; |
| 314 | |
| 315 | CPU13:cpu@D00 { |
| 316 | device_type = "cpu"; |
| 317 | compatible = "arm,armv8"; |
| 318 | reg = <0xD00>; |
| 319 | enable-method = "psci"; |
| 320 | clocks = <&scmi_dvfs 3>; |
| 321 | capacity-dmips-mhz = <BIG_CAPACITY>; |
| 322 | amu = <&amu>; |
| 323 | supports-mpmm; |
| 324 | }; |
| 325 | #endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */ |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 326 | }; |
| 327 | |
Arunachalam Ganapathy | 948bb44 | 2020-12-14 12:31:32 +0000 | [diff] [blame] | 328 | reserved-memory { |
| 329 | #address-cells = <2>; |
| 330 | #size-cells = <2>; |
| 331 | ranges; |
| 332 | |
Anders Dellien | a6c9b72 | 2021-12-08 21:57:21 +0000 | [diff] [blame] | 333 | linux,cma { |
| 334 | compatible = "shared-dma-pool"; |
| 335 | reusable; |
| 336 | size = <0x0 0x8000000>; |
| 337 | linux,cma-default; |
| 338 | }; |
| 339 | |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 340 | optee@f8e00000 { |
Davidson K | 4662a88 | 2022-12-14 17:38:14 +0530 | [diff] [blame] | 341 | compatible = "restricted-dma-pool"; |
Arunachalam Ganapathy | ac9e120 | 2022-04-11 17:38:17 +0100 | [diff] [blame] | 342 | reg = <0x00000000 0xf8e00000 0 0x00200000>; |
Arunachalam Ganapathy | 948bb44 | 2020-12-14 12:31:32 +0000 | [diff] [blame] | 343 | }; |
Tudor Cretu | 77b301a | 2021-09-24 12:09:53 +0000 | [diff] [blame] | 344 | |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 345 | fwu_mm@fca00000 { |
Tudor Cretu | 77b301a | 2021-09-24 12:09:53 +0000 | [diff] [blame] | 346 | reg = <0x00000000 0xfca00000 0 0x00400000>; |
| 347 | no-map; |
| 348 | }; |
Arunachalam Ganapathy | 948bb44 | 2020-12-14 12:31:32 +0000 | [diff] [blame] | 349 | }; |
| 350 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 351 | psci { |
Usama Arif | 7a64bfa | 2021-05-27 20:09:17 +0100 | [diff] [blame] | 352 | compatible = "arm,psci-1.0", "arm,psci-0.2"; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 353 | method = "smc"; |
| 354 | }; |
| 355 | |
Boyan Karatotev | 4fef47c | 2023-11-15 11:29:59 +0000 | [diff] [blame] | 356 | cpu-pmu { |
| 357 | compatible = "arm,armv8-pmuv3"; |
| 358 | interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| 359 | interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, |
| 360 | <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7> |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 361 | #if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 |
| 362 | ,<&CPU8>, <&CPU9>, <&CPU10>, <&CPU11>, |
| 363 | <&CPU12>, <&CPU13> |
| 364 | #endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */ |
Boyan Karatotev | 4fef47c | 2023-11-15 11:29:59 +0000 | [diff] [blame] | 365 | ; |
| 366 | }; |
| 367 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 368 | sram: sram@6000000 { |
| 369 | compatible = "mmio-sram"; |
| 370 | reg = <0x0 0x06000000 0x0 0x8000>; |
| 371 | |
| 372 | #address-cells = <1>; |
| 373 | #size-cells = <1>; |
| 374 | ranges = <0 0x0 0x06000000 0x8000>; |
| 375 | |
| 376 | cpu_scp_scmi_mem: scp-shmem@0 { |
| 377 | compatible = "arm,scmi-shmem"; |
| 378 | reg = <0x0 0x80>; |
| 379 | }; |
| 380 | }; |
| 381 | |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame] | 382 | mbox_db_rx: mhu@MHU_RX_ADDR() { |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 383 | compatible = "arm,mhuv2-rx","arm,primecell"; |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame] | 384 | reg = <0x0 MHU_RX_ADDR(0x) 0x0 0x1000>; |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 385 | clocks = <&soc_refclk>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 386 | clock-names = "apb_pclk"; |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 387 | #mbox-cells = <2>; |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame] | 388 | interrupts = <GIC_SPI INT_MBOX_RX IRQ_TYPE_LEVEL_HIGH>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 389 | interrupt-names = "mhu_rx"; |
| 390 | mhu-protocol = "doorbell"; |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 391 | arm,mhuv2-protocols = <0 1>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 392 | }; |
| 393 | |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame] | 394 | mbox_db_tx: mhu@MHU_TX_ADDR() { |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 395 | compatible = "arm,mhuv2-tx","arm,primecell"; |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame] | 396 | reg = <0x0 MHU_TX_ADDR(0x) 0x0 0x1000>; |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 397 | clocks = <&soc_refclk>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 398 | clock-names = "apb_pclk"; |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 399 | #mbox-cells = <2>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 400 | interrupt-names = "mhu_tx"; |
| 401 | mhu-protocol = "doorbell"; |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 402 | arm,mhuv2-protocols = <0 1>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 403 | }; |
| 404 | |
| 405 | scmi { |
| 406 | compatible = "arm,scmi"; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 407 | mbox-names = "tx", "rx"; |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 408 | mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 409 | shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>; |
| 410 | #address-cells = <1>; |
| 411 | #size-cells = <0>; |
| 412 | |
Kshitij Sisodia | 090a6aa | 2023-11-22 17:03:45 +0000 | [diff] [blame] | 413 | #if TC_SCMI_PD_CTRL_EN |
Ben Horgan | 80781a5 | 2023-07-26 20:45:27 +0100 | [diff] [blame] | 414 | scmi_devpd: protocol@11 { |
| 415 | reg = <0x11>; |
| 416 | #power-domain-cells = <1>; |
| 417 | }; |
Kshitij Sisodia | 090a6aa | 2023-11-22 17:03:45 +0000 | [diff] [blame] | 418 | #endif /* TC_SCMI_PD_CTRL_EN */ |
Ben Horgan | 80781a5 | 2023-07-26 20:45:27 +0100 | [diff] [blame] | 419 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 420 | scmi_dvfs: protocol@13 { |
| 421 | reg = <0x13>; |
| 422 | #clock-cells = <1>; |
| 423 | }; |
| 424 | |
| 425 | scmi_clk: protocol@14 { |
| 426 | reg = <0x14>; |
| 427 | #clock-cells = <1>; |
| 428 | }; |
| 429 | }; |
| 430 | |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame] | 431 | gic: interrupt-controller@GIC_CTRL_ADDR { |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 432 | compatible = "arm,gic-v3"; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 433 | #address-cells = <2>; |
| 434 | #interrupt-cells = <3>; |
| 435 | #size-cells = <2>; |
| 436 | ranges; |
| 437 | interrupt-controller; |
| 438 | reg = <0x0 0x30000000 0 0x10000>, /* GICD */ |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame] | 439 | <0x0 0x30080000 0 GIC_GICR_OFFSET>; /* GICR */ |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 440 | interrupts = <GIC_PPI 0x9 IRQ_TYPE_LEVEL_LOW>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 441 | }; |
| 442 | |
| 443 | timer { |
| 444 | compatible = "arm,armv8-timer"; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 445 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| 446 | <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| 447 | <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| 448 | <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 449 | }; |
| 450 | |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 451 | soc_refclk: refclk { |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 452 | compatible = "fixed-clock"; |
| 453 | #clock-cells = <0>; |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame] | 454 | clock-frequency = <1000000000>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 455 | clock-output-names = "apb_pclk"; |
| 456 | }; |
| 457 | |
| 458 | soc_refclk60mhz: refclk60mhz { |
| 459 | compatible = "fixed-clock"; |
| 460 | #clock-cells = <0>; |
| 461 | clock-frequency = <60000000>; |
| 462 | clock-output-names = "iofpga_clk"; |
| 463 | }; |
| 464 | |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 465 | soc_uartclk: uartclk { |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 466 | compatible = "fixed-clock"; |
| 467 | #clock-cells = <0>; |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame] | 468 | clock-frequency = <UARTCLK_FREQ>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 469 | clock-output-names = "uartclk"; |
| 470 | }; |
| 471 | |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame] | 472 | /* soc_uart0 on FPGA, ap_ns_uart on FVP */ |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 473 | os_uart: serial@2a400000 { |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 474 | compatible = "arm,pl011", "arm,primecell"; |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame] | 475 | reg = <0x0 0x2A400000 0x0 UART_OFFSET>; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 476 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 477 | clocks = <&soc_uartclk>, <&soc_refclk>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 478 | clock-names = "uartclk", "apb_pclk"; |
| 479 | status = "okay"; |
| 480 | }; |
| 481 | |
| 482 | vencoder { |
| 483 | compatible = "drm,virtual-encoder"; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 484 | port { |
| 485 | vencoder_in: endpoint { |
Avinash Mehta | df71a60 | 2020-07-22 16:40:07 +0100 | [diff] [blame] | 486 | remote-endpoint = <&dp_pl0_out0>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 487 | }; |
| 488 | }; |
| 489 | |
| 490 | display-timings { |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 491 | timing-panel { |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame] | 492 | VENCODER_TIMING; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 493 | }; |
| 494 | }; |
| 495 | |
| 496 | }; |
| 497 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 498 | ethernet@18000000 { |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame] | 499 | compatible = ETH_COMPATIBLE; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 500 | reg = <0x0 0x18000000 0x0 0x10000>; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 501 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame] | 502 | |
| 503 | /* FPGA only but will work on FVP. Keep for simplicity */ |
| 504 | phy-mode = "mii"; |
| 505 | reg-io-width = <2>; |
| 506 | smsc,irq-push-pull; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 507 | }; |
| 508 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 509 | bp_clock24mhz: clock24mhz { |
| 510 | compatible = "fixed-clock"; |
| 511 | #clock-cells = <0>; |
| 512 | clock-frequency = <24000000>; |
| 513 | clock-output-names = "bp:clock24mhz"; |
| 514 | }; |
| 515 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 516 | |
Usama Arif | 1cd56dc | 2020-06-10 16:27:53 +0100 | [diff] [blame] | 517 | sysreg: sysreg@1c010000 { |
| 518 | compatible = "arm,vexpress-sysreg"; |
| 519 | reg = <0x0 0x001c010000 0x0 0x1000>; |
| 520 | gpio-controller; |
| 521 | #gpio-cells = <2>; |
| 522 | }; |
| 523 | |
| 524 | fixed_3v3: v2m-3v3 { |
| 525 | compatible = "regulator-fixed"; |
| 526 | regulator-name = "3V3"; |
| 527 | regulator-min-microvolt = <3300000>; |
| 528 | regulator-max-microvolt = <3300000>; |
| 529 | regulator-always-on; |
| 530 | }; |
| 531 | |
| 532 | mmci@1c050000 { |
| 533 | compatible = "arm,pl180", "arm,primecell"; |
| 534 | reg = <0x0 0x001c050000 0x0 0x1000>; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 535 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
| 536 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame] | 537 | MMC_REMOVABLE; |
Usama Arif | 1cd56dc | 2020-06-10 16:27:53 +0100 | [diff] [blame] | 538 | wp-gpios = <&sysreg 1 0>; |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame] | 539 | bus-width = <4>; |
| 540 | max-frequency = <25000000>; |
Usama Arif | 1cd56dc | 2020-06-10 16:27:53 +0100 | [diff] [blame] | 541 | vmmc-supply = <&fixed_3v3>; |
| 542 | clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; |
| 543 | clock-names = "mclk", "apb_pclk"; |
| 544 | }; |
| 545 | |
Rupinderjit Singh | b2a75b8 | 2023-02-03 09:29:57 +0000 | [diff] [blame] | 546 | gpu_clk: gpu_clk { |
| 547 | compatible = "fixed-clock"; |
| 548 | #clock-cells = <0>; |
| 549 | clock-frequency = <1000000000>; |
| 550 | }; |
| 551 | |
| 552 | gpu_core_clk: gpu_core_clk { |
| 553 | compatible = "fixed-clock"; |
| 554 | #clock-cells = <0>; |
| 555 | clock-frequency = <1000000000>; |
| 556 | }; |
| 557 | |
Anders Dellien | 7a84980 | 2022-01-01 21:51:21 +0000 | [diff] [blame] | 558 | gpu: gpu@2d000000 { |
| 559 | compatible = "arm,mali-midgard"; |
| 560 | reg = <0x0 0x2d000000 0x0 0x200000>; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 561 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, |
| 562 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, |
| 563 | <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
Anders Dellien | 7a84980 | 2022-01-01 21:51:21 +0000 | [diff] [blame] | 564 | interrupt-names = "JOB", "MMU", "GPU"; |
Ben Horgan | 80781a5 | 2023-07-26 20:45:27 +0100 | [diff] [blame] | 565 | clocks = <&gpu_core_clk>; |
| 566 | clock-names = "shadercores"; |
Kshitij Sisodia | 090a6aa | 2023-11-22 17:03:45 +0000 | [diff] [blame] | 567 | #if TC_SCMI_PD_CTRL_EN |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 568 | power-domains = <&scmi_devpd GPU_SCMI_PD_IDX>; |
Ben Horgan | 80781a5 | 2023-07-26 20:45:27 +0100 | [diff] [blame] | 569 | scmi-perf-domain = <3>; |
Kshitij Sisodia | 090a6aa | 2023-11-22 17:03:45 +0000 | [diff] [blame] | 570 | #endif /* TC_SCMI_PD_CTRL_EN */ |
| 571 | |
| 572 | #if TC_IOMMU_EN |
Davidson K | ce63312 | 2022-11-21 17:49:51 +0530 | [diff] [blame] | 573 | iommus = <&smmu_700 0x200>; |
Kshitij Sisodia | 090a6aa | 2023-11-22 17:03:45 +0000 | [diff] [blame] | 574 | #endif /* TC_IOMMU_EN */ |
Anders Dellien | 7a84980 | 2022-01-01 21:51:21 +0000 | [diff] [blame] | 575 | }; |
| 576 | |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 577 | power_model_simple { |
Rupinderjit Singh | b2a75b8 | 2023-02-03 09:29:57 +0000 | [diff] [blame] | 578 | /* |
| 579 | * Numbers used are irrelevant to Titan, |
| 580 | * it helps suppressing the kernel warnings. |
| 581 | */ |
| 582 | compatible = "arm,mali-simple-power-model"; |
| 583 | static-coefficient = <2427750>; |
| 584 | dynamic-coefficient = <4687>; |
| 585 | ts = <20000 2000 (-20) 2>; |
| 586 | thermal-zone = ""; |
| 587 | }; |
| 588 | |
Kshitij Sisodia | 090a6aa | 2023-11-22 17:03:45 +0000 | [diff] [blame] | 589 | #if TC_IOMMU_EN |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 590 | smmu_700: iommu@3f000000 { |
Anders Dellien | a191413 | 2022-01-01 21:56:25 +0000 | [diff] [blame] | 591 | #iommu-cells = <1>; |
| 592 | compatible = "arm,smmu-v3"; |
Davidson K | ce63312 | 2022-11-21 17:49:51 +0530 | [diff] [blame] | 593 | reg = <0x0 0x3f000000 0x0 0x5000000>; |
Kshitij Sisodia | b32a8f4 | 2023-08-16 09:46:05 +0100 | [diff] [blame] | 594 | interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, |
| 595 | <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, |
| 596 | <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>; |
| 597 | interrupt-names = "eventq", "cmdq-sync", "gerror"; |
Davidson K | ce63312 | 2022-11-21 17:49:51 +0530 | [diff] [blame] | 598 | dma-coherent; |
Anders Dellien | a191413 | 2022-01-01 21:56:25 +0000 | [diff] [blame] | 599 | }; |
Kshitij Sisodia | 090a6aa | 2023-11-22 17:03:45 +0000 | [diff] [blame] | 600 | #endif /* TC_IOMMU_EN */ |
Anders Dellien | a191413 | 2022-01-01 21:56:25 +0000 | [diff] [blame] | 601 | |
Davidson K | 938124e | 2023-12-14 12:03:23 +0530 | [diff] [blame] | 602 | dp0: display@DPU_ADDR() { |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 603 | #address-cells = <1>; |
| 604 | #size-cells = <0>; |
| 605 | compatible = "arm,mali-d71"; |
Davidson K | 938124e | 2023-12-14 12:03:23 +0530 | [diff] [blame] | 606 | reg = <HI(DPU_ADDR(0x)) LO(DPU_ADDR(0x)) 0 0x20000>; |
| 607 | interrupts = <GIC_SPI DPU_IRQ IRQ_TYPE_LEVEL_HIGH>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 608 | interrupt-names = "DPU"; |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame] | 609 | DPU_CLK_ATTR1; |
Kshitij Sisodia | 090a6aa | 2023-11-22 17:03:45 +0000 | [diff] [blame] | 610 | #if TC_IOMMU_EN |
Davidson K | ce63312 | 2022-11-21 17:49:51 +0530 | [diff] [blame] | 611 | iommus = <&smmu_700 0x100>; |
Kshitij Sisodia | 090a6aa | 2023-11-22 17:03:45 +0000 | [diff] [blame] | 612 | #endif /* TC_IOMMU_EN */ |
| 613 | #if TC_SCMI_PD_CTRL_EN && (TARGET_PLATFORM != 3) |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 614 | power-domains = <&scmi_devpd DPU_SCMI_PD_IDX>; |
Kshitij Sisodia | 090a6aa | 2023-11-22 17:03:45 +0000 | [diff] [blame] | 615 | #endif /* TC_SCMI_PD_CTRL_EN && (TARGET_PLATFORM != 3) */ |
| 616 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 617 | pl0: pipeline@0 { |
| 618 | reg = <0>; |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame] | 619 | DPU_CLK_ATTR2; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 620 | pl_id = <0>; |
| 621 | ports { |
| 622 | #address-cells = <1>; |
| 623 | #size-cells = <0>; |
| 624 | port@0 { |
| 625 | reg = <0>; |
| 626 | dp_pl0_out0: endpoint { |
| 627 | remote-endpoint = <&vencoder_in>; |
| 628 | }; |
| 629 | }; |
| 630 | }; |
| 631 | }; |
| 632 | |
| 633 | pl1: pipeline@1 { |
| 634 | reg = <1>; |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame] | 635 | DPU_CLK_ATTR3; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 636 | pl_id = <1>; |
| 637 | ports { |
| 638 | #address-cells = <1>; |
| 639 | #size-cells = <0>; |
| 640 | port@0 { |
| 641 | reg = <0>; |
| 642 | }; |
| 643 | }; |
| 644 | }; |
| 645 | }; |
Arunachalam Ganapathy | c44e43d | 2020-11-17 15:05:01 +0000 | [diff] [blame] | 646 | |
Davidson K | 1ad2c41 | 2023-01-13 14:02:13 +0530 | [diff] [blame] | 647 | /* |
| 648 | * L3 cache in the DSU is the Memory System Component (MSC) |
| 649 | * The MPAM registers are accessed through utility bus in the DSU |
| 650 | */ |
| 651 | msc0 { |
| 652 | compatible = "arm,mpam-msc"; |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame] | 653 | reg = <MPAM_ADDR 0x0 0x2000>; |
Davidson K | 1ad2c41 | 2023-01-13 14:02:13 +0530 | [diff] [blame] | 654 | }; |
| 655 | |
Davidson K | 6536105 | 2021-10-13 18:49:41 +0530 | [diff] [blame] | 656 | ete0 { |
| 657 | compatible = "arm,embedded-trace-extension"; |
| 658 | cpu = <&CPU0>; |
| 659 | }; |
| 660 | |
| 661 | ete1 { |
| 662 | compatible = "arm,embedded-trace-extension"; |
| 663 | cpu = <&CPU1>; |
| 664 | }; |
| 665 | |
| 666 | ete2 { |
| 667 | compatible = "arm,embedded-trace-extension"; |
| 668 | cpu = <&CPU2>; |
| 669 | }; |
| 670 | |
| 671 | ete3 { |
| 672 | compatible = "arm,embedded-trace-extension"; |
| 673 | cpu = <&CPU3>; |
| 674 | }; |
| 675 | |
| 676 | ete4 { |
| 677 | compatible = "arm,embedded-trace-extension"; |
| 678 | cpu = <&CPU4>; |
| 679 | }; |
| 680 | |
| 681 | ete5 { |
| 682 | compatible = "arm,embedded-trace-extension"; |
| 683 | cpu = <&CPU5>; |
| 684 | }; |
| 685 | |
| 686 | ete6 { |
| 687 | compatible = "arm,embedded-trace-extension"; |
| 688 | cpu = <&CPU6>; |
| 689 | }; |
| 690 | |
| 691 | ete7 { |
| 692 | compatible = "arm,embedded-trace-extension"; |
| 693 | cpu = <&CPU7>; |
| 694 | }; |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 695 | |
| 696 | #if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 |
| 697 | ete8 { |
| 698 | compatible = "arm,embedded-trace-extension"; |
| 699 | cpu = <&CPU8>; |
| 700 | }; |
| 701 | |
| 702 | ete9 { |
| 703 | compatible = "arm,embedded-trace-extension"; |
| 704 | cpu = <&CPU9>; |
| 705 | }; |
| 706 | |
| 707 | ete10 { |
| 708 | compatible = "arm,embedded-trace-extension"; |
| 709 | cpu = <&CPU10>; |
| 710 | }; |
| 711 | |
| 712 | ete11 { |
| 713 | compatible = "arm,embedded-trace-extension"; |
| 714 | cpu = <&CPU11>; |
| 715 | }; |
| 716 | |
| 717 | ete12 { |
| 718 | compatible = "arm,embedded-trace-extension"; |
| 719 | cpu = <&CPU12>; |
| 720 | }; |
| 721 | |
| 722 | ete13 { |
| 723 | compatible = "arm,embedded-trace-extension"; |
| 724 | cpu = <&CPU13>; |
| 725 | }; |
| 726 | #endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */ |
Davidson K | 6536105 | 2021-10-13 18:49:41 +0530 | [diff] [blame] | 727 | |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 728 | trbe { |
Davidson K | 6536105 | 2021-10-13 18:49:41 +0530 | [diff] [blame] | 729 | compatible = "arm,trace-buffer-extension"; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 730 | interrupts = <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>; |
Davidson K | 6536105 | 2021-10-13 18:49:41 +0530 | [diff] [blame] | 731 | }; |
Arunachalam Ganapathy | 63128dc | 2022-04-11 14:43:15 +0100 | [diff] [blame] | 732 | |
| 733 | trusty { |
| 734 | #size-cells = <0x02>; |
| 735 | #address-cells = <0x02>; |
| 736 | ranges = <0x00>; |
| 737 | compatible = "android,trusty-v1"; |
| 738 | |
| 739 | virtio { |
| 740 | compatible = "android,trusty-virtio-v1"; |
| 741 | }; |
| 742 | |
| 743 | test { |
| 744 | compatible = "android,trusty-test-v1"; |
| 745 | }; |
| 746 | |
| 747 | log { |
| 748 | compatible = "android,trusty-log-v1"; |
| 749 | }; |
| 750 | |
| 751 | irq { |
| 752 | ipi-range = <0x08 0x0f 0x08>; |
| 753 | interrupt-ranges = <0x00 0x0f 0x00 0x10 0x1f 0x01 0x20 0x3f 0x02>; |
| 754 | interrupt-templates = <0x01 0x00 0x8001 0x01 0x01 0x04 0x8001 0x01 0x00 0x04>; |
| 755 | compatible = "android,trusty-irq-v1"; |
| 756 | }; |
| 757 | }; |
Boyan Karatotev | d2ca287 | 2023-11-28 16:08:52 +0000 | [diff] [blame^] | 758 | |
| 759 | /* used in U-boot, Linux doesn't care */ |
| 760 | arm_ffa { |
| 761 | compatible = "arm,ffa"; |
| 762 | method = "smc"; |
| 763 | }; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 764 | }; |