blob: e736e49756db85b50d1d23dd93b099ed63c68bf2 [file] [log] [blame]
Usama Arifbec5afd2020-04-17 16:13:39 +01001/*
2 * Copyright (c) 2020, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/dts-v1/;
8
9/ {
10 compatible = "arm,tc0";
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
14
15 aliases {
16 serial0 = &soc_uart0;
17 };
18
19 chosen {
20 stdout-path = "soc_uart0:115200n8";
21 };
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 cpu-map {
28 cluster0 {
29 core0 {
30 cpu = <&CPU0>;
31 };
32 core1 {
33 cpu = <&CPU1>;
34 };
35 core2 {
36 cpu = <&CPU2>;
37 };
38 core3 {
39 cpu = <&CPU3>;
40 };
41 };
42 };
43
44 CPU0:cpu@0 {
45 device_type = "cpu";
46 compatible = "arm,armv8";
47 reg = <0x0>;
48 enable-method = "psci";
49 clocks = <&scmi_dvfs 0>;
50 };
51
52 CPU1:cpu@100 {
53 device_type = "cpu";
54 compatible = "arm,armv8";
55 reg = <0x100>;
56 enable-method = "psci";
57 clocks = <&scmi_dvfs 0>;
58 };
59
60 CPU2:cpu@200 {
61 device_type = "cpu";
62 compatible = "arm,armv8";
63 reg = <0x200>;
64 enable-method = "psci";
65 clocks = <&scmi_dvfs 0>;
66 };
67
68 CPU3:cpu@300 {
69 device_type = "cpu";
70 compatible = "arm,armv8";
71 reg = <0x300>;
72 enable-method = "psci";
73 clocks = <&scmi_dvfs 0>;
74 };
75
76 };
77
78 memory@80000000 {
79 device_type = "memory";
80 reg = <0x0 0x80000000 0x0 0x80000000>;
81 };
82
83 psci {
84 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
85 method = "smc";
86 };
87
88 sram: sram@6000000 {
89 compatible = "mmio-sram";
90 reg = <0x0 0x06000000 0x0 0x8000>;
91
92 #address-cells = <1>;
93 #size-cells = <1>;
94 ranges = <0 0x0 0x06000000 0x8000>;
95
96 cpu_scp_scmi_mem: scp-shmem@0 {
97 compatible = "arm,scmi-shmem";
98 reg = <0x0 0x80>;
99 };
100 };
101
102 mbox_db_rx: mhu@45010000 {
103 compatible = "arm,mhuv2","arm,primecell";
104 reg = <0x0 0x45010000 0x0 0x1000>;
105 clocks = <&soc_refclk100mhz>;
106 clock-names = "apb_pclk";
107 #mbox-cells = <1>;
108 interrupts = <0 316 4>;
109 interrupt-names = "mhu_rx";
110 mhu-protocol = "doorbell";
111 };
112
113 mbox_db_tx: mhu@45000000 {
114 compatible = "arm,mhuv2","arm,primecell";
115 reg = <0x0 0x45000000 0x0 0x1000>;
116 clocks = <&soc_refclk100mhz>;
117 clock-names = "apb_pclk";
118 #mbox-cells = <1>;
119 interrupt-names = "mhu_tx";
120 mhu-protocol = "doorbell";
121 };
122
123 scmi {
124 compatible = "arm,scmi";
125 method = "mailbox-doorbell";
126 mbox-names = "tx", "rx";
127 mboxes = <&mbox_db_tx 0 &mbox_db_rx 0>;
128 shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>;
129 #address-cells = <1>;
130 #size-cells = <0>;
131
132 scmi_dvfs: protocol@13 {
133 reg = <0x13>;
134 #clock-cells = <1>;
135 };
136
137 scmi_clk: protocol@14 {
138 reg = <0x14>;
139 #clock-cells = <1>;
140 };
141 };
142
143 gic: interrupt-controller@2c010000 {
144 compatible = "arm,gic-600", "arm,gic-v3";
145 #address-cells = <2>;
146 #interrupt-cells = <3>;
147 #size-cells = <2>;
148 ranges;
149 interrupt-controller;
150 reg = <0x0 0x30000000 0 0x10000>, /* GICD */
151 <0x0 0x30140000 0 0x200000>; /* GICR */
152 interrupts = <0x1 0x9 0x4>;
153 };
154
155 timer {
156 compatible = "arm,armv8-timer";
157 interrupts = <0x1 13 0x8>,
158 <0x1 14 0x8>,
159 <0x1 11 0x8>,
160 <0x1 10 0x8>;
161 };
162
163 soc_refclk100mhz: refclk100mhz {
164 compatible = "fixed-clock";
165 #clock-cells = <0>;
166 clock-frequency = <100000000>;
167 clock-output-names = "apb_pclk";
168 };
169
170 soc_refclk60mhz: refclk60mhz {
171 compatible = "fixed-clock";
172 #clock-cells = <0>;
173 clock-frequency = <60000000>;
174 clock-output-names = "iofpga_clk";
175 };
176
177 soc_uartclk: uartclk {
178 compatible = "fixed-clock";
179 #clock-cells = <0>;
180 clock-frequency = <50000000>;
181 clock-output-names = "uartclk";
182 };
183
184 soc_uart0: uart@7ff80000 {
185 compatible = "arm,pl011", "arm,primecell";
186 reg = <0x0 0x7ff80000 0x0 0x1000>;
187 interrupts = <0x0 116 0x4>;
188 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
189 clock-names = "uartclk", "apb_pclk";
190 status = "okay";
191 };
192
193 vencoder {
194 compatible = "drm,virtual-encoder";
195
196 port {
197 vencoder_in: endpoint {
198 remote-endpoint = <&hdlcd_out>;
199 };
200 };
201
202 display-timings {
203 panel-timing {
204 clock-frequency = <25175000>;
205 hactive = <640>;
206 vactive = <480>;
207 hfront-porch = <16>;
208 hback-porch = <48>;
209 hsync-len = <96>;
210 vfront-porch = <10>;
211 vback-porch = <33>;
212 vsync-len = <2>;
213 };
214 };
215
216 };
217
218 hdlcd: hdlcd@7ff60000 {
219 compatible = "arm,hdlcd";
220 reg = <0x0 0x7ff60000 0x0 0x1000>;
221 interrupts = <0x0 117 0x4>;
222 clocks = <&fake_hdlcd_clk>;
223 clock-names = "pxlclk";
224 status = "ok";
225
226 port {
227 hdlcd_out: endpoint {
228 remote-endpoint = <&vencoder_in>;
229 };
230 };
231 };
232
233 fake_hdlcd_clk: fake-hdlcd-clk {
234 compatible = "fixed-clock";
235 #clock-cells = <0>;
236 clock-frequency = <25175000>;
237 clock-output-names = "pxlclk";
238 };
239
240 ethernet@18000000 {
241 compatible = "smsc,lan91c111";
242 reg = <0x0 0x18000000 0x0 0x10000>;
243 interrupts = <0 109 4>;
244 };
245
246 kmi@1c060000 {
247 compatible = "arm,pl050", "arm,primecell";
248 reg = <0x0 0x001c060000 0x0 0x1000>;
249 interrupts = <0 197 4>;
250 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
251 clock-names = "KMIREFCLK", "apb_pclk";
252 };
253
254 kmi@1c070000 {
255 compatible = "arm,pl050", "arm,primecell";
256 reg = <0x0 0x001c070000 0x0 0x1000>;
257 interrupts = <0 103 4>;
258 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
259 clock-names = "KMIREFCLK", "apb_pclk";
260 };
261
262 bp_clock24mhz: clock24mhz {
263 compatible = "fixed-clock";
264 #clock-cells = <0>;
265 clock-frequency = <24000000>;
266 clock-output-names = "bp:clock24mhz";
267 };
268
269 virtio_block@1c130000 {
270 compatible = "virtio,mmio";
271 reg = <0x0 0x1c130000 0x0 0x200>;
272 interrupts = <0 204 4>;
273 };
274
275 dp0: display@2cc00000 {
276 #address-cells = <1>;
277 #size-cells = <0>;
278 compatible = "arm,mali-d71";
279 reg = <0 0x2cc00000 0 0x20000>;
280 interrupts = <0 69 4>;
281 interrupt-names = "DPU";
282 clocks = <&scmi_clk 0>;
283 clock-names = "aclk";
284 status = "disabled";
285 pl0: pipeline@0 {
286 reg = <0>;
287 clocks = <&scmi_clk 1>;
288 clock-names = "pxclk";
289 pl_id = <0>;
290 ports {
291 #address-cells = <1>;
292 #size-cells = <0>;
293 port@0 {
294 reg = <0>;
295 dp_pl0_out0: endpoint {
296 remote-endpoint = <&vencoder_in>;
297 };
298 };
299 };
300 };
301
302 pl1: pipeline@1 {
303 reg = <1>;
304 clocks = <&scmi_clk 2>;
305 clock-names = "pxclk";
306 pl_id = <1>;
307 ports {
308 #address-cells = <1>;
309 #size-cells = <0>;
310 port@0 {
311 reg = <0>;
312 };
313 };
314 };
315 };
316};