Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 1 | /* |
annsai01 | 7c607f2 | 2023-02-20 13:34:57 +0000 | [diff] [blame] | 2 | * Copyright (c) 2020-2024, Arm Limited. All rights reserved. |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | |
Kshitij Sisodia | b32a8f4 | 2023-08-16 09:46:05 +0100 | [diff] [blame] | 9 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 10 | #include <dt-bindings/interrupt-controller/irq.h> |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 11 | #include "platform_def.h" |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame] | 12 | #include "tc_vers.dtsi" |
Kshitij Sisodia | b32a8f4 | 2023-08-16 09:46:05 +0100 | [diff] [blame] | 13 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 14 | / { |
Usama Arif | f151362 | 2021-04-09 17:07:41 +0100 | [diff] [blame] | 15 | compatible = "arm,tc"; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 16 | interrupt-parent = <&gic>; |
| 17 | #address-cells = <2>; |
| 18 | #size-cells = <2>; |
| 19 | |
| 20 | aliases { |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 21 | serial0 = &os_uart; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 22 | }; |
| 23 | |
| 24 | chosen { |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame^] | 25 | stdout-path = STDOUT_PATH; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 26 | }; |
| 27 | |
| 28 | cpus { |
| 29 | #address-cells = <1>; |
| 30 | #size-cells = <0>; |
| 31 | |
| 32 | cpu-map { |
| 33 | cluster0 { |
| 34 | core0 { |
| 35 | cpu = <&CPU0>; |
| 36 | }; |
| 37 | core1 { |
| 38 | cpu = <&CPU1>; |
| 39 | }; |
| 40 | core2 { |
| 41 | cpu = <&CPU2>; |
| 42 | }; |
| 43 | core3 { |
| 44 | cpu = <&CPU3>; |
| 45 | }; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 46 | core4 { |
| 47 | cpu = <&CPU4>; |
| 48 | }; |
| 49 | core5 { |
| 50 | cpu = <&CPU5>; |
| 51 | }; |
| 52 | core6 { |
| 53 | cpu = <&CPU6>; |
| 54 | }; |
| 55 | core7 { |
| 56 | cpu = <&CPU7>; |
| 57 | }; |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 58 | #if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 |
| 59 | core8 { |
| 60 | cpu = <&CPU8>; |
| 61 | }; |
| 62 | core9 { |
| 63 | cpu = <&CPU9>; |
| 64 | }; |
| 65 | core10 { |
| 66 | cpu = <&CPU10>; |
| 67 | }; |
| 68 | core11 { |
| 69 | cpu = <&CPU11>; |
| 70 | }; |
| 71 | core12 { |
| 72 | cpu = <&CPU12>; |
| 73 | }; |
| 74 | core13 { |
| 75 | cpu = <&CPU13>; |
| 76 | }; |
| 77 | #endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */ |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 78 | }; |
| 79 | }; |
| 80 | |
Usama Arif | 5790078 | 2020-08-12 17:14:37 +0100 | [diff] [blame] | 81 | /* |
| 82 | * The timings below are just to demonstrate working cpuidle. |
| 83 | * These values may be inaccurate. |
| 84 | */ |
| 85 | idle-states { |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 86 | entry-method = "psci"; |
Usama Arif | 5790078 | 2020-08-12 17:14:37 +0100 | [diff] [blame] | 87 | |
| 88 | CPU_SLEEP_0: cpu-sleep-0 { |
| 89 | compatible = "arm,idle-state"; |
| 90 | arm,psci-suspend-param = <0x0010000>; |
| 91 | local-timer-stop; |
| 92 | entry-latency-us = <300>; |
| 93 | exit-latency-us = <1200>; |
| 94 | min-residency-us = <2000>; |
| 95 | }; |
| 96 | CLUSTER_SLEEP_0: cluster-sleep-0 { |
| 97 | compatible = "arm,idle-state"; |
| 98 | arm,psci-suspend-param = <0x1010000>; |
| 99 | local-timer-stop; |
| 100 | entry-latency-us = <400>; |
| 101 | exit-latency-us = <1200>; |
| 102 | min-residency-us = <2500>; |
| 103 | }; |
| 104 | }; |
| 105 | |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 106 | amus { |
| 107 | amu: amu-0 { |
| 108 | #address-cells = <1>; |
| 109 | #size-cells = <0>; |
| 110 | |
| 111 | mpmm_gear0: counter@0 { |
| 112 | reg = <0>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 113 | enable-at-el3; |
| 114 | }; |
| 115 | |
| 116 | mpmm_gear1: counter@1 { |
| 117 | reg = <1>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 118 | enable-at-el3; |
| 119 | }; |
| 120 | |
| 121 | mpmm_gear2: counter@2 { |
| 122 | reg = <2>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 123 | enable-at-el3; |
| 124 | }; |
| 125 | }; |
| 126 | }; |
| 127 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 128 | CPU0:cpu@0 { |
| 129 | device_type = "cpu"; |
| 130 | compatible = "arm,armv8"; |
| 131 | reg = <0x0>; |
| 132 | enable-method = "psci"; |
| 133 | clocks = <&scmi_dvfs 0>; |
Usama Arif | 5790078 | 2020-08-12 17:14:37 +0100 | [diff] [blame] | 134 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 135 | capacity-dmips-mhz = <LIT_CAPACITY>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 136 | amu = <&amu>; |
| 137 | supports-mpmm; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 138 | }; |
| 139 | |
| 140 | CPU1:cpu@100 { |
| 141 | device_type = "cpu"; |
| 142 | compatible = "arm,armv8"; |
| 143 | reg = <0x100>; |
| 144 | enable-method = "psci"; |
| 145 | clocks = <&scmi_dvfs 0>; |
Usama Arif | 5790078 | 2020-08-12 17:14:37 +0100 | [diff] [blame] | 146 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 147 | capacity-dmips-mhz = <LIT_CAPACITY>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 148 | amu = <&amu>; |
| 149 | supports-mpmm; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 150 | }; |
| 151 | |
| 152 | CPU2:cpu@200 { |
| 153 | device_type = "cpu"; |
| 154 | compatible = "arm,armv8"; |
| 155 | reg = <0x200>; |
| 156 | enable-method = "psci"; |
Usama Arif | 5790078 | 2020-08-12 17:14:37 +0100 | [diff] [blame] | 157 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 158 | #if TARGET_PLATFORM <= 2 |
| 159 | clocks = <&scmi_dvfs 0>; |
| 160 | capacity-dmips-mhz = <LIT_CAPACITY>; |
| 161 | #elif TARGET_PLATFORM == 3 |
| 162 | clocks = <&scmi_dvfs 1>; |
| 163 | capacity-dmips-mhz = <MID_CAPACITY>; |
| 164 | #endif /* TARGET_PLATFORM == 3 */ |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 165 | amu = <&amu>; |
| 166 | supports-mpmm; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 167 | }; |
| 168 | |
| 169 | CPU3:cpu@300 { |
| 170 | device_type = "cpu"; |
| 171 | compatible = "arm,armv8"; |
| 172 | reg = <0x300>; |
| 173 | enable-method = "psci"; |
Usama Arif | 5790078 | 2020-08-12 17:14:37 +0100 | [diff] [blame] | 174 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 175 | #if TARGET_PLATFORM <= 2 |
| 176 | clocks = <&scmi_dvfs 0>; |
| 177 | capacity-dmips-mhz = <LIT_CAPACITY>; |
| 178 | #elif TARGET_PLATFORM == 3 |
| 179 | clocks = <&scmi_dvfs 1>; |
| 180 | capacity-dmips-mhz = <MID_CAPACITY>; |
| 181 | #endif /* TARGET_PLATFORM == 3 */ |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 182 | amu = <&amu>; |
| 183 | supports-mpmm; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 184 | }; |
| 185 | |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 186 | CPU4:cpu@400 { |
| 187 | device_type = "cpu"; |
| 188 | compatible = "arm,armv8"; |
| 189 | reg = <0x400>; |
| 190 | enable-method = "psci"; |
Usama Arif | 75edb75 | 2021-02-03 15:40:46 +0000 | [diff] [blame] | 191 | clocks = <&scmi_dvfs 1>; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 192 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 193 | capacity-dmips-mhz = <MID_CAPACITY>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 194 | amu = <&amu>; |
| 195 | supports-mpmm; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 196 | }; |
| 197 | |
| 198 | CPU5:cpu@500 { |
| 199 | device_type = "cpu"; |
| 200 | compatible = "arm,armv8"; |
| 201 | reg = <0x500>; |
| 202 | enable-method = "psci"; |
Usama Arif | 75edb75 | 2021-02-03 15:40:46 +0000 | [diff] [blame] | 203 | clocks = <&scmi_dvfs 1>; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 204 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 205 | capacity-dmips-mhz = <MID_CAPACITY>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 206 | amu = <&amu>; |
| 207 | supports-mpmm; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 208 | }; |
| 209 | |
| 210 | CPU6:cpu@600 { |
| 211 | device_type = "cpu"; |
| 212 | compatible = "arm,armv8"; |
| 213 | reg = <0x600>; |
| 214 | enable-method = "psci"; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 215 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 216 | #if TARGET_PLATFORM <= 2 |
| 217 | clocks = <&scmi_dvfs 1>; |
| 218 | capacity-dmips-mhz = <MID_CAPACITY>; |
| 219 | #elif TARGET_PLATFORM == 3 |
| 220 | clocks = <&scmi_dvfs 2>; |
| 221 | capacity-dmips-mhz = <BIG_CAPACITY>; |
| 222 | #endif /* TARGET_PLATFORM == 3 */ |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 223 | amu = <&amu>; |
| 224 | supports-mpmm; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 225 | }; |
| 226 | |
| 227 | CPU7:cpu@700 { |
| 228 | device_type = "cpu"; |
| 229 | compatible = "arm,armv8"; |
| 230 | reg = <0x700>; |
| 231 | enable-method = "psci"; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 232 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 233 | #if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 |
| 234 | clocks = <&scmi_dvfs 1>; |
| 235 | capacity-dmips-mhz = <MID_CAPACITY>; |
| 236 | #else |
| 237 | clocks = <&scmi_dvfs 2>; |
| 238 | capacity-dmips-mhz = <BIG_CAPACITY>; |
| 239 | #endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */ |
| 240 | amu = <&amu>; |
| 241 | supports-mpmm; |
| 242 | }; |
| 243 | |
| 244 | #if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 |
| 245 | CPU8:cpu@800 { |
| 246 | device_type = "cpu"; |
| 247 | compatible = "arm,armv8"; |
| 248 | reg = <0x800>; |
| 249 | enable-method = "psci"; |
| 250 | clocks = <&scmi_dvfs 1>; |
| 251 | capacity-dmips-mhz = <MID_CAPACITY>; |
| 252 | amu = <&amu>; |
| 253 | supports-mpmm; |
| 254 | }; |
| 255 | |
| 256 | CPU9:cpu@900 { |
| 257 | device_type = "cpu"; |
| 258 | compatible = "arm,armv8"; |
| 259 | reg = <0x900>; |
| 260 | enable-method = "psci"; |
| 261 | clocks = <&scmi_dvfs 2>; |
| 262 | capacity-dmips-mhz = <BIG2_CAPACITY>; |
| 263 | amu = <&amu>; |
| 264 | supports-mpmm; |
| 265 | }; |
| 266 | |
| 267 | CPU10:cpu@A00 { |
| 268 | device_type = "cpu"; |
| 269 | compatible = "arm,armv8"; |
| 270 | reg = <0xA00>; |
| 271 | enable-method = "psci"; |
| 272 | clocks = <&scmi_dvfs 2>; |
| 273 | capacity-dmips-mhz = <BIG2_CAPACITY>; |
| 274 | amu = <&amu>; |
| 275 | supports-mpmm; |
| 276 | }; |
| 277 | |
| 278 | CPU11:cpu@B00 { |
| 279 | device_type = "cpu"; |
| 280 | compatible = "arm,armv8"; |
| 281 | reg = <0xB00>; |
| 282 | enable-method = "psci"; |
| 283 | clocks = <&scmi_dvfs 2>; |
| 284 | capacity-dmips-mhz = <BIG2_CAPACITY>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 285 | amu = <&amu>; |
| 286 | supports-mpmm; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 287 | }; |
| 288 | |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 289 | CPU12:cpu@C00 { |
| 290 | device_type = "cpu"; |
| 291 | compatible = "arm,armv8"; |
| 292 | reg = <0xC00>; |
| 293 | enable-method = "psci"; |
| 294 | clocks = <&scmi_dvfs 3>; |
| 295 | capacity-dmips-mhz = <BIG_CAPACITY>; |
| 296 | amu = <&amu>; |
| 297 | supports-mpmm; |
| 298 | }; |
| 299 | |
| 300 | CPU13:cpu@D00 { |
| 301 | device_type = "cpu"; |
| 302 | compatible = "arm,armv8"; |
| 303 | reg = <0xD00>; |
| 304 | enable-method = "psci"; |
| 305 | clocks = <&scmi_dvfs 3>; |
| 306 | capacity-dmips-mhz = <BIG_CAPACITY>; |
| 307 | amu = <&amu>; |
| 308 | supports-mpmm; |
| 309 | }; |
| 310 | #endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */ |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 311 | }; |
| 312 | |
Arunachalam Ganapathy | 948bb44 | 2020-12-14 12:31:32 +0000 | [diff] [blame] | 313 | reserved-memory { |
| 314 | #address-cells = <2>; |
| 315 | #size-cells = <2>; |
| 316 | ranges; |
| 317 | |
Anders Dellien | a6c9b72 | 2021-12-08 21:57:21 +0000 | [diff] [blame] | 318 | linux,cma { |
| 319 | compatible = "shared-dma-pool"; |
| 320 | reusable; |
| 321 | size = <0x0 0x8000000>; |
| 322 | linux,cma-default; |
| 323 | }; |
| 324 | |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 325 | optee@f8e00000 { |
Davidson K | 4662a88 | 2022-12-14 17:38:14 +0530 | [diff] [blame] | 326 | compatible = "restricted-dma-pool"; |
Arunachalam Ganapathy | ac9e120 | 2022-04-11 17:38:17 +0100 | [diff] [blame] | 327 | reg = <0x00000000 0xf8e00000 0 0x00200000>; |
Arunachalam Ganapathy | 948bb44 | 2020-12-14 12:31:32 +0000 | [diff] [blame] | 328 | }; |
Tudor Cretu | 77b301a | 2021-09-24 12:09:53 +0000 | [diff] [blame] | 329 | |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 330 | fwu_mm@fca00000 { |
Tudor Cretu | 77b301a | 2021-09-24 12:09:53 +0000 | [diff] [blame] | 331 | reg = <0x00000000 0xfca00000 0 0x00400000>; |
| 332 | no-map; |
| 333 | }; |
Arunachalam Ganapathy | 948bb44 | 2020-12-14 12:31:32 +0000 | [diff] [blame] | 334 | }; |
| 335 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 336 | psci { |
Usama Arif | 7a64bfa | 2021-05-27 20:09:17 +0100 | [diff] [blame] | 337 | compatible = "arm,psci-1.0", "arm,psci-0.2"; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 338 | method = "smc"; |
| 339 | }; |
| 340 | |
Boyan Karatotev | 4fef47c | 2023-11-15 11:29:59 +0000 | [diff] [blame] | 341 | cpu-pmu { |
| 342 | compatible = "arm,armv8-pmuv3"; |
| 343 | interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| 344 | interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, |
| 345 | <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7> |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 346 | #if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 |
| 347 | ,<&CPU8>, <&CPU9>, <&CPU10>, <&CPU11>, |
| 348 | <&CPU12>, <&CPU13> |
| 349 | #endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */ |
Boyan Karatotev | 4fef47c | 2023-11-15 11:29:59 +0000 | [diff] [blame] | 350 | ; |
| 351 | }; |
| 352 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 353 | sram: sram@6000000 { |
| 354 | compatible = "mmio-sram"; |
| 355 | reg = <0x0 0x06000000 0x0 0x8000>; |
| 356 | |
| 357 | #address-cells = <1>; |
| 358 | #size-cells = <1>; |
| 359 | ranges = <0 0x0 0x06000000 0x8000>; |
| 360 | |
| 361 | cpu_scp_scmi_mem: scp-shmem@0 { |
| 362 | compatible = "arm,scmi-shmem"; |
| 363 | reg = <0x0 0x80>; |
| 364 | }; |
| 365 | }; |
| 366 | |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame] | 367 | mbox_db_rx: mhu@MHU_RX_ADDR() { |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 368 | compatible = "arm,mhuv2-rx","arm,primecell"; |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame] | 369 | reg = <0x0 MHU_RX_ADDR(0x) 0x0 0x1000>; |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 370 | clocks = <&soc_refclk>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 371 | clock-names = "apb_pclk"; |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 372 | #mbox-cells = <2>; |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame] | 373 | interrupts = <GIC_SPI INT_MBOX_RX IRQ_TYPE_LEVEL_HIGH>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 374 | interrupt-names = "mhu_rx"; |
| 375 | mhu-protocol = "doorbell"; |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 376 | arm,mhuv2-protocols = <0 1>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 377 | }; |
| 378 | |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame] | 379 | mbox_db_tx: mhu@MHU_TX_ADDR() { |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 380 | compatible = "arm,mhuv2-tx","arm,primecell"; |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame] | 381 | reg = <0x0 MHU_TX_ADDR(0x) 0x0 0x1000>; |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 382 | clocks = <&soc_refclk>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 383 | clock-names = "apb_pclk"; |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 384 | #mbox-cells = <2>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 385 | interrupt-names = "mhu_tx"; |
| 386 | mhu-protocol = "doorbell"; |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 387 | arm,mhuv2-protocols = <0 1>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 388 | }; |
| 389 | |
| 390 | scmi { |
| 391 | compatible = "arm,scmi"; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 392 | mbox-names = "tx", "rx"; |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 393 | mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 394 | shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>; |
| 395 | #address-cells = <1>; |
| 396 | #size-cells = <0>; |
| 397 | |
Ben Horgan | 80781a5 | 2023-07-26 20:45:27 +0100 | [diff] [blame] | 398 | scmi_devpd: protocol@11 { |
| 399 | reg = <0x11>; |
| 400 | #power-domain-cells = <1>; |
| 401 | }; |
| 402 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 403 | scmi_dvfs: protocol@13 { |
| 404 | reg = <0x13>; |
| 405 | #clock-cells = <1>; |
| 406 | }; |
| 407 | |
| 408 | scmi_clk: protocol@14 { |
| 409 | reg = <0x14>; |
| 410 | #clock-cells = <1>; |
| 411 | }; |
| 412 | }; |
| 413 | |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame^] | 414 | gic: interrupt-controller@GIC_CTRL_ADDR { |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 415 | compatible = "arm,gic-v3"; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 416 | #address-cells = <2>; |
| 417 | #interrupt-cells = <3>; |
| 418 | #size-cells = <2>; |
| 419 | ranges; |
| 420 | interrupt-controller; |
| 421 | reg = <0x0 0x30000000 0 0x10000>, /* GICD */ |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame^] | 422 | <0x0 0x30080000 0 GIC_GICR_OFFSET>; /* GICR */ |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 423 | interrupts = <GIC_PPI 0x9 IRQ_TYPE_LEVEL_LOW>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 424 | }; |
| 425 | |
| 426 | timer { |
| 427 | compatible = "arm,armv8-timer"; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 428 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| 429 | <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| 430 | <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| 431 | <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 432 | }; |
| 433 | |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 434 | soc_refclk: refclk { |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 435 | compatible = "fixed-clock"; |
| 436 | #clock-cells = <0>; |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame^] | 437 | clock-frequency = <1000000000>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 438 | clock-output-names = "apb_pclk"; |
| 439 | }; |
| 440 | |
| 441 | soc_refclk60mhz: refclk60mhz { |
| 442 | compatible = "fixed-clock"; |
| 443 | #clock-cells = <0>; |
| 444 | clock-frequency = <60000000>; |
| 445 | clock-output-names = "iofpga_clk"; |
| 446 | }; |
| 447 | |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 448 | soc_uartclk: uartclk { |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 449 | compatible = "fixed-clock"; |
| 450 | #clock-cells = <0>; |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame] | 451 | clock-frequency = <UARTCLK_FREQ>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 452 | clock-output-names = "uartclk"; |
| 453 | }; |
| 454 | |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame^] | 455 | /* soc_uart0 on FPGA, ap_ns_uart on FVP */ |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 456 | os_uart: serial@2a400000 { |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 457 | compatible = "arm,pl011", "arm,primecell"; |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame^] | 458 | reg = <0x0 0x2A400000 0x0 UART_OFFSET>; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 459 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 460 | clocks = <&soc_uartclk>, <&soc_refclk>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 461 | clock-names = "uartclk", "apb_pclk"; |
| 462 | status = "okay"; |
| 463 | }; |
| 464 | |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 465 | rtc@1c170000 { |
Jayanth Dodderi Chidanand | 2858cf5 | 2022-09-28 11:41:48 +0100 | [diff] [blame] | 466 | compatible = "arm,pl031", "arm,primecell"; |
| 467 | reg = <0x0 0x1C170000 0x0 0x1000>; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 468 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 469 | clocks = <&soc_refclk>; |
Jayanth Dodderi Chidanand | 2858cf5 | 2022-09-28 11:41:48 +0100 | [diff] [blame] | 470 | clock-names = "apb_pclk"; |
Jayanth Dodderi Chidanand | 2858cf5 | 2022-09-28 11:41:48 +0100 | [diff] [blame] | 471 | }; |
Rupinderjit Singh | d2d0298 | 2022-09-12 17:25:32 +0100 | [diff] [blame] | 472 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 473 | vencoder { |
| 474 | compatible = "drm,virtual-encoder"; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 475 | port { |
| 476 | vencoder_in: endpoint { |
Avinash Mehta | df71a60 | 2020-07-22 16:40:07 +0100 | [diff] [blame] | 477 | remote-endpoint = <&dp_pl0_out0>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 478 | }; |
| 479 | }; |
| 480 | |
| 481 | display-timings { |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 482 | timing-panel { |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame^] | 483 | VENCODER_TIMING; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 484 | }; |
| 485 | }; |
| 486 | |
| 487 | }; |
| 488 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 489 | ethernet@18000000 { |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame^] | 490 | compatible = ETH_COMPATIBLE; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 491 | reg = <0x0 0x18000000 0x0 0x10000>; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 492 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame^] | 493 | |
| 494 | /* FPGA only but will work on FVP. Keep for simplicity */ |
| 495 | phy-mode = "mii"; |
| 496 | reg-io-width = <2>; |
| 497 | smsc,irq-push-pull; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 498 | }; |
| 499 | |
| 500 | kmi@1c060000 { |
| 501 | compatible = "arm,pl050", "arm,primecell"; |
| 502 | reg = <0x0 0x001c060000 0x0 0x1000>; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 503 | interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 504 | clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; |
| 505 | clock-names = "KMIREFCLK", "apb_pclk"; |
| 506 | }; |
| 507 | |
| 508 | kmi@1c070000 { |
| 509 | compatible = "arm,pl050", "arm,primecell"; |
| 510 | reg = <0x0 0x001c070000 0x0 0x1000>; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 511 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 512 | clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; |
| 513 | clock-names = "KMIREFCLK", "apb_pclk"; |
| 514 | }; |
| 515 | |
| 516 | bp_clock24mhz: clock24mhz { |
| 517 | compatible = "fixed-clock"; |
| 518 | #clock-cells = <0>; |
| 519 | clock-frequency = <24000000>; |
| 520 | clock-output-names = "bp:clock24mhz"; |
| 521 | }; |
| 522 | |
| 523 | virtio_block@1c130000 { |
| 524 | compatible = "virtio,mmio"; |
| 525 | reg = <0x0 0x1c130000 0x0 0x200>; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 526 | /* spec lists this wrong */ |
| 527 | interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 528 | }; |
| 529 | |
Usama Arif | 1cd56dc | 2020-06-10 16:27:53 +0100 | [diff] [blame] | 530 | sysreg: sysreg@1c010000 { |
| 531 | compatible = "arm,vexpress-sysreg"; |
| 532 | reg = <0x0 0x001c010000 0x0 0x1000>; |
| 533 | gpio-controller; |
| 534 | #gpio-cells = <2>; |
| 535 | }; |
| 536 | |
| 537 | fixed_3v3: v2m-3v3 { |
| 538 | compatible = "regulator-fixed"; |
| 539 | regulator-name = "3V3"; |
| 540 | regulator-min-microvolt = <3300000>; |
| 541 | regulator-max-microvolt = <3300000>; |
| 542 | regulator-always-on; |
| 543 | }; |
| 544 | |
| 545 | mmci@1c050000 { |
| 546 | compatible = "arm,pl180", "arm,primecell"; |
| 547 | reg = <0x0 0x001c050000 0x0 0x1000>; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 548 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
| 549 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame^] | 550 | MMC_REMOVABLE; |
Usama Arif | 1cd56dc | 2020-06-10 16:27:53 +0100 | [diff] [blame] | 551 | wp-gpios = <&sysreg 1 0>; |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame^] | 552 | bus-width = <4>; |
| 553 | max-frequency = <25000000>; |
Usama Arif | 1cd56dc | 2020-06-10 16:27:53 +0100 | [diff] [blame] | 554 | vmmc-supply = <&fixed_3v3>; |
| 555 | clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; |
| 556 | clock-names = "mclk", "apb_pclk"; |
| 557 | }; |
| 558 | |
Rupinderjit Singh | b2a75b8 | 2023-02-03 09:29:57 +0000 | [diff] [blame] | 559 | gpu_clk: gpu_clk { |
| 560 | compatible = "fixed-clock"; |
| 561 | #clock-cells = <0>; |
| 562 | clock-frequency = <1000000000>; |
| 563 | }; |
| 564 | |
| 565 | gpu_core_clk: gpu_core_clk { |
| 566 | compatible = "fixed-clock"; |
| 567 | #clock-cells = <0>; |
| 568 | clock-frequency = <1000000000>; |
| 569 | }; |
| 570 | |
Anders Dellien | 7a84980 | 2022-01-01 21:51:21 +0000 | [diff] [blame] | 571 | gpu: gpu@2d000000 { |
| 572 | compatible = "arm,mali-midgard"; |
| 573 | reg = <0x0 0x2d000000 0x0 0x200000>; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 574 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, |
| 575 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, |
| 576 | <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
Anders Dellien | 7a84980 | 2022-01-01 21:51:21 +0000 | [diff] [blame] | 577 | interrupt-names = "JOB", "MMU", "GPU"; |
Ben Horgan | 80781a5 | 2023-07-26 20:45:27 +0100 | [diff] [blame] | 578 | clocks = <&gpu_core_clk>; |
| 579 | clock-names = "shadercores"; |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 580 | power-domains = <&scmi_devpd GPU_SCMI_PD_IDX>; |
Ben Horgan | 80781a5 | 2023-07-26 20:45:27 +0100 | [diff] [blame] | 581 | scmi-perf-domain = <3>; |
Davidson K | ce63312 | 2022-11-21 17:49:51 +0530 | [diff] [blame] | 582 | iommus = <&smmu_700 0x200>; |
Anders Dellien | 7a84980 | 2022-01-01 21:51:21 +0000 | [diff] [blame] | 583 | }; |
| 584 | |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 585 | power_model_simple { |
Rupinderjit Singh | b2a75b8 | 2023-02-03 09:29:57 +0000 | [diff] [blame] | 586 | /* |
| 587 | * Numbers used are irrelevant to Titan, |
| 588 | * it helps suppressing the kernel warnings. |
| 589 | */ |
| 590 | compatible = "arm,mali-simple-power-model"; |
| 591 | static-coefficient = <2427750>; |
| 592 | dynamic-coefficient = <4687>; |
| 593 | ts = <20000 2000 (-20) 2>; |
| 594 | thermal-zone = ""; |
| 595 | }; |
| 596 | |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 597 | smmu_700: iommu@3f000000 { |
Anders Dellien | a191413 | 2022-01-01 21:56:25 +0000 | [diff] [blame] | 598 | #iommu-cells = <1>; |
| 599 | compatible = "arm,smmu-v3"; |
Davidson K | ce63312 | 2022-11-21 17:49:51 +0530 | [diff] [blame] | 600 | reg = <0x0 0x3f000000 0x0 0x5000000>; |
Kshitij Sisodia | b32a8f4 | 2023-08-16 09:46:05 +0100 | [diff] [blame] | 601 | interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, |
| 602 | <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, |
| 603 | <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>; |
| 604 | interrupt-names = "eventq", "cmdq-sync", "gerror"; |
Davidson K | ce63312 | 2022-11-21 17:49:51 +0530 | [diff] [blame] | 605 | dma-coherent; |
Anders Dellien | a191413 | 2022-01-01 21:56:25 +0000 | [diff] [blame] | 606 | }; |
| 607 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 608 | dp0: display@2cc00000 { |
| 609 | #address-cells = <1>; |
| 610 | #size-cells = <0>; |
| 611 | compatible = "arm,mali-d71"; |
| 612 | reg = <0 0x2cc00000 0 0x20000>; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 613 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 614 | interrupt-names = "DPU"; |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame^] | 615 | DPU_CLK_ATTR1; |
Davidson K | ce63312 | 2022-11-21 17:49:51 +0530 | [diff] [blame] | 616 | iommus = <&smmu_700 0x100>; |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 617 | power-domains = <&scmi_devpd DPU_SCMI_PD_IDX>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 618 | pl0: pipeline@0 { |
| 619 | reg = <0>; |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame^] | 620 | DPU_CLK_ATTR2; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 621 | pl_id = <0>; |
| 622 | ports { |
| 623 | #address-cells = <1>; |
| 624 | #size-cells = <0>; |
| 625 | port@0 { |
| 626 | reg = <0>; |
| 627 | dp_pl0_out0: endpoint { |
| 628 | remote-endpoint = <&vencoder_in>; |
| 629 | }; |
| 630 | }; |
| 631 | }; |
| 632 | }; |
| 633 | |
| 634 | pl1: pipeline@1 { |
| 635 | reg = <1>; |
Boyan Karatotev | 9556276 | 2023-11-15 11:54:33 +0000 | [diff] [blame^] | 636 | DPU_CLK_ATTR3; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 637 | pl_id = <1>; |
| 638 | ports { |
| 639 | #address-cells = <1>; |
| 640 | #size-cells = <0>; |
| 641 | port@0 { |
| 642 | reg = <0>; |
| 643 | }; |
| 644 | }; |
| 645 | }; |
| 646 | }; |
Arunachalam Ganapathy | c44e43d | 2020-11-17 15:05:01 +0000 | [diff] [blame] | 647 | |
Davidson K | 1ad2c41 | 2023-01-13 14:02:13 +0530 | [diff] [blame] | 648 | /* |
| 649 | * L3 cache in the DSU is the Memory System Component (MSC) |
| 650 | * The MPAM registers are accessed through utility bus in the DSU |
| 651 | */ |
| 652 | msc0 { |
| 653 | compatible = "arm,mpam-msc"; |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame] | 654 | reg = <MPAM_ADDR 0x0 0x2000>; |
Davidson K | 1ad2c41 | 2023-01-13 14:02:13 +0530 | [diff] [blame] | 655 | }; |
| 656 | |
Davidson K | 6536105 | 2021-10-13 18:49:41 +0530 | [diff] [blame] | 657 | ete0 { |
| 658 | compatible = "arm,embedded-trace-extension"; |
| 659 | cpu = <&CPU0>; |
| 660 | }; |
| 661 | |
| 662 | ete1 { |
| 663 | compatible = "arm,embedded-trace-extension"; |
| 664 | cpu = <&CPU1>; |
| 665 | }; |
| 666 | |
| 667 | ete2 { |
| 668 | compatible = "arm,embedded-trace-extension"; |
| 669 | cpu = <&CPU2>; |
| 670 | }; |
| 671 | |
| 672 | ete3 { |
| 673 | compatible = "arm,embedded-trace-extension"; |
| 674 | cpu = <&CPU3>; |
| 675 | }; |
| 676 | |
| 677 | ete4 { |
| 678 | compatible = "arm,embedded-trace-extension"; |
| 679 | cpu = <&CPU4>; |
| 680 | }; |
| 681 | |
| 682 | ete5 { |
| 683 | compatible = "arm,embedded-trace-extension"; |
| 684 | cpu = <&CPU5>; |
| 685 | }; |
| 686 | |
| 687 | ete6 { |
| 688 | compatible = "arm,embedded-trace-extension"; |
| 689 | cpu = <&CPU6>; |
| 690 | }; |
| 691 | |
| 692 | ete7 { |
| 693 | compatible = "arm,embedded-trace-extension"; |
| 694 | cpu = <&CPU7>; |
| 695 | }; |
Boyan Karatotev | 192ad5d | 2023-12-12 15:59:01 +0000 | [diff] [blame] | 696 | |
| 697 | #if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 |
| 698 | ete8 { |
| 699 | compatible = "arm,embedded-trace-extension"; |
| 700 | cpu = <&CPU8>; |
| 701 | }; |
| 702 | |
| 703 | ete9 { |
| 704 | compatible = "arm,embedded-trace-extension"; |
| 705 | cpu = <&CPU9>; |
| 706 | }; |
| 707 | |
| 708 | ete10 { |
| 709 | compatible = "arm,embedded-trace-extension"; |
| 710 | cpu = <&CPU10>; |
| 711 | }; |
| 712 | |
| 713 | ete11 { |
| 714 | compatible = "arm,embedded-trace-extension"; |
| 715 | cpu = <&CPU11>; |
| 716 | }; |
| 717 | |
| 718 | ete12 { |
| 719 | compatible = "arm,embedded-trace-extension"; |
| 720 | cpu = <&CPU12>; |
| 721 | }; |
| 722 | |
| 723 | ete13 { |
| 724 | compatible = "arm,embedded-trace-extension"; |
| 725 | cpu = <&CPU13>; |
| 726 | }; |
| 727 | #endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */ |
Davidson K | 6536105 | 2021-10-13 18:49:41 +0530 | [diff] [blame] | 728 | |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 729 | trbe { |
Davidson K | 6536105 | 2021-10-13 18:49:41 +0530 | [diff] [blame] | 730 | compatible = "arm,trace-buffer-extension"; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 731 | interrupts = <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>; |
Davidson K | 6536105 | 2021-10-13 18:49:41 +0530 | [diff] [blame] | 732 | }; |
Arunachalam Ganapathy | 63128dc | 2022-04-11 14:43:15 +0100 | [diff] [blame] | 733 | |
| 734 | trusty { |
| 735 | #size-cells = <0x02>; |
| 736 | #address-cells = <0x02>; |
| 737 | ranges = <0x00>; |
| 738 | compatible = "android,trusty-v1"; |
| 739 | |
| 740 | virtio { |
| 741 | compatible = "android,trusty-virtio-v1"; |
| 742 | }; |
| 743 | |
| 744 | test { |
| 745 | compatible = "android,trusty-test-v1"; |
| 746 | }; |
| 747 | |
| 748 | log { |
| 749 | compatible = "android,trusty-log-v1"; |
| 750 | }; |
| 751 | |
| 752 | irq { |
| 753 | ipi-range = <0x08 0x0f 0x08>; |
| 754 | interrupt-ranges = <0x00 0x0f 0x00 0x10 0x1f 0x01 0x20 0x3f 0x02>; |
| 755 | interrupt-templates = <0x01 0x00 0x8001 0x01 0x01 0x04 0x8001 0x01 0x00 0x04>; |
| 756 | compatible = "android,trusty-irq-v1"; |
| 757 | }; |
| 758 | }; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 759 | }; |