refactor(tc): sanitise the device tree
We have lots of errors in our device tree when running dt-validate.
Remove the majority so that dt-validate-ing is useful now.
Do this by renaming nodes to conform to spec, making addresses lowercase
with no 0x at the front, and removing nodes that shouldn't be there.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I1840f0f5de34a56ee240c07eff08d73c856b338e
diff --git a/fdts/tc.dts b/fdts/tc.dts
index 68f9221..e0e2df5 100644
--- a/fdts/tc.dts
+++ b/fdts/tc.dts
@@ -16,7 +16,7 @@
#size-cells = <2>;
aliases {
- serial0 = &ap_ns_uart;
+ serial0 = &os_uart;
};
chosen {
@@ -61,7 +61,7 @@
* These values may be inaccurate.
*/
idle-states {
- entry-method = "arm,psci";
+ entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
@@ -216,12 +216,12 @@
linux,cma-default;
};
- optee@0xf8e00000 {
+ optee@f8e00000 {
compatible = "restricted-dma-pool";
reg = <0x00000000 0xf8e00000 0 0x00200000>;
};
- fwu_mm@0xfca00000 {
+ fwu_mm@fca00000 {
reg = <0x00000000 0xfca00000 0 0x00400000>;
no-map;
};
@@ -257,7 +257,7 @@
mbox_db_rx: mhu@45010000 {
compatible = "arm,mhuv2-rx","arm,primecell";
reg = <0x0 0x45010000 0x0 0x1000>;
- clocks = <&soc_refclk100mhz>;
+ clocks = <&soc_refclk>;
clock-names = "apb_pclk";
#mbox-cells = <2>;
interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
@@ -269,7 +269,7 @@
mbox_db_tx: mhu@45000000 {
compatible = "arm,mhuv2-tx","arm,primecell";
reg = <0x0 0x45000000 0x0 0x1000>;
- clocks = <&soc_refclk100mhz>;
+ clocks = <&soc_refclk>;
clock-names = "apb_pclk";
#mbox-cells = <2>;
interrupt-names = "mhu_tx";
@@ -308,7 +308,7 @@
};
gic: interrupt-controller@2c010000 {
- compatible = "arm,gic-600", "arm,gic-v3";
+ compatible = "arm,gic-v3";
#address-cells = <2>;
#interrupt-cells = <3>;
#size-cells = <2>;
@@ -327,7 +327,7 @@
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
- soc_refclk100mhz: refclk100mhz {
+ soc_refclk: refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
@@ -341,29 +341,28 @@
clock-output-names = "iofpga_clk";
};
- soc_uartclk: uartclk {
+ soc_uartclk: uartclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
clock-output-names = "uartclk";
};
- ap_ns_uart: uart@2A400000 {
+ os_uart: serial@2a400000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x2A400000 0x0 0x1000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
+ clocks = <&soc_uartclk>, <&soc_refclk>;
clock-names = "uartclk", "apb_pclk";
status = "okay";
};
- rtc0: rtc@1C170000 {
+ rtc@1c170000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x0 0x1C170000 0x0 0x1000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&soc_refclk100mhz>;
+ clocks = <&soc_refclk>;
clock-names = "apb_pclk";
- wakeup-source;
};
vencoder {
@@ -375,7 +374,7 @@
};
display-timings {
- panel-timing {
+ timing-panel {
clock-frequency = <25175000>;
hactive = <640>;
vactive = <480>;
@@ -481,7 +480,7 @@
iommus = <&smmu_700 0x200>;
};
- power_model@simple {
+ power_model_simple {
/*
* Numbers used are irrelevant to Titan,
* it helps suppressing the kernel warnings.
@@ -493,7 +492,7 @@
thermal-zone = "";
};
- smmu_700: smmu_700@3f000000 {
+ smmu_700: iommu@3f000000 {
#iommu-cells = <1>;
compatible = "arm,smmu-v3";
reg = <0x0 0x3f000000 0x0 0x5000000>;
@@ -596,7 +595,7 @@
cpu = <&CPU7>;
};
- trbe0 {
+ trbe {
compatible = "arm,trace-buffer-extension";
interrupts = <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>;
};