Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 1 | /* |
annsai01 | 7c607f2 | 2023-02-20 13:34:57 +0000 | [diff] [blame] | 2 | * Copyright (c) 2020-2024, Arm Limited. All rights reserved. |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | |
Kshitij Sisodia | b32a8f4 | 2023-08-16 09:46:05 +0100 | [diff] [blame] | 9 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 10 | #include <dt-bindings/interrupt-controller/irq.h> |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame^] | 11 | #include "tc_vers.dtsi" |
Kshitij Sisodia | b32a8f4 | 2023-08-16 09:46:05 +0100 | [diff] [blame] | 12 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 13 | / { |
Usama Arif | f151362 | 2021-04-09 17:07:41 +0100 | [diff] [blame] | 14 | compatible = "arm,tc"; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 15 | interrupt-parent = <&gic>; |
| 16 | #address-cells = <2>; |
| 17 | #size-cells = <2>; |
| 18 | |
| 19 | aliases { |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 20 | serial0 = &os_uart; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 21 | }; |
| 22 | |
| 23 | chosen { |
Nikos Nikoleris | 35800bd | 2021-01-21 13:50:25 +0000 | [diff] [blame] | 24 | stdout-path = "serial0:115200n8"; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 25 | }; |
| 26 | |
| 27 | cpus { |
| 28 | #address-cells = <1>; |
| 29 | #size-cells = <0>; |
| 30 | |
| 31 | cpu-map { |
| 32 | cluster0 { |
| 33 | core0 { |
| 34 | cpu = <&CPU0>; |
| 35 | }; |
| 36 | core1 { |
| 37 | cpu = <&CPU1>; |
| 38 | }; |
| 39 | core2 { |
| 40 | cpu = <&CPU2>; |
| 41 | }; |
| 42 | core3 { |
| 43 | cpu = <&CPU3>; |
| 44 | }; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 45 | core4 { |
| 46 | cpu = <&CPU4>; |
| 47 | }; |
| 48 | core5 { |
| 49 | cpu = <&CPU5>; |
| 50 | }; |
| 51 | core6 { |
| 52 | cpu = <&CPU6>; |
| 53 | }; |
| 54 | core7 { |
| 55 | cpu = <&CPU7>; |
| 56 | }; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 57 | }; |
| 58 | }; |
| 59 | |
Usama Arif | 5790078 | 2020-08-12 17:14:37 +0100 | [diff] [blame] | 60 | /* |
| 61 | * The timings below are just to demonstrate working cpuidle. |
| 62 | * These values may be inaccurate. |
| 63 | */ |
| 64 | idle-states { |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 65 | entry-method = "psci"; |
Usama Arif | 5790078 | 2020-08-12 17:14:37 +0100 | [diff] [blame] | 66 | |
| 67 | CPU_SLEEP_0: cpu-sleep-0 { |
| 68 | compatible = "arm,idle-state"; |
| 69 | arm,psci-suspend-param = <0x0010000>; |
| 70 | local-timer-stop; |
| 71 | entry-latency-us = <300>; |
| 72 | exit-latency-us = <1200>; |
| 73 | min-residency-us = <2000>; |
| 74 | }; |
| 75 | CLUSTER_SLEEP_0: cluster-sleep-0 { |
| 76 | compatible = "arm,idle-state"; |
| 77 | arm,psci-suspend-param = <0x1010000>; |
| 78 | local-timer-stop; |
| 79 | entry-latency-us = <400>; |
| 80 | exit-latency-us = <1200>; |
| 81 | min-residency-us = <2500>; |
| 82 | }; |
| 83 | }; |
| 84 | |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 85 | amus { |
| 86 | amu: amu-0 { |
| 87 | #address-cells = <1>; |
| 88 | #size-cells = <0>; |
| 89 | |
| 90 | mpmm_gear0: counter@0 { |
| 91 | reg = <0>; |
| 92 | |
| 93 | enable-at-el3; |
| 94 | }; |
| 95 | |
| 96 | mpmm_gear1: counter@1 { |
| 97 | reg = <1>; |
| 98 | |
| 99 | enable-at-el3; |
| 100 | }; |
| 101 | |
| 102 | mpmm_gear2: counter@2 { |
| 103 | reg = <2>; |
| 104 | |
| 105 | enable-at-el3; |
| 106 | }; |
| 107 | }; |
| 108 | }; |
| 109 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 110 | CPU0:cpu@0 { |
| 111 | device_type = "cpu"; |
| 112 | compatible = "arm,armv8"; |
| 113 | reg = <0x0>; |
| 114 | enable-method = "psci"; |
| 115 | clocks = <&scmi_dvfs 0>; |
Usama Arif | 5790078 | 2020-08-12 17:14:37 +0100 | [diff] [blame] | 116 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Usama Arif | ecbc846 | 2021-06-14 12:38:37 +0100 | [diff] [blame] | 117 | capacity-dmips-mhz = <406>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 118 | amu = <&amu>; |
| 119 | supports-mpmm; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 120 | }; |
| 121 | |
| 122 | CPU1:cpu@100 { |
| 123 | device_type = "cpu"; |
| 124 | compatible = "arm,armv8"; |
| 125 | reg = <0x100>; |
| 126 | enable-method = "psci"; |
| 127 | clocks = <&scmi_dvfs 0>; |
Usama Arif | 5790078 | 2020-08-12 17:14:37 +0100 | [diff] [blame] | 128 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Usama Arif | ecbc846 | 2021-06-14 12:38:37 +0100 | [diff] [blame] | 129 | capacity-dmips-mhz = <406>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 130 | amu = <&amu>; |
| 131 | supports-mpmm; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 132 | }; |
| 133 | |
| 134 | CPU2:cpu@200 { |
| 135 | device_type = "cpu"; |
| 136 | compatible = "arm,armv8"; |
| 137 | reg = <0x200>; |
| 138 | enable-method = "psci"; |
| 139 | clocks = <&scmi_dvfs 0>; |
Usama Arif | 5790078 | 2020-08-12 17:14:37 +0100 | [diff] [blame] | 140 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Usama Arif | ecbc846 | 2021-06-14 12:38:37 +0100 | [diff] [blame] | 141 | capacity-dmips-mhz = <406>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 142 | amu = <&amu>; |
| 143 | supports-mpmm; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 144 | }; |
| 145 | |
| 146 | CPU3:cpu@300 { |
| 147 | device_type = "cpu"; |
| 148 | compatible = "arm,armv8"; |
| 149 | reg = <0x300>; |
| 150 | enable-method = "psci"; |
| 151 | clocks = <&scmi_dvfs 0>; |
Usama Arif | 5790078 | 2020-08-12 17:14:37 +0100 | [diff] [blame] | 152 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Usama Arif | ecbc846 | 2021-06-14 12:38:37 +0100 | [diff] [blame] | 153 | capacity-dmips-mhz = <406>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 154 | amu = <&amu>; |
| 155 | supports-mpmm; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 156 | }; |
| 157 | |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 158 | CPU4:cpu@400 { |
| 159 | device_type = "cpu"; |
| 160 | compatible = "arm,armv8"; |
| 161 | reg = <0x400>; |
| 162 | enable-method = "psci"; |
Usama Arif | 75edb75 | 2021-02-03 15:40:46 +0000 | [diff] [blame] | 163 | clocks = <&scmi_dvfs 1>; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 164 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Usama Arif | ecbc846 | 2021-06-14 12:38:37 +0100 | [diff] [blame] | 165 | capacity-dmips-mhz = <912>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 166 | amu = <&amu>; |
| 167 | supports-mpmm; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 168 | }; |
| 169 | |
| 170 | CPU5:cpu@500 { |
| 171 | device_type = "cpu"; |
| 172 | compatible = "arm,armv8"; |
| 173 | reg = <0x500>; |
| 174 | enable-method = "psci"; |
Usama Arif | 75edb75 | 2021-02-03 15:40:46 +0000 | [diff] [blame] | 175 | clocks = <&scmi_dvfs 1>; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 176 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Usama Arif | ecbc846 | 2021-06-14 12:38:37 +0100 | [diff] [blame] | 177 | capacity-dmips-mhz = <912>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 178 | amu = <&amu>; |
| 179 | supports-mpmm; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 180 | }; |
| 181 | |
| 182 | CPU6:cpu@600 { |
| 183 | device_type = "cpu"; |
| 184 | compatible = "arm,armv8"; |
| 185 | reg = <0x600>; |
| 186 | enable-method = "psci"; |
Usama Arif | 75edb75 | 2021-02-03 15:40:46 +0000 | [diff] [blame] | 187 | clocks = <&scmi_dvfs 1>; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 188 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Usama Arif | ecbc846 | 2021-06-14 12:38:37 +0100 | [diff] [blame] | 189 | capacity-dmips-mhz = <912>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 190 | amu = <&amu>; |
| 191 | supports-mpmm; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 192 | }; |
| 193 | |
| 194 | CPU7:cpu@700 { |
| 195 | device_type = "cpu"; |
| 196 | compatible = "arm,armv8"; |
| 197 | reg = <0x700>; |
| 198 | enable-method = "psci"; |
Usama Arif | 410d50d | 2021-04-07 11:48:22 +0100 | [diff] [blame] | 199 | clocks = <&scmi_dvfs 2>; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 200 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
Usama Arif | ecbc846 | 2021-06-14 12:38:37 +0100 | [diff] [blame] | 201 | capacity-dmips-mhz = <1024>; |
Chris Kay | c2d29ba | 2021-05-18 18:49:51 +0100 | [diff] [blame] | 202 | amu = <&amu>; |
| 203 | supports-mpmm; |
Avinash Mehta | f68a084 | 2020-10-28 16:43:28 +0000 | [diff] [blame] | 204 | }; |
| 205 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 206 | }; |
| 207 | |
Arunachalam Ganapathy | 948bb44 | 2020-12-14 12:31:32 +0000 | [diff] [blame] | 208 | reserved-memory { |
| 209 | #address-cells = <2>; |
| 210 | #size-cells = <2>; |
| 211 | ranges; |
| 212 | |
Anders Dellien | a6c9b72 | 2021-12-08 21:57:21 +0000 | [diff] [blame] | 213 | linux,cma { |
| 214 | compatible = "shared-dma-pool"; |
| 215 | reusable; |
| 216 | size = <0x0 0x8000000>; |
| 217 | linux,cma-default; |
| 218 | }; |
| 219 | |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 220 | optee@f8e00000 { |
Davidson K | 4662a88 | 2022-12-14 17:38:14 +0530 | [diff] [blame] | 221 | compatible = "restricted-dma-pool"; |
Arunachalam Ganapathy | ac9e120 | 2022-04-11 17:38:17 +0100 | [diff] [blame] | 222 | reg = <0x00000000 0xf8e00000 0 0x00200000>; |
Arunachalam Ganapathy | 948bb44 | 2020-12-14 12:31:32 +0000 | [diff] [blame] | 223 | }; |
Tudor Cretu | 77b301a | 2021-09-24 12:09:53 +0000 | [diff] [blame] | 224 | |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 225 | fwu_mm@fca00000 { |
Tudor Cretu | 77b301a | 2021-09-24 12:09:53 +0000 | [diff] [blame] | 226 | reg = <0x00000000 0xfca00000 0 0x00400000>; |
| 227 | no-map; |
| 228 | }; |
Arunachalam Ganapathy | 948bb44 | 2020-12-14 12:31:32 +0000 | [diff] [blame] | 229 | }; |
| 230 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 231 | psci { |
Usama Arif | 7a64bfa | 2021-05-27 20:09:17 +0100 | [diff] [blame] | 232 | compatible = "arm,psci-1.0", "arm,psci-0.2"; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 233 | method = "smc"; |
| 234 | }; |
| 235 | |
Boyan Karatotev | 4fef47c | 2023-11-15 11:29:59 +0000 | [diff] [blame] | 236 | cpu-pmu { |
| 237 | compatible = "arm,armv8-pmuv3"; |
| 238 | interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| 239 | interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, |
| 240 | <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7> |
| 241 | ; |
| 242 | }; |
| 243 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 244 | sram: sram@6000000 { |
| 245 | compatible = "mmio-sram"; |
| 246 | reg = <0x0 0x06000000 0x0 0x8000>; |
| 247 | |
| 248 | #address-cells = <1>; |
| 249 | #size-cells = <1>; |
| 250 | ranges = <0 0x0 0x06000000 0x8000>; |
| 251 | |
| 252 | cpu_scp_scmi_mem: scp-shmem@0 { |
| 253 | compatible = "arm,scmi-shmem"; |
| 254 | reg = <0x0 0x80>; |
| 255 | }; |
| 256 | }; |
| 257 | |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame^] | 258 | mbox_db_rx: mhu@MHU_RX_ADDR() { |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 259 | compatible = "arm,mhuv2-rx","arm,primecell"; |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame^] | 260 | reg = <0x0 MHU_RX_ADDR(0x) 0x0 0x1000>; |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 261 | clocks = <&soc_refclk>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 262 | clock-names = "apb_pclk"; |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 263 | #mbox-cells = <2>; |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame^] | 264 | interrupts = <GIC_SPI INT_MBOX_RX IRQ_TYPE_LEVEL_HIGH>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 265 | interrupt-names = "mhu_rx"; |
| 266 | mhu-protocol = "doorbell"; |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 267 | arm,mhuv2-protocols = <0 1>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 268 | }; |
| 269 | |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame^] | 270 | mbox_db_tx: mhu@MHU_TX_ADDR() { |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 271 | compatible = "arm,mhuv2-tx","arm,primecell"; |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame^] | 272 | reg = <0x0 MHU_TX_ADDR(0x) 0x0 0x1000>; |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 273 | clocks = <&soc_refclk>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 274 | clock-names = "apb_pclk"; |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 275 | #mbox-cells = <2>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 276 | interrupt-names = "mhu_tx"; |
| 277 | mhu-protocol = "doorbell"; |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 278 | arm,mhuv2-protocols = <0 1>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 279 | }; |
| 280 | |
| 281 | scmi { |
| 282 | compatible = "arm,scmi"; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 283 | mbox-names = "tx", "rx"; |
Usama Arif | b315c70 | 2021-05-27 20:01:39 +0100 | [diff] [blame] | 284 | mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 285 | shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>; |
| 286 | #address-cells = <1>; |
| 287 | #size-cells = <0>; |
| 288 | |
Ben Horgan | 80781a5 | 2023-07-26 20:45:27 +0100 | [diff] [blame] | 289 | scmi_devpd: protocol@11 { |
| 290 | reg = <0x11>; |
| 291 | #power-domain-cells = <1>; |
| 292 | }; |
| 293 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 294 | scmi_dvfs: protocol@13 { |
| 295 | reg = <0x13>; |
| 296 | #clock-cells = <1>; |
| 297 | }; |
| 298 | |
| 299 | scmi_clk: protocol@14 { |
| 300 | reg = <0x14>; |
| 301 | #clock-cells = <1>; |
| 302 | }; |
| 303 | }; |
| 304 | |
| 305 | gic: interrupt-controller@2c010000 { |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 306 | compatible = "arm,gic-v3"; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 307 | #address-cells = <2>; |
| 308 | #interrupt-cells = <3>; |
| 309 | #size-cells = <2>; |
| 310 | ranges; |
| 311 | interrupt-controller; |
| 312 | reg = <0x0 0x30000000 0 0x10000>, /* GICD */ |
Usama Arif | fdfd250 | 2021-03-30 16:39:19 +0100 | [diff] [blame] | 313 | <0x0 0x30080000 0 0x200000>; /* GICR */ |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 314 | interrupts = <GIC_PPI 0x9 IRQ_TYPE_LEVEL_LOW>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 315 | }; |
| 316 | |
| 317 | timer { |
| 318 | compatible = "arm,armv8-timer"; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 319 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| 320 | <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| 321 | <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| 322 | <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 323 | }; |
| 324 | |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 325 | soc_refclk: refclk { |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 326 | compatible = "fixed-clock"; |
| 327 | #clock-cells = <0>; |
| 328 | clock-frequency = <100000000>; |
| 329 | clock-output-names = "apb_pclk"; |
| 330 | }; |
| 331 | |
| 332 | soc_refclk60mhz: refclk60mhz { |
| 333 | compatible = "fixed-clock"; |
| 334 | #clock-cells = <0>; |
| 335 | clock-frequency = <60000000>; |
| 336 | clock-output-names = "iofpga_clk"; |
| 337 | }; |
| 338 | |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 339 | soc_uartclk: uartclk { |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 340 | compatible = "fixed-clock"; |
| 341 | #clock-cells = <0>; |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame^] | 342 | clock-frequency = <UARTCLK_FREQ>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 343 | clock-output-names = "uartclk"; |
| 344 | }; |
| 345 | |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 346 | os_uart: serial@2a400000 { |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 347 | compatible = "arm,pl011", "arm,primecell"; |
annsai01 | 7c607f2 | 2023-02-20 13:34:57 +0000 | [diff] [blame] | 348 | reg = <0x0 0x2A400000 0x0 0x1000>; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 349 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 350 | clocks = <&soc_uartclk>, <&soc_refclk>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 351 | clock-names = "uartclk", "apb_pclk"; |
| 352 | status = "okay"; |
| 353 | }; |
| 354 | |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 355 | rtc@1c170000 { |
Jayanth Dodderi Chidanand | 2858cf5 | 2022-09-28 11:41:48 +0100 | [diff] [blame] | 356 | compatible = "arm,pl031", "arm,primecell"; |
| 357 | reg = <0x0 0x1C170000 0x0 0x1000>; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 358 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 359 | clocks = <&soc_refclk>; |
Jayanth Dodderi Chidanand | 2858cf5 | 2022-09-28 11:41:48 +0100 | [diff] [blame] | 360 | clock-names = "apb_pclk"; |
Jayanth Dodderi Chidanand | 2858cf5 | 2022-09-28 11:41:48 +0100 | [diff] [blame] | 361 | }; |
Rupinderjit Singh | d2d0298 | 2022-09-12 17:25:32 +0100 | [diff] [blame] | 362 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 363 | vencoder { |
| 364 | compatible = "drm,virtual-encoder"; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 365 | port { |
| 366 | vencoder_in: endpoint { |
Avinash Mehta | df71a60 | 2020-07-22 16:40:07 +0100 | [diff] [blame] | 367 | remote-endpoint = <&dp_pl0_out0>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 368 | }; |
| 369 | }; |
| 370 | |
| 371 | display-timings { |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 372 | timing-panel { |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 373 | clock-frequency = <25175000>; |
| 374 | hactive = <640>; |
| 375 | vactive = <480>; |
| 376 | hfront-porch = <16>; |
| 377 | hback-porch = <48>; |
| 378 | hsync-len = <96>; |
| 379 | vfront-porch = <10>; |
| 380 | vback-porch = <33>; |
| 381 | vsync-len = <2>; |
| 382 | }; |
| 383 | }; |
| 384 | |
| 385 | }; |
| 386 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 387 | ethernet@18000000 { |
| 388 | compatible = "smsc,lan91c111"; |
| 389 | reg = <0x0 0x18000000 0x0 0x10000>; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 390 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 391 | }; |
| 392 | |
| 393 | kmi@1c060000 { |
| 394 | compatible = "arm,pl050", "arm,primecell"; |
| 395 | reg = <0x0 0x001c060000 0x0 0x1000>; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 396 | interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 397 | clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; |
| 398 | clock-names = "KMIREFCLK", "apb_pclk"; |
| 399 | }; |
| 400 | |
| 401 | kmi@1c070000 { |
| 402 | compatible = "arm,pl050", "arm,primecell"; |
| 403 | reg = <0x0 0x001c070000 0x0 0x1000>; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 404 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 405 | clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; |
| 406 | clock-names = "KMIREFCLK", "apb_pclk"; |
| 407 | }; |
| 408 | |
| 409 | bp_clock24mhz: clock24mhz { |
| 410 | compatible = "fixed-clock"; |
| 411 | #clock-cells = <0>; |
| 412 | clock-frequency = <24000000>; |
| 413 | clock-output-names = "bp:clock24mhz"; |
| 414 | }; |
| 415 | |
| 416 | virtio_block@1c130000 { |
| 417 | compatible = "virtio,mmio"; |
| 418 | reg = <0x0 0x1c130000 0x0 0x200>; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 419 | /* spec lists this wrong */ |
| 420 | interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 421 | }; |
| 422 | |
Usama Arif | 1cd56dc | 2020-06-10 16:27:53 +0100 | [diff] [blame] | 423 | sysreg: sysreg@1c010000 { |
| 424 | compatible = "arm,vexpress-sysreg"; |
| 425 | reg = <0x0 0x001c010000 0x0 0x1000>; |
| 426 | gpio-controller; |
| 427 | #gpio-cells = <2>; |
| 428 | }; |
| 429 | |
| 430 | fixed_3v3: v2m-3v3 { |
| 431 | compatible = "regulator-fixed"; |
| 432 | regulator-name = "3V3"; |
| 433 | regulator-min-microvolt = <3300000>; |
| 434 | regulator-max-microvolt = <3300000>; |
| 435 | regulator-always-on; |
| 436 | }; |
| 437 | |
| 438 | mmci@1c050000 { |
| 439 | compatible = "arm,pl180", "arm,primecell"; |
| 440 | reg = <0x0 0x001c050000 0x0 0x1000>; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 441 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
| 442 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
Usama Arif | 1cd56dc | 2020-06-10 16:27:53 +0100 | [diff] [blame] | 443 | cd-gpios = <&sysreg 0 0>; |
| 444 | wp-gpios = <&sysreg 1 0>; |
| 445 | bus-width = <8>; |
| 446 | max-frequency = <12000000>; |
| 447 | vmmc-supply = <&fixed_3v3>; |
| 448 | clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; |
| 449 | clock-names = "mclk", "apb_pclk"; |
| 450 | }; |
| 451 | |
Rupinderjit Singh | b2a75b8 | 2023-02-03 09:29:57 +0000 | [diff] [blame] | 452 | gpu_clk: gpu_clk { |
| 453 | compatible = "fixed-clock"; |
| 454 | #clock-cells = <0>; |
| 455 | clock-frequency = <1000000000>; |
| 456 | }; |
| 457 | |
| 458 | gpu_core_clk: gpu_core_clk { |
| 459 | compatible = "fixed-clock"; |
| 460 | #clock-cells = <0>; |
| 461 | clock-frequency = <1000000000>; |
| 462 | }; |
| 463 | |
Anders Dellien | 7a84980 | 2022-01-01 21:51:21 +0000 | [diff] [blame] | 464 | gpu: gpu@2d000000 { |
| 465 | compatible = "arm,mali-midgard"; |
| 466 | reg = <0x0 0x2d000000 0x0 0x200000>; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 467 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, |
| 468 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, |
| 469 | <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
Anders Dellien | 7a84980 | 2022-01-01 21:51:21 +0000 | [diff] [blame] | 470 | interrupt-names = "JOB", "MMU", "GPU"; |
Ben Horgan | 80781a5 | 2023-07-26 20:45:27 +0100 | [diff] [blame] | 471 | clocks = <&gpu_core_clk>; |
| 472 | clock-names = "shadercores"; |
| 473 | power-domains = <&scmi_devpd 9>; |
| 474 | scmi-perf-domain = <3>; |
Davidson K | ce63312 | 2022-11-21 17:49:51 +0530 | [diff] [blame] | 475 | iommus = <&smmu_700 0x200>; |
Anders Dellien | 7a84980 | 2022-01-01 21:51:21 +0000 | [diff] [blame] | 476 | }; |
| 477 | |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 478 | power_model_simple { |
Rupinderjit Singh | b2a75b8 | 2023-02-03 09:29:57 +0000 | [diff] [blame] | 479 | /* |
| 480 | * Numbers used are irrelevant to Titan, |
| 481 | * it helps suppressing the kernel warnings. |
| 482 | */ |
| 483 | compatible = "arm,mali-simple-power-model"; |
| 484 | static-coefficient = <2427750>; |
| 485 | dynamic-coefficient = <4687>; |
| 486 | ts = <20000 2000 (-20) 2>; |
| 487 | thermal-zone = ""; |
| 488 | }; |
| 489 | |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 490 | smmu_700: iommu@3f000000 { |
Anders Dellien | a191413 | 2022-01-01 21:56:25 +0000 | [diff] [blame] | 491 | #iommu-cells = <1>; |
| 492 | compatible = "arm,smmu-v3"; |
Davidson K | ce63312 | 2022-11-21 17:49:51 +0530 | [diff] [blame] | 493 | reg = <0x0 0x3f000000 0x0 0x5000000>; |
Kshitij Sisodia | b32a8f4 | 2023-08-16 09:46:05 +0100 | [diff] [blame] | 494 | interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, |
| 495 | <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, |
| 496 | <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>; |
| 497 | interrupt-names = "eventq", "cmdq-sync", "gerror"; |
Davidson K | ce63312 | 2022-11-21 17:49:51 +0530 | [diff] [blame] | 498 | dma-coherent; |
Anders Dellien | a191413 | 2022-01-01 21:56:25 +0000 | [diff] [blame] | 499 | }; |
| 500 | |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 501 | dp0: display@2cc00000 { |
| 502 | #address-cells = <1>; |
| 503 | #size-cells = <0>; |
| 504 | compatible = "arm,mali-d71"; |
| 505 | reg = <0 0x2cc00000 0 0x20000>; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 506 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 507 | interrupt-names = "DPU"; |
| 508 | clocks = <&scmi_clk 0>; |
| 509 | clock-names = "aclk"; |
Davidson K | ce63312 | 2022-11-21 17:49:51 +0530 | [diff] [blame] | 510 | iommus = <&smmu_700 0x100>; |
Ben Horgan | 80781a5 | 2023-07-26 20:45:27 +0100 | [diff] [blame] | 511 | power-domains = <&scmi_devpd 10>; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 512 | pl0: pipeline@0 { |
| 513 | reg = <0>; |
| 514 | clocks = <&scmi_clk 1>; |
| 515 | clock-names = "pxclk"; |
| 516 | pl_id = <0>; |
| 517 | ports { |
| 518 | #address-cells = <1>; |
| 519 | #size-cells = <0>; |
| 520 | port@0 { |
| 521 | reg = <0>; |
| 522 | dp_pl0_out0: endpoint { |
| 523 | remote-endpoint = <&vencoder_in>; |
| 524 | }; |
| 525 | }; |
| 526 | }; |
| 527 | }; |
| 528 | |
| 529 | pl1: pipeline@1 { |
| 530 | reg = <1>; |
| 531 | clocks = <&scmi_clk 2>; |
| 532 | clock-names = "pxclk"; |
| 533 | pl_id = <1>; |
| 534 | ports { |
| 535 | #address-cells = <1>; |
| 536 | #size-cells = <0>; |
| 537 | port@0 { |
| 538 | reg = <0>; |
| 539 | }; |
| 540 | }; |
| 541 | }; |
| 542 | }; |
Arunachalam Ganapathy | c44e43d | 2020-11-17 15:05:01 +0000 | [diff] [blame] | 543 | |
Davidson K | 1ad2c41 | 2023-01-13 14:02:13 +0530 | [diff] [blame] | 544 | /* |
| 545 | * L3 cache in the DSU is the Memory System Component (MSC) |
| 546 | * The MPAM registers are accessed through utility bus in the DSU |
| 547 | */ |
| 548 | msc0 { |
| 549 | compatible = "arm,mpam-msc"; |
Boyan Karatotev | 6ed3bf6 | 2023-07-07 13:33:19 +0000 | [diff] [blame^] | 550 | reg = <MPAM_ADDR 0x0 0x2000>; |
Davidson K | 1ad2c41 | 2023-01-13 14:02:13 +0530 | [diff] [blame] | 551 | }; |
| 552 | |
Davidson K | 6536105 | 2021-10-13 18:49:41 +0530 | [diff] [blame] | 553 | ete0 { |
| 554 | compatible = "arm,embedded-trace-extension"; |
| 555 | cpu = <&CPU0>; |
| 556 | }; |
| 557 | |
| 558 | ete1 { |
| 559 | compatible = "arm,embedded-trace-extension"; |
| 560 | cpu = <&CPU1>; |
| 561 | }; |
| 562 | |
| 563 | ete2 { |
| 564 | compatible = "arm,embedded-trace-extension"; |
| 565 | cpu = <&CPU2>; |
| 566 | }; |
| 567 | |
| 568 | ete3 { |
| 569 | compatible = "arm,embedded-trace-extension"; |
| 570 | cpu = <&CPU3>; |
| 571 | }; |
| 572 | |
| 573 | ete4 { |
| 574 | compatible = "arm,embedded-trace-extension"; |
| 575 | cpu = <&CPU4>; |
| 576 | }; |
| 577 | |
| 578 | ete5 { |
| 579 | compatible = "arm,embedded-trace-extension"; |
| 580 | cpu = <&CPU5>; |
| 581 | }; |
| 582 | |
| 583 | ete6 { |
| 584 | compatible = "arm,embedded-trace-extension"; |
| 585 | cpu = <&CPU6>; |
| 586 | }; |
| 587 | |
| 588 | ete7 { |
| 589 | compatible = "arm,embedded-trace-extension"; |
| 590 | cpu = <&CPU7>; |
| 591 | }; |
| 592 | |
Boyan Karatotev | 13b8e74 | 2023-11-14 13:57:56 +0000 | [diff] [blame] | 593 | trbe { |
Davidson K | 6536105 | 2021-10-13 18:49:41 +0530 | [diff] [blame] | 594 | compatible = "arm,trace-buffer-extension"; |
Boyan Karatotev | 25c4fb7 | 2023-08-08 15:37:52 +0100 | [diff] [blame] | 595 | interrupts = <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>; |
Davidson K | 6536105 | 2021-10-13 18:49:41 +0530 | [diff] [blame] | 596 | }; |
Arunachalam Ganapathy | 63128dc | 2022-04-11 14:43:15 +0100 | [diff] [blame] | 597 | |
| 598 | trusty { |
| 599 | #size-cells = <0x02>; |
| 600 | #address-cells = <0x02>; |
| 601 | ranges = <0x00>; |
| 602 | compatible = "android,trusty-v1"; |
| 603 | |
| 604 | virtio { |
| 605 | compatible = "android,trusty-virtio-v1"; |
| 606 | }; |
| 607 | |
| 608 | test { |
| 609 | compatible = "android,trusty-test-v1"; |
| 610 | }; |
| 611 | |
| 612 | log { |
| 613 | compatible = "android,trusty-log-v1"; |
| 614 | }; |
| 615 | |
| 616 | irq { |
| 617 | ipi-range = <0x08 0x0f 0x08>; |
| 618 | interrupt-ranges = <0x00 0x0f 0x00 0x10 0x1f 0x01 0x20 0x3f 0x02>; |
| 619 | interrupt-templates = <0x01 0x00 0x8001 0x01 0x01 0x04 0x8001 0x01 0x00 0x04>; |
| 620 | compatible = "android,trusty-irq-v1"; |
| 621 | }; |
| 622 | }; |
Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 623 | }; |