blob: 382860d9dfe8891bbb086146b4404ce27ff7cf3e [file] [log] [blame]
Usama Arifbec5afd2020-04-17 16:13:39 +01001/*
Usama Ariffdfd2502021-03-30 16:39:19 +01002 * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
Usama Arifbec5afd2020-04-17 16:13:39 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/dts-v1/;
8
9/ {
10 compatible = "arm,tc0";
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
14
15 aliases {
16 serial0 = &soc_uart0;
17 };
18
19 chosen {
Nikos Nikoleris35800bd2021-01-21 13:50:25 +000020 stdout-path = "serial0:115200n8";
Usama Arifbec5afd2020-04-17 16:13:39 +010021 };
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 cpu-map {
28 cluster0 {
29 core0 {
30 cpu = <&CPU0>;
31 };
32 core1 {
33 cpu = <&CPU1>;
34 };
35 core2 {
36 cpu = <&CPU2>;
37 };
38 core3 {
39 cpu = <&CPU3>;
40 };
Avinash Mehtaf68a0842020-10-28 16:43:28 +000041 core4 {
42 cpu = <&CPU4>;
43 };
44 core5 {
45 cpu = <&CPU5>;
46 };
47 core6 {
48 cpu = <&CPU6>;
49 };
50 core7 {
51 cpu = <&CPU7>;
52 };
Usama Arifbec5afd2020-04-17 16:13:39 +010053 };
54 };
55
Usama Arif57900782020-08-12 17:14:37 +010056 /*
57 * The timings below are just to demonstrate working cpuidle.
58 * These values may be inaccurate.
59 */
60 idle-states {
61 entry-method = "arm,psci";
62
63 CPU_SLEEP_0: cpu-sleep-0 {
64 compatible = "arm,idle-state";
65 arm,psci-suspend-param = <0x0010000>;
66 local-timer-stop;
67 entry-latency-us = <300>;
68 exit-latency-us = <1200>;
69 min-residency-us = <2000>;
70 };
71 CLUSTER_SLEEP_0: cluster-sleep-0 {
72 compatible = "arm,idle-state";
73 arm,psci-suspend-param = <0x1010000>;
74 local-timer-stop;
75 entry-latency-us = <400>;
76 exit-latency-us = <1200>;
77 min-residency-us = <2500>;
78 };
79 };
80
Usama Arifbec5afd2020-04-17 16:13:39 +010081 CPU0:cpu@0 {
82 device_type = "cpu";
83 compatible = "arm,armv8";
84 reg = <0x0>;
85 enable-method = "psci";
86 clocks = <&scmi_dvfs 0>;
Usama Arif57900782020-08-12 17:14:37 +010087 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifbec5afd2020-04-17 16:13:39 +010088 };
89
90 CPU1:cpu@100 {
91 device_type = "cpu";
92 compatible = "arm,armv8";
93 reg = <0x100>;
94 enable-method = "psci";
95 clocks = <&scmi_dvfs 0>;
Usama Arif57900782020-08-12 17:14:37 +010096 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifbec5afd2020-04-17 16:13:39 +010097 };
98
99 CPU2:cpu@200 {
100 device_type = "cpu";
101 compatible = "arm,armv8";
102 reg = <0x200>;
103 enable-method = "psci";
104 clocks = <&scmi_dvfs 0>;
Usama Arif57900782020-08-12 17:14:37 +0100105 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100106 };
107
108 CPU3:cpu@300 {
109 device_type = "cpu";
110 compatible = "arm,armv8";
111 reg = <0x300>;
112 enable-method = "psci";
113 clocks = <&scmi_dvfs 0>;
Usama Arif57900782020-08-12 17:14:37 +0100114 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100115 };
116
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000117 CPU4:cpu@400 {
118 device_type = "cpu";
119 compatible = "arm,armv8";
120 reg = <0x400>;
121 enable-method = "psci";
Usama Arif75edb752021-02-03 15:40:46 +0000122 clocks = <&scmi_dvfs 1>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000123 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
124 };
125
126 CPU5:cpu@500 {
127 device_type = "cpu";
128 compatible = "arm,armv8";
129 reg = <0x500>;
130 enable-method = "psci";
Usama Arif75edb752021-02-03 15:40:46 +0000131 clocks = <&scmi_dvfs 1>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000132 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
133 };
134
135 CPU6:cpu@600 {
136 device_type = "cpu";
137 compatible = "arm,armv8";
138 reg = <0x600>;
139 enable-method = "psci";
Usama Arif75edb752021-02-03 15:40:46 +0000140 clocks = <&scmi_dvfs 1>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000141 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
142 };
143
144 CPU7:cpu@700 {
145 device_type = "cpu";
146 compatible = "arm,armv8";
147 reg = <0x700>;
148 enable-method = "psci";
Usama Arif75edb752021-02-03 15:40:46 +0000149 clocks = <&scmi_dvfs 1>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000150 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
151 };
152
Usama Arifbec5afd2020-04-17 16:13:39 +0100153 };
154
155 memory@80000000 {
156 device_type = "memory";
Arunachalam Ganapathy81da5582020-09-22 12:47:33 +0100157 reg = <0x0 0x80000000 0x0 0x7d000000>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100158 };
159
Arunachalam Ganapathy948bb442020-12-14 12:31:32 +0000160 reserved-memory {
161 #address-cells = <2>;
162 #size-cells = <2>;
163 ranges;
164
165 optee@0xfce00000 {
166 reg = <0x00000000 0xfce00000 0 0x00200000>;
167 no-map;
168 };
169 };
170
Usama Arifbec5afd2020-04-17 16:13:39 +0100171 psci {
172 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
173 method = "smc";
174 };
175
176 sram: sram@6000000 {
177 compatible = "mmio-sram";
178 reg = <0x0 0x06000000 0x0 0x8000>;
179
180 #address-cells = <1>;
181 #size-cells = <1>;
182 ranges = <0 0x0 0x06000000 0x8000>;
183
184 cpu_scp_scmi_mem: scp-shmem@0 {
185 compatible = "arm,scmi-shmem";
186 reg = <0x0 0x80>;
187 };
188 };
189
190 mbox_db_rx: mhu@45010000 {
191 compatible = "arm,mhuv2","arm,primecell";
192 reg = <0x0 0x45010000 0x0 0x1000>;
193 clocks = <&soc_refclk100mhz>;
194 clock-names = "apb_pclk";
195 #mbox-cells = <1>;
Usama Arif884f40d2020-08-18 12:56:44 +0100196 interrupts = <0 317 4>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100197 interrupt-names = "mhu_rx";
198 mhu-protocol = "doorbell";
199 };
200
201 mbox_db_tx: mhu@45000000 {
202 compatible = "arm,mhuv2","arm,primecell";
203 reg = <0x0 0x45000000 0x0 0x1000>;
204 clocks = <&soc_refclk100mhz>;
205 clock-names = "apb_pclk";
206 #mbox-cells = <1>;
207 interrupt-names = "mhu_tx";
208 mhu-protocol = "doorbell";
209 };
210
211 scmi {
212 compatible = "arm,scmi";
213 method = "mailbox-doorbell";
214 mbox-names = "tx", "rx";
215 mboxes = <&mbox_db_tx 0 &mbox_db_rx 0>;
216 shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>;
217 #address-cells = <1>;
218 #size-cells = <0>;
219
220 scmi_dvfs: protocol@13 {
221 reg = <0x13>;
222 #clock-cells = <1>;
223 };
224
225 scmi_clk: protocol@14 {
226 reg = <0x14>;
227 #clock-cells = <1>;
228 };
229 };
230
231 gic: interrupt-controller@2c010000 {
232 compatible = "arm,gic-600", "arm,gic-v3";
233 #address-cells = <2>;
234 #interrupt-cells = <3>;
235 #size-cells = <2>;
236 ranges;
237 interrupt-controller;
238 reg = <0x0 0x30000000 0 0x10000>, /* GICD */
Usama Ariffdfd2502021-03-30 16:39:19 +0100239 <0x0 0x30080000 0 0x200000>; /* GICR */
Usama Arifbec5afd2020-04-17 16:13:39 +0100240 interrupts = <0x1 0x9 0x4>;
241 };
242
243 timer {
244 compatible = "arm,armv8-timer";
245 interrupts = <0x1 13 0x8>,
246 <0x1 14 0x8>,
247 <0x1 11 0x8>,
248 <0x1 10 0x8>;
249 };
250
251 soc_refclk100mhz: refclk100mhz {
252 compatible = "fixed-clock";
253 #clock-cells = <0>;
254 clock-frequency = <100000000>;
255 clock-output-names = "apb_pclk";
256 };
257
258 soc_refclk60mhz: refclk60mhz {
259 compatible = "fixed-clock";
260 #clock-cells = <0>;
261 clock-frequency = <60000000>;
262 clock-output-names = "iofpga_clk";
263 };
264
265 soc_uartclk: uartclk {
266 compatible = "fixed-clock";
267 #clock-cells = <0>;
268 clock-frequency = <50000000>;
269 clock-output-names = "uartclk";
270 };
271
272 soc_uart0: uart@7ff80000 {
273 compatible = "arm,pl011", "arm,primecell";
274 reg = <0x0 0x7ff80000 0x0 0x1000>;
275 interrupts = <0x0 116 0x4>;
276 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
277 clock-names = "uartclk", "apb_pclk";
278 status = "okay";
279 };
280
281 vencoder {
282 compatible = "drm,virtual-encoder";
283
284 port {
285 vencoder_in: endpoint {
Avinash Mehtadf71a602020-07-22 16:40:07 +0100286 remote-endpoint = <&dp_pl0_out0>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100287 };
288 };
289
290 display-timings {
291 panel-timing {
292 clock-frequency = <25175000>;
293 hactive = <640>;
294 vactive = <480>;
295 hfront-porch = <16>;
296 hback-porch = <48>;
297 hsync-len = <96>;
298 vfront-porch = <10>;
299 vback-porch = <33>;
300 vsync-len = <2>;
301 };
302 };
303
304 };
305
306 hdlcd: hdlcd@7ff60000 {
307 compatible = "arm,hdlcd";
308 reg = <0x0 0x7ff60000 0x0 0x1000>;
309 interrupts = <0x0 117 0x4>;
310 clocks = <&fake_hdlcd_clk>;
311 clock-names = "pxlclk";
Avinash Mehtadf71a602020-07-22 16:40:07 +0100312 status = "disabled";
Usama Arifbec5afd2020-04-17 16:13:39 +0100313
314 port {
315 hdlcd_out: endpoint {
316 remote-endpoint = <&vencoder_in>;
317 };
318 };
319 };
320
321 fake_hdlcd_clk: fake-hdlcd-clk {
322 compatible = "fixed-clock";
323 #clock-cells = <0>;
324 clock-frequency = <25175000>;
325 clock-output-names = "pxlclk";
326 };
327
328 ethernet@18000000 {
329 compatible = "smsc,lan91c111";
330 reg = <0x0 0x18000000 0x0 0x10000>;
331 interrupts = <0 109 4>;
332 };
333
334 kmi@1c060000 {
335 compatible = "arm,pl050", "arm,primecell";
336 reg = <0x0 0x001c060000 0x0 0x1000>;
337 interrupts = <0 197 4>;
338 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
339 clock-names = "KMIREFCLK", "apb_pclk";
340 };
341
342 kmi@1c070000 {
343 compatible = "arm,pl050", "arm,primecell";
344 reg = <0x0 0x001c070000 0x0 0x1000>;
345 interrupts = <0 103 4>;
346 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
347 clock-names = "KMIREFCLK", "apb_pclk";
348 };
349
350 bp_clock24mhz: clock24mhz {
351 compatible = "fixed-clock";
352 #clock-cells = <0>;
353 clock-frequency = <24000000>;
354 clock-output-names = "bp:clock24mhz";
355 };
356
357 virtio_block@1c130000 {
358 compatible = "virtio,mmio";
359 reg = <0x0 0x1c130000 0x0 0x200>;
360 interrupts = <0 204 4>;
361 };
362
Usama Arif1cd56dc2020-06-10 16:27:53 +0100363 sysreg: sysreg@1c010000 {
364 compatible = "arm,vexpress-sysreg";
365 reg = <0x0 0x001c010000 0x0 0x1000>;
366 gpio-controller;
367 #gpio-cells = <2>;
368 };
369
370 fixed_3v3: v2m-3v3 {
371 compatible = "regulator-fixed";
372 regulator-name = "3V3";
373 regulator-min-microvolt = <3300000>;
374 regulator-max-microvolt = <3300000>;
375 regulator-always-on;
376 };
377
378 mmci@1c050000 {
379 compatible = "arm,pl180", "arm,primecell";
380 reg = <0x0 0x001c050000 0x0 0x1000>;
381 interrupts = <0 107 0x4>,
382 <0 108 0x4>;
383 cd-gpios = <&sysreg 0 0>;
384 wp-gpios = <&sysreg 1 0>;
385 bus-width = <8>;
386 max-frequency = <12000000>;
387 vmmc-supply = <&fixed_3v3>;
388 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
389 clock-names = "mclk", "apb_pclk";
390 };
391
Usama Arifbec5afd2020-04-17 16:13:39 +0100392 dp0: display@2cc00000 {
393 #address-cells = <1>;
394 #size-cells = <0>;
395 compatible = "arm,mali-d71";
396 reg = <0 0x2cc00000 0 0x20000>;
397 interrupts = <0 69 4>;
398 interrupt-names = "DPU";
399 clocks = <&scmi_clk 0>;
400 clock-names = "aclk";
Usama Arifbec5afd2020-04-17 16:13:39 +0100401 pl0: pipeline@0 {
402 reg = <0>;
403 clocks = <&scmi_clk 1>;
404 clock-names = "pxclk";
405 pl_id = <0>;
406 ports {
407 #address-cells = <1>;
408 #size-cells = <0>;
409 port@0 {
410 reg = <0>;
411 dp_pl0_out0: endpoint {
412 remote-endpoint = <&vencoder_in>;
413 };
414 };
415 };
416 };
417
418 pl1: pipeline@1 {
419 reg = <1>;
420 clocks = <&scmi_clk 2>;
421 clock-names = "pxclk";
422 pl_id = <1>;
423 ports {
424 #address-cells = <1>;
425 #size-cells = <0>;
426 port@0 {
427 reg = <0>;
428 };
429 };
430 };
431 };
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000432
433 ffa {
434 compatible = "arm,ffa";
435 conduit = "smc";
436 mem_share_buffer = "tx";
437 };
438
439 firmware {
440 optee {
441 compatible = "linaro,optee-tz";
442 method = "ffa";
443 };
444 };
Usama Arifbec5afd2020-04-17 16:13:39 +0100445};