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Usama Arifbec5afd2020-04-17 16:13:39 +01001/*
2 * Copyright (c) 2020, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/dts-v1/;
8
9/ {
10 compatible = "arm,tc0";
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
14
15 aliases {
16 serial0 = &soc_uart0;
17 };
18
19 chosen {
20 stdout-path = "soc_uart0:115200n8";
21 };
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 cpu-map {
28 cluster0 {
29 core0 {
30 cpu = <&CPU0>;
31 };
32 core1 {
33 cpu = <&CPU1>;
34 };
35 core2 {
36 cpu = <&CPU2>;
37 };
38 core3 {
39 cpu = <&CPU3>;
40 };
41 };
42 };
43
Usama Arif57900782020-08-12 17:14:37 +010044 /*
45 * The timings below are just to demonstrate working cpuidle.
46 * These values may be inaccurate.
47 */
48 idle-states {
49 entry-method = "arm,psci";
50
51 CPU_SLEEP_0: cpu-sleep-0 {
52 compatible = "arm,idle-state";
53 arm,psci-suspend-param = <0x0010000>;
54 local-timer-stop;
55 entry-latency-us = <300>;
56 exit-latency-us = <1200>;
57 min-residency-us = <2000>;
58 };
59 CLUSTER_SLEEP_0: cluster-sleep-0 {
60 compatible = "arm,idle-state";
61 arm,psci-suspend-param = <0x1010000>;
62 local-timer-stop;
63 entry-latency-us = <400>;
64 exit-latency-us = <1200>;
65 min-residency-us = <2500>;
66 };
67 };
68
Usama Arifbec5afd2020-04-17 16:13:39 +010069 CPU0:cpu@0 {
70 device_type = "cpu";
71 compatible = "arm,armv8";
72 reg = <0x0>;
73 enable-method = "psci";
74 clocks = <&scmi_dvfs 0>;
Usama Arif57900782020-08-12 17:14:37 +010075 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifbec5afd2020-04-17 16:13:39 +010076 };
77
78 CPU1:cpu@100 {
79 device_type = "cpu";
80 compatible = "arm,armv8";
81 reg = <0x100>;
82 enable-method = "psci";
83 clocks = <&scmi_dvfs 0>;
Usama Arif57900782020-08-12 17:14:37 +010084 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifbec5afd2020-04-17 16:13:39 +010085 };
86
87 CPU2:cpu@200 {
88 device_type = "cpu";
89 compatible = "arm,armv8";
90 reg = <0x200>;
91 enable-method = "psci";
92 clocks = <&scmi_dvfs 0>;
Usama Arif57900782020-08-12 17:14:37 +010093 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifbec5afd2020-04-17 16:13:39 +010094 };
95
96 CPU3:cpu@300 {
97 device_type = "cpu";
98 compatible = "arm,armv8";
99 reg = <0x300>;
100 enable-method = "psci";
101 clocks = <&scmi_dvfs 0>;
Usama Arif57900782020-08-12 17:14:37 +0100102 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100103 };
104
105 };
106
107 memory@80000000 {
108 device_type = "memory";
109 reg = <0x0 0x80000000 0x0 0x80000000>;
110 };
111
112 psci {
113 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
114 method = "smc";
115 };
116
117 sram: sram@6000000 {
118 compatible = "mmio-sram";
119 reg = <0x0 0x06000000 0x0 0x8000>;
120
121 #address-cells = <1>;
122 #size-cells = <1>;
123 ranges = <0 0x0 0x06000000 0x8000>;
124
125 cpu_scp_scmi_mem: scp-shmem@0 {
126 compatible = "arm,scmi-shmem";
127 reg = <0x0 0x80>;
128 };
129 };
130
131 mbox_db_rx: mhu@45010000 {
132 compatible = "arm,mhuv2","arm,primecell";
133 reg = <0x0 0x45010000 0x0 0x1000>;
134 clocks = <&soc_refclk100mhz>;
135 clock-names = "apb_pclk";
136 #mbox-cells = <1>;
Usama Arif884f40d2020-08-18 12:56:44 +0100137 interrupts = <0 317 4>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100138 interrupt-names = "mhu_rx";
139 mhu-protocol = "doorbell";
140 };
141
142 mbox_db_tx: mhu@45000000 {
143 compatible = "arm,mhuv2","arm,primecell";
144 reg = <0x0 0x45000000 0x0 0x1000>;
145 clocks = <&soc_refclk100mhz>;
146 clock-names = "apb_pclk";
147 #mbox-cells = <1>;
148 interrupt-names = "mhu_tx";
149 mhu-protocol = "doorbell";
150 };
151
152 scmi {
153 compatible = "arm,scmi";
154 method = "mailbox-doorbell";
155 mbox-names = "tx", "rx";
156 mboxes = <&mbox_db_tx 0 &mbox_db_rx 0>;
157 shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>;
158 #address-cells = <1>;
159 #size-cells = <0>;
160
161 scmi_dvfs: protocol@13 {
162 reg = <0x13>;
163 #clock-cells = <1>;
164 };
165
166 scmi_clk: protocol@14 {
167 reg = <0x14>;
168 #clock-cells = <1>;
169 };
170 };
171
172 gic: interrupt-controller@2c010000 {
173 compatible = "arm,gic-600", "arm,gic-v3";
174 #address-cells = <2>;
175 #interrupt-cells = <3>;
176 #size-cells = <2>;
177 ranges;
178 interrupt-controller;
179 reg = <0x0 0x30000000 0 0x10000>, /* GICD */
180 <0x0 0x30140000 0 0x200000>; /* GICR */
181 interrupts = <0x1 0x9 0x4>;
182 };
183
184 timer {
185 compatible = "arm,armv8-timer";
186 interrupts = <0x1 13 0x8>,
187 <0x1 14 0x8>,
188 <0x1 11 0x8>,
189 <0x1 10 0x8>;
190 };
191
192 soc_refclk100mhz: refclk100mhz {
193 compatible = "fixed-clock";
194 #clock-cells = <0>;
195 clock-frequency = <100000000>;
196 clock-output-names = "apb_pclk";
197 };
198
199 soc_refclk60mhz: refclk60mhz {
200 compatible = "fixed-clock";
201 #clock-cells = <0>;
202 clock-frequency = <60000000>;
203 clock-output-names = "iofpga_clk";
204 };
205
206 soc_uartclk: uartclk {
207 compatible = "fixed-clock";
208 #clock-cells = <0>;
209 clock-frequency = <50000000>;
210 clock-output-names = "uartclk";
211 };
212
213 soc_uart0: uart@7ff80000 {
214 compatible = "arm,pl011", "arm,primecell";
215 reg = <0x0 0x7ff80000 0x0 0x1000>;
216 interrupts = <0x0 116 0x4>;
217 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
218 clock-names = "uartclk", "apb_pclk";
219 status = "okay";
220 };
221
222 vencoder {
223 compatible = "drm,virtual-encoder";
224
225 port {
226 vencoder_in: endpoint {
Avinash Mehtadf71a602020-07-22 16:40:07 +0100227 remote-endpoint = <&dp_pl0_out0>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100228 };
229 };
230
231 display-timings {
232 panel-timing {
233 clock-frequency = <25175000>;
234 hactive = <640>;
235 vactive = <480>;
236 hfront-porch = <16>;
237 hback-porch = <48>;
238 hsync-len = <96>;
239 vfront-porch = <10>;
240 vback-porch = <33>;
241 vsync-len = <2>;
242 };
243 };
244
245 };
246
247 hdlcd: hdlcd@7ff60000 {
248 compatible = "arm,hdlcd";
249 reg = <0x0 0x7ff60000 0x0 0x1000>;
250 interrupts = <0x0 117 0x4>;
251 clocks = <&fake_hdlcd_clk>;
252 clock-names = "pxlclk";
Avinash Mehtadf71a602020-07-22 16:40:07 +0100253 status = "disabled";
Usama Arifbec5afd2020-04-17 16:13:39 +0100254
255 port {
256 hdlcd_out: endpoint {
257 remote-endpoint = <&vencoder_in>;
258 };
259 };
260 };
261
262 fake_hdlcd_clk: fake-hdlcd-clk {
263 compatible = "fixed-clock";
264 #clock-cells = <0>;
265 clock-frequency = <25175000>;
266 clock-output-names = "pxlclk";
267 };
268
269 ethernet@18000000 {
270 compatible = "smsc,lan91c111";
271 reg = <0x0 0x18000000 0x0 0x10000>;
272 interrupts = <0 109 4>;
273 };
274
275 kmi@1c060000 {
276 compatible = "arm,pl050", "arm,primecell";
277 reg = <0x0 0x001c060000 0x0 0x1000>;
278 interrupts = <0 197 4>;
279 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
280 clock-names = "KMIREFCLK", "apb_pclk";
281 };
282
283 kmi@1c070000 {
284 compatible = "arm,pl050", "arm,primecell";
285 reg = <0x0 0x001c070000 0x0 0x1000>;
286 interrupts = <0 103 4>;
287 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
288 clock-names = "KMIREFCLK", "apb_pclk";
289 };
290
291 bp_clock24mhz: clock24mhz {
292 compatible = "fixed-clock";
293 #clock-cells = <0>;
294 clock-frequency = <24000000>;
295 clock-output-names = "bp:clock24mhz";
296 };
297
298 virtio_block@1c130000 {
299 compatible = "virtio,mmio";
300 reg = <0x0 0x1c130000 0x0 0x200>;
301 interrupts = <0 204 4>;
302 };
303
Usama Arif1cd56dc2020-06-10 16:27:53 +0100304 sysreg: sysreg@1c010000 {
305 compatible = "arm,vexpress-sysreg";
306 reg = <0x0 0x001c010000 0x0 0x1000>;
307 gpio-controller;
308 #gpio-cells = <2>;
309 };
310
311 fixed_3v3: v2m-3v3 {
312 compatible = "regulator-fixed";
313 regulator-name = "3V3";
314 regulator-min-microvolt = <3300000>;
315 regulator-max-microvolt = <3300000>;
316 regulator-always-on;
317 };
318
319 mmci@1c050000 {
320 compatible = "arm,pl180", "arm,primecell";
321 reg = <0x0 0x001c050000 0x0 0x1000>;
322 interrupts = <0 107 0x4>,
323 <0 108 0x4>;
324 cd-gpios = <&sysreg 0 0>;
325 wp-gpios = <&sysreg 1 0>;
326 bus-width = <8>;
327 max-frequency = <12000000>;
328 vmmc-supply = <&fixed_3v3>;
329 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
330 clock-names = "mclk", "apb_pclk";
331 };
332
Usama Arifbec5afd2020-04-17 16:13:39 +0100333 dp0: display@2cc00000 {
334 #address-cells = <1>;
335 #size-cells = <0>;
336 compatible = "arm,mali-d71";
337 reg = <0 0x2cc00000 0 0x20000>;
338 interrupts = <0 69 4>;
339 interrupt-names = "DPU";
340 clocks = <&scmi_clk 0>;
341 clock-names = "aclk";
Usama Arifbec5afd2020-04-17 16:13:39 +0100342 pl0: pipeline@0 {
343 reg = <0>;
344 clocks = <&scmi_clk 1>;
345 clock-names = "pxclk";
346 pl_id = <0>;
347 ports {
348 #address-cells = <1>;
349 #size-cells = <0>;
350 port@0 {
351 reg = <0>;
352 dp_pl0_out0: endpoint {
353 remote-endpoint = <&vencoder_in>;
354 };
355 };
356 };
357 };
358
359 pl1: pipeline@1 {
360 reg = <1>;
361 clocks = <&scmi_clk 2>;
362 clock-names = "pxclk";
363 pl_id = <1>;
364 ports {
365 #address-cells = <1>;
366 #size-cells = <0>;
367 port@0 {
368 reg = <0>;
369 };
370 };
371 };
372 };
373};