blob: 13c9e16e4da0e674b67e63c5168b6f91fd3ee0fe [file] [log] [blame]
Usama Arifbec5afd2020-04-17 16:13:39 +01001/*
Usama Ariffdfd2502021-03-30 16:39:19 +01002 * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
Usama Arifbec5afd2020-04-17 16:13:39 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/dts-v1/;
8
9/ {
Usama Ariff1513622021-04-09 17:07:41 +010010 compatible = "arm,tc";
Usama Arifbec5afd2020-04-17 16:13:39 +010011 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
14
15 aliases {
16 serial0 = &soc_uart0;
17 };
18
19 chosen {
Anders Dellien1509a272021-06-08 09:27:17 +010020 bootargs = "console=ttyAMA0 debug user_debug=31 earlycon=pl011,0x7ff80000 loglevel=9 androidboot.hardware=total_compute androidboot.boot_devices=1c050000.mmci ip=dhcp androidboot.selinux=permissive allow_mismatched_32bit_el0";
Nikos Nikoleris35800bd2021-01-21 13:50:25 +000021 stdout-path = "serial0:115200n8";
Usama Arifbec5afd2020-04-17 16:13:39 +010022 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 cpu-map {
29 cluster0 {
30 core0 {
31 cpu = <&CPU0>;
32 };
33 core1 {
34 cpu = <&CPU1>;
35 };
36 core2 {
37 cpu = <&CPU2>;
38 };
39 core3 {
40 cpu = <&CPU3>;
41 };
Avinash Mehtaf68a0842020-10-28 16:43:28 +000042 core4 {
43 cpu = <&CPU4>;
44 };
45 core5 {
46 cpu = <&CPU5>;
47 };
48 core6 {
49 cpu = <&CPU6>;
50 };
51 core7 {
52 cpu = <&CPU7>;
53 };
Usama Arifbec5afd2020-04-17 16:13:39 +010054 };
55 };
56
Usama Arif57900782020-08-12 17:14:37 +010057 /*
58 * The timings below are just to demonstrate working cpuidle.
59 * These values may be inaccurate.
60 */
61 idle-states {
62 entry-method = "arm,psci";
63
64 CPU_SLEEP_0: cpu-sleep-0 {
65 compatible = "arm,idle-state";
66 arm,psci-suspend-param = <0x0010000>;
67 local-timer-stop;
68 entry-latency-us = <300>;
69 exit-latency-us = <1200>;
70 min-residency-us = <2000>;
71 };
72 CLUSTER_SLEEP_0: cluster-sleep-0 {
73 compatible = "arm,idle-state";
74 arm,psci-suspend-param = <0x1010000>;
75 local-timer-stop;
76 entry-latency-us = <400>;
77 exit-latency-us = <1200>;
78 min-residency-us = <2500>;
79 };
80 };
81
Chris Kayc2d29ba2021-05-18 18:49:51 +010082 amus {
83 amu: amu-0 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86
87 mpmm_gear0: counter@0 {
88 reg = <0>;
89
90 enable-at-el3;
91 };
92
93 mpmm_gear1: counter@1 {
94 reg = <1>;
95
96 enable-at-el3;
97 };
98
99 mpmm_gear2: counter@2 {
100 reg = <2>;
101
102 enable-at-el3;
103 };
104 };
105 };
106
Usama Arifbec5afd2020-04-17 16:13:39 +0100107 CPU0:cpu@0 {
108 device_type = "cpu";
109 compatible = "arm,armv8";
110 reg = <0x0>;
111 enable-method = "psci";
112 clocks = <&scmi_dvfs 0>;
Usama Arif57900782020-08-12 17:14:37 +0100113 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100114 capacity-dmips-mhz = <406>;
Chris Kayc2d29ba2021-05-18 18:49:51 +0100115 amu = <&amu>;
116 supports-mpmm;
Usama Arifbec5afd2020-04-17 16:13:39 +0100117 };
118
119 CPU1:cpu@100 {
120 device_type = "cpu";
121 compatible = "arm,armv8";
122 reg = <0x100>;
123 enable-method = "psci";
124 clocks = <&scmi_dvfs 0>;
Usama Arif57900782020-08-12 17:14:37 +0100125 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100126 capacity-dmips-mhz = <406>;
Chris Kayc2d29ba2021-05-18 18:49:51 +0100127 amu = <&amu>;
128 supports-mpmm;
Usama Arifbec5afd2020-04-17 16:13:39 +0100129 };
130
131 CPU2:cpu@200 {
132 device_type = "cpu";
133 compatible = "arm,armv8";
134 reg = <0x200>;
135 enable-method = "psci";
136 clocks = <&scmi_dvfs 0>;
Usama Arif57900782020-08-12 17:14:37 +0100137 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100138 capacity-dmips-mhz = <406>;
Chris Kayc2d29ba2021-05-18 18:49:51 +0100139 amu = <&amu>;
140 supports-mpmm;
Usama Arifbec5afd2020-04-17 16:13:39 +0100141 };
142
143 CPU3:cpu@300 {
144 device_type = "cpu";
145 compatible = "arm,armv8";
146 reg = <0x300>;
147 enable-method = "psci";
148 clocks = <&scmi_dvfs 0>;
Usama Arif57900782020-08-12 17:14:37 +0100149 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100150 capacity-dmips-mhz = <406>;
Chris Kayc2d29ba2021-05-18 18:49:51 +0100151 amu = <&amu>;
152 supports-mpmm;
Usama Arifbec5afd2020-04-17 16:13:39 +0100153 };
154
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000155 CPU4:cpu@400 {
156 device_type = "cpu";
157 compatible = "arm,armv8";
158 reg = <0x400>;
159 enable-method = "psci";
Usama Arif75edb752021-02-03 15:40:46 +0000160 clocks = <&scmi_dvfs 1>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000161 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100162 capacity-dmips-mhz = <912>;
Chris Kayc2d29ba2021-05-18 18:49:51 +0100163 amu = <&amu>;
164 supports-mpmm;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000165 };
166
167 CPU5:cpu@500 {
168 device_type = "cpu";
169 compatible = "arm,armv8";
170 reg = <0x500>;
171 enable-method = "psci";
Usama Arif75edb752021-02-03 15:40:46 +0000172 clocks = <&scmi_dvfs 1>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000173 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100174 capacity-dmips-mhz = <912>;
Chris Kayc2d29ba2021-05-18 18:49:51 +0100175 amu = <&amu>;
176 supports-mpmm;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000177 };
178
179 CPU6:cpu@600 {
180 device_type = "cpu";
181 compatible = "arm,armv8";
182 reg = <0x600>;
183 enable-method = "psci";
Usama Arif75edb752021-02-03 15:40:46 +0000184 clocks = <&scmi_dvfs 1>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000185 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100186 capacity-dmips-mhz = <912>;
Chris Kayc2d29ba2021-05-18 18:49:51 +0100187 amu = <&amu>;
188 supports-mpmm;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000189 };
190
191 CPU7:cpu@700 {
192 device_type = "cpu";
193 compatible = "arm,armv8";
194 reg = <0x700>;
195 enable-method = "psci";
Usama Arif410d50d2021-04-07 11:48:22 +0100196 clocks = <&scmi_dvfs 2>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000197 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100198 capacity-dmips-mhz = <1024>;
Chris Kayc2d29ba2021-05-18 18:49:51 +0100199 amu = <&amu>;
200 supports-mpmm;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000201 };
202
Usama Arifbec5afd2020-04-17 16:13:39 +0100203 };
204
Arunachalam Ganapathy948bb442020-12-14 12:31:32 +0000205 reserved-memory {
206 #address-cells = <2>;
207 #size-cells = <2>;
208 ranges;
209
210 optee@0xfce00000 {
211 reg = <0x00000000 0xfce00000 0 0x00200000>;
212 no-map;
213 };
214 };
215
Usama Arifbec5afd2020-04-17 16:13:39 +0100216 psci {
Usama Arif7a64bfa2021-05-27 20:09:17 +0100217 compatible = "arm,psci-1.0", "arm,psci-0.2";
Usama Arifbec5afd2020-04-17 16:13:39 +0100218 method = "smc";
219 };
220
221 sram: sram@6000000 {
222 compatible = "mmio-sram";
223 reg = <0x0 0x06000000 0x0 0x8000>;
224
225 #address-cells = <1>;
226 #size-cells = <1>;
227 ranges = <0 0x0 0x06000000 0x8000>;
228
229 cpu_scp_scmi_mem: scp-shmem@0 {
230 compatible = "arm,scmi-shmem";
231 reg = <0x0 0x80>;
232 };
233 };
234
235 mbox_db_rx: mhu@45010000 {
Usama Arifb315c702021-05-27 20:01:39 +0100236 compatible = "arm,mhuv2-rx","arm,primecell";
Usama Arifbec5afd2020-04-17 16:13:39 +0100237 reg = <0x0 0x45010000 0x0 0x1000>;
238 clocks = <&soc_refclk100mhz>;
239 clock-names = "apb_pclk";
Usama Arifb315c702021-05-27 20:01:39 +0100240 #mbox-cells = <2>;
Usama Arif884f40d2020-08-18 12:56:44 +0100241 interrupts = <0 317 4>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100242 interrupt-names = "mhu_rx";
243 mhu-protocol = "doorbell";
Usama Arifb315c702021-05-27 20:01:39 +0100244 arm,mhuv2-protocols = <0 1>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100245 };
246
247 mbox_db_tx: mhu@45000000 {
Usama Arifb315c702021-05-27 20:01:39 +0100248 compatible = "arm,mhuv2-tx","arm,primecell";
Usama Arifbec5afd2020-04-17 16:13:39 +0100249 reg = <0x0 0x45000000 0x0 0x1000>;
250 clocks = <&soc_refclk100mhz>;
251 clock-names = "apb_pclk";
Usama Arifb315c702021-05-27 20:01:39 +0100252 #mbox-cells = <2>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100253 interrupt-names = "mhu_tx";
254 mhu-protocol = "doorbell";
Usama Arifb315c702021-05-27 20:01:39 +0100255 arm,mhuv2-protocols = <0 1>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100256 };
257
258 scmi {
259 compatible = "arm,scmi";
Usama Arifbec5afd2020-04-17 16:13:39 +0100260 mbox-names = "tx", "rx";
Usama Arifb315c702021-05-27 20:01:39 +0100261 mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >;
Usama Arifbec5afd2020-04-17 16:13:39 +0100262 shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>;
263 #address-cells = <1>;
264 #size-cells = <0>;
265
266 scmi_dvfs: protocol@13 {
267 reg = <0x13>;
268 #clock-cells = <1>;
269 };
270
271 scmi_clk: protocol@14 {
272 reg = <0x14>;
273 #clock-cells = <1>;
274 };
275 };
276
277 gic: interrupt-controller@2c010000 {
278 compatible = "arm,gic-600", "arm,gic-v3";
279 #address-cells = <2>;
280 #interrupt-cells = <3>;
281 #size-cells = <2>;
282 ranges;
283 interrupt-controller;
284 reg = <0x0 0x30000000 0 0x10000>, /* GICD */
Usama Ariffdfd2502021-03-30 16:39:19 +0100285 <0x0 0x30080000 0 0x200000>; /* GICR */
Usama Arifbec5afd2020-04-17 16:13:39 +0100286 interrupts = <0x1 0x9 0x4>;
287 };
288
289 timer {
290 compatible = "arm,armv8-timer";
291 interrupts = <0x1 13 0x8>,
292 <0x1 14 0x8>,
293 <0x1 11 0x8>,
294 <0x1 10 0x8>;
295 };
296
297 soc_refclk100mhz: refclk100mhz {
298 compatible = "fixed-clock";
299 #clock-cells = <0>;
300 clock-frequency = <100000000>;
301 clock-output-names = "apb_pclk";
302 };
303
304 soc_refclk60mhz: refclk60mhz {
305 compatible = "fixed-clock";
306 #clock-cells = <0>;
307 clock-frequency = <60000000>;
308 clock-output-names = "iofpga_clk";
309 };
310
311 soc_uartclk: uartclk {
312 compatible = "fixed-clock";
313 #clock-cells = <0>;
314 clock-frequency = <50000000>;
315 clock-output-names = "uartclk";
316 };
317
318 soc_uart0: uart@7ff80000 {
319 compatible = "arm,pl011", "arm,primecell";
320 reg = <0x0 0x7ff80000 0x0 0x1000>;
321 interrupts = <0x0 116 0x4>;
322 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
323 clock-names = "uartclk", "apb_pclk";
324 status = "okay";
325 };
326
327 vencoder {
328 compatible = "drm,virtual-encoder";
329
330 port {
331 vencoder_in: endpoint {
Avinash Mehtadf71a602020-07-22 16:40:07 +0100332 remote-endpoint = <&dp_pl0_out0>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100333 };
334 };
335
336 display-timings {
337 panel-timing {
338 clock-frequency = <25175000>;
339 hactive = <640>;
340 vactive = <480>;
341 hfront-porch = <16>;
342 hback-porch = <48>;
343 hsync-len = <96>;
344 vfront-porch = <10>;
345 vback-porch = <33>;
346 vsync-len = <2>;
347 };
348 };
349
350 };
351
352 hdlcd: hdlcd@7ff60000 {
353 compatible = "arm,hdlcd";
354 reg = <0x0 0x7ff60000 0x0 0x1000>;
355 interrupts = <0x0 117 0x4>;
356 clocks = <&fake_hdlcd_clk>;
357 clock-names = "pxlclk";
Avinash Mehtadf71a602020-07-22 16:40:07 +0100358 status = "disabled";
Usama Arifbec5afd2020-04-17 16:13:39 +0100359
360 port {
361 hdlcd_out: endpoint {
362 remote-endpoint = <&vencoder_in>;
363 };
364 };
365 };
366
367 fake_hdlcd_clk: fake-hdlcd-clk {
368 compatible = "fixed-clock";
369 #clock-cells = <0>;
370 clock-frequency = <25175000>;
371 clock-output-names = "pxlclk";
372 };
373
374 ethernet@18000000 {
375 compatible = "smsc,lan91c111";
376 reg = <0x0 0x18000000 0x0 0x10000>;
377 interrupts = <0 109 4>;
378 };
379
380 kmi@1c060000 {
381 compatible = "arm,pl050", "arm,primecell";
382 reg = <0x0 0x001c060000 0x0 0x1000>;
383 interrupts = <0 197 4>;
384 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
385 clock-names = "KMIREFCLK", "apb_pclk";
386 };
387
388 kmi@1c070000 {
389 compatible = "arm,pl050", "arm,primecell";
390 reg = <0x0 0x001c070000 0x0 0x1000>;
391 interrupts = <0 103 4>;
392 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
393 clock-names = "KMIREFCLK", "apb_pclk";
394 };
395
396 bp_clock24mhz: clock24mhz {
397 compatible = "fixed-clock";
398 #clock-cells = <0>;
399 clock-frequency = <24000000>;
400 clock-output-names = "bp:clock24mhz";
401 };
402
403 virtio_block@1c130000 {
404 compatible = "virtio,mmio";
405 reg = <0x0 0x1c130000 0x0 0x200>;
406 interrupts = <0 204 4>;
407 };
408
Usama Arif1cd56dc2020-06-10 16:27:53 +0100409 sysreg: sysreg@1c010000 {
410 compatible = "arm,vexpress-sysreg";
411 reg = <0x0 0x001c010000 0x0 0x1000>;
412 gpio-controller;
413 #gpio-cells = <2>;
414 };
415
416 fixed_3v3: v2m-3v3 {
417 compatible = "regulator-fixed";
418 regulator-name = "3V3";
419 regulator-min-microvolt = <3300000>;
420 regulator-max-microvolt = <3300000>;
421 regulator-always-on;
422 };
423
424 mmci@1c050000 {
425 compatible = "arm,pl180", "arm,primecell";
426 reg = <0x0 0x001c050000 0x0 0x1000>;
427 interrupts = <0 107 0x4>,
428 <0 108 0x4>;
429 cd-gpios = <&sysreg 0 0>;
430 wp-gpios = <&sysreg 1 0>;
431 bus-width = <8>;
432 max-frequency = <12000000>;
433 vmmc-supply = <&fixed_3v3>;
434 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
435 clock-names = "mclk", "apb_pclk";
436 };
437
Usama Arifbec5afd2020-04-17 16:13:39 +0100438 dp0: display@2cc00000 {
439 #address-cells = <1>;
440 #size-cells = <0>;
441 compatible = "arm,mali-d71";
442 reg = <0 0x2cc00000 0 0x20000>;
443 interrupts = <0 69 4>;
444 interrupt-names = "DPU";
445 clocks = <&scmi_clk 0>;
446 clock-names = "aclk";
Usama Arifbec5afd2020-04-17 16:13:39 +0100447 pl0: pipeline@0 {
448 reg = <0>;
449 clocks = <&scmi_clk 1>;
450 clock-names = "pxclk";
451 pl_id = <0>;
452 ports {
453 #address-cells = <1>;
454 #size-cells = <0>;
455 port@0 {
456 reg = <0>;
457 dp_pl0_out0: endpoint {
458 remote-endpoint = <&vencoder_in>;
459 };
460 };
461 };
462 };
463
464 pl1: pipeline@1 {
465 reg = <1>;
466 clocks = <&scmi_clk 2>;
467 clock-names = "pxclk";
468 pl_id = <1>;
469 ports {
470 #address-cells = <1>;
471 #size-cells = <0>;
472 port@0 {
473 reg = <0>;
474 };
475 };
476 };
477 };
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000478
Usama Arifbec5afd2020-04-17 16:13:39 +0100479};