blob: 31fcfe2de85b7a95c5459ae2c6c084342eb8cf25 [file] [log] [blame]
Usama Arifbec5afd2020-04-17 16:13:39 +01001/*
Usama Ariffdfd2502021-03-30 16:39:19 +01002 * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
Usama Arifbec5afd2020-04-17 16:13:39 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/dts-v1/;
8
9/ {
Usama Ariff1513622021-04-09 17:07:41 +010010 compatible = "arm,tc";
Usama Arifbec5afd2020-04-17 16:13:39 +010011 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
14
15 aliases {
16 serial0 = &soc_uart0;
17 };
18
19 chosen {
Anders Dellien1509a272021-06-08 09:27:17 +010020 bootargs = "console=ttyAMA0 debug user_debug=31 earlycon=pl011,0x7ff80000 loglevel=9 androidboot.hardware=total_compute androidboot.boot_devices=1c050000.mmci ip=dhcp androidboot.selinux=permissive allow_mismatched_32bit_el0";
Nikos Nikoleris35800bd2021-01-21 13:50:25 +000021 stdout-path = "serial0:115200n8";
Usama Arifbec5afd2020-04-17 16:13:39 +010022 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 cpu-map {
29 cluster0 {
30 core0 {
31 cpu = <&CPU0>;
32 };
33 core1 {
34 cpu = <&CPU1>;
35 };
36 core2 {
37 cpu = <&CPU2>;
38 };
39 core3 {
40 cpu = <&CPU3>;
41 };
Avinash Mehtaf68a0842020-10-28 16:43:28 +000042 core4 {
43 cpu = <&CPU4>;
44 };
45 core5 {
46 cpu = <&CPU5>;
47 };
48 core6 {
49 cpu = <&CPU6>;
50 };
51 core7 {
52 cpu = <&CPU7>;
53 };
Usama Arifbec5afd2020-04-17 16:13:39 +010054 };
55 };
56
Usama Arif57900782020-08-12 17:14:37 +010057 /*
58 * The timings below are just to demonstrate working cpuidle.
59 * These values may be inaccurate.
60 */
61 idle-states {
62 entry-method = "arm,psci";
63
64 CPU_SLEEP_0: cpu-sleep-0 {
65 compatible = "arm,idle-state";
66 arm,psci-suspend-param = <0x0010000>;
67 local-timer-stop;
68 entry-latency-us = <300>;
69 exit-latency-us = <1200>;
70 min-residency-us = <2000>;
71 };
72 CLUSTER_SLEEP_0: cluster-sleep-0 {
73 compatible = "arm,idle-state";
74 arm,psci-suspend-param = <0x1010000>;
75 local-timer-stop;
76 entry-latency-us = <400>;
77 exit-latency-us = <1200>;
78 min-residency-us = <2500>;
79 };
80 };
81
Usama Arifbec5afd2020-04-17 16:13:39 +010082 CPU0:cpu@0 {
83 device_type = "cpu";
84 compatible = "arm,armv8";
85 reg = <0x0>;
86 enable-method = "psci";
87 clocks = <&scmi_dvfs 0>;
Usama Arif57900782020-08-12 17:14:37 +010088 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +010089 capacity-dmips-mhz = <406>;
Usama Arifbec5afd2020-04-17 16:13:39 +010090 };
91
92 CPU1:cpu@100 {
93 device_type = "cpu";
94 compatible = "arm,armv8";
95 reg = <0x100>;
96 enable-method = "psci";
97 clocks = <&scmi_dvfs 0>;
Usama Arif57900782020-08-12 17:14:37 +010098 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +010099 capacity-dmips-mhz = <406>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100100 };
101
102 CPU2:cpu@200 {
103 device_type = "cpu";
104 compatible = "arm,armv8";
105 reg = <0x200>;
106 enable-method = "psci";
107 clocks = <&scmi_dvfs 0>;
Usama Arif57900782020-08-12 17:14:37 +0100108 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100109 capacity-dmips-mhz = <406>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100110 };
111
112 CPU3:cpu@300 {
113 device_type = "cpu";
114 compatible = "arm,armv8";
115 reg = <0x300>;
116 enable-method = "psci";
117 clocks = <&scmi_dvfs 0>;
Usama Arif57900782020-08-12 17:14:37 +0100118 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100119 capacity-dmips-mhz = <406>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100120 };
121
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000122 CPU4:cpu@400 {
123 device_type = "cpu";
124 compatible = "arm,armv8";
125 reg = <0x400>;
126 enable-method = "psci";
Usama Arif75edb752021-02-03 15:40:46 +0000127 clocks = <&scmi_dvfs 1>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000128 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100129 capacity-dmips-mhz = <912>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000130 };
131
132 CPU5:cpu@500 {
133 device_type = "cpu";
134 compatible = "arm,armv8";
135 reg = <0x500>;
136 enable-method = "psci";
Usama Arif75edb752021-02-03 15:40:46 +0000137 clocks = <&scmi_dvfs 1>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000138 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100139 capacity-dmips-mhz = <912>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000140 };
141
142 CPU6:cpu@600 {
143 device_type = "cpu";
144 compatible = "arm,armv8";
145 reg = <0x600>;
146 enable-method = "psci";
Usama Arif75edb752021-02-03 15:40:46 +0000147 clocks = <&scmi_dvfs 1>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000148 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100149 capacity-dmips-mhz = <912>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000150 };
151
152 CPU7:cpu@700 {
153 device_type = "cpu";
154 compatible = "arm,armv8";
155 reg = <0x700>;
156 enable-method = "psci";
Usama Arif410d50d2021-04-07 11:48:22 +0100157 clocks = <&scmi_dvfs 2>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000158 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100159 capacity-dmips-mhz = <1024>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000160 };
161
Usama Arifbec5afd2020-04-17 16:13:39 +0100162 };
163
Arunachalam Ganapathy948bb442020-12-14 12:31:32 +0000164 reserved-memory {
165 #address-cells = <2>;
166 #size-cells = <2>;
167 ranges;
168
169 optee@0xfce00000 {
170 reg = <0x00000000 0xfce00000 0 0x00200000>;
171 no-map;
172 };
173 };
174
Usama Arifbec5afd2020-04-17 16:13:39 +0100175 psci {
Usama Arif7a64bfa2021-05-27 20:09:17 +0100176 compatible = "arm,psci-1.0", "arm,psci-0.2";
Usama Arifbec5afd2020-04-17 16:13:39 +0100177 method = "smc";
178 };
179
180 sram: sram@6000000 {
181 compatible = "mmio-sram";
182 reg = <0x0 0x06000000 0x0 0x8000>;
183
184 #address-cells = <1>;
185 #size-cells = <1>;
186 ranges = <0 0x0 0x06000000 0x8000>;
187
188 cpu_scp_scmi_mem: scp-shmem@0 {
189 compatible = "arm,scmi-shmem";
190 reg = <0x0 0x80>;
191 };
192 };
193
194 mbox_db_rx: mhu@45010000 {
Usama Arifb315c702021-05-27 20:01:39 +0100195 compatible = "arm,mhuv2-rx","arm,primecell";
Usama Arifbec5afd2020-04-17 16:13:39 +0100196 reg = <0x0 0x45010000 0x0 0x1000>;
197 clocks = <&soc_refclk100mhz>;
198 clock-names = "apb_pclk";
Usama Arifb315c702021-05-27 20:01:39 +0100199 #mbox-cells = <2>;
Usama Arif884f40d2020-08-18 12:56:44 +0100200 interrupts = <0 317 4>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100201 interrupt-names = "mhu_rx";
202 mhu-protocol = "doorbell";
Usama Arifb315c702021-05-27 20:01:39 +0100203 arm,mhuv2-protocols = <0 1>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100204 };
205
206 mbox_db_tx: mhu@45000000 {
Usama Arifb315c702021-05-27 20:01:39 +0100207 compatible = "arm,mhuv2-tx","arm,primecell";
Usama Arifbec5afd2020-04-17 16:13:39 +0100208 reg = <0x0 0x45000000 0x0 0x1000>;
209 clocks = <&soc_refclk100mhz>;
210 clock-names = "apb_pclk";
Usama Arifb315c702021-05-27 20:01:39 +0100211 #mbox-cells = <2>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100212 interrupt-names = "mhu_tx";
213 mhu-protocol = "doorbell";
Usama Arifb315c702021-05-27 20:01:39 +0100214 arm,mhuv2-protocols = <0 1>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100215 };
216
217 scmi {
218 compatible = "arm,scmi";
Usama Arifbec5afd2020-04-17 16:13:39 +0100219 mbox-names = "tx", "rx";
Usama Arifb315c702021-05-27 20:01:39 +0100220 mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >;
Usama Arifbec5afd2020-04-17 16:13:39 +0100221 shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>;
222 #address-cells = <1>;
223 #size-cells = <0>;
224
225 scmi_dvfs: protocol@13 {
226 reg = <0x13>;
227 #clock-cells = <1>;
228 };
229
230 scmi_clk: protocol@14 {
231 reg = <0x14>;
232 #clock-cells = <1>;
233 };
234 };
235
236 gic: interrupt-controller@2c010000 {
237 compatible = "arm,gic-600", "arm,gic-v3";
238 #address-cells = <2>;
239 #interrupt-cells = <3>;
240 #size-cells = <2>;
241 ranges;
242 interrupt-controller;
243 reg = <0x0 0x30000000 0 0x10000>, /* GICD */
Usama Ariffdfd2502021-03-30 16:39:19 +0100244 <0x0 0x30080000 0 0x200000>; /* GICR */
Usama Arifbec5afd2020-04-17 16:13:39 +0100245 interrupts = <0x1 0x9 0x4>;
246 };
247
248 timer {
249 compatible = "arm,armv8-timer";
250 interrupts = <0x1 13 0x8>,
251 <0x1 14 0x8>,
252 <0x1 11 0x8>,
253 <0x1 10 0x8>;
254 };
255
256 soc_refclk100mhz: refclk100mhz {
257 compatible = "fixed-clock";
258 #clock-cells = <0>;
259 clock-frequency = <100000000>;
260 clock-output-names = "apb_pclk";
261 };
262
263 soc_refclk60mhz: refclk60mhz {
264 compatible = "fixed-clock";
265 #clock-cells = <0>;
266 clock-frequency = <60000000>;
267 clock-output-names = "iofpga_clk";
268 };
269
270 soc_uartclk: uartclk {
271 compatible = "fixed-clock";
272 #clock-cells = <0>;
273 clock-frequency = <50000000>;
274 clock-output-names = "uartclk";
275 };
276
277 soc_uart0: uart@7ff80000 {
278 compatible = "arm,pl011", "arm,primecell";
279 reg = <0x0 0x7ff80000 0x0 0x1000>;
280 interrupts = <0x0 116 0x4>;
281 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
282 clock-names = "uartclk", "apb_pclk";
283 status = "okay";
284 };
285
286 vencoder {
287 compatible = "drm,virtual-encoder";
288
289 port {
290 vencoder_in: endpoint {
Avinash Mehtadf71a602020-07-22 16:40:07 +0100291 remote-endpoint = <&dp_pl0_out0>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100292 };
293 };
294
295 display-timings {
296 panel-timing {
297 clock-frequency = <25175000>;
298 hactive = <640>;
299 vactive = <480>;
300 hfront-porch = <16>;
301 hback-porch = <48>;
302 hsync-len = <96>;
303 vfront-porch = <10>;
304 vback-porch = <33>;
305 vsync-len = <2>;
306 };
307 };
308
309 };
310
311 hdlcd: hdlcd@7ff60000 {
312 compatible = "arm,hdlcd";
313 reg = <0x0 0x7ff60000 0x0 0x1000>;
314 interrupts = <0x0 117 0x4>;
315 clocks = <&fake_hdlcd_clk>;
316 clock-names = "pxlclk";
Avinash Mehtadf71a602020-07-22 16:40:07 +0100317 status = "disabled";
Usama Arifbec5afd2020-04-17 16:13:39 +0100318
319 port {
320 hdlcd_out: endpoint {
321 remote-endpoint = <&vencoder_in>;
322 };
323 };
324 };
325
326 fake_hdlcd_clk: fake-hdlcd-clk {
327 compatible = "fixed-clock";
328 #clock-cells = <0>;
329 clock-frequency = <25175000>;
330 clock-output-names = "pxlclk";
331 };
332
333 ethernet@18000000 {
334 compatible = "smsc,lan91c111";
335 reg = <0x0 0x18000000 0x0 0x10000>;
336 interrupts = <0 109 4>;
337 };
338
339 kmi@1c060000 {
340 compatible = "arm,pl050", "arm,primecell";
341 reg = <0x0 0x001c060000 0x0 0x1000>;
342 interrupts = <0 197 4>;
343 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
344 clock-names = "KMIREFCLK", "apb_pclk";
345 };
346
347 kmi@1c070000 {
348 compatible = "arm,pl050", "arm,primecell";
349 reg = <0x0 0x001c070000 0x0 0x1000>;
350 interrupts = <0 103 4>;
351 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
352 clock-names = "KMIREFCLK", "apb_pclk";
353 };
354
355 bp_clock24mhz: clock24mhz {
356 compatible = "fixed-clock";
357 #clock-cells = <0>;
358 clock-frequency = <24000000>;
359 clock-output-names = "bp:clock24mhz";
360 };
361
362 virtio_block@1c130000 {
363 compatible = "virtio,mmio";
364 reg = <0x0 0x1c130000 0x0 0x200>;
365 interrupts = <0 204 4>;
366 };
367
Usama Arif1cd56dc2020-06-10 16:27:53 +0100368 sysreg: sysreg@1c010000 {
369 compatible = "arm,vexpress-sysreg";
370 reg = <0x0 0x001c010000 0x0 0x1000>;
371 gpio-controller;
372 #gpio-cells = <2>;
373 };
374
375 fixed_3v3: v2m-3v3 {
376 compatible = "regulator-fixed";
377 regulator-name = "3V3";
378 regulator-min-microvolt = <3300000>;
379 regulator-max-microvolt = <3300000>;
380 regulator-always-on;
381 };
382
383 mmci@1c050000 {
384 compatible = "arm,pl180", "arm,primecell";
385 reg = <0x0 0x001c050000 0x0 0x1000>;
386 interrupts = <0 107 0x4>,
387 <0 108 0x4>;
388 cd-gpios = <&sysreg 0 0>;
389 wp-gpios = <&sysreg 1 0>;
390 bus-width = <8>;
391 max-frequency = <12000000>;
392 vmmc-supply = <&fixed_3v3>;
393 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
394 clock-names = "mclk", "apb_pclk";
395 };
396
Usama Arifbec5afd2020-04-17 16:13:39 +0100397 dp0: display@2cc00000 {
398 #address-cells = <1>;
399 #size-cells = <0>;
400 compatible = "arm,mali-d71";
401 reg = <0 0x2cc00000 0 0x20000>;
402 interrupts = <0 69 4>;
403 interrupt-names = "DPU";
404 clocks = <&scmi_clk 0>;
405 clock-names = "aclk";
Usama Arifbec5afd2020-04-17 16:13:39 +0100406 pl0: pipeline@0 {
407 reg = <0>;
408 clocks = <&scmi_clk 1>;
409 clock-names = "pxclk";
410 pl_id = <0>;
411 ports {
412 #address-cells = <1>;
413 #size-cells = <0>;
414 port@0 {
415 reg = <0>;
416 dp_pl0_out0: endpoint {
417 remote-endpoint = <&vencoder_in>;
418 };
419 };
420 };
421 };
422
423 pl1: pipeline@1 {
424 reg = <1>;
425 clocks = <&scmi_clk 2>;
426 clock-names = "pxclk";
427 pl_id = <1>;
428 ports {
429 #address-cells = <1>;
430 #size-cells = <0>;
431 port@0 {
432 reg = <0>;
433 };
434 };
435 };
436 };
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000437
Usama Arifbec5afd2020-04-17 16:13:39 +0100438};