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Achin Gupta7aea9082014-02-01 07:51:28 +00001/*
Govindraj Raja24d3a4e2023-12-21 13:57:49 -06002 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
Varun Wadekarcc238bb2022-09-13 12:38:47 +01003 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved.
Achin Gupta7aea9082014-02-01 07:51:28 +00004 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta7aea9082014-02-01 07:51:28 +00006 */
7
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <assert.h>
9#include <stdbool.h>
10#include <string.h>
11
12#include <platform_def.h>
13
Achin Gupta27b895e2014-05-04 18:38:28 +010014#include <arch.h>
Achin Gupta7aea9082014-02-01 07:51:28 +000015#include <arch_helpers.h>
Soby Mathew830f0ad2019-07-12 09:23:38 +010016#include <arch_features.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <bl31/interrupt_mgmt.h>
18#include <common/bl_common.h>
Claus Pedersen785e66c2022-09-12 22:42:58 +000019#include <common/debug.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010020#include <context.h>
Zelalem Awekef92c0cb2022-01-31 16:59:42 -060021#include <drivers/arm/gicv3.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000022#include <lib/el3_runtime/context_mgmt.h>
Elizabeth Ho4fc00d22023-07-18 14:10:25 +010023#include <lib/el3_runtime/cpu_data.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000024#include <lib/el3_runtime/pubsub_events.h>
25#include <lib/extensions/amu.h>
johpow0181865962022-01-28 17:06:20 -060026#include <lib/extensions/brbe.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000027#include <lib/extensions/mpam.h>
Boyan Karatotev05504ba2023-02-15 13:21:50 +000028#include <lib/extensions/pmuv3.h>
johpow019baade32021-07-08 14:14:00 -050029#include <lib/extensions/sme.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000030#include <lib/extensions/spe.h>
31#include <lib/extensions/sve.h>
Manish V Badarkhef356f7e2021-06-29 11:44:20 +010032#include <lib/extensions/sys_reg_trace.h>
Manish V Badarkhe20df29c2021-07-02 09:10:56 +010033#include <lib/extensions/trbe.h>
Manish V Badarkhe51a97112021-07-08 09:33:18 +010034#include <lib/extensions/trf.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000035#include <lib/utils.h>
Achin Gupta7aea9082014-02-01 07:51:28 +000036
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +010037#if ENABLE_FEAT_TWED
38/* Make sure delay value fits within the range(0-15) */
39CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check);
40#endif /* ENABLE_FEAT_TWED */
Achin Gupta7aea9082014-02-01 07:51:28 +000041
Elizabeth Ho4fc00d22023-07-18 14:10:25 +010042per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM];
43static bool has_secure_perworld_init;
44
Boyan Karatotev36cebf92023-03-08 11:56:49 +000045static void manage_extensions_nonsecure(cpu_context_t *ctx);
Jayanth Dodderi Chidanand4b5489c2022-03-28 15:28:55 +010046static void manage_extensions_secure(cpu_context_t *ctx);
Elizabeth Ho4fc00d22023-07-18 14:10:25 +010047static void manage_extensions_secure_per_world(void);
Zelalem Aweke20126002022-04-08 16:48:05 -050048
49static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep)
50{
51 u_register_t sctlr_elx, actlr_elx;
52
53 /*
54 * Initialise SCTLR_EL1 to the reset value corresponding to the target
55 * execution state setting all fields rather than relying on the hw.
56 * Some fields have architecturally UNKNOWN reset values and these are
57 * set to zero.
58 *
59 * SCTLR.EE: Endianness is taken from the entrypoint attributes.
60 *
61 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as
62 * required by PSCI specification)
63 */
64 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL;
65 if (GET_RW(ep->spsr) == MODE_RW_64) {
66 sctlr_elx |= SCTLR_EL1_RES1;
67 } else {
68 /*
69 * If the target execution state is AArch32 then the following
70 * fields need to be set.
71 *
72 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE
73 * instructions are not trapped to EL1.
74 *
75 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI
76 * instructions are not trapped to EL1.
77 *
78 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the
79 * CP15DMB, CP15DSB, and CP15ISB instructions.
80 */
81 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT
82 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT;
83 }
84
85#if ERRATA_A75_764081
86 /*
87 * If workaround of errata 764081 for Cortex-A75 is used then set
88 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier.
89 */
90 sctlr_elx |= SCTLR_IESB_BIT;
91#endif
92 /* Store the initialised SCTLR_EL1 value in the cpu_context */
93 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx);
94
95 /*
96 * Base the context ACTLR_EL1 on the current value, as it is
97 * implementation defined. The context restore process will write
98 * the value from the context to the actual register and can cause
99 * problems for processor cores that don't expect certain bits to
100 * be zero.
101 */
102 actlr_elx = read_actlr_el1();
103 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx));
104}
105
Zelalem Aweke42401112022-01-05 17:12:24 -0600106/******************************************************************************
107 * This function performs initializations that are specific to SECURE state
108 * and updates the cpu context specified by 'ctx'.
109 *****************************************************************************/
110static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep)
Achin Gupta7aea9082014-02-01 07:51:28 +0000111{
Zelalem Aweke42401112022-01-05 17:12:24 -0600112 u_register_t scr_el3;
113 el3_state_t *state;
114
115 state = get_el3state_ctx(ctx);
116 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
117
118#if defined(IMAGE_BL31) && !defined(SPD_spmd)
Achin Gupta7aea9082014-02-01 07:51:28 +0000119 /*
Zelalem Aweke42401112022-01-05 17:12:24 -0600120 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
121 * indicated by the interrupt routing model for BL31.
122 */
123 scr_el3 |= get_scr_el3_from_routing_model(SECURE);
124#endif
125
Govindraj Raja24d3a4e2023-12-21 13:57:49 -0600126 /* Allow access to Allocation Tags when mte is set*/
127 if (is_feat_mte_supported()) {
Zelalem Aweke42401112022-01-05 17:12:24 -0600128 scr_el3 |= SCR_ATA_BIT;
129 }
Zelalem Aweke42401112022-01-05 17:12:24 -0600130
Zelalem Aweke42401112022-01-05 17:12:24 -0600131 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
132
Zelalem Aweke20126002022-04-08 16:48:05 -0500133 /*
134 * Initialize EL1 context registers unless SPMC is running
135 * at S-EL2.
136 */
137#if !SPMD_SPM_AT_SEL2
138 setup_el1_context(ctx, ep);
139#endif
140
Zelalem Aweke42401112022-01-05 17:12:24 -0600141 manage_extensions_secure(ctx);
Elizabeth Ho4fc00d22023-07-18 14:10:25 +0100142
143 /**
144 * manage_extensions_secure_per_world api has to be executed once,
145 * as the registers getting initialised, maintain constant value across
146 * all the cpus for the secure world.
147 * Henceforth, this check ensures that the registers are initialised once
148 * and avoids re-initialization from multiple cores.
149 */
150 if (!has_secure_perworld_init) {
151 manage_extensions_secure_per_world();
152 }
153
Achin Gupta7aea9082014-02-01 07:51:28 +0000154}
155
Zelalem Aweke42401112022-01-05 17:12:24 -0600156#if ENABLE_RME
157/******************************************************************************
158 * This function performs initializations that are specific to REALM state
159 * and updates the cpu context specified by 'ctx'.
160 *****************************************************************************/
161static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep)
162{
163 u_register_t scr_el3;
164 el3_state_t *state;
165
166 state = get_el3state_ctx(ctx);
167 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
168
Maksims Svecovs1e25c5b2023-02-02 16:10:22 +0000169 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT;
170
Sona Mathew3b84c962023-10-25 16:48:19 -0500171 /* CSV2 version 2 and above */
Andre Przywara902c9022022-11-17 17:30:43 +0000172 if (is_feat_csv2_2_supported()) {
173 /* Enable access to the SCXTNUM_ELx registers. */
174 scr_el3 |= SCR_EnSCXT_BIT;
175 }
Zelalem Aweke42401112022-01-05 17:12:24 -0600176
177 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
178}
179#endif /* ENABLE_RME */
180
181/******************************************************************************
182 * This function performs initializations that are specific to NON-SECURE state
183 * and updates the cpu context specified by 'ctx'.
184 *****************************************************************************/
185static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep)
186{
187 u_register_t scr_el3;
188 el3_state_t *state;
189
190 state = get_el3state_ctx(ctx);
191 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
192
193 /* SCR_NS: Set the NS bit */
194 scr_el3 |= SCR_NS_BIT;
195
Boyan Karatotev8ae58f02023-04-20 11:00:50 +0100196 /* Allow access to Allocation Tags when MTE is implemented. */
197 scr_el3 |= SCR_ATA_BIT;
198
Zelalem Aweke42401112022-01-05 17:12:24 -0600199#if !CTX_INCLUDE_PAUTH_REGS
200 /*
Boyan Karatotev8ae58f02023-04-20 11:00:50 +0100201 * Pointer Authentication feature, if present, is always enabled by default
202 * for Non secure lower exception levels. We do not have an explicit
203 * flag to set it.
204 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower
205 * exception levels of secure and realm worlds.
Zelalem Aweke42401112022-01-05 17:12:24 -0600206 *
Boyan Karatotev8ae58f02023-04-20 11:00:50 +0100207 * To prevent the leakage between the worlds during world switch,
208 * we enable it only for the non-secure world.
209 *
210 * If the Secure/realm world wants to use pointer authentication,
211 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case
212 * it will be enabled globally for all the contexts.
213 *
214 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs
215 * other than EL3
216 *
217 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other
218 * than EL3
Zelalem Aweke42401112022-01-05 17:12:24 -0600219 */
220 scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
Zelalem Aweke42401112022-01-05 17:12:24 -0600221
Boyan Karatotev8ae58f02023-04-20 11:00:50 +0100222#endif /* CTX_INCLUDE_PAUTH_REGS */
Zelalem Aweke42401112022-01-05 17:12:24 -0600223
Manish Pandey0e3379d2022-10-10 11:43:08 +0100224#if HANDLE_EA_EL3_FIRST_NS
225 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */
226 scr_el3 |= SCR_EA_BIT;
227#endif
228
Manish Pandey7c6fcb42022-09-27 14:30:34 +0100229#if RAS_TRAP_NS_ERR_REC_ACCESS
230 /*
231 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR
232 * and RAS ERX registers from EL1 and EL2(from any security state)
233 * are trapped to EL3.
234 * Set here to trap only for NS EL1/EL2
235 *
236 */
237 scr_el3 |= SCR_TERR_BIT;
238#endif
239
Sona Mathew3b84c962023-10-25 16:48:19 -0500240 /* CSV2 version 2 and above */
Andre Przywara902c9022022-11-17 17:30:43 +0000241 if (is_feat_csv2_2_supported()) {
242 /* Enable access to the SCXTNUM_ELx registers. */
243 scr_el3 |= SCR_EnSCXT_BIT;
244 }
Maksims Svecovs1e25c5b2023-02-02 16:10:22 +0000245
Zelalem Aweke42401112022-01-05 17:12:24 -0600246#ifdef IMAGE_BL31
247 /*
248 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
249 * indicated by the interrupt routing model for BL31.
250 */
251 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE);
252#endif
253 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
Zelalem Awekef92c0cb2022-01-31 16:59:42 -0600254
Zelalem Aweke20126002022-04-08 16:48:05 -0500255 /* Initialize EL1 context registers */
256 setup_el1_context(ctx, ep);
257
Zelalem Awekef92c0cb2022-01-31 16:59:42 -0600258 /* Initialize EL2 context registers */
259#if CTX_INCLUDE_EL2_REGS
260
261 /*
262 * Initialize SCTLR_EL2 context register using Endianness value
263 * taken from the entrypoint attribute.
264 */
265 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL;
266 sctlr_el2 |= SCTLR_EL2_RES1;
267 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2,
268 sctlr_el2);
269
Juan Pablo Conde72e0da12023-02-22 10:09:52 -0600270 if (is_feat_hcx_supported()) {
271 /*
272 * Initialize register HCRX_EL2 with its init value.
273 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a
274 * chance that this can lead to unexpected behavior in lower
275 * ELs that have not been updated since the introduction of
276 * this feature if not properly initialized, especially when
277 * it comes to those bits that enable/disable traps.
278 */
279 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HCRX_EL2,
280 HCRX_EL2_INIT_VAL);
281 }
Juan Pablo Condef7252982023-07-10 16:00:41 -0500282
283 if (is_feat_fgt_supported()) {
284 /*
285 * Initialize HFG*_EL2 registers with a default value so legacy
286 * systems unaware of FEAT_FGT do not get trapped due to their lack
287 * of initialization for this feature.
288 */
289 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGITR_EL2,
290 HFGITR_EL2_INIT_VAL);
291 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGRTR_EL2,
292 HFGRTR_EL2_INIT_VAL);
293 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGWTR_EL2,
294 HFGWTR_EL2_INIT_VAL);
295 }
Zelalem Awekef92c0cb2022-01-31 16:59:42 -0600296#endif /* CTX_INCLUDE_EL2_REGS */
Boyan Karatotev36cebf92023-03-08 11:56:49 +0000297
298 manage_extensions_nonsecure(ctx);
Zelalem Aweke42401112022-01-05 17:12:24 -0600299}
300
Achin Gupta7aea9082014-02-01 07:51:28 +0000301/*******************************************************************************
Zelalem Aweke42401112022-01-05 17:12:24 -0600302 * The following function performs initialization of the cpu_context 'ctx'
303 * for first use that is common to all security states, and sets the
304 * initial entrypoint state as specified by the entry_point_info structure.
Andrew Thoelke4e126072014-06-04 21:10:52 +0100305 *
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000306 * The EE and ST attributes are used to configure the endianness and secure
Soby Mathewb0082d22015-04-09 13:40:55 +0100307 * timer availability for the new execution context.
Andrew Thoelke4e126072014-06-04 21:10:52 +0100308 ******************************************************************************/
Zelalem Aweke42401112022-01-05 17:12:24 -0600309static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep)
Andrew Thoelke4e126072014-06-04 21:10:52 +0100310{
Louis Mayencourt1c819c32020-01-24 13:30:28 +0000311 u_register_t scr_el3;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100312 el3_state_t *state;
313 gp_regs_t *gp_regs;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100314
Boyan Karatotev8ae58f02023-04-20 11:00:50 +0100315 state = get_el3state_ctx(ctx);
316
Andrew Thoelke4e126072014-06-04 21:10:52 +0100317 /* Clear any residual register values from the context */
Douglas Raillarda8954fc2017-01-26 15:54:44 +0000318 zeromem(ctx, sizeof(*ctx));
Andrew Thoelke4e126072014-06-04 21:10:52 +0100319
320 /*
Boyan Karatotevef25db32023-05-23 12:04:00 +0100321 * The lower-EL context is zeroed so that no stale values leak to a world.
322 * It is assumed that an all-zero lower-EL context is good enough for it
323 * to boot correctly. However, there are very few registers where this
324 * is not true and some values need to be recreated.
325 */
326#if CTX_INCLUDE_EL2_REGS
327 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx);
328
329 /*
330 * These bits are set in the gicv3 driver. Losing them (especially the
331 * SRE bit) is problematic for all worlds. Henceforth recreate them.
332 */
333 u_register_t icc_sre_el2 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT |
334 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT;
335 write_ctx_reg(el2_ctx, CTX_ICC_SRE_EL2, icc_sre_el2);
336#endif /* CTX_INCLUDE_EL2_REGS */
337
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +0100338 /* Start with a clean SCR_EL3 copy as all relevant values are set */
339 scr_el3 = SCR_RESET_VAL;
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500340
David Cunadofee86532017-04-13 22:38:29 +0100341 /*
Boyan Karatotev8ae58f02023-04-20 11:00:50 +0100342 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at
343 * EL2, EL1 and EL0 are not trapped to EL3.
344 *
345 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at
346 * EL2, EL1 and EL0 are not trapped to EL3.
347 *
348 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from
349 * both Security states and both Execution states.
350 *
351 * SCR_EL3.SIF: Set to one to disable secure instruction execution from
352 * Non-secure memory.
353 */
354 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT);
355
356 scr_el3 |= SCR_SIF_BIT;
357
358 /*
David Cunadofee86532017-04-13 22:38:29 +0100359 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next
360 * Exception level as specified by SPSR.
361 */
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500362 if (GET_RW(ep->spsr) == MODE_RW_64) {
Andrew Thoelke4e126072014-06-04 21:10:52 +0100363 scr_el3 |= SCR_RW_BIT;
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500364 }
Zelalem Aweke42401112022-01-05 17:12:24 -0600365
David Cunadofee86532017-04-13 22:38:29 +0100366 /*
367 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical
Zelalem Aweke20126002022-04-08 16:48:05 -0500368 * Secure timer registers to EL3, from AArch64 state only, if specified
369 * by the entrypoint attributes. If SEL2 is present and enabled, the ST
370 * bit always behaves as 1 (i.e. secure physical timer register access
371 * is not trapped)
David Cunadofee86532017-04-13 22:38:29 +0100372 */
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500373 if (EP_GET_ST(ep->h.attr) != 0U) {
Andrew Thoelke4e126072014-06-04 21:10:52 +0100374 scr_el3 |= SCR_ST_BIT;
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500375 }
Andrew Thoelke4e126072014-06-04 21:10:52 +0100376
johpow01f91e59f2021-08-04 19:38:18 -0500377 /*
378 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting
379 * SCR_EL3.HXEn.
380 */
Andre Przywara1d8795e2022-11-15 11:45:19 +0000381 if (is_feat_hcx_supported()) {
382 scr_el3 |= SCR_HXEn_BIT;
383 }
johpow01f91e59f2021-08-04 19:38:18 -0500384
Juan Pablo Conde42305f22022-07-12 16:40:29 -0400385 /*
386 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS
387 * registers are trapped to EL3.
388 */
389#if ENABLE_FEAT_RNG_TRAP
390 scr_el3 |= SCR_TRNDR_BIT;
391#endif
392
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000393#if FAULT_INJECTION_SUPPORT
394 /* Enable fault injection from lower ELs */
395 scr_el3 |= SCR_FIEN_BIT;
396#endif
397
Boyan Karatotev8ae58f02023-04-20 11:00:50 +0100398#if CTX_INCLUDE_PAUTH_REGS
399 /*
400 * Enable Pointer Authentication globally for all the worlds.
401 *
402 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs
403 * other than EL3
404 *
405 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other
406 * than EL3
407 */
408 scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
409#endif /* CTX_INCLUDE_PAUTH_REGS */
410
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000411 /*
Mark Brownc37eee72023-03-14 20:13:03 +0000412 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present.
413 */
414 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) {
415 scr_el3 |= SCR_TCR2EN_BIT;
416 }
417
418 /*
Mark Brown293a6612023-03-14 20:48:43 +0000419 * SCR_EL3.PIEN: Enable permission indirection and overlay
420 * registers for AArch64 if present.
421 */
422 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) {
423 scr_el3 |= SCR_PIEN_BIT;
424 }
425
426 /*
Mark Brown326f2952023-03-14 21:33:04 +0000427 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present.
428 */
429 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) {
430 scr_el3 |= SCR_GCSEn_BIT;
431 }
432
433 /*
David Cunadofee86532017-04-13 22:38:29 +0100434 * SCR_EL3.HCE: Enable HVC instructions if next execution state is
435 * AArch64 and next EL is EL2, or if next execution state is AArch32 and
436 * next mode is Hyp.
Jimmy Brissonecc3c672020-04-16 10:47:56 -0500437 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the
438 * same conditions as HVC instructions and when the processor supports
439 * ARMv8.6-FGT.
Jimmy Brisson83573892020-04-16 10:48:02 -0500440 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV)
441 * CNTPOFF_EL2 register under the same conditions as HVC instructions
442 * and when the processor supports ECV.
David Cunadofee86532017-04-13 22:38:29 +0100443 */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000444 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2))
445 || ((GET_RW(ep->spsr) != MODE_RW_64)
446 && (GET_M32(ep->spsr) == MODE32_hyp))) {
David Cunadofee86532017-04-13 22:38:29 +0100447 scr_el3 |= SCR_HCE_BIT;
Jimmy Brissonecc3c672020-04-16 10:47:56 -0500448
Andre Przywarae8920f62022-11-10 14:28:01 +0000449 if (is_feat_fgt_supported()) {
Jimmy Brissonecc3c672020-04-16 10:47:56 -0500450 scr_el3 |= SCR_FGTEN_BIT;
451 }
Jimmy Brisson83573892020-04-16 10:48:02 -0500452
Andre Przywarac3464182022-11-17 17:30:43 +0000453 if (is_feat_ecv_supported()) {
Jimmy Brisson83573892020-04-16 10:48:02 -0500454 scr_el3 |= SCR_ECVEN_BIT;
455 }
David Cunadofee86532017-04-13 22:38:29 +0100456 }
457
johpow013e24c162020-04-22 14:05:13 -0500458 /* Enable WFE trap delay in SCR_EL3 if supported and configured */
Andre Przywara0cf77402023-01-27 12:25:49 +0000459 if (is_feat_twed_supported()) {
460 /* Set delay in SCR_EL3 */
461 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT);
462 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK)
463 << SCR_TWEDEL_SHIFT);
johpow013e24c162020-04-22 14:05:13 -0500464
Andre Przywara0cf77402023-01-27 12:25:49 +0000465 /* Enable WFE delay */
466 scr_el3 |= SCR_TWEDEn_BIT;
467 }
Jayanth Dodderi Chidanandf870cf62023-09-22 15:30:13 +0100468
469#if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2
470 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */
471 if (is_feat_sel2_supported()) {
472 scr_el3 |= SCR_EEL2_BIT;
473 }
474#endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */
johpow013e24c162020-04-22 14:05:13 -0500475
David Cunadofee86532017-04-13 22:38:29 +0100476 /*
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100477 * Populate EL3 state so that we've the right context
478 * before doing ERET
479 */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100480 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
481 write_ctx_reg(state, CTX_ELR_EL3, ep->pc);
482 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr);
483
484 /*
485 * Store the X0-X7 value from the entrypoint into the context
486 * Use memcpy as we are in control of the layout of the structures
487 */
488 gp_regs = get_gpregs_ctx(ctx);
489 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t));
490}
491
492/*******************************************************************************
Zelalem Aweke42401112022-01-05 17:12:24 -0600493 * Context management library initialization routine. This library is used by
494 * runtime services to share pointers to 'cpu_context' structures for secure
495 * non-secure and realm states. Management of the structures and their associated
496 * memory is not done by the context management library e.g. the PSCI service
497 * manages the cpu context used for entry from and exit to the non-secure state.
498 * The Secure payload dispatcher service manages the context(s) corresponding to
499 * the secure state. It also uses this library to get access to the non-secure
500 * state cpu context pointers.
501 * Lastly, this library provides the API to make SP_EL3 point to the cpu context
502 * which will be used for programming an entry into a lower EL. The same context
503 * will be used to save state upon exception entry from that EL.
504 ******************************************************************************/
505void __init cm_init(void)
506{
507 /*
Elyes Haouas2be03c02023-02-13 09:14:48 +0100508 * The context management library has only global data to initialize, but
Zelalem Aweke42401112022-01-05 17:12:24 -0600509 * that will be done when the BSS is zeroed out.
510 */
511}
512
513/*******************************************************************************
514 * This is the high-level function used to initialize the cpu_context 'ctx' for
515 * first use. It performs initializations that are common to all security states
516 * and initializations specific to the security state specified in 'ep'
517 ******************************************************************************/
518void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
519{
520 unsigned int security_state;
521
522 assert(ctx != NULL);
523
524 /*
525 * Perform initializations that are common
526 * to all security states
527 */
528 setup_context_common(ctx, ep);
529
530 security_state = GET_SECURITY_STATE(ep->h.attr);
531
532 /* Perform security state specific initializations */
533 switch (security_state) {
534 case SECURE:
535 setup_secure_context(ctx, ep);
536 break;
537#if ENABLE_RME
538 case REALM:
539 setup_realm_context(ctx, ep);
540 break;
541#endif
542 case NON_SECURE:
543 setup_ns_context(ctx, ep);
544 break;
545 default:
546 ERROR("Invalid security state\n");
547 panic();
548 break;
549 }
550}
551
552/*******************************************************************************
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000553 * Enable architecture extensions for EL3 execution. This function only updates
554 * registers in-place which are expected to either never change or be
555 * overwritten by el3_exit.
556 ******************************************************************************/
557#if IMAGE_BL31
558void cm_manage_extensions_el3(void)
559{
560 if (is_feat_spe_supported()) {
561 spe_init_el3();
Boyan Karatotev7f5dcc72023-03-08 16:29:26 +0000562 }
563
Boyan Karatotev1e966f32023-03-27 17:02:43 +0100564 if (is_feat_amu_supported()) {
565 amu_init_el3();
566 }
567
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +0000568 if (is_feat_sme_supported()) {
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000569 sme_init_el3();
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +0000570 }
Arunachalam Ganapathycac7d162021-07-08 09:35:57 +0100571
Andre Przywara191eff62022-11-17 16:42:09 +0000572 if (is_feat_trbe_supported()) {
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000573 trbe_init_el3();
Andre Przywara191eff62022-11-17 16:42:09 +0000574 }
Manish V Badarkhe20df29c2021-07-02 09:10:56 +0100575
Andre Przywarac97c5512022-11-17 16:42:09 +0000576 if (is_feat_brbe_supported()) {
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000577 brbe_init_el3();
Andre Przywarac97c5512022-11-17 16:42:09 +0000578 }
johpow0181865962022-01-28 17:06:20 -0600579
Andre Przywara06ea44e2022-11-17 17:30:43 +0000580 if (is_feat_trf_supported()) {
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000581 trf_init_el3();
Andre Przywara06ea44e2022-11-17 17:30:43 +0000582 }
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000583
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000584 pmuv3_init_el3();
Boyan Karatotev36cebf92023-03-08 11:56:49 +0000585}
586#endif /* IMAGE_BL31 */
587
Jayanth Dodderi Chidanand56aa3822023-12-11 11:22:02 +0000588/******************************************************************************
589 * Function to initialise the registers with the RESET values in the context
590 * memory, which are maintained per world.
591 ******************************************************************************/
592#if IMAGE_BL31
593void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx)
594{
595 /*
596 * Initialise CPTR_EL3, setting all fields rather than relying on hw.
597 *
598 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers
599 * by Advanced SIMD, floating-point or SVE instructions (if
600 * implemented) do not trap to EL3.
601 *
602 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1,
603 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3.
604 */
605 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT);
Arvind Ram Prakashb5d95592023-11-08 12:28:30 -0600606
Jayanth Dodderi Chidanand56aa3822023-12-11 11:22:02 +0000607 per_world_ctx->ctx_cptr_el3 = cptr_el3;
Arvind Ram Prakashb5d95592023-11-08 12:28:30 -0600608
609 /*
610 * Initialize MPAM3_EL3 to its default reset value
611 *
612 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces
613 * all lower ELn MPAM3_EL3 register access to, trap to EL3
614 */
615
616 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL;
Jayanth Dodderi Chidanand56aa3822023-12-11 11:22:02 +0000617}
618#endif /* IMAGE_BL31 */
619
Boyan Karatotev36cebf92023-03-08 11:56:49 +0000620/*******************************************************************************
Elizabeth Ho4fc00d22023-07-18 14:10:25 +0100621 * Initialise per_world_context for Non-Secure world.
622 * This function enables the architecture extensions, which have same value
623 * across the cores for the non-secure world.
Boyan Karatotev36cebf92023-03-08 11:56:49 +0000624 ******************************************************************************/
Boyan Karatotev36cebf92023-03-08 11:56:49 +0000625#if IMAGE_BL31
Elizabeth Ho4fc00d22023-07-18 14:10:25 +0100626void manage_extensions_nonsecure_per_world(void)
627{
Jayanth Dodderi Chidanand56aa3822023-12-11 11:22:02 +0000628 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]);
629
Elizabeth Ho4fc00d22023-07-18 14:10:25 +0100630 if (is_feat_sme_supported()) {
631 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
Boyan Karatotev1e966f32023-03-27 17:02:43 +0100632 }
633
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000634 if (is_feat_sve_supported()) {
Elizabeth Ho4fc00d22023-07-18 14:10:25 +0100635 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
636 }
637
638 if (is_feat_amu_supported()) {
639 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
640 }
641
642 if (is_feat_sys_reg_trace_supported()) {
643 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000644 }
Arvind Ram Prakashb5d95592023-11-08 12:28:30 -0600645
646 if (is_feat_mpam_supported()) {
647 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
648 }
Elizabeth Ho4fc00d22023-07-18 14:10:25 +0100649}
650#endif /* IMAGE_BL31 */
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000651
Elizabeth Ho4fc00d22023-07-18 14:10:25 +0100652/*******************************************************************************
653 * Initialise per_world_context for Secure world.
654 * This function enables the architecture extensions, which have same value
655 * across the cores for the secure world.
656 ******************************************************************************/
Elizabeth Ho4fc00d22023-07-18 14:10:25 +0100657static void manage_extensions_secure_per_world(void)
658{
659#if IMAGE_BL31
Jayanth Dodderi Chidanand56aa3822023-12-11 11:22:02 +0000660 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
661
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000662 if (is_feat_sme_supported()) {
Elizabeth Ho4fc00d22023-07-18 14:10:25 +0100663
664 if (ENABLE_SME_FOR_SWD) {
665 /*
666 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure
667 * SME, SVE, and FPU/SIMD context properly managed.
668 */
669 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
670 } else {
671 /*
672 * Disable SME, SVE, FPU/SIMD in secure context so non-secure
673 * world can safely use the associated registers.
674 */
675 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
676 }
677 }
678 if (is_feat_sve_supported()) {
679 if (ENABLE_SVE_FOR_SWD) {
680 /*
681 * Enable SVE and FPU in secure context, SPM must ensure
682 * that the SVE and FPU register contexts are properly managed.
683 */
684 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
685 } else {
686 /*
687 * Disable SVE and FPU in secure context so non-secure world
688 * can safely use them.
689 */
690 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
691 }
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000692 }
693
Elizabeth Ho4fc00d22023-07-18 14:10:25 +0100694 /* NS can access this but Secure shouldn't */
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000695 if (is_feat_sys_reg_trace_supported()) {
Elizabeth Ho4fc00d22023-07-18 14:10:25 +0100696 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000697 }
698
Elizabeth Ho4fc00d22023-07-18 14:10:25 +0100699 has_secure_perworld_init = true;
700#endif /* IMAGE_BL31 */
701}
702
703/*******************************************************************************
704 * Enable architecture extensions on first entry to Non-secure world.
705 ******************************************************************************/
706static void manage_extensions_nonsecure(cpu_context_t *ctx)
707{
708#if IMAGE_BL31
709 if (is_feat_amu_supported()) {
710 amu_enable(ctx);
711 }
712
713 if (is_feat_sme_supported()) {
714 sme_enable(ctx);
715 }
716
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000717 pmuv3_enable(ctx);
Boyan Karatotev36cebf92023-03-08 11:56:49 +0000718#endif /* IMAGE_BL31 */
719}
720
Boyan Karatotevfe1cd942023-03-08 17:04:00 +0000721/* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */
722static __unused void enable_pauth_el2(void)
723{
724 u_register_t hcr_el2 = read_hcr_el2();
725 /*
726 * For Armv8.3 pointer authentication feature, disable traps to EL2 when
727 * accessing key registers or using pointer authentication instructions
728 * from lower ELs.
729 */
730 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT);
731
732 write_hcr_el2(hcr_el2);
733}
734
Arvind Ram Prakash8bd27c92023-08-15 16:28:06 -0500735#if INIT_UNUSED_NS_EL2
Boyan Karatotev36cebf92023-03-08 11:56:49 +0000736/*******************************************************************************
737 * Enable architecture extensions in-place at EL2 on first entry to Non-secure
738 * world when EL2 is empty and unused.
739 ******************************************************************************/
740static void manage_extensions_nonsecure_el2_unused(void)
741{
742#if IMAGE_BL31
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000743 if (is_feat_spe_supported()) {
744 spe_init_el2_unused();
745 }
746
Boyan Karatotev1e966f32023-03-27 17:02:43 +0100747 if (is_feat_amu_supported()) {
748 amu_init_el2_unused();
749 }
750
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000751 if (is_feat_mpam_supported()) {
752 mpam_init_el2_unused();
753 }
754
755 if (is_feat_trbe_supported()) {
756 trbe_init_el2_unused();
757 }
758
759 if (is_feat_sys_reg_trace_supported()) {
760 sys_reg_trace_init_el2_unused();
761 }
762
763 if (is_feat_trf_supported()) {
764 trf_init_el2_unused();
765 }
766
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000767 pmuv3_init_el2_unused();
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000768
769 if (is_feat_sve_supported()) {
770 sve_init_el2_unused();
771 }
772
773 if (is_feat_sme_supported()) {
774 sme_init_el2_unused();
775 }
Boyan Karatotevfe1cd942023-03-08 17:04:00 +0000776
777#if ENABLE_PAUTH
778 enable_pauth_el2();
779#endif /* ENABLE_PAUTH */
Boyan Karatotev36cebf92023-03-08 11:56:49 +0000780#endif /* IMAGE_BL31 */
781}
Arvind Ram Prakash8bd27c92023-08-15 16:28:06 -0500782#endif /* INIT_UNUSED_NS_EL2 */
Boyan Karatotev36cebf92023-03-08 11:56:49 +0000783
784/*******************************************************************************
Arunachalam Ganapathycac7d162021-07-08 09:35:57 +0100785 * Enable architecture extensions on first entry to Secure world.
786 ******************************************************************************/
johpow019baade32021-07-08 14:14:00 -0500787static void manage_extensions_secure(cpu_context_t *ctx)
Arunachalam Ganapathycac7d162021-07-08 09:35:57 +0100788{
789#if IMAGE_BL31
Boyan Karatotev7f5dcc72023-03-08 16:29:26 +0000790 if (is_feat_sme_supported()) {
791 if (ENABLE_SME_FOR_SWD) {
792 /*
793 * Enable SME, SVE, FPU/SIMD in secure context, secure manager
794 * must ensure SME, SVE, and FPU/SIMD context properly managed.
795 */
Boyan Karatotev6468d4a2023-02-16 15:12:45 +0000796 sme_init_el3();
Boyan Karatotev7f5dcc72023-03-08 16:29:26 +0000797 sme_enable(ctx);
798 } else {
799 /*
800 * Disable SME, SVE, FPU/SIMD in secure context so non-secure
801 * world can safely use the associated registers.
802 */
803 sme_disable(ctx);
804 }
805 }
johpow019baade32021-07-08 14:14:00 -0500806#endif /* IMAGE_BL31 */
Arunachalam Ganapathycac7d162021-07-08 09:35:57 +0100807}
808
809/*******************************************************************************
Soby Mathewb0082d22015-04-09 13:40:55 +0100810 * The following function initializes the cpu_context for a CPU specified by
811 * its `cpu_idx` for first use, and sets the initial entrypoint state as
812 * specified by the entry_point_info structure.
813 ******************************************************************************/
814void cm_init_context_by_index(unsigned int cpu_idx,
815 const entry_point_info_t *ep)
816{
817 cpu_context_t *ctx;
818 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr));
Antonio Nino Diaz28dce9e2018-05-22 10:09:10 +0100819 cm_setup_context(ctx, ep);
Soby Mathewb0082d22015-04-09 13:40:55 +0100820}
821
822/*******************************************************************************
823 * The following function initializes the cpu_context for the current CPU
824 * for first use, and sets the initial entrypoint state as specified by the
825 * entry_point_info structure.
826 ******************************************************************************/
827void cm_init_my_context(const entry_point_info_t *ep)
828{
829 cpu_context_t *ctx;
830 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr));
Antonio Nino Diaz28dce9e2018-05-22 10:09:10 +0100831 cm_setup_context(ctx, ep);
Soby Mathewb0082d22015-04-09 13:40:55 +0100832}
833
Boyan Karatotevfe1cd942023-03-08 17:04:00 +0000834/* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */
Arvind Ram Prakash8bd27c92023-08-15 16:28:06 -0500835static void init_nonsecure_el2_unused(cpu_context_t *ctx)
Boyan Karatotevfe1cd942023-03-08 17:04:00 +0000836{
Arvind Ram Prakash8bd27c92023-08-15 16:28:06 -0500837#if INIT_UNUSED_NS_EL2
Boyan Karatotevfe1cd942023-03-08 17:04:00 +0000838 u_register_t hcr_el2 = HCR_RESET_VAL;
839 u_register_t mdcr_el2;
840 u_register_t scr_el3;
841
842 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3);
843
844 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */
845 if ((scr_el3 & SCR_RW_BIT) != 0U) {
846 hcr_el2 |= HCR_RW_BIT;
847 }
848
849 write_hcr_el2(hcr_el2);
850
851 /*
852 * Initialise CPTR_EL2 setting all fields rather than relying on the hw.
853 * All fields have architecturally UNKNOWN reset values.
854 */
855 write_cptr_el2(CPTR_EL2_RESET_VAL);
856
857 /*
858 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on
859 * reset and are set to zero except for field(s) listed below.
860 *
861 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of
862 * Non-secure EL0 and EL1 accesses to the physical timer registers.
863 *
864 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of
865 * Non-secure EL0 and EL1 accesses to the physical counter registers.
866 */
867 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT);
868
869 /*
870 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally
871 * UNKNOWN value.
872 */
873 write_cntvoff_el2(0);
874
875 /*
876 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1
877 * respectively.
878 */
879 write_vpidr_el2(read_midr_el1());
880 write_vmpidr_el2(read_mpidr_el1());
881
882 /*
883 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset.
884 *
885 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address
886 * translation is disabled, cache maintenance operations depend on the
887 * VMID.
888 *
889 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is
890 * disabled.
891 */
892 write_vttbr_el2(VTTBR_RESET_VAL &
893 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) |
894 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT)));
895
896 /*
897 * Initialise MDCR_EL2, setting all fields rather than relying on hw.
898 * Some fields are architecturally UNKNOWN on reset.
899 *
900 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System
901 * register accesses to the Debug ROM registers are not trapped to EL2.
902 *
903 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register
904 * accesses to the powerdown debug registers are not trapped to EL2.
905 *
906 * MDCR_EL2.TDA: Set to zero so that System register accesses to the
907 * debug registers do not trap to EL2.
908 *
909 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to
910 * EL2.
911 */
912 mdcr_el2 = MDCR_EL2_RESET_VAL &
913 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT |
914 MDCR_EL2_TDE_BIT);
915
916 write_mdcr_el2(mdcr_el2);
917
918 /*
919 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset.
920 *
921 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or
922 * EL1 accesses to System registers do not trap to EL2.
923 */
924 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK));
925
926 /*
927 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on
928 * reset.
929 *
930 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer
931 * and prevent timer interrupts.
932 */
933 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT));
934
935 manage_extensions_nonsecure_el2_unused();
Arvind Ram Prakash8bd27c92023-08-15 16:28:06 -0500936#endif /* INIT_UNUSED_NS_EL2 */
Boyan Karatotevfe1cd942023-03-08 17:04:00 +0000937}
938
Soby Mathewb0082d22015-04-09 13:40:55 +0100939/*******************************************************************************
Zelalem Awekeb6301e62021-07-09 17:54:30 -0500940 * Prepare the CPU system registers for first entry into realm, secure, or
941 * normal world.
Andrew Thoelke4e126072014-06-04 21:10:52 +0100942 *
943 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized
944 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports
945 * EL2 then EL2 is disabled by configuring all necessary EL2 registers.
946 * For all entries, the EL1 registers are initialized from the cpu_context
947 ******************************************************************************/
948void cm_prepare_el3_exit(uint32_t security_state)
949{
Boyan Karatotevfe1cd942023-03-08 17:04:00 +0000950 u_register_t sctlr_elx, scr_el3;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100951 cpu_context_t *ctx = cm_get_context(security_state);
952
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000953 assert(ctx != NULL);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100954
955 if (security_state == NON_SECURE) {
Juan Pablo Conde72e0da12023-02-22 10:09:52 -0600956 uint64_t el2_implemented = el_implemented(2);
957
Louis Mayencourt1c819c32020-01-24 13:30:28 +0000958 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx),
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000959 CTX_SCR_EL3);
Juan Pablo Conde72e0da12023-02-22 10:09:52 -0600960
961 if (((scr_el3 & SCR_HCE_BIT) != 0U)
962 || (el2_implemented != EL_IMPL_NONE)) {
963 /*
964 * If context is not being used for EL2, initialize
965 * HCRX_EL2 with its init value here.
966 */
967 if (is_feat_hcx_supported()) {
968 write_hcrx_el2(HCRX_EL2_INIT_VAL);
969 }
Juan Pablo Condef7252982023-07-10 16:00:41 -0500970
971 /*
972 * Initialize Fine-grained trap registers introduced
973 * by FEAT_FGT so all traps are initially disabled when
974 * switching to EL2 or a lower EL, preventing undesired
975 * behavior.
976 */
977 if (is_feat_fgt_supported()) {
978 /*
979 * Initialize HFG*_EL2 registers with a default
980 * value so legacy systems unaware of FEAT_FGT
981 * do not get trapped due to their lack of
982 * initialization for this feature.
983 */
984 write_hfgitr_el2(HFGITR_EL2_INIT_VAL);
985 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL);
986 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL);
987 }
Juan Pablo Conde72e0da12023-02-22 10:09:52 -0600988 }
989
Juan Pablo Condef7252982023-07-10 16:00:41 -0500990
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000991 if ((scr_el3 & SCR_HCE_BIT) != 0U) {
Andrew Thoelke4e126072014-06-04 21:10:52 +0100992 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000993 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx),
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000994 CTX_SCTLR_EL1);
Ken Kuang00eac152017-08-23 16:03:29 +0800995 sctlr_elx &= SCTLR_EE_BIT;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100996 sctlr_elx |= SCTLR_EL2_RES1;
Louis Mayencourt78a0aed2019-02-20 12:11:41 +0000997#if ERRATA_A75_764081
998 /*
999 * If workaround of errata 764081 for Cortex-A75 is used
1000 * then set SCTLR_EL2.IESB to enable Implicit Error
1001 * Synchronization Barrier.
1002 */
1003 sctlr_elx |= SCTLR_IESB_BIT;
1004#endif
Andrew Thoelke4e126072014-06-04 21:10:52 +01001005 write_sctlr_el2(sctlr_elx);
Juan Pablo Conde72e0da12023-02-22 10:09:52 -06001006 } else if (el2_implemented != EL_IMPL_NONE) {
Boyan Karatotevfe1cd942023-03-08 17:04:00 +00001007 init_nonsecure_el2_unused(ctx);
Andrew Thoelke4e126072014-06-04 21:10:52 +01001008 }
1009 }
1010
Dimitris Papastamosa7921b92017-10-13 15:27:58 +01001011 cm_el1_sysregs_context_restore(security_state);
1012 cm_set_next_eret_context(security_state);
Andrew Thoelke4e126072014-06-04 21:10:52 +01001013}
1014
Max Shvetsovbdf502d2020-02-25 13:56:19 +00001015#if CTX_INCLUDE_EL2_REGS
Andre Przywara5d6d2ab2022-11-10 14:40:37 +00001016
1017static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx)
1018{
Andre Przywara8258f142023-02-15 15:56:15 +00001019 write_ctx_reg(ctx, CTX_HDFGRTR_EL2, read_hdfgrtr_el2());
1020 if (is_feat_amu_supported()) {
1021 write_ctx_reg(ctx, CTX_HAFGRTR_EL2, read_hafgrtr_el2());
Andre Przywara5d6d2ab2022-11-10 14:40:37 +00001022 }
Andre Przywara8258f142023-02-15 15:56:15 +00001023 write_ctx_reg(ctx, CTX_HDFGWTR_EL2, read_hdfgwtr_el2());
1024 write_ctx_reg(ctx, CTX_HFGITR_EL2, read_hfgitr_el2());
1025 write_ctx_reg(ctx, CTX_HFGRTR_EL2, read_hfgrtr_el2());
1026 write_ctx_reg(ctx, CTX_HFGWTR_EL2, read_hfgwtr_el2());
Andre Przywara5d6d2ab2022-11-10 14:40:37 +00001027}
1028
1029static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx)
1030{
Andre Przywara8258f142023-02-15 15:56:15 +00001031 write_hdfgrtr_el2(read_ctx_reg(ctx, CTX_HDFGRTR_EL2));
1032 if (is_feat_amu_supported()) {
1033 write_hafgrtr_el2(read_ctx_reg(ctx, CTX_HAFGRTR_EL2));
Andre Przywara5d6d2ab2022-11-10 14:40:37 +00001034 }
Andre Przywara8258f142023-02-15 15:56:15 +00001035 write_hdfgwtr_el2(read_ctx_reg(ctx, CTX_HDFGWTR_EL2));
1036 write_hfgitr_el2(read_ctx_reg(ctx, CTX_HFGITR_EL2));
1037 write_hfgrtr_el2(read_ctx_reg(ctx, CTX_HFGRTR_EL2));
1038 write_hfgwtr_el2(read_ctx_reg(ctx, CTX_HFGWTR_EL2));
Andre Przywara5d6d2ab2022-11-10 14:40:37 +00001039}
1040
Arvind Ram Prakash4851b492023-10-06 14:35:21 -05001041#if CTX_INCLUDE_MPAM_REGS
1042
1043static void el2_sysregs_context_save_mpam(mpam_t *ctx)
Andre Przywara84b86532022-11-17 16:42:09 +00001044{
1045 u_register_t mpam_idr = read_mpamidr_el1();
1046
1047 write_ctx_reg(ctx, CTX_MPAM2_EL2, read_mpam2_el2());
1048
1049 /*
1050 * The context registers that we intend to save would be part of the
1051 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1.
1052 */
1053 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) {
1054 return;
1055 }
1056
1057 /*
1058 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if
1059 * MPAMIDR_HAS_HCR_BIT == 1.
1060 */
1061 write_ctx_reg(ctx, CTX_MPAMHCR_EL2, read_mpamhcr_el2());
1062 write_ctx_reg(ctx, CTX_MPAMVPM0_EL2, read_mpamvpm0_el2());
1063 write_ctx_reg(ctx, CTX_MPAMVPMV_EL2, read_mpamvpmv_el2());
1064
1065 /*
1066 * The number of MPAMVPM registers is implementation defined, their
1067 * number is stored in the MPAMIDR_EL1 register.
1068 */
1069 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) {
1070 case 7:
1071 write_ctx_reg(ctx, CTX_MPAMVPM7_EL2, read_mpamvpm7_el2());
1072 __fallthrough;
1073 case 6:
1074 write_ctx_reg(ctx, CTX_MPAMVPM6_EL2, read_mpamvpm6_el2());
1075 __fallthrough;
1076 case 5:
1077 write_ctx_reg(ctx, CTX_MPAMVPM5_EL2, read_mpamvpm5_el2());
1078 __fallthrough;
1079 case 4:
1080 write_ctx_reg(ctx, CTX_MPAMVPM4_EL2, read_mpamvpm4_el2());
1081 __fallthrough;
1082 case 3:
1083 write_ctx_reg(ctx, CTX_MPAMVPM3_EL2, read_mpamvpm3_el2());
1084 __fallthrough;
1085 case 2:
1086 write_ctx_reg(ctx, CTX_MPAMVPM2_EL2, read_mpamvpm2_el2());
1087 __fallthrough;
1088 case 1:
1089 write_ctx_reg(ctx, CTX_MPAMVPM1_EL2, read_mpamvpm1_el2());
1090 break;
1091 }
1092}
1093
Arvind Ram Prakash4851b492023-10-06 14:35:21 -05001094#endif /* CTX_INCLUDE_MPAM_REGS */
1095
1096#if CTX_INCLUDE_MPAM_REGS
1097static void el2_sysregs_context_restore_mpam(mpam_t *ctx)
Andre Przywara84b86532022-11-17 16:42:09 +00001098{
1099 u_register_t mpam_idr = read_mpamidr_el1();
1100
1101 write_mpam2_el2(read_ctx_reg(ctx, CTX_MPAM2_EL2));
1102
1103 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) {
1104 return;
1105 }
1106
1107 write_mpamhcr_el2(read_ctx_reg(ctx, CTX_MPAMHCR_EL2));
1108 write_mpamvpm0_el2(read_ctx_reg(ctx, CTX_MPAMVPM0_EL2));
1109 write_mpamvpmv_el2(read_ctx_reg(ctx, CTX_MPAMVPMV_EL2));
1110
1111 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) {
1112 case 7:
1113 write_mpamvpm7_el2(read_ctx_reg(ctx, CTX_MPAMVPM7_EL2));
1114 __fallthrough;
1115 case 6:
1116 write_mpamvpm6_el2(read_ctx_reg(ctx, CTX_MPAMVPM6_EL2));
1117 __fallthrough;
1118 case 5:
1119 write_mpamvpm5_el2(read_ctx_reg(ctx, CTX_MPAMVPM5_EL2));
1120 __fallthrough;
1121 case 4:
1122 write_mpamvpm4_el2(read_ctx_reg(ctx, CTX_MPAMVPM4_EL2));
1123 __fallthrough;
1124 case 3:
1125 write_mpamvpm3_el2(read_ctx_reg(ctx, CTX_MPAMVPM3_EL2));
1126 __fallthrough;
1127 case 2:
1128 write_mpamvpm2_el2(read_ctx_reg(ctx, CTX_MPAMVPM2_EL2));
1129 __fallthrough;
1130 case 1:
1131 write_mpamvpm1_el2(read_ctx_reg(ctx, CTX_MPAMVPM1_EL2));
1132 break;
1133 }
1134}
Arvind Ram Prakash4851b492023-10-06 14:35:21 -05001135#endif /* CTX_INCLUDE_MPAM_REGS */
Andre Przywara84b86532022-11-17 16:42:09 +00001136
Boyan Karatoteva6989892023-05-15 15:09:16 +01001137/* -----------------------------------------------------
1138 * The following registers are not added:
1139 * AMEVCNTVOFF0<n>_EL2
1140 * AMEVCNTVOFF1<n>_EL2
1141 * ICH_AP0R<n>_EL2
1142 * ICH_AP1R<n>_EL2
1143 * ICH_LR<n>_EL2
1144 * -----------------------------------------------------
1145 */
1146static void el2_sysregs_context_save_common(el2_sysregs_t *ctx)
1147{
1148 write_ctx_reg(ctx, CTX_ACTLR_EL2, read_actlr_el2());
1149 write_ctx_reg(ctx, CTX_AFSR0_EL2, read_afsr0_el2());
1150 write_ctx_reg(ctx, CTX_AFSR1_EL2, read_afsr1_el2());
1151 write_ctx_reg(ctx, CTX_AMAIR_EL2, read_amair_el2());
1152 write_ctx_reg(ctx, CTX_CNTHCTL_EL2, read_cnthctl_el2());
1153 write_ctx_reg(ctx, CTX_CNTVOFF_EL2, read_cntvoff_el2());
1154 write_ctx_reg(ctx, CTX_CPTR_EL2, read_cptr_el2());
1155 if (CTX_INCLUDE_AARCH32_REGS) {
1156 write_ctx_reg(ctx, CTX_DBGVCR32_EL2, read_dbgvcr32_el2());
1157 }
1158 write_ctx_reg(ctx, CTX_ELR_EL2, read_elr_el2());
1159 write_ctx_reg(ctx, CTX_ESR_EL2, read_esr_el2());
1160 write_ctx_reg(ctx, CTX_FAR_EL2, read_far_el2());
1161 write_ctx_reg(ctx, CTX_HACR_EL2, read_hacr_el2());
1162 write_ctx_reg(ctx, CTX_HCR_EL2, read_hcr_el2());
1163 write_ctx_reg(ctx, CTX_HPFAR_EL2, read_hpfar_el2());
1164 write_ctx_reg(ctx, CTX_HSTR_EL2, read_hstr_el2());
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001165
1166 /*
1167 * Set the NS bit to be able to access the ICC_SRE_EL2 register
1168 * TODO: remove with root context
1169 */
1170 u_register_t scr_el3 = read_scr_el3();
1171
1172 write_scr_el3(scr_el3 | SCR_NS_BIT);
1173 isb();
Boyan Karatoteva6989892023-05-15 15:09:16 +01001174 write_ctx_reg(ctx, CTX_ICC_SRE_EL2, read_icc_sre_el2());
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001175
1176 write_scr_el3(scr_el3);
1177 isb();
1178
Boyan Karatoteva6989892023-05-15 15:09:16 +01001179 write_ctx_reg(ctx, CTX_ICH_HCR_EL2, read_ich_hcr_el2());
1180 write_ctx_reg(ctx, CTX_ICH_VMCR_EL2, read_ich_vmcr_el2());
1181 write_ctx_reg(ctx, CTX_MAIR_EL2, read_mair_el2());
1182 write_ctx_reg(ctx, CTX_MDCR_EL2, read_mdcr_el2());
1183 write_ctx_reg(ctx, CTX_SCTLR_EL2, read_sctlr_el2());
1184 write_ctx_reg(ctx, CTX_SPSR_EL2, read_spsr_el2());
1185 write_ctx_reg(ctx, CTX_SP_EL2, read_sp_el2());
1186 write_ctx_reg(ctx, CTX_TCR_EL2, read_tcr_el2());
1187 write_ctx_reg(ctx, CTX_TPIDR_EL2, read_tpidr_el2());
1188 write_ctx_reg(ctx, CTX_TTBR0_EL2, read_ttbr0_el2());
1189 write_ctx_reg(ctx, CTX_VBAR_EL2, read_vbar_el2());
1190 write_ctx_reg(ctx, CTX_VMPIDR_EL2, read_vmpidr_el2());
1191 write_ctx_reg(ctx, CTX_VPIDR_EL2, read_vpidr_el2());
1192 write_ctx_reg(ctx, CTX_VTCR_EL2, read_vtcr_el2());
1193 write_ctx_reg(ctx, CTX_VTTBR_EL2, read_vttbr_el2());
1194}
1195
1196static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx)
1197{
1198 write_actlr_el2(read_ctx_reg(ctx, CTX_ACTLR_EL2));
1199 write_afsr0_el2(read_ctx_reg(ctx, CTX_AFSR0_EL2));
1200 write_afsr1_el2(read_ctx_reg(ctx, CTX_AFSR1_EL2));
1201 write_amair_el2(read_ctx_reg(ctx, CTX_AMAIR_EL2));
1202 write_cnthctl_el2(read_ctx_reg(ctx, CTX_CNTHCTL_EL2));
1203 write_cntvoff_el2(read_ctx_reg(ctx, CTX_CNTVOFF_EL2));
1204 write_cptr_el2(read_ctx_reg(ctx, CTX_CPTR_EL2));
1205 if (CTX_INCLUDE_AARCH32_REGS) {
1206 write_dbgvcr32_el2(read_ctx_reg(ctx, CTX_DBGVCR32_EL2));
1207 }
1208 write_elr_el2(read_ctx_reg(ctx, CTX_ELR_EL2));
1209 write_esr_el2(read_ctx_reg(ctx, CTX_ESR_EL2));
1210 write_far_el2(read_ctx_reg(ctx, CTX_FAR_EL2));
1211 write_hacr_el2(read_ctx_reg(ctx, CTX_HACR_EL2));
1212 write_hcr_el2(read_ctx_reg(ctx, CTX_HCR_EL2));
1213 write_hpfar_el2(read_ctx_reg(ctx, CTX_HPFAR_EL2));
1214 write_hstr_el2(read_ctx_reg(ctx, CTX_HSTR_EL2));
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001215
1216 /*
1217 * Set the NS bit to be able to access the ICC_SRE_EL2 register
1218 * TODO: remove with root context
1219 */
1220 u_register_t scr_el3 = read_scr_el3();
1221
1222 write_scr_el3(scr_el3 | SCR_NS_BIT);
1223 isb();
Boyan Karatoteva6989892023-05-15 15:09:16 +01001224 write_icc_sre_el2(read_ctx_reg(ctx, CTX_ICC_SRE_EL2));
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001225
1226 write_scr_el3(scr_el3);
1227 isb();
1228
Boyan Karatoteva6989892023-05-15 15:09:16 +01001229 write_ich_hcr_el2(read_ctx_reg(ctx, CTX_ICH_HCR_EL2));
1230 write_ich_vmcr_el2(read_ctx_reg(ctx, CTX_ICH_VMCR_EL2));
1231 write_mair_el2(read_ctx_reg(ctx, CTX_MAIR_EL2));
1232 write_mdcr_el2(read_ctx_reg(ctx, CTX_MDCR_EL2));
1233 write_sctlr_el2(read_ctx_reg(ctx, CTX_SCTLR_EL2));
1234 write_spsr_el2(read_ctx_reg(ctx, CTX_SPSR_EL2));
1235 write_sp_el2(read_ctx_reg(ctx, CTX_SP_EL2));
1236 write_tcr_el2(read_ctx_reg(ctx, CTX_TCR_EL2));
1237 write_tpidr_el2(read_ctx_reg(ctx, CTX_TPIDR_EL2));
1238 write_ttbr0_el2(read_ctx_reg(ctx, CTX_TTBR0_EL2));
1239 write_vbar_el2(read_ctx_reg(ctx, CTX_VBAR_EL2));
1240 write_vmpidr_el2(read_ctx_reg(ctx, CTX_VMPIDR_EL2));
1241 write_vpidr_el2(read_ctx_reg(ctx, CTX_VPIDR_EL2));
1242 write_vtcr_el2(read_ctx_reg(ctx, CTX_VTCR_EL2));
1243 write_vttbr_el2(read_ctx_reg(ctx, CTX_VTTBR_EL2));
1244}
1245
Max Shvetsovbdf502d2020-02-25 13:56:19 +00001246/*******************************************************************************
1247 * Save EL2 sysreg context
1248 ******************************************************************************/
1249void cm_el2_sysregs_context_save(uint32_t security_state)
1250{
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001251 cpu_context_t *ctx;
1252 el2_sysregs_t *el2_sysregs_ctx;
Max Shvetsovbdf502d2020-02-25 13:56:19 +00001253
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001254 ctx = cm_get_context(security_state);
1255 assert(ctx != NULL);
Max Shvetsovbdf502d2020-02-25 13:56:19 +00001256
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001257 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx);
Zelalem Aweke5362beb2022-04-04 17:42:48 -05001258
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001259 el2_sysregs_context_save_common(el2_sysregs_ctx);
Govindraj Raja24d3a4e2023-12-21 13:57:49 -06001260
1261 if (is_feat_mte_supported()) {
1262 write_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2, read_tfsr_el2());
1263 }
Arvind Ram Prakash4851b492023-10-06 14:35:21 -05001264
1265#if CTX_INCLUDE_MPAM_REGS
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001266 if (is_feat_mpam_supported()) {
Arvind Ram Prakash4851b492023-10-06 14:35:21 -05001267 mpam_t *mpam_ctx = get_mpam_ctx(ctx);
1268 el2_sysregs_context_save_mpam(mpam_ctx);
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001269 }
Arvind Ram Prakash4851b492023-10-06 14:35:21 -05001270#endif
Andre Przywara5d6d2ab2022-11-10 14:40:37 +00001271
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001272 if (is_feat_fgt_supported()) {
1273 el2_sysregs_context_save_fgt(el2_sysregs_ctx);
1274 }
Andre Przywara5d6d2ab2022-11-10 14:40:37 +00001275
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001276 if (is_feat_ecv_v2_supported()) {
1277 write_ctx_reg(el2_sysregs_ctx, CTX_CNTPOFF_EL2, read_cntpoff_el2());
1278 }
Andre Przywarac3464182022-11-17 17:30:43 +00001279
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001280 if (is_feat_vhe_supported()) {
1281 write_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2, read_contextidr_el2());
1282 write_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2, read_ttbr1_el2());
1283 }
Andre Przywara870627e2023-01-27 12:25:49 +00001284
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001285 if (is_feat_ras_supported()) {
1286 write_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2, read_vdisr_el2());
1287 write_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2, read_vsesr_el2());
1288 }
Andre Przywaraedc449d2023-01-27 14:09:20 +00001289
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001290 if (is_feat_nv2_supported()) {
1291 write_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2, read_vncr_el2());
1292 }
Andre Przywaraedc449d2023-01-27 14:09:20 +00001293
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001294 if (is_feat_trf_supported()) {
1295 write_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2, read_trfcr_el2());
1296 }
Andre Przywara902c9022022-11-17 17:30:43 +00001297
Sona Mathew3b84c962023-10-25 16:48:19 -05001298 /* CSV2 version 2 and above */
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001299 if (is_feat_csv2_2_supported()) {
1300 write_ctx_reg(el2_sysregs_ctx, CTX_SCXTNUM_EL2, read_scxtnum_el2());
1301 }
Andre Przywara902c9022022-11-17 17:30:43 +00001302
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001303 if (is_feat_hcx_supported()) {
1304 write_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2, read_hcrx_el2());
1305 }
1306 if (is_feat_tcr2_supported()) {
1307 write_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2, read_tcr2_el2());
1308 }
1309 if (is_feat_sxpie_supported()) {
1310 write_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2, read_pire0_el2());
1311 write_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2, read_pir_el2());
1312 }
1313 if (is_feat_s2pie_supported()) {
1314 write_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2, read_s2pir_el2());
1315 }
1316 if (is_feat_sxpoe_supported()) {
1317 write_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2, read_por_el2());
1318 }
1319 if (is_feat_gcs_supported()) {
1320 write_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2, read_gcspr_el2());
1321 write_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2, read_gcscr_el2());
Max Shvetsovbdf502d2020-02-25 13:56:19 +00001322 }
1323}
1324
1325/*******************************************************************************
1326 * Restore EL2 sysreg context
1327 ******************************************************************************/
1328void cm_el2_sysregs_context_restore(uint32_t security_state)
1329{
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001330 cpu_context_t *ctx;
1331 el2_sysregs_t *el2_sysregs_ctx;
Max Shvetsovbdf502d2020-02-25 13:56:19 +00001332
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001333 ctx = cm_get_context(security_state);
1334 assert(ctx != NULL);
Max Shvetsovbdf502d2020-02-25 13:56:19 +00001335
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001336 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx);
Zelalem Aweke5362beb2022-04-04 17:42:48 -05001337
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001338 el2_sysregs_context_restore_common(el2_sysregs_ctx);
Govindraj Raja77922ca2024-01-25 08:09:39 -06001339
1340 if (is_feat_mte_supported()) {
1341 write_tfsr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2));
1342 }
Arvind Ram Prakash4851b492023-10-06 14:35:21 -05001343
1344#if CTX_INCLUDE_MPAM_REGS
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001345 if (is_feat_mpam_supported()) {
Arvind Ram Prakash4851b492023-10-06 14:35:21 -05001346 mpam_t *mpam_ctx = get_mpam_ctx(ctx);
1347 el2_sysregs_context_restore_mpam(mpam_ctx);
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001348 }
Arvind Ram Prakash4851b492023-10-06 14:35:21 -05001349#endif
Andre Przywara5d6d2ab2022-11-10 14:40:37 +00001350
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001351 if (is_feat_fgt_supported()) {
1352 el2_sysregs_context_restore_fgt(el2_sysregs_ctx);
1353 }
Andre Przywara5d6d2ab2022-11-10 14:40:37 +00001354
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001355 if (is_feat_ecv_v2_supported()) {
1356 write_cntpoff_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CNTPOFF_EL2));
1357 }
Andre Przywarac3464182022-11-17 17:30:43 +00001358
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001359 if (is_feat_vhe_supported()) {
1360 write_contextidr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2));
1361 write_ttbr1_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2));
1362 }
Andre Przywara870627e2023-01-27 12:25:49 +00001363
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001364 if (is_feat_ras_supported()) {
1365 write_vdisr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2));
1366 write_vsesr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2));
1367 }
Andre Przywaraedc449d2023-01-27 14:09:20 +00001368
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001369 if (is_feat_nv2_supported()) {
1370 write_vncr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2));
1371 }
1372 if (is_feat_trf_supported()) {
1373 write_trfcr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2));
1374 }
Andre Przywara902c9022022-11-17 17:30:43 +00001375
Sona Mathew3b84c962023-10-25 16:48:19 -05001376 /* CSV2 version 2 and above */
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001377 if (is_feat_csv2_2_supported()) {
1378 write_scxtnum_el2(read_ctx_reg(el2_sysregs_ctx, CTX_SCXTNUM_EL2));
1379 }
Andre Przywara902c9022022-11-17 17:30:43 +00001380
Boyan Karatotev2e9e6f02023-05-22 15:53:58 +01001381 if (is_feat_hcx_supported()) {
1382 write_hcrx_el2(read_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2));
1383 }
1384 if (is_feat_tcr2_supported()) {
1385 write_tcr2_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2));
1386 }
1387 if (is_feat_sxpie_supported()) {
1388 write_pire0_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2));
1389 write_pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2));
1390 }
1391 if (is_feat_s2pie_supported()) {
1392 write_s2pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2));
1393 }
1394 if (is_feat_sxpoe_supported()) {
1395 write_por_el2(read_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2));
1396 }
1397 if (is_feat_gcs_supported()) {
1398 write_gcscr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2));
1399 write_gcspr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2));
Max Shvetsovbdf502d2020-02-25 13:56:19 +00001400 }
1401}
1402#endif /* CTX_INCLUDE_EL2_REGS */
1403
Andrew Thoelke4e126072014-06-04 21:10:52 +01001404/*******************************************************************************
Zelalem Awekef92c0cb2022-01-31 16:59:42 -06001405 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS
1406 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly
1407 * updating EL1 and EL2 registers. Otherwise, it calls the generic
1408 * cm_prepare_el3_exit function.
1409 ******************************************************************************/
1410void cm_prepare_el3_exit_ns(void)
1411{
1412#if CTX_INCLUDE_EL2_REGS
Boyan Karatotev1e966f32023-03-27 17:02:43 +01001413#if ENABLE_ASSERTIONS
Zelalem Awekef92c0cb2022-01-31 16:59:42 -06001414 cpu_context_t *ctx = cm_get_context(NON_SECURE);
1415 assert(ctx != NULL);
1416
Zelalem Aweke20126002022-04-08 16:48:05 -05001417 /* Assert that EL2 is used. */
Boyan Karatotev1e966f32023-03-27 17:02:43 +01001418 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3);
Zelalem Aweke20126002022-04-08 16:48:05 -05001419 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) &&
1420 (el_implemented(2U) != EL_IMPL_NONE));
Boyan Karatotev1e966f32023-03-27 17:02:43 +01001421#endif /* ENABLE_ASSERTIONS */
Zelalem Awekef92c0cb2022-01-31 16:59:42 -06001422
Zelalem Awekef92c0cb2022-01-31 16:59:42 -06001423 /* Restore EL2 and EL1 sysreg contexts */
1424 cm_el2_sysregs_context_restore(NON_SECURE);
1425 cm_el1_sysregs_context_restore(NON_SECURE);
1426 cm_set_next_eret_context(NON_SECURE);
1427#else
1428 cm_prepare_el3_exit(NON_SECURE);
1429#endif /* CTX_INCLUDE_EL2_REGS */
1430}
1431
1432/*******************************************************************************
Soby Mathew2ed46e92014-07-04 16:02:26 +01001433 * The next four functions are used by runtime services to save and restore
1434 * EL1 context on the 'cpu_context' structure for the specified security
Achin Gupta7aea9082014-02-01 07:51:28 +00001435 * state.
1436 ******************************************************************************/
Achin Gupta7aea9082014-02-01 07:51:28 +00001437void cm_el1_sysregs_context_save(uint32_t security_state)
1438{
Dan Handleye2712bc2014-04-10 15:37:22 +01001439 cpu_context_t *ctx;
Achin Gupta7aea9082014-02-01 07:51:28 +00001440
Andrew Thoelkea2f65532014-05-14 17:09:32 +01001441 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00001442 assert(ctx != NULL);
Achin Gupta7aea9082014-02-01 07:51:28 +00001443
Max Shvetsovc9e2c922020-02-17 16:15:47 +00001444 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx));
Dimitris Papastamosa7921b92017-10-13 15:27:58 +01001445
1446#if IMAGE_BL31
1447 if (security_state == SECURE)
1448 PUBLISH_EVENT(cm_exited_secure_world);
1449 else
1450 PUBLISH_EVENT(cm_exited_normal_world);
1451#endif
Achin Gupta7aea9082014-02-01 07:51:28 +00001452}
1453
1454void cm_el1_sysregs_context_restore(uint32_t security_state)
1455{
Dan Handleye2712bc2014-04-10 15:37:22 +01001456 cpu_context_t *ctx;
Achin Gupta7aea9082014-02-01 07:51:28 +00001457
Andrew Thoelkea2f65532014-05-14 17:09:32 +01001458 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00001459 assert(ctx != NULL);
Achin Gupta7aea9082014-02-01 07:51:28 +00001460
Max Shvetsovc9e2c922020-02-17 16:15:47 +00001461 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx));
Dimitris Papastamosa7921b92017-10-13 15:27:58 +01001462
1463#if IMAGE_BL31
1464 if (security_state == SECURE)
1465 PUBLISH_EVENT(cm_entering_secure_world);
1466 else
1467 PUBLISH_EVENT(cm_entering_normal_world);
1468#endif
Achin Gupta7aea9082014-02-01 07:51:28 +00001469}
1470
1471/*******************************************************************************
Andrew Thoelke4e126072014-06-04 21:10:52 +01001472 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the
1473 * given security state with the given entrypoint
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001474 ******************************************************************************/
Soby Mathewa0fedc42016-06-16 14:52:04 +01001475void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint)
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001476{
Dan Handleye2712bc2014-04-10 15:37:22 +01001477 cpu_context_t *ctx;
1478 el3_state_t *state;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001479
Andrew Thoelkea2f65532014-05-14 17:09:32 +01001480 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00001481 assert(ctx != NULL);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001482
Andrew Thoelke4e126072014-06-04 21:10:52 +01001483 /* Populate EL3 state so that ERET jumps to the correct entry */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001484 state = get_el3state_ctx(ctx);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001485 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001486}
1487
1488/*******************************************************************************
Andrew Thoelke4e126072014-06-04 21:10:52 +01001489 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context'
1490 * pertaining to the given security state
Achin Gupta607084e2014-02-09 18:24:19 +00001491 ******************************************************************************/
Andrew Thoelke4e126072014-06-04 21:10:52 +01001492void cm_set_elr_spsr_el3(uint32_t security_state,
Soby Mathewa0fedc42016-06-16 14:52:04 +01001493 uintptr_t entrypoint, uint32_t spsr)
Achin Gupta607084e2014-02-09 18:24:19 +00001494{
Dan Handleye2712bc2014-04-10 15:37:22 +01001495 cpu_context_t *ctx;
1496 el3_state_t *state;
Achin Gupta607084e2014-02-09 18:24:19 +00001497
Andrew Thoelkea2f65532014-05-14 17:09:32 +01001498 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00001499 assert(ctx != NULL);
Achin Gupta607084e2014-02-09 18:24:19 +00001500
1501 /* Populate EL3 state so that ERET jumps to the correct entry */
1502 state = get_el3state_ctx(ctx);
1503 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
Andrew Thoelke4e126072014-06-04 21:10:52 +01001504 write_ctx_reg(state, CTX_SPSR_EL3, spsr);
Achin Gupta607084e2014-02-09 18:24:19 +00001505}
1506
1507/*******************************************************************************
Achin Gupta27b895e2014-05-04 18:38:28 +01001508 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context'
1509 * pertaining to the given security state using the value and bit position
1510 * specified in the parameters. It preserves all other bits.
1511 ******************************************************************************/
1512void cm_write_scr_el3_bit(uint32_t security_state,
1513 uint32_t bit_pos,
1514 uint32_t value)
1515{
1516 cpu_context_t *ctx;
1517 el3_state_t *state;
Louis Mayencourt1c819c32020-01-24 13:30:28 +00001518 u_register_t scr_el3;
Achin Gupta27b895e2014-05-04 18:38:28 +01001519
Andrew Thoelkea2f65532014-05-14 17:09:32 +01001520 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00001521 assert(ctx != NULL);
Achin Gupta27b895e2014-05-04 18:38:28 +01001522
1523 /* Ensure that the bit position is a valid one */
Jimmy Brissoned202072020-08-04 16:18:52 -05001524 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U);
Achin Gupta27b895e2014-05-04 18:38:28 +01001525
1526 /* Ensure that the 'value' is only a bit wide */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00001527 assert(value <= 1U);
Achin Gupta27b895e2014-05-04 18:38:28 +01001528
1529 /*
1530 * Get the SCR_EL3 value from the cpu context, clear the desired bit
1531 * and set it to its new value.
1532 */
1533 state = get_el3state_ctx(ctx);
Louis Mayencourt1c819c32020-01-24 13:30:28 +00001534 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
Jimmy Brissoned202072020-08-04 16:18:52 -05001535 scr_el3 &= ~(1UL << bit_pos);
Louis Mayencourt1c819c32020-01-24 13:30:28 +00001536 scr_el3 |= (u_register_t)value << bit_pos;
Achin Gupta27b895e2014-05-04 18:38:28 +01001537 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
1538}
1539
1540/*******************************************************************************
1541 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the
1542 * given security state.
1543 ******************************************************************************/
Louis Mayencourt1c819c32020-01-24 13:30:28 +00001544u_register_t cm_get_scr_el3(uint32_t security_state)
Achin Gupta27b895e2014-05-04 18:38:28 +01001545{
1546 cpu_context_t *ctx;
1547 el3_state_t *state;
1548
Andrew Thoelkea2f65532014-05-14 17:09:32 +01001549 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00001550 assert(ctx != NULL);
Achin Gupta27b895e2014-05-04 18:38:28 +01001551
1552 /* Populate EL3 state so that ERET jumps to the correct entry */
1553 state = get_el3state_ctx(ctx);
Louis Mayencourt1c819c32020-01-24 13:30:28 +00001554 return read_ctx_reg(state, CTX_SCR_EL3);
Achin Gupta27b895e2014-05-04 18:38:28 +01001555}
1556
1557/*******************************************************************************
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001558 * This function is used to program the context that's used for exception
1559 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for
1560 * the required security state
Achin Gupta7aea9082014-02-01 07:51:28 +00001561 ******************************************************************************/
1562void cm_set_next_eret_context(uint32_t security_state)
1563{
Dan Handleye2712bc2014-04-10 15:37:22 +01001564 cpu_context_t *ctx;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +00001565
Andrew Thoelkea2f65532014-05-14 17:09:32 +01001566 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00001567 assert(ctx != NULL);
Achin Gupta7aea9082014-02-01 07:51:28 +00001568
Andrew Thoelke4e126072014-06-04 21:10:52 +01001569 cm_set_next_context(ctx);
Achin Gupta7aea9082014-02-01 07:51:28 +00001570}