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Paul Beesleyfc9ee362019-03-07 15:47:15 +00001User Guide
2==========
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
Dan Handley610e7e12018-03-01 18:44:00 +00004This document describes how to build Trusted Firmware-A (TF-A) and run it with a
Douglas Raillardd7c21b72017-06-28 15:23:03 +01005tested set of other software components using defined configurations on the Juno
Dan Handley610e7e12018-03-01 18:44:00 +00006Arm development platform and Arm Fixed Virtual Platform (FVP) models. It is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01007possible to use other software components, configurations and platforms but that
8is outside the scope of this document.
9
10This document assumes that the reader has previous experience running a fully
11bootable Linux software stack on Juno or FVP using the prebuilt binaries and
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010012filesystems provided by `Linaro`_. Further information may be found in the
13`Linaro instructions`_. It also assumes that the user understands the role of
14the different software components required to boot a Linux system:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010015
16- Specific firmware images required by the platform (e.g. SCP firmware on Juno)
17- Normal world bootloader (e.g. UEFI or U-Boot)
18- Device tree
19- Linux kernel image
20- Root filesystem
21
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010022This document also assumes that the user is familiar with the `FVP models`_ and
Douglas Raillardd7c21b72017-06-28 15:23:03 +010023the different command line options available to launch the model.
24
25This document should be used in conjunction with the `Firmware Design`_.
26
27Host machine requirements
28-------------------------
29
30The minimum recommended machine specification for building the software and
31running the FVP models is a dual-core processor running at 2GHz with 12GB of
32RAM. For best performance, use a machine with a quad-core processor running at
332.6GHz with 16GB of RAM.
34
Joel Huttonfe027712018-03-19 11:59:57 +000035The software has been tested on Ubuntu 16.04 LTS (64-bit). Packages used for
Douglas Raillardd7c21b72017-06-28 15:23:03 +010036building the software were installed from that distribution unless otherwise
37specified.
38
39The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE,
David Cunadob2de0992017-06-29 12:01:33 +010040Cygwin, and Msys (MinGW) shells, using version 5.3.1 of the GNU toolchain.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010041
42Tools
43-----
44
Dan Handley610e7e12018-03-01 18:44:00 +000045Install the required packages to build TF-A with the following command:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010046
Paul Beesley493e3492019-03-13 15:11:04 +000047.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +010048
Sathees Balya2d0aeb02018-07-10 14:46:51 +010049 sudo apt-get install device-tree-compiler build-essential gcc make git libssl-dev
Douglas Raillardd7c21b72017-06-28 15:23:03 +010050
David Cunado05845bf2017-12-19 16:33:25 +000051TF-A has been tested with Linaro Release 18.04.
David Cunadob2de0992017-06-29 12:01:33 +010052
Louis Mayencourt545a9ed2019-03-08 15:35:40 +000053Download and install the AArch32 or AArch64 little-endian GCC cross compiler. If
54you would like to use the latest features available, download GCC 8.2-2019.01
55compiler from `arm Developer page`_. Otherwise, the `Linaro Release Notes`_
56documents which version of the compiler to use for a given Linaro Release. Also,
57these `Linaro instructions`_ provide further guidance and a script, which can be
58used to download Linaro deliverables automatically.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010059
Roberto Vargas0489bc02018-04-16 15:43:26 +010060Optionally, TF-A can be built using clang version 4.0 or newer or Arm
61Compiler 6. See instructions below on how to switch the default compiler.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010062
63In addition, the following optional packages and tools may be needed:
64
Sathees Balya017a67e2018-08-17 10:22:01 +010065- ``device-tree-compiler`` (dtc) package if you need to rebuild the Flattened Device
66 Tree (FDT) source files (``.dts`` files) provided with this software. The
67 version of dtc must be 1.4.6 or above.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010068
Dan Handley610e7e12018-03-01 18:44:00 +000069- For debugging, Arm `Development Studio 5 (DS-5)`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010070
Antonio Nino Diazb5d68092017-05-23 11:49:22 +010071- To create and modify the diagram files included in the documentation, `Dia`_.
72 This tool can be found in most Linux distributions. Inkscape is needed to
Antonio Nino Diaz80914a82018-08-08 16:28:43 +010073 generate the actual \*.png files.
Antonio Nino Diazb5d68092017-05-23 11:49:22 +010074
Dan Handley610e7e12018-03-01 18:44:00 +000075Getting the TF-A source code
76----------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +010077
Louis Mayencourt72ef3d42019-03-22 11:47:22 +000078Clone the repository from the Gerrit server. The project details may be found
79on the `arm-trusted-firmware-a project page`_. We recommend the "`Clone with
80commit-msg hook`" clone method, which will setup the git commit hook that
81automatically generates and inserts appropriate `Change-Id:` lines in your
82commit messages.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010083
Paul Beesley8b4bdeb2019-01-21 12:06:24 +000084Checking source code style
85~~~~~~~~~~~~~~~~~~~~~~~~~~
86
87Trusted Firmware follows the `Linux Coding Style`_ . When making changes to the
88source, for submission to the project, the source must be in compliance with
89this style guide.
90
91Additional, project-specific guidelines are defined in the `Trusted Firmware-A
92Coding Guidelines`_ document.
93
94To assist with coding style compliance, the project Makefile contains two
95targets which both utilise the `checkpatch.pl` script that ships with the Linux
96source tree. The project also defines certain *checkpatch* options in the
97``.checkpatch.conf`` file in the top-level directory.
98
Paul Beesleyba3ed402019-03-13 16:20:44 +000099.. note::
100 Checkpatch errors will gate upstream merging of pull requests.
101 Checkpatch warnings will not gate merging but should be reviewed and fixed if
102 possible.
Paul Beesley8b4bdeb2019-01-21 12:06:24 +0000103
104To check the entire source tree, you must first download copies of
105``checkpatch.pl``, ``spelling.txt`` and ``const_structs.checkpatch`` available
106in the `Linux master tree`_ *scripts* directory, then set the ``CHECKPATCH``
107environment variable to point to ``checkpatch.pl`` (with the other 2 files in
108the same directory) and build the `checkcodebase` target:
109
Paul Beesley493e3492019-03-13 15:11:04 +0000110.. code:: shell
Paul Beesley8b4bdeb2019-01-21 12:06:24 +0000111
112 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkcodebase
113
114To just check the style on the files that differ between your local branch and
115the remote master, use:
116
Paul Beesley493e3492019-03-13 15:11:04 +0000117.. code:: shell
Paul Beesley8b4bdeb2019-01-21 12:06:24 +0000118
119 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkpatch
120
121If you wish to check your patch against something other than the remote master,
122set the ``BASE_COMMIT`` variable to your desired branch. By default, ``BASE_COMMIT``
123is set to ``origin/master``.
124
Dan Handley610e7e12018-03-01 18:44:00 +0000125Building TF-A
126-------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100127
Dan Handley610e7e12018-03-01 18:44:00 +0000128- Before building TF-A, the environment variable ``CROSS_COMPILE`` must point
129 to the Linaro cross compiler.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100130
131 For AArch64:
132
Paul Beesley493e3492019-03-13 15:11:04 +0000133 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100134
135 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
136
137 For AArch32:
138
Paul Beesley493e3492019-03-13 15:11:04 +0000139 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100140
141 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
142
Roberto Vargas07b1e242018-04-23 08:38:12 +0100143 It is possible to build TF-A using Clang or Arm Compiler 6. To do so
144 ``CC`` needs to point to the clang or armclang binary, which will
145 also select the clang or armclang assembler. Be aware that the
146 GNU linker is used by default. In case of being needed the linker
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000147 can be overridden using the ``LD`` variable. Clang linker version 6 is
Roberto Vargas07b1e242018-04-23 08:38:12 +0100148 known to work with TF-A.
149
150 In both cases ``CROSS_COMPILE`` should be set as described above.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100151
Dan Handley610e7e12018-03-01 18:44:00 +0000152 Arm Compiler 6 will be selected when the base name of the path assigned
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100153 to ``CC`` matches the string 'armclang'.
154
Dan Handley610e7e12018-03-01 18:44:00 +0000155 For AArch64 using Arm Compiler 6:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100156
Paul Beesley493e3492019-03-13 15:11:04 +0000157 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100158
159 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
160 make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
161
162 Clang will be selected when the base name of the path assigned to ``CC``
163 contains the string 'clang'. This is to allow both clang and clang-X.Y
164 to work.
165
166 For AArch64 using clang:
167
Paul Beesley493e3492019-03-13 15:11:04 +0000168 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100169
170 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
171 make CC=<path-to-clang>/bin/clang PLAT=<platform> all
172
Dan Handley610e7e12018-03-01 18:44:00 +0000173- Change to the root directory of the TF-A source tree and build.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100174
175 For AArch64:
176
Paul Beesley493e3492019-03-13 15:11:04 +0000177 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100178
179 make PLAT=<platform> all
180
181 For AArch32:
182
Paul Beesley493e3492019-03-13 15:11:04 +0000183 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100184
185 make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all
186
187 Notes:
188
189 - If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the
190 `Summary of build options`_ for more information on available build
191 options.
192
193 - (AArch32 only) Currently only ``PLAT=fvp`` is supported.
194
195 - (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100196 corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp_min, is
Dan Handley610e7e12018-03-01 18:44:00 +0000197 provided by TF-A to demonstrate how PSCI Library can be integrated with
198 an AArch32 EL3 Runtime Software. Some AArch32 EL3 Runtime Software may
199 include other runtime services, for example Trusted OS services. A guide
200 to integrate PSCI library with AArch32 EL3 Runtime Software can be found
201 `here`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100202
203 - (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32
204 image, is not compiled in by default. Refer to the
205 `Building the Test Secure Payload`_ section below.
206
207 - By default this produces a release version of the build. To produce a
208 debug version instead, refer to the "Debugging options" section below.
209
210 - The build process creates products in a ``build`` directory tree, building
211 the objects and binaries for each boot loader stage in separate
212 sub-directories. The following boot loader binary files are created
213 from the corresponding ELF files:
214
215 - ``build/<platform>/<build-type>/bl1.bin``
216 - ``build/<platform>/<build-type>/bl2.bin``
217 - ``build/<platform>/<build-type>/bl31.bin`` (AArch64 only)
218 - ``build/<platform>/<build-type>/bl32.bin`` (mandatory for AArch32)
219
220 where ``<platform>`` is the name of the chosen platform and ``<build-type>``
221 is either ``debug`` or ``release``. The actual number of images might differ
222 depending on the platform.
223
224- Build products for a specific build variant can be removed using:
225
Paul Beesley493e3492019-03-13 15:11:04 +0000226 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100227
228 make DEBUG=<D> PLAT=<platform> clean
229
230 ... where ``<D>`` is ``0`` or ``1``, as specified when building.
231
232 The build tree can be removed completely using:
233
Paul Beesley493e3492019-03-13 15:11:04 +0000234 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100235
236 make realclean
237
238Summary of build options
239~~~~~~~~~~~~~~~~~~~~~~~~
240
Dan Handley610e7e12018-03-01 18:44:00 +0000241The TF-A build system supports the following build options. Unless mentioned
242otherwise, these options are expected to be specified at the build command
243line and are not to be modified in any component makefiles. Note that the
244build system doesn't track dependency for build options. Therefore, if any of
245the build options are changed from a previous build, a clean build must be
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100246performed.
247
248Common build options
249^^^^^^^^^^^^^^^^^^^^
250
Antonio Nino Diaz80914a82018-08-08 16:28:43 +0100251- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the
252 compiler should use. Valid values are T32 and A32. It defaults to T32 due to
253 code having a smaller resulting size.
254
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100255- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
256 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
257 directory containing the SP source, relative to the ``bl32/``; the directory
258 is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
259
Dan Handley610e7e12018-03-01 18:44:00 +0000260- ``ARCH`` : Choose the target build architecture for TF-A. It can take either
261 ``aarch64`` or ``aarch32`` as values. By default, it is defined to
262 ``aarch64``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100263
Dan Handley610e7e12018-03-01 18:44:00 +0000264- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when
265 compiling TF-A. Its value must be numeric, and defaults to 8 . See also,
266 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in
267 `Firmware Design`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100268
Dan Handley610e7e12018-03-01 18:44:00 +0000269- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when
270 compiling TF-A. Its value must be a numeric, and defaults to 0. See also,
271 *Armv8 Architecture Extensions* in `Firmware Design`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100272
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100273- ``BL2``: This is an optional build option which specifies the path to BL2
Dan Handley610e7e12018-03-01 18:44:00 +0000274 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be
275 built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100276
277- ``BL2U``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000278 BL2U image. In this case, the BL2U in TF-A will not be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100279
John Tsichritzisee10e792018-06-06 09:38:10 +0100280- ``BL2_AT_EL3``: This is an optional build option that enables the use of
Roberto Vargasb1584272017-11-20 13:36:10 +0000281 BL2 at EL3 execution level.
282
John Tsichritzisee10e792018-06-06 09:38:10 +0100283- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000284 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize
285 the RW sections in RAM, while leaving the RO sections in place. This option
286 enable this use-case. For now, this option is only supported when BL2_AT_EL3
287 is set to '1'.
288
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100289- ``BL31``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000290 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not
291 be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100292
293- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
294 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
295 this file name will be used to save the key.
296
297- ``BL32``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000298 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not
299 be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100300
John Tsichritzisee10e792018-06-06 09:38:10 +0100301- ``BL32_EXTRA1``: This is an optional build option which specifies the path to
Summer Qin80726782017-04-20 16:28:39 +0100302 Trusted OS Extra1 image for the ``fip`` target.
303
John Tsichritzisee10e792018-06-06 09:38:10 +0100304- ``BL32_EXTRA2``: This is an optional build option which specifies the path to
Summer Qin80726782017-04-20 16:28:39 +0100305 Trusted OS Extra2 image for the ``fip`` target.
306
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100307- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
308 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
309 this file name will be used to save the key.
310
311- ``BL33``: Path to BL33 image in the host file system. This is mandatory for
Dan Handley610e7e12018-03-01 18:44:00 +0000312 ``fip`` target in case TF-A BL2 is used.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100313
314- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
315 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
316 this file name will be used to save the key.
317
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100318- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication
319 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves.
320 If enabled, it is needed to use a compiler that supports the option
321 ``-mbranch-protection``. Selects the branch protection features to use:
322- 0: Default value turns off all types of branch protection
323- 1: Enables all types of branch protection features
324- 2: Return address signing to its standard level
325- 3: Extend the signing to include leaf functions
326
327 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options
328 and resulting PAuth/BTI features.
329
330 +-------+--------------+-------+-----+
331 | Value | GCC option | PAuth | BTI |
332 +=======+==============+=======+=====+
333 | 0 | none | N | N |
334 +-------+--------------+-------+-----+
335 | 1 | standard | Y | Y |
336 +-------+--------------+-------+-----+
337 | 2 | pac-ret | Y | N |
338 +-------+--------------+-------+-----+
339 | 3 | pac-ret+leaf | Y | N |
340 +-------+--------------+-------+-----+
341
342 This option defaults to 0 and this is an experimental feature.
343 Note that Pointer Authentication is enabled for Non-secure world
344 irrespective of the value of this option if the CPU supports it.
345
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100346- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
347 compilation of each build. It must be set to a C string (including quotes
348 where applicable). Defaults to a string that contains the time and date of
349 the compilation.
350
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100351- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A
Dan Handley610e7e12018-03-01 18:44:00 +0000352 build to be uniquely identified. Defaults to the current git commit id.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100353
354- ``CFLAGS``: Extra user options appended on the compiler's command line in
355 addition to the options set by the build system.
356
357- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
358 release several CPUs out of reset. It can take either 0 (several CPUs may be
359 brought up) or 1 (only one CPU will ever be brought up during cold reset).
360 Default is 0. If the platform always brings up a single CPU, there is no
361 need to distinguish between primary and secondary CPUs and the boot path can
362 be optimised. The ``plat_is_my_cpu_primary()`` and
363 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
364 to be implemented in this case.
365
366- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
367 register state when an unexpected exception occurs during execution of
368 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
369 this is only enabled for a debug build of the firmware.
370
371- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
372 certificate generation tool to create new keys in case no valid keys are
373 present or specified. Allowed options are '0' or '1'. Default is '1'.
374
375- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
376 the AArch32 system registers to be included when saving and restoring the
377 CPU context. The option must be set to 0 for AArch64-only platforms (that
378 is on hardware that does not implement AArch32, or at least not at EL1 and
379 higher ELs). Default value is 1.
380
381- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
382 registers to be included when saving and restoring the CPU context. Default
383 is 0.
384
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100385- ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables
386 Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth
387 registers to be included when saving and restoring the CPU context as
388 part of world switch. Default value is 0 and this is an experimental feature.
389 Note that Pointer Authentication is enabled for Non-secure world irrespective
390 of the value of this flag if the CPU supports it.
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000391
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100392- ``DEBUG``: Chooses between a debug and release build. It can take either 0
393 (release) or 1 (debug) as values. 0 is the default.
394
Christoph Müllner4f088e42019-04-24 09:45:30 +0200395- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation
396 of the binary image. If set to 1, then only the ELF image is built.
397 0 is the default.
398
John Tsichritzisee10e792018-06-06 09:38:10 +0100399- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted
400 Board Boot authentication at runtime. This option is meant to be enabled only
Roberto Vargas025946a2018-09-24 17:20:48 +0100401 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this
402 flag has to be enabled. 0 is the default.
Soby Mathew9fe88042018-03-26 12:43:37 +0100403
Ambroise Vincentba0442d2019-06-06 10:26:41 +0100404- ``E``: Boolean option to make warnings into errors. Default is 1.
405
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100406- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
407 the normal boot flow. It must specify the entry point address of the EL3
408 payload. Please refer to the "Booting an EL3 payload" section for more
409 details.
410
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100411- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions.
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100412 This is an optional architectural feature available on v8.4 onwards. Some
413 v8.2 implementations also implement an AMU and this option can be used to
414 enable this feature on those systems as well. Default is 0.
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100415
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100416- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
417 are compiled out. For debug builds, this option defaults to 1, and calls to
418 ``assert()`` are left in place. For release builds, this option defaults to 0
419 and calls to ``assert()`` function are compiled out. This option can be set
420 independently of ``DEBUG``. It can also be used to hide any auxiliary code
421 that is only required for the assertion and does not fit in the assertion
422 itself.
423
Douglas Raillard77414632018-08-21 12:54:45 +0100424- ``ENABLE_BACKTRACE``: This option controls whether to enables backtrace
425 dumps or not. It is supported in both AArch64 and AArch32. However, in
426 AArch32 the format of the frame records are not defined in the AAPCS and they
427 are defined by the implementation. This implementation of backtrace only
428 supports the format used by GCC when T32 interworking is disabled. For this
429 reason enabling this option in AArch32 will force the compiler to only
430 generate A32 code. This option is enabled by default only in AArch64 debug
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000431 builds, but this behaviour can be overridden in each platform's Makefile or
432 in the build command line.
Douglas Raillard77414632018-08-21 12:54:45 +0100433
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100434- ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM
435 feature. MPAM is an optional Armv8.4 extension that enables various memory
436 system components and resources to define partitions; software running at
437 various ELs can assign themselves to desired partition to control their
438 performance aspects.
439
440 When this option is set to ``1``, EL3 allows lower ELs to access their own
441 MPAM registers without trapping into EL3. This option doesn't make use of
442 partitioning in EL3, however. Platform initialisation code should configure
443 and use partitions in EL3 as required. This option defaults to ``0``.
444
Soby Mathew078f1a42018-08-28 11:13:55 +0100445- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE)
446 support within generic code in TF-A. This option is currently only supported
447 in BL31. Default is 0.
448
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100449- ``ENABLE_PMF``: Boolean option to enable support for optional Performance
450 Measurement Framework(PMF). Default is 0.
451
452- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
453 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
454 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
455 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
456 software.
457
458- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
Dan Handley610e7e12018-03-01 18:44:00 +0000459 instrumentation which injects timestamp collection points into TF-A to
460 allow runtime performance to be measured. Currently, only PSCI is
461 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option
462 as well. Default is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100463
Jeenu Viswambharand73dcf32017-07-19 13:52:12 +0100464- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100465 extensions. This is an optional architectural feature for AArch64.
466 The default is 1 but is automatically disabled when the target architecture
467 is AArch32.
Jeenu Viswambharand73dcf32017-07-19 13:52:12 +0100468
Sandrine Bailleux604f0a42018-09-20 12:44:39 +0200469- ``ENABLE_SPM`` : Boolean option to enable the Secure Partition Manager (SPM).
470 Refer to the `Secure Partition Manager Design guide`_ for more details about
471 this feature. Default is 0.
472
David Cunadoce88eee2017-10-20 11:30:57 +0100473- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
474 (SVE) for the Non-secure world only. SVE is an optional architectural feature
475 for AArch64. Note that when SVE is enabled for the Non-secure world, access
476 to SIMD and floating-point functionality from the Secure world is disabled.
477 This is to avoid corruption of the Non-secure world data in the Z-registers
478 which are aliased by the SIMD and FP registers. The build option is not
479 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
480 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to
481 1. The default is 1 but is automatically disabled when the target
482 architecture is AArch32.
483
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100484- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
Louis Mayencourt768bf0c2019-03-26 16:59:26 +0000485 checks in GCC. Allowed values are "all", "strong", "default" and "none". The
486 default value is set to "none". "strong" is the recommended stack protection
487 level if this feature is desired. "none" disables the stack protection. For
488 all values other than "none", the ``plat_get_stack_protector_canary()``
489 platform hook needs to be implemented. The value is passed as the last
490 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100491
492- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
493 deprecated platform APIs, helper functions or drivers within Trusted
494 Firmware as error. It can take the value 1 (flag the use of deprecated
495 APIs as error) or 0. The default is 0.
496
Jeenu Viswambharan10a67272017-09-22 08:32:10 +0100497- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
498 targeted at EL3. When set ``0`` (default), no exceptions are expected or
499 handled at EL3, and a panic will result. This is supported only for AArch64
500 builds.
501
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000502- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000503 injection from lower ELs, and this build option enables lower ELs to use
504 Error Records accessed via System Registers to inject faults. This is
505 applicable only to AArch64 builds.
506
507 This feature is intended for testing purposes only, and is advisable to keep
508 disabled for production images.
509
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100510- ``FIP_NAME``: This is an optional build option which specifies the FIP
511 filename for the ``fip`` target. Default is ``fip.bin``.
512
513- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
514 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
515
516- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
517 tool to create certificates as per the Chain of Trust described in
518 `Trusted Board Boot`_. The build system then calls ``fiptool`` to
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100519 include the certificates in the FIP and FWU_FIP. Default value is '0'.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100520
521 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
522 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
523 the corresponding certificates, and to include those certificates in the
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100524 FIP and FWU_FIP.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100525
526 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
527 images will not include support for Trusted Board Boot. The FIP will still
528 include the corresponding certificates. This FIP can be used to verify the
529 Chain of Trust on the host machine through other mechanisms.
530
531 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100532 images will include support for Trusted Board Boot, but the FIP and FWU_FIP
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100533 will not include the corresponding certificates, causing a boot failure.
534
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100535- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
536 inherent support for specific EL3 type interrupts. Setting this build option
537 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both
538 by `platform abstraction layer`__ and `Interrupt Management Framework`__.
539 This allows GICv2 platforms to enable features requiring EL3 interrupt type.
540 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and
541 the Secure Payload interrupts needs to be synchronously handed over to Secure
542 EL1 for handling. The default value of this option is ``0``, which means the
543 Group 0 interrupts are assumed to be handled by Secure EL1.
544
545 .. __: `platform-interrupt-controller-API.rst`
546 .. __: `interrupt-framework-design.rst`
547
Julius Wernerc51a2ec2018-08-28 14:45:43 -0700548- ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError
549 Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to
550 ``0`` (default), these exceptions will be trapped in the current exception
551 level (or in EL1 if the current exception level is EL0).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100552
Dan Handley610e7e12018-03-01 18:44:00 +0000553- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100554 software operations are required for CPUs to enter and exit coherency.
John Tsichritzisfe6df392019-03-19 17:20:52 +0000555 However, newer systems exist where CPUs' entry to and exit from coherency
556 is managed in hardware. Such systems require software to only initiate these
557 operations, and the rest is managed in hardware, minimizing active software
558 management. In such systems, this boolean option enables TF-A to carry out
559 build and run-time optimizations during boot and power management operations.
560 This option defaults to 0 and if it is enabled, then it implies
561 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
562
563 If this flag is disabled while the platform which TF-A is compiled for
564 includes cores that manage coherency in hardware, then a compilation error is
565 generated. This is based on the fact that a system cannot have, at the same
566 time, cores that manage coherency in hardware and cores that don't. In other
567 words, a platform cannot have, at the same time, cores that require
568 ``HW_ASSISTED_COHERENCY=1`` and cores that require
569 ``HW_ASSISTED_COHERENCY=0``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100570
Jeenu Viswambharane834ee12018-04-27 15:17:03 +0100571 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of
572 translation library (xlat tables v2) must be used; version 1 of translation
573 library is not supported.
574
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100575- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3
576 runtime software in AArch32 mode, which is required to run AArch32 on Juno.
577 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in
578 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
579 images.
580
Soby Mathew13b16052017-08-31 11:49:32 +0100581- ``KEY_ALG``: This build flag enables the user to select the algorithm to be
582 used for generating the PKCS keys and subsequent signing of the certificate.
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +0000583 It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option
584 ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR
585 compliant and is retained only for compatibility. The default value of this
586 flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
Soby Mathew13b16052017-08-31 11:49:32 +0100587
Qixiang Xu1a1f2912017-11-09 13:56:29 +0800588- ``HASH_ALG``: This build flag enables the user to select the secure hash
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +0000589 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``.
Qixiang Xu1a1f2912017-11-09 13:56:29 +0800590 The default value of this flag is ``sha256``.
591
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100592- ``LDFLAGS``: Extra user options appended to the linkers' command line in
593 addition to the one set by the build system.
594
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100595- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
596 output compiled into the build. This should be one of the following:
597
598 ::
599
600 0 (LOG_LEVEL_NONE)
Daniel Boulby86c6b072018-06-14 10:07:40 +0100601 10 (LOG_LEVEL_ERROR)
602 20 (LOG_LEVEL_NOTICE)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100603 30 (LOG_LEVEL_WARNING)
604 40 (LOG_LEVEL_INFO)
605 50 (LOG_LEVEL_VERBOSE)
606
John Tsichritzis35006c42018-10-05 12:02:29 +0100607 All log output up to and including the selected log level is compiled into
608 the build. The default value is 40 in debug builds and 20 in release builds.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100609
610- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
611 specifies the file that contains the Non-Trusted World private key in PEM
612 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
613
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100614- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100615 optional. It is only needed if the platform makefile specifies that it
616 is required in order to build the ``fwu_fip`` target.
617
618- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
619 contents upon world switch. It can take either 0 (don't save and restore) or
620 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
621 wants the timer registers to be saved and restored.
622
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +0100623- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc
Varun Wadekar3f9002c2019-01-31 09:22:30 -0800624 for the BL image. It can be either 0 (include) or 1 (remove). The default
625 value is 0.
626
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100627- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
628 the underlying hardware is not a full PL011 UART but a minimally compliant
629 generic UART, which is a subset of the PL011. The driver will not access
630 any register that is not part of the SBSA generic UART specification.
631 Default value is 0 (a full PL011 compliant UART is present).
632
Dan Handley610e7e12018-03-01 18:44:00 +0000633- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name
634 must be subdirectory of any depth under ``plat/``, and must contain a
635 platform makefile named ``platform.mk``. For example, to build TF-A for the
636 Arm Juno board, select PLAT=juno.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100637
638- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
639 instead of the normal boot flow. When defined, it must specify the entry
640 point address for the preloaded BL33 image. This option is incompatible with
641 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
642 over ``PRELOADED_BL33_BASE``.
643
644- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
645 vector address can be programmed or is fixed on the platform. It can take
646 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
647 programmable reset address, it is expected that a CPU will start executing
648 code directly at the right address, both on a cold and warm reset. In this
649 case, there is no need to identify the entrypoint on boot and the boot path
650 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
651 does not need to be implemented in this case.
652
653- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +0000654 possible for the PSCI power-state parameter: original and extended State-ID
655 formats. This flag if set to 1, configures the generic PSCI layer to use the
656 extended format. The default value of this flag is 0, which means by default
657 the original power-state format is used by the PSCI implementation. This flag
658 should be specified by the platform makefile and it governs the return value
659 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is
660 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be
661 set to 1 as well.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100662
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100663- ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features
664 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2
665 or later CPUs.
666
667 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be
668 set to ``1``.
669
670 This option is disabled by default.
671
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100672- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
673 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
674 entrypoint) or 1 (CPU reset to BL31 entrypoint).
675 The default value is 0.
676
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100677- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided
678 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector
Dan Handley610e7e12018-03-01 18:44:00 +0000679 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100680 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100681
682- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
683 file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this
684 file name will be used to save the key.
685
686- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
687 certificate generation tool to save the keys used to establish the Chain of
688 Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
689
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100690- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional.
691 If a SCP_BL2 image is present then this option must be passed for the ``fip``
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100692 target.
693
694- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100695 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100696 this file name will be used to save the key.
697
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100698- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100699 optional. It is only needed if the platform makefile specifies that it
700 is required in order to build the ``fwu_fip`` target.
701
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +0100702- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software
703 Delegated Exception Interface to BL31 image. This defaults to ``0``.
704
705 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be
706 set to ``1``.
707
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100708- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
709 isolated on separate memory pages. This is a trade-off between security and
710 memory usage. See "Isolating code and read-only data on separate memory
711 pages" section in `Firmware Design`_. This flag is disabled by default and
712 affects all BL images.
713
Dan Handley610e7e12018-03-01 18:44:00 +0000714- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
715 This build option is only valid if ``ARCH=aarch64``. The value should be
716 the path to the directory containing the SPD source, relative to
717 ``services/spd/``; the directory is expected to contain a makefile called
718 ``<spd-value>.mk``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100719
720- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
721 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
722 execution in BL1 just before handing over to BL31. At this point, all
723 firmware images have been loaded in memory, and the MMU and caches are
724 turned off. Refer to the "Debugging options" section for more details.
725
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100726- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
Etienne Carrieredc0fea72017-08-09 15:48:53 +0200727 secure interrupts (caught through the FIQ line). Platforms can enable
728 this directive if they need to handle such interruption. When enabled,
729 the FIQ are handled in monitor mode and non secure world is not allowed
730 to mask these events. Platforms that enable FIQ handling in SP_MIN shall
731 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
732
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100733- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
734 Boot feature. When set to '1', BL1 and BL2 images include support to load
735 and verify the certificates and images in a FIP, and BL1 includes support
736 for the Firmware Update. The default value is '0'. Generation and inclusion
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100737 of certificates in the FIP and FWU_FIP depends upon the value of the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100738 ``GENERATE_COT`` option.
739
Paul Beesleyba3ed402019-03-13 16:20:44 +0000740 .. warning::
741 This option depends on ``CREATE_KEYS`` to be enabled. If the keys
742 already exist in disk, they will be overwritten without further notice.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100743
744- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
745 specifies the file that contains the Trusted World private key in PEM
746 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
747
748- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
749 synchronous, (see "Initializing a BL32 Image" section in
750 `Firmware Design`_). It can take the value 0 (BL32 is initialized using
751 synchronous method) or 1 (BL32 is initialized using asynchronous method).
752 Default is 0.
753
754- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
755 routing model which routes non-secure interrupts asynchronously from TSP
756 to EL3 causing immediate preemption of TSP. The EL3 is responsible
757 for saving and restoring the TSP context in this routing model. The
758 default routing model (when the value is 0) is to route non-secure
759 interrupts to TSP allowing it to save its context and hand over
760 synchronously to EL3 via an SMC.
761
Paul Beesleyba3ed402019-03-13 16:20:44 +0000762 .. note::
763 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT``
764 must also be set to ``1``.
Jeenu Viswambharan2f40f322018-01-11 14:30:22 +0000765
Varun Wadekar4d034c52019-01-11 14:47:48 -0800766- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM
767 linker. When the ``LINKER`` build variable points to the armlink linker,
768 this flag is enabled automatically. To enable support for armlink, platforms
769 will have to provide a scatter file for the BL image. Currently, Tegra
770 platforms use the armlink support to compile BL3-1 images.
771
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100772- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
773 memory region in the BL memory map or not (see "Use of Coherent memory in
Dan Handley610e7e12018-03-01 18:44:00 +0000774 TF-A" section in `Firmware Design`_). It can take the value 1
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100775 (Coherent memory region is included) or 0 (Coherent memory region is
776 excluded). Default is 1.
777
John Tsichritzis2e42b622019-03-19 12:12:55 +0000778- ``USE_ROMLIB``: This flag determines whether library at ROM will be used.
779 This feature creates a library of functions to be placed in ROM and thus
780 reduces SRAM usage. Refer to `Library at ROM`_ for further details. Default
781 is 0.
782
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100783- ``V``: Verbose build. If assigned anything other than 0, the build commands
784 are printed. Default is 0.
785
Dan Handley610e7e12018-03-01 18:44:00 +0000786- ``VERSION_STRING``: String used in the log output for each TF-A image.
787 Defaults to a string formed by concatenating the version number, build type
788 and build string.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100789
Ambroise Vincentba0442d2019-06-06 10:26:41 +0100790- ``W``: Warning level. Some compiler warning options of interest have been
791 regrouped and put in the root Makefile. This flag can take the values 0 to 3,
792 each level enabling more warning options. Default is 0.
793
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100794- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
795 the CPU after warm boot. This is applicable for platforms which do not
796 require interconnect programming to enable cache coherency (eg: single
797 cluster platforms). If this option is enabled, then warm boot path
798 enables D-caches immediately after enabling MMU. This option defaults to 0.
799
Dan Handley610e7e12018-03-01 18:44:00 +0000800Arm development platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100801^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
802
803- ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured
804 DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load
805 BL31 in TZC secured DRAM. If TSP is present, then setting this option also
806 sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build
807 flag.
808
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100809- ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
810 frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
811 frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which should
812 match the frame used by the Non-Secure image (normally the Linux kernel).
813 Default is true (access to the frame is allowed).
814
815- ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
Dan Handley610e7e12018-03-01 18:44:00 +0000816 By default, Arm platforms use a watchdog to trigger a system reset in case
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100817 an error is encountered during the boot process (for example, when an image
818 could not be loaded or authenticated). The watchdog is enabled in the early
819 platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The
820 Trusted Watchdog may be disabled at build time for testing or development
821 purposes.
822
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100823- ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to
824 have specific values at boot. This boolean option allows the Trusted Firmware
825 to have a Linux kernel image as BL33 by preparing the registers to these
Manish Pandey37c4ec22018-11-02 13:28:25 +0000826 values before jumping to BL33. This option defaults to 0 (disabled). For
827 AArch64 ``RESET_TO_BL31`` and for AArch32 ``RESET_TO_SP_MIN`` must be 1 when
828 using it. If this option is set to 1, ``ARM_PRELOADED_DTB_BASE`` must be set
829 to the location of a device tree blob (DTB) already loaded in memory. The
830 Linux Image address must be specified using the ``PRELOADED_BL33_BASE``
831 option.
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100832
Sandrine Bailleux281f8f72019-01-31 13:12:41 +0100833- ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to
834 cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
835 is set, the functions which deal with MPIDR assume that the ``MT`` bit in
836 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
837 this flag is 0. Note that this option is not used on FVP platforms.
838
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100839- ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding
840 for the construction of composite state-ID in the power-state parameter.
841 The existing PSCI clients currently do not support this encoding of
842 State-ID yet. Hence this flag is used to configure whether to use the
843 recommended State-ID encoding or not. The default value of this flag is 0,
844 in which case the platform is configured to expect NULL in the State-ID
845 field of power-state parameter.
846
847- ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the
848 location of the ROTPK hash returned by the function ``plat_get_rotpk_info()``
Dan Handley610e7e12018-03-01 18:44:00 +0000849 for Arm platforms. Depending on the selected option, the proper private key
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100850 must be specified using the ``ROT_KEY`` option when building the Trusted
851 Firmware. This private key will be used by the certificate generation tool
852 to sign the BL2 and Trusted Key certificates. Available options for
853 ``ARM_ROTPK_LOCATION`` are:
854
855 - ``regs`` : return the ROTPK hash stored in the Trusted root-key storage
856 registers. The private key corresponding to this ROTPK hash is not
857 currently available.
858 - ``devel_rsa`` : return a development public key hash embedded in the BL1
859 and BL2 binaries. This hash has been obtained from the RSA public key
860 ``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use
861 this option, ``arm_rotprivk_rsa.pem`` must be specified as ``ROT_KEY`` when
862 creating the certificates.
Qixiang Xu1c2aef12017-08-24 15:12:20 +0800863 - ``devel_ecdsa`` : return a development public key hash embedded in the BL1
864 and BL2 binaries. This hash has been obtained from the ECDSA public key
865 ``arm_rotpk_ecdsa.der``, located in ``plat/arm/board/common/rotpk``. To use
866 this option, ``arm_rotprivk_ecdsa.pem`` must be specified as ``ROT_KEY``
867 when creating the certificates.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100868
869- ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options:
870
Qixiang Xuc7b12c52017-10-13 09:04:12 +0800871 - ``tsram`` : Trusted SRAM (default option when TBB is not enabled)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100872 - ``tdram`` : Trusted DRAM (if available)
John Tsichritzisee10e792018-06-06 09:38:10 +0100873 - ``dram`` : Secure region in DRAM (default option when TBB is enabled,
874 configured by the TrustZone controller)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100875
Dan Handley610e7e12018-03-01 18:44:00 +0000876- ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile TF-A with version 1
877 of the translation tables library instead of version 2. It is set to 0 by
878 default, which selects version 2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100879
Dan Handley610e7e12018-03-01 18:44:00 +0000880- ``ARM_CRYPTOCELL_INTEG`` : bool option to enable TF-A to invoke Arm®
881 TrustZone® CryptoCell functionality for Trusted Board Boot on capable Arm
882 platforms. If this option is specified, then the path to the CryptoCell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100883 SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
884
Dan Handley610e7e12018-03-01 18:44:00 +0000885For a better understanding of these options, the Arm development platform memory
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100886map is explained in the `Firmware Design`_.
887
Dan Handley610e7e12018-03-01 18:44:00 +0000888Arm CSS platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100889^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
890
891- ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version
892 incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards
893 compatible change to the MTL protocol, used for AP/SCP communication.
Dan Handley610e7e12018-03-01 18:44:00 +0000894 TF-A no longer supports earlier SCP versions. If this option is set to 1
895 then TF-A will detect if an earlier version is in use. Default is 1.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100896
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100897- ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP_BL2 and
898 SCP_BL2U to the FIP and FWU_FIP respectively, and enables them to be loaded
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100899 during boot. Default is 1.
900
Soby Mathew1ced6b82017-06-12 12:37:10 +0100901- ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers
902 instead of SCPI/BOM driver for communicating with the SCP during power
903 management operations and for SCP RAM Firmware transfer. If this option
904 is set to 1, then SCMI/SDS drivers will be used. Default is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100905
Dan Handley610e7e12018-03-01 18:44:00 +0000906Arm FVP platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100907^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
908
909- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
Dan Handley610e7e12018-03-01 18:44:00 +0000910 build the topology tree within TF-A. By default TF-A is configured for dual
911 cluster topology and this option can be used to override the default value.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100912
913- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
914 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
915 explained in the options below:
916
917 - ``FVP_CCI`` : The CCI driver is selected. This is the default
918 if 0 < ``FVP_CLUSTER_COUNT`` <= 2.
919 - ``FVP_CCN`` : The CCN driver is selected. This is the default
920 if ``FVP_CLUSTER_COUNT`` > 2.
921
Jeenu Viswambharan75421132018-01-31 14:52:08 +0000922- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in
923 a single cluster. This option defaults to 4.
924
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000925- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
926 in the system. This option defaults to 1. Note that the build option
927 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms.
928
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100929- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
930
931 - ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected
932 - ``FVP_GICV2`` : The GICv2 only driver is selected
933 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100934
935- ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer
936 for functions that wait for an arbitrary time length (udelay and mdelay).
937 The default value is 0.
938
Soby Mathewb1bf0442018-02-16 14:52:52 +0000939- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled
940 to DTB and packaged in FIP as the HW_CONFIG. See `Firmware Design`_ for
941 details on HW_CONFIG. By default, this is initialized to a sensible DTS
942 file in ``fdts/`` folder depending on other build options. But some cases,
943 like shifted affinity format for MPIDR, cannot be detected at build time
944 and this option is needed to specify the appropriate DTS file.
945
946- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in
947 FIP. See `Firmware Design`_ for details on HW_CONFIG. This option is
948 similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the
949 HW_CONFIG blob instead of the DTS file. This option is useful to override
950 the default HW_CONFIG selected by the build system.
951
Summer Qin13b95c22018-03-02 15:51:14 +0800952ARM JUNO platform specific build options
953^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
954
955- ``JUNO_TZMP1`` : Boolean option to configure Juno to be used for TrustZone
956 Media Protection (TZ-MP1). Default value of this flag is 0.
957
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100958Debugging options
959~~~~~~~~~~~~~~~~~
960
961To compile a debug version and make the build more verbose use
962
Paul Beesley493e3492019-03-13 15:11:04 +0000963.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100964
965 make PLAT=<platform> DEBUG=1 V=1 all
966
967AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for
968example DS-5) might not support this and may need an older version of DWARF
969symbols to be emitted by GCC. This can be achieved by using the
970``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the
971version to 2 is recommended for DS-5 versions older than 5.16.
972
973When debugging logic problems it might also be useful to disable all compiler
974optimizations by using ``-O0``.
975
Paul Beesleyba3ed402019-03-13 16:20:44 +0000976.. warning::
977 Using ``-O0`` could cause output images to be larger and base addresses
978 might need to be recalculated (see the **Memory layout on Arm development
979 platforms** section in the `Firmware Design`_).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100980
981Extra debug options can be passed to the build system by setting ``CFLAGS`` or
982``LDFLAGS``:
983
Paul Beesley493e3492019-03-13 15:11:04 +0000984.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100985
986 CFLAGS='-O0 -gdwarf-2' \
987 make PLAT=<platform> DEBUG=1 V=1 all
988
989Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
990ignored as the linker is called directly.
991
992It is also possible to introduce an infinite loop to help in debugging the
Dan Handley610e7e12018-03-01 18:44:00 +0000993post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the
994``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the `Summary of build options`_
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100995section. In this case, the developer may take control of the target using a
996debugger when indicated by the console output. When using DS-5, the following
997commands can be used:
998
999::
1000
1001 # Stop target execution
1002 interrupt
1003
1004 #
1005 # Prepare your debugging environment, e.g. set breakpoints
1006 #
1007
1008 # Jump over the debug loop
1009 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
1010
1011 # Resume execution
1012 continue
1013
1014Building the Test Secure Payload
1015~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1016
1017The TSP is coupled with a companion runtime service in the BL31 firmware,
1018called the TSPD. Therefore, if you intend to use the TSP, the BL31 image
1019must be recompiled as well. For more information on SPs and SPDs, see the
1020`Secure-EL1 Payloads and Dispatchers`_ section in the `Firmware Design`_.
1021
Dan Handley610e7e12018-03-01 18:44:00 +00001022First clean the TF-A build directory to get rid of any previous BL31 binary.
1023Then to build the TSP image use:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001024
Paul Beesley493e3492019-03-13 15:11:04 +00001025.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001026
1027 make PLAT=<platform> SPD=tspd all
1028
1029An additional boot loader binary file is created in the ``build`` directory:
1030
1031::
1032
1033 build/<platform>/<build-type>/bl32.bin
1034
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001035
1036Building and using the FIP tool
1037~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1038
Dan Handley610e7e12018-03-01 18:44:00 +00001039Firmware Image Package (FIP) is a packaging format used by TF-A to package
1040firmware images in a single binary. The number and type of images that should
1041be packed in a FIP is platform specific and may include TF-A images and other
1042firmware images required by the platform. For example, most platforms require
1043a BL33 image which corresponds to the normal world bootloader (e.g. UEFI or
1044U-Boot).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001045
Dan Handley610e7e12018-03-01 18:44:00 +00001046The TF-A build system provides the make target ``fip`` to create a FIP file
1047for the specified platform using the FIP creation tool included in the TF-A
1048project. Examples below show how to build a FIP file for FVP, packaging TF-A
1049and BL33 images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001050
1051For AArch64:
1052
Paul Beesley493e3492019-03-13 15:11:04 +00001053.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001054
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001055 make PLAT=fvp BL33=<path-to>/bl33.bin fip
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001056
1057For AArch32:
1058
Paul Beesley493e3492019-03-13 15:11:04 +00001059.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001060
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001061 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path-to>/bl33.bin fip
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001062
1063The resulting FIP may be found in:
1064
1065::
1066
1067 build/fvp/<build-type>/fip.bin
1068
1069For advanced operations on FIP files, it is also possible to independently build
1070the tool and create or modify FIPs using this tool. To do this, follow these
1071steps:
1072
1073It is recommended to remove old artifacts before building the tool:
1074
Paul Beesley493e3492019-03-13 15:11:04 +00001075.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001076
1077 make -C tools/fiptool clean
1078
1079Build the tool:
1080
Paul Beesley493e3492019-03-13 15:11:04 +00001081.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001082
1083 make [DEBUG=1] [V=1] fiptool
1084
1085The tool binary can be located in:
1086
1087::
1088
1089 ./tools/fiptool/fiptool
1090
Alexei Fedorov2831d582019-03-13 11:05:07 +00001091Invoking the tool with ``help`` will print a help message with all available
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001092options.
1093
1094Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31:
1095
Paul Beesley493e3492019-03-13 15:11:04 +00001096.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001097
1098 ./tools/fiptool/fiptool create \
1099 --tb-fw build/<platform>/<build-type>/bl2.bin \
1100 --soc-fw build/<platform>/<build-type>/bl31.bin \
1101 fip.bin
1102
1103Example 2: view the contents of an existing Firmware package:
1104
Paul Beesley493e3492019-03-13 15:11:04 +00001105.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001106
1107 ./tools/fiptool/fiptool info <path-to>/fip.bin
1108
1109Example 3: update the entries of an existing Firmware package:
1110
Paul Beesley493e3492019-03-13 15:11:04 +00001111.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001112
1113 # Change the BL2 from Debug to Release version
1114 ./tools/fiptool/fiptool update \
1115 --tb-fw build/<platform>/release/bl2.bin \
1116 build/<platform>/debug/fip.bin
1117
1118Example 4: unpack all entries from an existing Firmware package:
1119
Paul Beesley493e3492019-03-13 15:11:04 +00001120.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001121
1122 # Images will be unpacked to the working directory
1123 ./tools/fiptool/fiptool unpack <path-to>/fip.bin
1124
1125Example 5: remove an entry from an existing Firmware package:
1126
Paul Beesley493e3492019-03-13 15:11:04 +00001127.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001128
1129 ./tools/fiptool/fiptool remove \
1130 --tb-fw build/<platform>/debug/fip.bin
1131
1132Note that if the destination FIP file exists, the create, update and
1133remove operations will automatically overwrite it.
1134
1135The unpack operation will fail if the images already exist at the
1136destination. In that case, use -f or --force to continue.
1137
1138More information about FIP can be found in the `Firmware Design`_ document.
1139
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001140Building FIP images with support for Trusted Board Boot
1141~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1142
1143Trusted Board Boot primarily consists of the following two features:
1144
1145- Image Authentication, described in `Trusted Board Boot`_, and
1146- Firmware Update, described in `Firmware Update`_
1147
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001148The following steps should be followed to build FIP and (optionally) FWU_FIP
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001149images with support for these features:
1150
1151#. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser
1152 modules by checking out a recent version of the `mbed TLS Repository`_. It
Dan Handley610e7e12018-03-01 18:44:00 +00001153 is important to use a version that is compatible with TF-A and fixes any
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001154 known security vulnerabilities. See `mbed TLS Security Center`_ for more
Dan Handley610e7e12018-03-01 18:44:00 +00001155 information. The latest version of TF-A is tested with tag
John Tsichritzisff4f9912019-03-12 16:11:17 +00001156 ``mbedtls-2.16.0``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001157
1158 The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS
1159 source files the modules depend upon.
1160 ``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration
1161 options required to build the mbed TLS sources.
1162
1163 Note that the mbed TLS library is licensed under the Apache version 2.0
Dan Handley610e7e12018-03-01 18:44:00 +00001164 license. Using mbed TLS source code will affect the licensing of TF-A
1165 binaries that are built using this library.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001166
1167#. To build the FIP image, ensure the following command line variables are set
Dan Handley610e7e12018-03-01 18:44:00 +00001168 while invoking ``make`` to build TF-A:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001169
1170 - ``MBEDTLS_DIR=<path of the directory containing mbed TLS sources>``
1171 - ``TRUSTED_BOARD_BOOT=1``
1172 - ``GENERATE_COT=1``
1173
Dan Handley610e7e12018-03-01 18:44:00 +00001174 In the case of Arm platforms, the location of the ROTPK hash must also be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001175 specified at build time. Two locations are currently supported (see
1176 ``ARM_ROTPK_LOCATION`` build option):
1177
1178 - ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted
1179 root-key storage registers present in the platform. On Juno, this
1180 registers are read-only. On FVP Base and Cortex models, the registers
1181 are read-only, but the value can be specified using the command line
1182 option ``bp.trusted_key_storage.public_key`` when launching the model.
1183 On both Juno and FVP models, the default value corresponds to an
1184 ECDSA-SECP256R1 public key hash, whose private part is not currently
1185 available.
1186
1187 - ``ARM_ROTPK_LOCATION=devel_rsa``: use the ROTPK hash that is hardcoded
Dan Handley610e7e12018-03-01 18:44:00 +00001188 in the Arm platform port. The private/public RSA key pair may be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001189 found in ``plat/arm/board/common/rotpk``.
1190
Qixiang Xu1c2aef12017-08-24 15:12:20 +08001191 - ``ARM_ROTPK_LOCATION=devel_ecdsa``: use the ROTPK hash that is hardcoded
Dan Handley610e7e12018-03-01 18:44:00 +00001192 in the Arm platform port. The private/public ECDSA key pair may be
Qixiang Xu1c2aef12017-08-24 15:12:20 +08001193 found in ``plat/arm/board/common/rotpk``.
1194
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001195 Example of command line using RSA development keys:
1196
Paul Beesley493e3492019-03-13 15:11:04 +00001197 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001198
1199 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1200 make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1201 ARM_ROTPK_LOCATION=devel_rsa \
1202 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1203 BL33=<path-to>/<bl33_image> \
1204 all fip
1205
1206 The result of this build will be the bl1.bin and the fip.bin binaries. This
1207 FIP will include the certificates corresponding to the Chain of Trust
1208 described in the TBBR-client document. These certificates can also be found
1209 in the output build directory.
1210
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001211#. The optional FWU_FIP contains any additional images to be loaded from
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001212 Non-Volatile storage during the `Firmware Update`_ process. To build the
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001213 FWU_FIP, any FWU images required by the platform must be specified on the
Dan Handley610e7e12018-03-01 18:44:00 +00001214 command line. On Arm development platforms like Juno, these are:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001215
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001216 - NS_BL2U. The AP non-secure Firmware Updater image.
1217 - SCP_BL2U. The SCP Firmware Update Configuration image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001218
1219 Example of Juno command line for generating both ``fwu`` and ``fwu_fip``
1220 targets using RSA development:
1221
1222 ::
1223
1224 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1225 make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1226 ARM_ROTPK_LOCATION=devel_rsa \
1227 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1228 BL33=<path-to>/<bl33_image> \
1229 SCP_BL2=<path-to>/<scp_bl2_image> \
1230 SCP_BL2U=<path-to>/<scp_bl2u_image> \
1231 NS_BL2U=<path-to>/<ns_bl2u_image> \
1232 all fip fwu_fip
1233
Paul Beesleyba3ed402019-03-13 16:20:44 +00001234 .. note::
1235 The BL2U image will be built by default and added to the FWU_FIP.
1236 The user may override this by adding ``BL2U=<path-to>/<bl2u_image>``
1237 to the command line above.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001238
Paul Beesleyba3ed402019-03-13 16:20:44 +00001239 .. note::
1240 Building and installing the non-secure and SCP FWU images (NS_BL1U,
1241 NS_BL2U and SCP_BL2U) is outside the scope of this document.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001242
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001243 The result of this build will be bl1.bin, fip.bin and fwu_fip.bin binaries.
1244 Both the FIP and FWU_FIP will include the certificates corresponding to the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001245 Chain of Trust described in the TBBR-client document. These certificates
1246 can also be found in the output build directory.
1247
1248Building the Certificate Generation Tool
1249~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1250
Dan Handley610e7e12018-03-01 18:44:00 +00001251The ``cert_create`` tool is built as part of the TF-A build process when the
1252``fip`` make target is specified and TBB is enabled (as described in the
1253previous section), but it can also be built separately with the following
1254command:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001255
Paul Beesley493e3492019-03-13 15:11:04 +00001256.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001257
1258 make PLAT=<platform> [DEBUG=1] [V=1] certtool
1259
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +01001260For platforms that require their own IDs in certificate files, the generic
Paul Beesley62761cd2019-04-11 13:35:26 +01001261'cert_create' tool can be built with the following command. Note that the target
1262platform must define its IDs within a ``platform_oid.h`` header file for the
1263build to succeed.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001264
Paul Beesley493e3492019-03-13 15:11:04 +00001265.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001266
Paul Beesley62761cd2019-04-11 13:35:26 +01001267 make PLAT=<platform> USE_TBBR_DEFS=0 [DEBUG=1] [V=1] certtool
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001268
1269``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
1270verbose. The following command should be used to obtain help about the tool:
1271
Paul Beesley493e3492019-03-13 15:11:04 +00001272.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001273
1274 ./tools/cert_create/cert_create -h
1275
1276Building a FIP for Juno and FVP
1277-------------------------------
1278
1279This section provides Juno and FVP specific instructions to build Trusted
1280Firmware, obtain the additional required firmware, and pack it all together in
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001281a single FIP binary. It assumes that a `Linaro Release`_ has been installed.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001282
Paul Beesleyba3ed402019-03-13 16:20:44 +00001283.. note::
1284 Pre-built binaries for AArch32 are available from Linaro Release 16.12
1285 onwards. Before that release, pre-built binaries are only available for
1286 AArch64.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001287
Paul Beesleyba3ed402019-03-13 16:20:44 +00001288.. warning::
1289 Follow the full instructions for one platform before switching to a
1290 different one. Mixing instructions for different platforms may result in
1291 corrupted binaries.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001292
Paul Beesleyba3ed402019-03-13 16:20:44 +00001293.. warning::
1294 The uboot image downloaded by the Linaro workspace script does not always
1295 match the uboot image packaged as BL33 in the corresponding fip file. It is
1296 recommended to use the version that is packaged in the fip file using the
1297 instructions below.
Joel Huttonfe027712018-03-19 11:59:57 +00001298
Paul Beesleyba3ed402019-03-13 16:20:44 +00001299.. note::
1300 For the FVP, the kernel FDT is packaged in FIP during build and loaded
1301 by the firmware at runtime. See `Obtaining the Flattened Device Trees`_
1302 section for more info on selecting the right FDT to use.
Soby Mathewecd94ad2018-05-09 13:59:29 +01001303
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001304#. Clean the working directory
1305
Paul Beesley493e3492019-03-13 15:11:04 +00001306 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001307
1308 make realclean
1309
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001310#. Obtain SCP_BL2 (Juno) and BL33 (all platforms)
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001311
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001312 Use the fiptool to extract the SCP_BL2 and BL33 images from the FIP
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001313 package included in the Linaro release:
1314
Paul Beesley493e3492019-03-13 15:11:04 +00001315 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001316
1317 # Build the fiptool
1318 make [DEBUG=1] [V=1] fiptool
1319
1320 # Unpack firmware images from Linaro FIP
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001321 ./tools/fiptool/fiptool unpack <path-to-linaro-release>/fip.bin
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001322
1323 The unpack operation will result in a set of binary images extracted to the
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001324 current working directory. The SCP_BL2 image corresponds to
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001325 ``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001326
Paul Beesleyba3ed402019-03-13 16:20:44 +00001327 .. note::
1328 The fiptool will complain if the images to be unpacked already
1329 exist in the current directory. If that is the case, either delete those
1330 files or use the ``--force`` option to overwrite.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001331
Paul Beesleyba3ed402019-03-13 16:20:44 +00001332 .. note::
1333 For AArch32, the instructions below assume that nt-fw.bin is a
1334 normal world boot loader that supports AArch32.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001335
Dan Handley610e7e12018-03-01 18:44:00 +00001336#. Build TF-A images and create a new FIP for FVP
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001337
Paul Beesley493e3492019-03-13 15:11:04 +00001338 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001339
1340 # AArch64
1341 make PLAT=fvp BL33=nt-fw.bin all fip
1342
1343 # AArch32
1344 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=nt-fw.bin all fip
1345
Dan Handley610e7e12018-03-01 18:44:00 +00001346#. Build TF-A images and create a new FIP for Juno
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001347
1348 For AArch64:
1349
1350 Building for AArch64 on Juno simply requires the addition of ``SCP_BL2``
1351 as a build parameter.
1352
Paul Beesley493e3492019-03-13 15:11:04 +00001353 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001354
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001355 make PLAT=juno BL33=nt-fw.bin SCP_BL2=scp-fw.bin all fip
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001356
1357 For AArch32:
1358
1359 Hardware restrictions on Juno prevent cold reset into AArch32 execution mode,
1360 therefore BL1 and BL2 must be compiled for AArch64, and BL32 is compiled
1361 separately for AArch32.
1362
1363 - Before building BL32, the environment variable ``CROSS_COMPILE`` must point
1364 to the AArch32 Linaro cross compiler.
1365
Paul Beesley493e3492019-03-13 15:11:04 +00001366 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001367
1368 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
1369
1370 - Build BL32 in AArch32.
1371
Paul Beesley493e3492019-03-13 15:11:04 +00001372 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001373
1374 make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \
1375 RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32
1376
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001377 - Save ``bl32.bin`` to a temporary location and clean the build products.
1378
1379 ::
1380
1381 cp <path-to-build>/bl32.bin <path-to-temporary>
1382 make realclean
1383
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001384 - Before building BL1 and BL2, the environment variable ``CROSS_COMPILE``
1385 must point to the AArch64 Linaro cross compiler.
1386
Paul Beesley493e3492019-03-13 15:11:04 +00001387 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001388
1389 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
1390
1391 - The following parameters should be used to build BL1 and BL2 in AArch64
1392 and point to the BL32 file.
1393
Paul Beesley493e3492019-03-13 15:11:04 +00001394 .. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001395
Soby Mathew97b1bff2018-09-27 16:46:41 +01001396 make ARCH=aarch64 PLAT=juno JUNO_AARCH32_EL3_RUNTIME=1 \
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001397 BL33=nt-fw.bin SCP_BL2=scp-fw.bin \
1398 BL32=<path-to-temporary>/bl32.bin all fip
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001399
1400The resulting BL1 and FIP images may be found in:
1401
1402::
1403
1404 # Juno
1405 ./build/juno/release/bl1.bin
1406 ./build/juno/release/fip.bin
1407
1408 # FVP
1409 ./build/fvp/release/bl1.bin
1410 ./build/fvp/release/fip.bin
1411
Roberto Vargas096f3a02017-10-17 10:19:00 +01001412
1413Booting Firmware Update images
1414-------------------------------------
1415
1416When Firmware Update (FWU) is enabled there are at least 2 new images
1417that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the
1418FWU FIP.
1419
1420Juno
1421~~~~
1422
1423The new images must be programmed in flash memory by adding
1424an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1425on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1426Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1427programming" for more information. User should ensure these do not
1428overlap with any other entries in the file.
1429
1430::
1431
1432 NOR10UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1433 NOR10ADDRESS: 0x00400000 ;Image Flash Address [ns_bl2u_base_address]
1434 NOR10FILE: \SOFTWARE\fwu_fip.bin ;Image File Name
1435 NOR10LOAD: 00000000 ;Image Load Address
1436 NOR10ENTRY: 00000000 ;Image Entry Point
1437
1438 NOR11UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1439 NOR11ADDRESS: 0x03EB8000 ;Image Flash Address [ns_bl1u_base_address]
1440 NOR11FILE: \SOFTWARE\ns_bl1u.bin ;Image File Name
1441 NOR11LOAD: 00000000 ;Image Load Address
1442
1443The address ns_bl1u_base_address is the value of NS_BL1U_BASE - 0x8000000.
1444In the same way, the address ns_bl2u_base_address is the value of
1445NS_BL2U_BASE - 0x8000000.
1446
1447FVP
1448~~~
1449
1450The additional fip images must be loaded with:
1451
1452::
1453
1454 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address]
1455 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address]
1456
1457The address ns_bl1u_base_address is the value of NS_BL1U_BASE.
1458In the same way, the address ns_bl2u_base_address is the value of
1459NS_BL2U_BASE.
1460
1461
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001462EL3 payloads alternative boot flow
1463----------------------------------
1464
1465On a pre-production system, the ability to execute arbitrary, bare-metal code at
1466the highest exception level is required. It allows full, direct access to the
1467hardware, for example to run silicon soak tests.
1468
1469Although it is possible to implement some baremetal secure firmware from
1470scratch, this is a complex task on some platforms, depending on the level of
1471configuration required to put the system in the expected state.
1472
1473Rather than booting a baremetal application, a possible compromise is to boot
Dan Handley610e7e12018-03-01 18:44:00 +00001474``EL3 payloads`` through TF-A instead. This is implemented as an alternative
1475boot flow, where a modified BL2 boots an EL3 payload, instead of loading the
1476other BL images and passing control to BL31. It reduces the complexity of
1477developing EL3 baremetal code by:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001478
1479- putting the system into a known architectural state;
1480- taking care of platform secure world initialization;
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001481- loading the SCP_BL2 image if required by the platform.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001482
Dan Handley610e7e12018-03-01 18:44:00 +00001483When booting an EL3 payload on Arm standard platforms, the configuration of the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001484TrustZone controller is simplified such that only region 0 is enabled and is
1485configured to permit secure access only. This gives full access to the whole
1486DRAM to the EL3 payload.
1487
1488The system is left in the same state as when entering BL31 in the default boot
1489flow. In particular:
1490
1491- Running in EL3;
1492- Current state is AArch64;
1493- Little-endian data access;
1494- All exceptions disabled;
1495- MMU disabled;
1496- Caches disabled.
1497
1498Booting an EL3 payload
1499~~~~~~~~~~~~~~~~~~~~~~
1500
1501The EL3 payload image is a standalone image and is not part of the FIP. It is
Dan Handley610e7e12018-03-01 18:44:00 +00001502not loaded by TF-A. Therefore, there are 2 possible scenarios:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001503
1504- The EL3 payload may reside in non-volatile memory (NVM) and execute in
1505 place. In this case, booting it is just a matter of specifying the right
Dan Handley610e7e12018-03-01 18:44:00 +00001506 address in NVM through ``EL3_PAYLOAD_BASE`` when building TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001507
1508- The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
1509 run-time.
1510
1511To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be
1512used. The infinite loop that it introduces in BL1 stops execution at the right
1513moment for a debugger to take control of the target and load the payload (for
1514example, over JTAG).
1515
1516It is expected that this loading method will work in most cases, as a debugger
1517connection is usually available in a pre-production system. The user is free to
1518use any other platform-specific mechanism to load the EL3 payload, though.
1519
1520Booting an EL3 payload on FVP
1521^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1522
1523The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
1524the secondary CPUs holding pen to work properly. Unfortunately, its reset value
1525is undefined on the FVP platform and the FVP platform code doesn't clear it.
1526Therefore, one must modify the way the model is normally invoked in order to
1527clear the mailbox at start-up.
1528
1529One way to do that is to create an 8-byte file containing all zero bytes using
1530the following command:
1531
Paul Beesley493e3492019-03-13 15:11:04 +00001532.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001533
1534 dd if=/dev/zero of=mailbox.dat bs=1 count=8
1535
1536and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
1537using the following model parameters:
1538
1539::
1540
1541 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
1542 --data=mailbox.dat@0x04000000 [Foundation FVP]
1543
1544To provide the model with the EL3 payload image, the following methods may be
1545used:
1546
1547#. If the EL3 payload is able to execute in place, it may be programmed into
1548 flash memory. On Base Cortex and AEM FVPs, the following model parameter
1549 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
1550 used for the FIP):
1551
1552 ::
1553
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001554 -C bp.flashloader1.fname="<path-to>/<el3-payload>"
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001555
1556 On Foundation FVP, there is no flash loader component and the EL3 payload
1557 may be programmed anywhere in flash using method 3 below.
1558
1559#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
1560 command may be used to load the EL3 payload ELF image over JTAG:
1561
1562 ::
1563
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001564 load <path-to>/el3-payload.elf
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001565
1566#. The EL3 payload may be pre-loaded in volatile memory using the following
1567 model parameters:
1568
1569 ::
1570
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001571 --data cluster0.cpu0="<path-to>/el3-payload>"@address [Base FVPs]
1572 --data="<path-to>/<el3-payload>"@address [Foundation FVP]
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001573
1574 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
Dan Handley610e7e12018-03-01 18:44:00 +00001575 used when building TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001576
1577Booting an EL3 payload on Juno
1578^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1579
1580If the EL3 payload is able to execute in place, it may be programmed in flash
1581memory by adding an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1582on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1583Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1584programming" for more information.
1585
1586Alternatively, the same DS-5 command mentioned in the FVP section above can
1587be used to load the EL3 payload's ELF file over JTAG on Juno.
1588
1589Preloaded BL33 alternative boot flow
1590------------------------------------
1591
1592Some platforms have the ability to preload BL33 into memory instead of relying
Dan Handley610e7e12018-03-01 18:44:00 +00001593on TF-A to load it. This may simplify packaging of the normal world code and
1594improve performance in a development environment. When secure world cold boot
1595is complete, TF-A simply jumps to a BL33 base address provided at build time.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001596
1597For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be
Dan Handley610e7e12018-03-01 18:44:00 +00001598used when compiling TF-A. For example, the following command will create a FIP
1599without a BL33 and prepare to jump to a BL33 image loaded at address
16000x80000000:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001601
Paul Beesley493e3492019-03-13 15:11:04 +00001602.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001603
1604 make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip
1605
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001606Boot of a preloaded kernel image on Base FVP
1607~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001608
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001609The following example uses a simplified boot flow by directly jumping from the
1610TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be
1611useful if both the kernel and the device tree blob (DTB) are already present in
1612memory (like in FVP).
1613
1614For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at
1615address ``0x82000000``, the firmware can be built like this:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001616
Paul Beesley493e3492019-03-13 15:11:04 +00001617.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001618
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001619 CROSS_COMPILE=aarch64-linux-gnu- \
1620 make PLAT=fvp DEBUG=1 \
1621 RESET_TO_BL31=1 \
1622 ARM_LINUX_KERNEL_AS_BL33=1 \
1623 PRELOADED_BL33_BASE=0x80080000 \
1624 ARM_PRELOADED_DTB_BASE=0x82000000 \
1625 all fip
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001626
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001627Now, it is needed to modify the DTB so that the kernel knows the address of the
1628ramdisk. The following script generates a patched DTB from the provided one,
1629assuming that the ramdisk is loaded at address ``0x84000000``. Note that this
1630script assumes that the user is using a ramdisk image prepared for U-Boot, like
1631the ones provided by Linaro. If using a ramdisk without this header,the ``0x40``
1632offset in ``INITRD_START`` has to be removed.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001633
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001634.. code:: bash
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001635
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001636 #!/bin/bash
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001637
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001638 # Path to the input DTB
1639 KERNEL_DTB=<path-to>/<fdt>
1640 # Path to the output DTB
1641 PATCHED_KERNEL_DTB=<path-to>/<patched-fdt>
1642 # Base address of the ramdisk
1643 INITRD_BASE=0x84000000
1644 # Path to the ramdisk
1645 INITRD=<path-to>/<ramdisk.img>
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001646
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001647 # Skip uboot header (64 bytes)
1648 INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) )
1649 INITRD_SIZE=$(stat -Lc %s ${INITRD})
1650 INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) )
1651
1652 CHOSEN_NODE=$(echo \
1653 "/ { \
1654 chosen { \
1655 linux,initrd-start = <${INITRD_START}>; \
1656 linux,initrd-end = <${INITRD_END}>; \
1657 }; \
1658 };")
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001659
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001660 echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \
1661 dtc -O dtb -o ${PATCHED_KERNEL_DTB} -
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001662
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001663And the FVP binary can be run with the following command:
1664
Paul Beesley493e3492019-03-13 15:11:04 +00001665.. code:: shell
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001666
1667 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1668 -C pctl.startup=0.0.0.0 \
1669 -C bp.secure_memory=1 \
1670 -C cluster0.NUM_CORES=4 \
1671 -C cluster1.NUM_CORES=4 \
1672 -C cache_state_modelled=1 \
1673 -C cluster0.cpu0.RVBAR=0x04020000 \
1674 -C cluster0.cpu1.RVBAR=0x04020000 \
1675 -C cluster0.cpu2.RVBAR=0x04020000 \
1676 -C cluster0.cpu3.RVBAR=0x04020000 \
1677 -C cluster1.cpu0.RVBAR=0x04020000 \
1678 -C cluster1.cpu1.RVBAR=0x04020000 \
1679 -C cluster1.cpu2.RVBAR=0x04020000 \
1680 -C cluster1.cpu3.RVBAR=0x04020000 \
1681 --data cluster0.cpu0="<path-to>/bl31.bin"@0x04020000 \
1682 --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \
1683 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1684 --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000
1685
1686Boot of a preloaded kernel image on Juno
1687~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001688
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001689The Trusted Firmware must be compiled in a similar way as for FVP explained
1690above. The process to load binaries to memory is the one explained in
1691`Booting an EL3 payload on Juno`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001692
1693Running the software on FVP
1694---------------------------
1695
David Cunado7c032642018-03-12 18:47:05 +00001696The latest version of the AArch64 build of TF-A has been tested on the following
1697Arm FVPs without shifted affinities, and that do not support threaded CPU cores
1698(64-bit host machine only).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001699
Paul Beesleyba3ed402019-03-13 16:20:44 +00001700.. note::
1701 The FVP models used are Version 11.6 Build 45, unless otherwise stated.
David Cunado124415e2017-06-27 17:31:12 +01001702
David Cunado05845bf2017-12-19 16:33:25 +00001703- ``FVP_Base_AEMv8A-AEMv8A``
1704- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
David Cunado05845bf2017-12-19 16:33:25 +00001705- ``FVP_Base_RevC-2xAEMv8A``
1706- ``FVP_Base_Cortex-A32x4``
David Cunado124415e2017-06-27 17:31:12 +01001707- ``FVP_Base_Cortex-A35x4``
1708- ``FVP_Base_Cortex-A53x4``
David Cunado05845bf2017-12-19 16:33:25 +00001709- ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
1710- ``FVP_Base_Cortex-A55x4``
Ambroise Vincent6f4c0fc2019-03-28 12:51:48 +00001711- ``FVP_Base_Cortex-A57x1-A53x1``
1712- ``FVP_Base_Cortex-A57x2-A53x4``
David Cunado124415e2017-06-27 17:31:12 +01001713- ``FVP_Base_Cortex-A57x4-A53x4``
1714- ``FVP_Base_Cortex-A57x4``
1715- ``FVP_Base_Cortex-A72x4-A53x4``
1716- ``FVP_Base_Cortex-A72x4``
1717- ``FVP_Base_Cortex-A73x4-A53x4``
1718- ``FVP_Base_Cortex-A73x4``
David Cunado05845bf2017-12-19 16:33:25 +00001719- ``FVP_Base_Cortex-A75x4``
1720- ``FVP_Base_Cortex-A76x4``
John Tsichritzisd1894252019-05-20 13:09:34 +01001721- ``FVP_Base_Cortex-A76AEx4``
1722- ``FVP_Base_Cortex-A76AEx8``
1723- ``FVP_Base_Neoverse-N1x4``
Ambroise Vincent6f4c0fc2019-03-28 12:51:48 +00001724- ``FVP_Base_Deimos``
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001725- ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
Ambroise Vincent6f4c0fc2019-03-28 12:51:48 +00001726- ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
1727- ``FVP_RD_E1Edge`` (Version 11.3 build 42)
John Tsichritzisd1894252019-05-20 13:09:34 +01001728- ``FVP_RD_N1Edge``
David Cunado05845bf2017-12-19 16:33:25 +00001729- ``Foundation_Platform``
David Cunado7c032642018-03-12 18:47:05 +00001730
1731The latest version of the AArch32 build of TF-A has been tested on the following
1732Arm FVPs without shifted affinities, and that do not support threaded CPU cores
1733(64-bit host machine only).
1734
1735- ``FVP_Base_AEMv8A-AEMv8A``
David Cunado124415e2017-06-27 17:31:12 +01001736- ``FVP_Base_Cortex-A32x4``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001737
Paul Beesleyba3ed402019-03-13 16:20:44 +00001738.. note::
1739 The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which
1740 is not compatible with legacy GIC configurations. Therefore this FVP does not
1741 support these legacy GIC configurations.
David Cunado7c032642018-03-12 18:47:05 +00001742
Paul Beesleyba3ed402019-03-13 16:20:44 +00001743.. note::
1744 The build numbers quoted above are those reported by launching the FVP
1745 with the ``--version`` parameter.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001746
Paul Beesleyba3ed402019-03-13 16:20:44 +00001747.. note::
1748 Linaro provides a ramdisk image in prebuilt FVP configurations and full
1749 file systems that can be downloaded separately. To run an FVP with a virtio
1750 file system image an additional FVP configuration option
1751 ``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
1752 used.
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001753
Paul Beesleyba3ed402019-03-13 16:20:44 +00001754.. note::
1755 The software will not work on Version 1.0 of the Foundation FVP.
1756 The commands below would report an ``unhandled argument`` error in this case.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001757
Paul Beesleyba3ed402019-03-13 16:20:44 +00001758.. note::
1759 FVPs can be launched with ``--cadi-server`` option such that a
1760 CADI-compliant debugger (for example, Arm DS-5) can connect to and control
1761 its execution.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001762
Paul Beesleyba3ed402019-03-13 16:20:44 +00001763.. warning::
1764 Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
1765 the internal synchronisation timings changed compared to older versions of
1766 the models. The models can be launched with ``-Q 100`` option if they are
1767 required to match the run time characteristics of the older versions.
David Cunado97309462017-07-31 12:24:51 +01001768
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001769The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be
Dan Handley610e7e12018-03-01 18:44:00 +00001770downloaded for free from `Arm's website`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001771
David Cunado124415e2017-06-27 17:31:12 +01001772The Cortex-A models listed above are also available to download from
Dan Handley610e7e12018-03-01 18:44:00 +00001773`Arm's website`_.
David Cunado124415e2017-06-27 17:31:12 +01001774
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001775Please refer to the FVP documentation for a detailed description of the model
Dan Handley610e7e12018-03-01 18:44:00 +00001776parameter options. A brief description of the important ones that affect TF-A
1777and normal world software behavior is provided below.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001778
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001779Obtaining the Flattened Device Trees
1780~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1781
1782Depending on the FVP configuration and Linux configuration used, different
Soby Mathewecd94ad2018-05-09 13:59:29 +01001783FDT files are required. FDT source files for the Foundation and Base FVPs can
1784be found in the TF-A source directory under ``fdts/``. The Foundation FVP has
1785a subset of the Base FVP components. For example, the Foundation FVP lacks
1786CLCD and MMC support, and has only one CPU cluster.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001787
Paul Beesleyba3ed402019-03-13 16:20:44 +00001788.. note::
1789 It is not recommended to use the FDTs built along the kernel because not
1790 all FDTs are available from there.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001791
Soby Mathewecd94ad2018-05-09 13:59:29 +01001792The dynamic configuration capability is enabled in the firmware for FVPs.
1793This means that the firmware can authenticate and load the FDT if present in
1794FIP. A default FDT is packaged into FIP during the build based on
1795the build configuration. This can be overridden by using the ``FVP_HW_CONFIG``
1796or ``FVP_HW_CONFIG_DTS`` build options (refer to the
1797`Arm FVP platform specific build options`_ section for detail on the options).
1798
1799- ``fvp-base-gicv2-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001800
David Cunado7c032642018-03-12 18:47:05 +00001801 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
1802 affinities and with Base memory map configuration.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001803
Soby Mathewecd94ad2018-05-09 13:59:29 +01001804- ``fvp-base-gicv2-psci-aarch32.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001805
David Cunado7c032642018-03-12 18:47:05 +00001806 For use with models such as the Cortex-A32 Base FVPs without shifted
1807 affinities and running Linux in AArch32 state with Base memory map
1808 configuration.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001809
Soby Mathewecd94ad2018-05-09 13:59:29 +01001810- ``fvp-base-gicv3-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001811
David Cunado7c032642018-03-12 18:47:05 +00001812 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
1813 affinities and with Base memory map configuration and Linux GICv3 support.
1814
Soby Mathewecd94ad2018-05-09 13:59:29 +01001815- ``fvp-base-gicv3-psci-1t.dts``
David Cunado7c032642018-03-12 18:47:05 +00001816
1817 For use with models such as the AEMv8-RevC Base FVP with shifted affinities,
1818 single threaded CPUs, Base memory map configuration and Linux GICv3 support.
1819
Soby Mathewecd94ad2018-05-09 13:59:29 +01001820- ``fvp-base-gicv3-psci-dynamiq.dts``
David Cunado7c032642018-03-12 18:47:05 +00001821
1822 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities,
1823 single cluster, single threaded CPUs, Base memory map configuration and Linux
1824 GICv3 support.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001825
Soby Mathewecd94ad2018-05-09 13:59:29 +01001826- ``fvp-base-gicv3-psci-aarch32.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001827
David Cunado7c032642018-03-12 18:47:05 +00001828 For use with models such as the Cortex-A32 Base FVPs without shifted
1829 affinities and running Linux in AArch32 state with Base memory map
1830 configuration and Linux GICv3 support.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001831
Soby Mathewecd94ad2018-05-09 13:59:29 +01001832- ``fvp-foundation-gicv2-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001833
1834 For use with Foundation FVP with Base memory map configuration.
1835
Soby Mathewecd94ad2018-05-09 13:59:29 +01001836- ``fvp-foundation-gicv3-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001837
1838 (Default) For use with Foundation FVP with Base memory map configuration
1839 and Linux GICv3 support.
1840
1841Running on the Foundation FVP with reset to BL1 entrypoint
1842~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1843
1844The following ``Foundation_Platform`` parameters should be used to boot Linux with
Dan Handley610e7e12018-03-01 18:44:00 +000018454 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001846
Paul Beesley493e3492019-03-13 15:11:04 +00001847.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001848
1849 <path-to>/Foundation_Platform \
1850 --cores=4 \
Antonio Nino Diazb44eda52018-02-23 11:01:31 +00001851 --arm-v8.0 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001852 --secure-memory \
1853 --visualization \
1854 --gicv3 \
1855 --data="<path-to>/<bl1-binary>"@0x0 \
1856 --data="<path-to>/<FIP-binary>"@0x08000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001857 --data="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001858 --data="<path-to>/<ramdisk-binary>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001859
1860Notes:
1861
1862- BL1 is loaded at the start of the Trusted ROM.
1863- The Firmware Image Package is loaded at the start of NOR FLASH0.
Soby Mathewecd94ad2018-05-09 13:59:29 +01001864- The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address
1865 is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001866- The default use-case for the Foundation FVP is to use the ``--gicv3`` option
1867 and enable the GICv3 device in the model. Note that without this option,
1868 the Foundation FVP defaults to legacy (Versatile Express) memory map which
Dan Handley610e7e12018-03-01 18:44:00 +00001869 is not supported by TF-A.
1870- In order for TF-A to run correctly on the Foundation FVP, the architecture
1871 versions must match. The Foundation FVP defaults to the highest v8.x
1872 version it supports but the default build for TF-A is for v8.0. To avoid
1873 issues either start the Foundation FVP to use v8.0 architecture using the
1874 ``--arm-v8.0`` option, or build TF-A with an appropriate value for
1875 ``ARM_ARCH_MINOR``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001876
1877Running on the AEMv8 Base FVP with reset to BL1 entrypoint
1878~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1879
David Cunado7c032642018-03-12 18:47:05 +00001880The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001881with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001882
Paul Beesley493e3492019-03-13 15:11:04 +00001883.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001884
David Cunado7c032642018-03-12 18:47:05 +00001885 <path-to>/FVP_Base_RevC-2xAEMv8A \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001886 -C pctl.startup=0.0.0.0 \
1887 -C bp.secure_memory=1 \
1888 -C bp.tzc_400.diagnostics=1 \
1889 -C cluster0.NUM_CORES=4 \
1890 -C cluster1.NUM_CORES=4 \
1891 -C cache_state_modelled=1 \
1892 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1893 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001894 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001895 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001896
Paul Beesleyba3ed402019-03-13 16:20:44 +00001897.. note::
1898 The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires
1899 a specific DTS for all the CPUs to be loaded.
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001900
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001901Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
1902~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1903
1904The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001905with 8 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001906
Paul Beesley493e3492019-03-13 15:11:04 +00001907.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001908
1909 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1910 -C pctl.startup=0.0.0.0 \
1911 -C bp.secure_memory=1 \
1912 -C bp.tzc_400.diagnostics=1 \
1913 -C cluster0.NUM_CORES=4 \
1914 -C cluster1.NUM_CORES=4 \
1915 -C cache_state_modelled=1 \
1916 -C cluster0.cpu0.CONFIG64=0 \
1917 -C cluster0.cpu1.CONFIG64=0 \
1918 -C cluster0.cpu2.CONFIG64=0 \
1919 -C cluster0.cpu3.CONFIG64=0 \
1920 -C cluster1.cpu0.CONFIG64=0 \
1921 -C cluster1.cpu1.CONFIG64=0 \
1922 -C cluster1.cpu2.CONFIG64=0 \
1923 -C cluster1.cpu3.CONFIG64=0 \
1924 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1925 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001926 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001927 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001928
1929Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
1930~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1931
1932The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001933boot Linux with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001934
Paul Beesley493e3492019-03-13 15:11:04 +00001935.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001936
1937 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1938 -C pctl.startup=0.0.0.0 \
1939 -C bp.secure_memory=1 \
1940 -C bp.tzc_400.diagnostics=1 \
1941 -C cache_state_modelled=1 \
1942 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1943 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001944 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001945 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001946
1947Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
1948~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1949
1950The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001951boot Linux with 4 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001952
Paul Beesley493e3492019-03-13 15:11:04 +00001953.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001954
1955 <path-to>/FVP_Base_Cortex-A32x4 \
1956 -C pctl.startup=0.0.0.0 \
1957 -C bp.secure_memory=1 \
1958 -C bp.tzc_400.diagnostics=1 \
1959 -C cache_state_modelled=1 \
1960 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1961 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001962 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001963 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001964
1965Running on the AEMv8 Base FVP with reset to BL31 entrypoint
1966~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1967
David Cunado7c032642018-03-12 18:47:05 +00001968The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001969with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001970
Paul Beesley493e3492019-03-13 15:11:04 +00001971.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001972
David Cunado7c032642018-03-12 18:47:05 +00001973 <path-to>/FVP_Base_RevC-2xAEMv8A \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001974 -C pctl.startup=0.0.0.0 \
1975 -C bp.secure_memory=1 \
1976 -C bp.tzc_400.diagnostics=1 \
1977 -C cluster0.NUM_CORES=4 \
1978 -C cluster1.NUM_CORES=4 \
1979 -C cache_state_modelled=1 \
Soby Mathewba678c32018-12-12 14:54:23 +00001980 -C cluster0.cpu0.RVBAR=0x04010000 \
1981 -C cluster0.cpu1.RVBAR=0x04010000 \
1982 -C cluster0.cpu2.RVBAR=0x04010000 \
1983 -C cluster0.cpu3.RVBAR=0x04010000 \
1984 -C cluster1.cpu0.RVBAR=0x04010000 \
1985 -C cluster1.cpu1.RVBAR=0x04010000 \
1986 -C cluster1.cpu2.RVBAR=0x04010000 \
1987 -C cluster1.cpu3.RVBAR=0x04010000 \
1988 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
1989 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001990 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001991 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001992 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001993 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001994
1995Notes:
1996
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00001997- If Position Independent Executable (PIE) support is enabled for BL31
Soby Mathewba678c32018-12-12 14:54:23 +00001998 in this config, it can be loaded at any valid address for execution.
1999
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002000- Since a FIP is not loaded when using BL31 as reset entrypoint, the
2001 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
2002 parameter is needed to load the individual bootloader images in memory.
2003 BL32 image is only needed if BL31 has been built to expect a Secure-EL1
Soby Mathewecd94ad2018-05-09 13:59:29 +01002004 Payload. For the same reason, the FDT needs to be compiled from the DT source
2005 and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000``
2006 parameter.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002007
Ambroise Vincentc3568ef2019-03-14 10:53:16 +00002008- The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a
2009 specific DTS for all the CPUs to be loaded.
2010
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002011- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
2012 X and Y are the cluster and CPU numbers respectively, is used to set the
2013 reset vector for each core.
2014
2015- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
2016 changing the value of
2017 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
2018 ``BL32_BASE``.
2019
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01002020Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint
2021~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002022
2023The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00002024with 8 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002025
Paul Beesley493e3492019-03-13 15:11:04 +00002026.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002027
2028 <path-to>/FVP_Base_AEMv8A-AEMv8A \
2029 -C pctl.startup=0.0.0.0 \
2030 -C bp.secure_memory=1 \
2031 -C bp.tzc_400.diagnostics=1 \
2032 -C cluster0.NUM_CORES=4 \
2033 -C cluster1.NUM_CORES=4 \
2034 -C cache_state_modelled=1 \
2035 -C cluster0.cpu0.CONFIG64=0 \
2036 -C cluster0.cpu1.CONFIG64=0 \
2037 -C cluster0.cpu2.CONFIG64=0 \
2038 -C cluster0.cpu3.CONFIG64=0 \
2039 -C cluster1.cpu0.CONFIG64=0 \
2040 -C cluster1.cpu1.CONFIG64=0 \
2041 -C cluster1.cpu2.CONFIG64=0 \
2042 -C cluster1.cpu3.CONFIG64=0 \
Soby Mathewba678c32018-12-12 14:54:23 +00002043 -C cluster0.cpu0.RVBAR=0x04002000 \
2044 -C cluster0.cpu1.RVBAR=0x04002000 \
2045 -C cluster0.cpu2.RVBAR=0x04002000 \
2046 -C cluster0.cpu3.RVBAR=0x04002000 \
2047 -C cluster1.cpu0.RVBAR=0x04002000 \
2048 -C cluster1.cpu1.RVBAR=0x04002000 \
2049 -C cluster1.cpu2.RVBAR=0x04002000 \
2050 -C cluster1.cpu3.RVBAR=0x04002000 \
Soby Mathewaf14b462018-06-01 16:53:38 +01002051 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002052 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002053 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002054 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002055 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002056
Paul Beesleyba3ed402019-03-13 16:20:44 +00002057.. note::
2058 The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
2059 It should match the address programmed into the RVBAR register as well.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002060
2061Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
2062~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2063
2064The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00002065boot Linux with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002066
Paul Beesley493e3492019-03-13 15:11:04 +00002067.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002068
2069 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
2070 -C pctl.startup=0.0.0.0 \
2071 -C bp.secure_memory=1 \
2072 -C bp.tzc_400.diagnostics=1 \
2073 -C cache_state_modelled=1 \
Soby Mathewba678c32018-12-12 14:54:23 +00002074 -C cluster0.cpu0.RVBARADDR=0x04010000 \
2075 -C cluster0.cpu1.RVBARADDR=0x04010000 \
2076 -C cluster0.cpu2.RVBARADDR=0x04010000 \
2077 -C cluster0.cpu3.RVBARADDR=0x04010000 \
2078 -C cluster1.cpu0.RVBARADDR=0x04010000 \
2079 -C cluster1.cpu1.RVBARADDR=0x04010000 \
2080 -C cluster1.cpu2.RVBARADDR=0x04010000 \
2081 -C cluster1.cpu3.RVBARADDR=0x04010000 \
2082 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
2083 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002084 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002085 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002086 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002087 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002088
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01002089Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint
2090~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002091
2092The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00002093boot Linux with 4 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002094
Paul Beesley493e3492019-03-13 15:11:04 +00002095.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002096
2097 <path-to>/FVP_Base_Cortex-A32x4 \
2098 -C pctl.startup=0.0.0.0 \
2099 -C bp.secure_memory=1 \
2100 -C bp.tzc_400.diagnostics=1 \
2101 -C cache_state_modelled=1 \
Soby Mathewba678c32018-12-12 14:54:23 +00002102 -C cluster0.cpu0.RVBARADDR=0x04002000 \
2103 -C cluster0.cpu1.RVBARADDR=0x04002000 \
2104 -C cluster0.cpu2.RVBARADDR=0x04002000 \
2105 -C cluster0.cpu3.RVBARADDR=0x04002000 \
Soby Mathewaf14b462018-06-01 16:53:38 +01002106 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002107 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002108 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002109 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002110 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002111
2112Running the software on Juno
2113----------------------------
2114
Dan Handley610e7e12018-03-01 18:44:00 +00002115This version of TF-A has been tested on variants r0, r1 and r2 of Juno.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002116
2117To execute the software stack on Juno, the version of the Juno board recovery
2118image indicated in the `Linaro Release Notes`_ must be installed. If you have an
2119earlier version installed or are unsure which version is installed, please
2120re-install the recovery image by following the
2121`Instructions for using Linaro's deliverables on Juno`_.
2122
Dan Handley610e7e12018-03-01 18:44:00 +00002123Preparing TF-A images
2124~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002125
Dan Handley610e7e12018-03-01 18:44:00 +00002126After building TF-A, the files ``bl1.bin`` and ``fip.bin`` need copying to the
2127``SOFTWARE/`` directory of the Juno SD card.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002128
2129Other Juno software information
2130~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2131
Dan Handley610e7e12018-03-01 18:44:00 +00002132Please visit the `Arm Platforms Portal`_ to get support and obtain any other Juno
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002133software information. Please also refer to the `Juno Getting Started Guide`_ to
Dan Handley610e7e12018-03-01 18:44:00 +00002134get more detailed information about the Juno Arm development platform and how to
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002135configure it.
2136
2137Testing SYSTEM SUSPEND on Juno
2138~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2139
2140The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend
2141to RAM. For more details refer to section 5.16 of `PSCI`_. To test system suspend
2142on Juno, at the linux shell prompt, issue the following command:
2143
Paul Beesley493e3492019-03-13 15:11:04 +00002144.. code:: shell
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002145
2146 echo +10 > /sys/class/rtc/rtc0/wakealarm
2147 echo -n mem > /sys/power/state
2148
2149The Juno board should suspend to RAM and then wakeup after 10 seconds due to
2150wakeup interrupt from RTC.
2151
2152--------------
2153
Antonio Nino Diaz0e402d32019-01-30 16:01:49 +00002154*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002155
Louis Mayencourt545a9ed2019-03-08 15:35:40 +00002156.. _arm Developer page: https://developer.arm.com/open-source/gnu-toolchain/gnu-a/downloads
David Cunadob2de0992017-06-29 12:01:33 +01002157.. _Linaro: `Linaro Release Notes`_
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002158.. _Linaro Release: `Linaro Release Notes`_
Paul Beesley2437ddc2019-02-08 16:43:05 +00002159.. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-release-notes
2160.. _Linaro instructions: https://community.arm.com/dev-platforms/w/docs/304/arm-reference-platforms-deliverables
David Cunado82509be2017-12-19 16:33:25 +00002161.. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno
Dan Handley610e7e12018-03-01 18:44:00 +00002162.. _Arm Platforms Portal: https://community.arm.com/dev-platforms/
Paul Beesley2437ddc2019-02-08 16:43:05 +00002163.. _Development Studio 5 (DS-5): https://developer.arm.com/products/software-development-tools/ds-5-development-studio
Louis Mayencourt72ef3d42019-03-22 11:47:22 +00002164.. _arm-trusted-firmware-a project page: https://review.trustedfirmware.org/admin/projects/TF-A/trusted-firmware-a
Paul Beesley8b4bdeb2019-01-21 12:06:24 +00002165.. _`Linux Coding Style`: https://www.kernel.org/doc/html/latest/process/coding-style.html
Sandrine Bailleux771535b2018-09-20 10:27:13 +02002166.. _Linux master tree: https://github.com/torvalds/linux/tree/master/
Antonio Nino Diazb5d68092017-05-23 11:49:22 +01002167.. _Dia: https://wiki.gnome.org/Apps/Dia/Download
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002168.. _here: psci-lib-integration-guide.rst
John Tsichritzis2fd3d922019-05-28 13:13:39 +01002169.. _Trusted Board Boot: ../design/trusted-board-boot.rst
2170.. _TB_FW_CONFIG for FVP: ../../plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
2171.. _Secure-EL1 Payloads and Dispatchers: ../design/firmware-design.rst#user-content-secure-el1-payloads-and-dispatchers
2172.. _Firmware Update: ../components/firmware-update.rst
2173.. _Firmware Design: ../design/firmware-design.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002174.. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git
2175.. _mbed TLS Security Center: https://tls.mbed.org/security
Dan Handley610e7e12018-03-01 18:44:00 +00002176.. _Arm's website: `FVP models`_
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002177.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002178.. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf
David Cunadob2de0992017-06-29 12:01:33 +01002179.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
John Tsichritzis2fd3d922019-05-28 13:13:39 +01002180.. _Secure Partition Manager Design guide: ../components/secure-partition-manager-design.rst
2181.. _`Trusted Firmware-A Coding Guidelines`: ../process/coding-guidelines.rst
2182.. _Library at ROM: ../components/romlib-design.rst