Blame - arch/arm/cpu/armv7/ls102xa/Kconfig - filogic/uboot

blob: c496e6439199125cddb3a5c0d04578c7a3494aff [file] [log] [blame]

York Sun	149eb33	2016-09-26 08:09:27 -0700	[diff] [blame]	1	config ARCH_LS1021A
York Sun	fcd0e74	2016-10-04 14:31:47 -0700	[diff] [blame]	2	bool
Tom Rini	05b419e	2021-12-11 14:55:49 -0500	[diff] [blame]	3	select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI
Michal Simek	7e7ba3b	2018-07-23 15:55:15 +0200	[diff] [blame]	4	select SYS_FSL_DDR_BE if SYS_FSL_DDR
				5	select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
York Sun	1dc61ca	2016-12-28 08:43:41 -0800	[diff] [blame]	6	select SYS_FSL_ERRATUM_A008378
				7	select SYS_FSL_ERRATUM_A008407
Tom Rini	5618460	2022-02-25 11:19:53 -0500	[diff] [blame]	8	select SYS_FSL_ERRATUM_A008850 if SYS_FSL_DDR
Aleksandar Gerasimovski	58aeddc	2020-11-26 10:52:41 +0000	[diff] [blame]	9	select SYS_FSL_ERRATUM_A008997 if USB
Aleksandar Gerasimovski	58aeddc	2020-11-26 10:52:41 +0000	[diff] [blame]	10	select SYS_FSL_ERRATUM_A009008 if USB
York Sun	1dc61ca	2016-12-28 08:43:41 -0800	[diff] [blame]	11	select SYS_FSL_ERRATUM_A009663
Aleksandar Gerasimovski	58aeddc	2020-11-26 10:52:41 +0000	[diff] [blame]	12	select SYS_FSL_ERRATUM_A009798 if USB
York Sun	1dc61ca	2016-12-28 08:43:41 -0800	[diff] [blame]	13	select SYS_FSL_ERRATUM_A009942
York Sun	149eb33	2016-09-26 08:09:27 -0700	[diff] [blame]	14	select SYS_FSL_ERRATUM_A010315
Ashish Kumar	1123406	2017-08-11 11:09:14 +0530	[diff] [blame]	15	select SYS_FSL_HAS_CCI400
York Sun	d297d39	2016-12-28 08:43:40 -0800	[diff] [blame]	16	select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
				17	select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
York Sun	92c36e2	2016-12-28 08:43:30 -0800	[diff] [blame]	18	select SYS_FSL_HAS_SEC
				19	select SYS_FSL_SEC_COMPAT_5
York Sun	fa419942	2016-12-28 08:43:31 -0800	[diff] [blame]	20	select SYS_FSL_SEC_LE
Michal Simek	7e7ba3b	2018-07-23 15:55:15 +0200	[diff] [blame]	21	select SYS_FSL_SRDS_1
				22	select SYS_HAS_SERDES
Tom Rini	1a19588	2021-08-18 23:12:33 -0400	[diff] [blame]	23	select SYS_I2C_MXC
Michal Simek	7e7ba3b	2018-07-23 15:55:15 +0200	[diff] [blame]	24	imply CMD_PCI
Simon Glass	0e5faf0	2017-06-14 21:28:21 -0600	[diff] [blame]	25	imply SCSI
Tuomas Tynkkynen	edf9f62	2017-12-08 15:36:19 +0200	[diff] [blame]	26	imply SCSI_AHCI
York Sun	4de7e93	2016-09-26 08:09:29 -0700	[diff] [blame]	27
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	28	menu "LS102xA architecture"
				29	depends on ARCH_LS1021A
				30
York Sun	4de7e93	2016-09-26 08:09:29 -0700	[diff] [blame]	31	config LS1_DEEP_SLEEP
York Sun	fcd0e74	2016-10-04 14:31:47 -0700	[diff] [blame]	32	bool "Deep sleep"
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	33
York Sun	f188d22	2016-10-04 14:45:01 -0700	[diff] [blame]	34	config MAX_CPUS
				35	int "Maximum number of CPUs permitted for LS102xA"
York Sun	f188d22	2016-10-04 14:45:01 -0700	[diff] [blame]	36	default 2
				37	help
				38	Set this number to the maximum number of possible CPUs in the SoC.
				39	SoCs may have multiple clusters with each cluster may have multiple
				40	ports. If some ports are reserved but higher ports are used for
				41	cores, count the reserved ports. This will allocate enough memory
				42	in spin table to properly handle all cores.
				43
Udit Agarwal	22ec238	2019-11-07 16:11:32 +0000	[diff] [blame]	44	config NXP_ESBC
				45	bool "NXP_ESBC"
York Sun	dfa93a9	2016-12-02 09:31:43 -0800	[diff] [blame]	46	help
				47	Enable Freescale Secure Boot feature. Normally selected
				48	by defconfig. If unsure, do not change.
				49
Ashish Kumar	1123406	2017-08-11 11:09:14 +0530	[diff] [blame]	50	config SYS_CCI400_OFFSET
				51	hex "Offset for CCI400 base"
				52	depends on SYS_FSL_HAS_CCI400
				53	default 0x180000
				54	help
				55	Offset for CCI400 base.
				56	CCI400 base addr = CCSRBAR + CCI400_OFFSET
				57
Alison Wang	d6be97b	2019-03-06 14:49:14 +0800	[diff] [blame]	58	config SYS_FSL_ERRATUM_A008850
				59	bool
				60	help
				61	Workaround for DDR erratum A008850
				62
Ran Wang	373a7b0	2017-09-04 18:46:54 +0800	[diff] [blame]	63	config SYS_FSL_ERRATUM_A008997
				64	bool
				65	help
				66	Workaround for USB PHY erratum A008997
				67
Ran Wang	2eb4898	2017-09-04 18:46:55 +0800	[diff] [blame]	68	config SYS_FSL_ERRATUM_A009007
				69	bool
				70	help
				71	Workaround for USB PHY erratum A009007
				72
Ran Wang	1509c8a	2017-09-04 18:46:52 +0800	[diff] [blame]	73	config SYS_FSL_ERRATUM_A009008
				74	bool
				75	help
				76	Workaround for USB PHY erratum A009008
				77
Ran Wang	d2b711b7	2017-09-04 18:46:53 +0800	[diff] [blame]	78	config SYS_FSL_ERRATUM_A009798
				79	bool
				80	help
				81	Workaround for USB PHY erratum A009798
				82
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	83	config SYS_FSL_ERRATUM_A010315
				84	bool "Workaround for PCIe erratum A010315"
				85
Ashish Kumar	1123406	2017-08-11 11:09:14 +0530	[diff] [blame]	86	config SYS_FSL_HAS_CCI400
				87	bool
				88
York Sun	6b62ef0	2016-10-04 18:01:34 -0700	[diff] [blame]	89	config SYS_FSL_SRDS_1
				90	bool
				91
				92	config SYS_FSL_SRDS_2
				93	bool
				94
				95	config SYS_HAS_SERDES
				96	bool
York Sun	f64fc5c	2016-10-04 18:04:37 -0700	[diff] [blame]	97
York Sun	e7310a3	2016-10-04 14:45:54 -0700	[diff] [blame]	98	config SYS_FSL_IFC_BANK_COUNT
				99	int "Maximum banks of Integrated flash controller"
York Sun	e7310a3	2016-10-04 14:45:54 -0700	[diff] [blame]	100	default 8
				101
York Sun	1dc61ca	2016-12-28 08:43:41 -0800	[diff] [blame]	102	config SYS_FSL_ERRATUM_A008407
				103	bool
				104
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	105	endmenu