Blame - arch/arm/cpu/armv7/ls102xa/Kconfig - filogic/uboot

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York Sun	149eb33	2016-09-26 08:09:27 -0700	[diff] [blame]	1	config ARCH_LS1021A
York Sun	fcd0e74	2016-10-04 14:31:47 -0700	[diff] [blame]	2	bool
York Sun	1dc61ca	2016-12-28 08:43:41 -0800	[diff] [blame]	3	select SYS_FSL_ERRATUM_A008378
				4	select SYS_FSL_ERRATUM_A008407
Ran Wang	373a7b0	2017-09-04 18:46:54 +0800	[diff] [blame^]	5	select SYS_FSL_ERRATUM_A008997
Ran Wang	1509c8a	2017-09-04 18:46:52 +0800	[diff] [blame]	6	select SYS_FSL_ERRATUM_A009008
York Sun	1dc61ca	2016-12-28 08:43:41 -0800	[diff] [blame]	7	select SYS_FSL_ERRATUM_A009663
Ran Wang	d2b711b7	2017-09-04 18:46:53 +0800	[diff] [blame]	8	select SYS_FSL_ERRATUM_A009798
York Sun	1dc61ca	2016-12-28 08:43:41 -0800	[diff] [blame]	9	select SYS_FSL_ERRATUM_A009942
York Sun	149eb33	2016-09-26 08:09:27 -0700	[diff] [blame]	10	select SYS_FSL_ERRATUM_A010315
Ashish Kumar	1123406	2017-08-11 11:09:14 +0530	[diff] [blame]	11	select SYS_FSL_HAS_CCI400
York Sun	6b62ef0	2016-10-04 18:01:34 -0700	[diff] [blame]	12	select SYS_FSL_SRDS_1
				13	select SYS_HAS_SERDES
York Sun	d297d39	2016-12-28 08:43:40 -0800	[diff] [blame]	14	select SYS_FSL_DDR_BE if SYS_FSL_DDR
				15	select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
				16	select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
				17	select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
York Sun	92c36e2	2016-12-28 08:43:30 -0800	[diff] [blame]	18	select SYS_FSL_HAS_SEC
				19	select SYS_FSL_SEC_COMPAT_5
York Sun	fa419942	2016-12-28 08:43:31 -0800	[diff] [blame]	20	select SYS_FSL_SEC_LE
Simon Glass	0e5faf0	2017-06-14 21:28:21 -0600	[diff] [blame]	21	imply SCSI
Simon Glass	c88a09a	2017-08-04 16:34:34 -0600	[diff] [blame]	22	imply CMD_PCI
York Sun	4de7e93	2016-09-26 08:09:29 -0700	[diff] [blame]	23
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	24	menu "LS102xA architecture"
				25	depends on ARCH_LS1021A
				26
Hou Zhiqiang	d553bf2	2016-12-13 14:54:24 +0800	[diff] [blame]	27	config FSL_PCIE_COMPAT
				28	string "PCIe compatible of Kernel DT"
				29	depends on PCIE_LAYERSCAPE
				30	default "fsl,ls1021a-pcie" if ARCH_LS1021A
				31	help
				32	This compatible is used to find pci controller node in Kernel DT
				33	to complete fixup.
				34
York Sun	4de7e93	2016-09-26 08:09:29 -0700	[diff] [blame]	35	config LS1_DEEP_SLEEP
York Sun	fcd0e74	2016-10-04 14:31:47 -0700	[diff] [blame]	36	bool "Deep sleep"
				37	depends on ARCH_LS1021A
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	38
York Sun	f188d22	2016-10-04 14:45:01 -0700	[diff] [blame]	39	config MAX_CPUS
				40	int "Maximum number of CPUs permitted for LS102xA"
				41	depends on ARCH_LS1021A
				42	default 2
				43	help
				44	Set this number to the maximum number of possible CPUs in the SoC.
				45	SoCs may have multiple clusters with each cluster may have multiple
				46	ports. If some ports are reserved but higher ports are used for
				47	cores, count the reserved ports. This will allocate enough memory
				48	in spin table to properly handle all cores.
				49
York Sun	dfa93a9	2016-12-02 09:31:43 -0800	[diff] [blame]	50	config SECURE_BOOT
				51	bool "Secure Boot"
				52	help
				53	Enable Freescale Secure Boot feature. Normally selected
				54	by defconfig. If unsure, do not change.
				55
Ashish Kumar	1123406	2017-08-11 11:09:14 +0530	[diff] [blame]	56	config SYS_CCI400_OFFSET
				57	hex "Offset for CCI400 base"
				58	depends on SYS_FSL_HAS_CCI400
				59	default 0x180000
				60	help
				61	Offset for CCI400 base.
				62	CCI400 base addr = CCSRBAR + CCI400_OFFSET
				63
Ran Wang	373a7b0	2017-09-04 18:46:54 +0800	[diff] [blame^]	64	config SYS_FSL_ERRATUM_A008997
				65	bool
				66	help
				67	Workaround for USB PHY erratum A008997
				68
Ran Wang	1509c8a	2017-09-04 18:46:52 +0800	[diff] [blame]	69	config SYS_FSL_ERRATUM_A009008
				70	bool
				71	help
				72	Workaround for USB PHY erratum A009008
				73
Ran Wang	d2b711b7	2017-09-04 18:46:53 +0800	[diff] [blame]	74	config SYS_FSL_ERRATUM_A009798
				75	bool
				76	help
				77	Workaround for USB PHY erratum A009798
				78
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	79	config SYS_FSL_ERRATUM_A010315
				80	bool "Workaround for PCIe erratum A010315"
				81
Ashish Kumar	1123406	2017-08-11 11:09:14 +0530	[diff] [blame]	82	config SYS_FSL_HAS_CCI400
				83	bool
				84
York Sun	6b62ef0	2016-10-04 18:01:34 -0700	[diff] [blame]	85	config SYS_FSL_SRDS_1
				86	bool
				87
				88	config SYS_FSL_SRDS_2
				89	bool
				90
				91	config SYS_HAS_SERDES
				92	bool
York Sun	f64fc5c	2016-10-04 18:04:37 -0700	[diff] [blame]	93
York Sun	e7310a3	2016-10-04 14:45:54 -0700	[diff] [blame]	94	config SYS_FSL_IFC_BANK_COUNT
				95	int "Maximum banks of Integrated flash controller"
				96	depends on ARCH_LS1021A
				97	default 8
				98
York Sun	1dc61ca	2016-12-28 08:43:41 -0800	[diff] [blame]	99	config SYS_FSL_ERRATUM_A008407
				100	bool
				101
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	102	endmenu